I2C Register Masks

Macros
#define	I2C0_BASE   (0x40066000u)
#define	I2C0   ((I2C_Type *)I2C0_BASE)
#define	I2C1_BASE   (0x40067000u)
#define	I2C1   ((I2C_Type *)I2C1_BASE)
#define	I2C_BASE_ADDRS   { I2C0_BASE, I2C1_BASE }
#define	I2C_BASE_PTRS   { I2C0, I2C1 }
#define	I2C_IRQS   { I2C0_IRQn, I2C1_IRQn }

A1 - I2C Address Register 1
#define	I2C_A1_AD_MASK   (0xFEU)
#define	I2C_A1_AD_SHIFT   (1U)
#define	I2C_A1_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
#define	I2C_A1_AD_MASK   0xFEu
#define	I2C_A1_AD_SHIFT   1
#define	I2C_A1_AD(x)   (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
#define	I2C_A1_AD_MASK   (0xFEU)
#define	I2C_A1_AD_SHIFT   (1U)
#define	I2C_A1_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
#define	I2C_A1_AD_MASK   (0xFEU)
#define	I2C_A1_AD_SHIFT   (1U)
#define	I2C_A1_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
#define	I2C_A1_AD_MASK   (0xFEU)
#define	I2C_A1_AD_SHIFT   (1U)
#define	I2C_A1_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
#define	I2C_A1_AD_MASK   (0xFEU)
#define	I2C_A1_AD_SHIFT   (1U)
#define	I2C_A1_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)

F - I2C Frequency Divider register
#define	I2C_F_ICR_MASK   (0x3FU)
#define	I2C_F_ICR_SHIFT   (0U)
#define	I2C_F_ICR(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
#define	I2C_F_MULT_MASK   (0xC0U)
#define	I2C_F_MULT_SHIFT   (6U)
#define	I2C_F_MULT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
#define	I2C_F_ICR_MASK   0x3Fu
#define	I2C_F_ICR_SHIFT   0
#define	I2C_F_ICR(x)   (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
#define	I2C_F_MULT_MASK   0xC0u
#define	I2C_F_MULT_SHIFT   6
#define	I2C_F_MULT(x)   (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
#define	I2C_F_ICR_MASK   (0x3FU)
#define	I2C_F_ICR_SHIFT   (0U)
#define	I2C_F_ICR(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
#define	I2C_F_MULT_MASK   (0xC0U)
#define	I2C_F_MULT_SHIFT   (6U)
#define	I2C_F_MULT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
#define	I2C_F_ICR_MASK   (0x3FU)
#define	I2C_F_ICR_SHIFT   (0U)
#define	I2C_F_ICR(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
#define	I2C_F_MULT_MASK   (0xC0U)
#define	I2C_F_MULT_SHIFT   (6U)
#define	I2C_F_MULT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
#define	I2C_F_ICR_MASK   (0x3FU)
#define	I2C_F_ICR_SHIFT   (0U)
#define	I2C_F_ICR(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
#define	I2C_F_MULT_MASK   (0xC0U)
#define	I2C_F_MULT_SHIFT   (6U)
#define	I2C_F_MULT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
#define	I2C_F_ICR_MASK   (0x3FU)
#define	I2C_F_ICR_SHIFT   (0U)
#define	I2C_F_ICR(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
#define	I2C_F_MULT_MASK   (0xC0U)
#define	I2C_F_MULT_SHIFT   (6U)
#define	I2C_F_MULT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)

C1 - I2C Control Register 1
#define	I2C_C1_DMAEN_MASK   (0x1U)
#define	I2C_C1_DMAEN_SHIFT   (0U)
#define	I2C_C1_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
#define	I2C_C1_WUEN_MASK   (0x2U)
#define	I2C_C1_WUEN_SHIFT   (1U)
#define	I2C_C1_WUEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
#define	I2C_C1_RSTA_MASK   (0x4U)
#define	I2C_C1_RSTA_SHIFT   (2U)
#define	I2C_C1_RSTA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
#define	I2C_C1_TXAK_MASK   (0x8U)
#define	I2C_C1_TXAK_SHIFT   (3U)
#define	I2C_C1_TXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
#define	I2C_C1_TX_MASK   (0x10U)
#define	I2C_C1_TX_SHIFT   (4U)
#define	I2C_C1_TX(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
#define	I2C_C1_MST_MASK   (0x20U)
#define	I2C_C1_MST_SHIFT   (5U)
#define	I2C_C1_MST(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
#define	I2C_C1_IICIE_MASK   (0x40U)
#define	I2C_C1_IICIE_SHIFT   (6U)
#define	I2C_C1_IICIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
#define	I2C_C1_IICEN_MASK   (0x80U)
#define	I2C_C1_IICEN_SHIFT   (7U)
#define	I2C_C1_IICEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
#define	I2C_C1_DMAEN_MASK   0x1u
#define	I2C_C1_DMAEN_SHIFT   0
#define	I2C_C1_WUEN_MASK   0x2u
#define	I2C_C1_WUEN_SHIFT   1
#define	I2C_C1_RSTA_MASK   0x4u
#define	I2C_C1_RSTA_SHIFT   2
#define	I2C_C1_TXAK_MASK   0x8u
#define	I2C_C1_TXAK_SHIFT   3
#define	I2C_C1_TX_MASK   0x10u
#define	I2C_C1_TX_SHIFT   4
#define	I2C_C1_MST_MASK   0x20u
#define	I2C_C1_MST_SHIFT   5
#define	I2C_C1_IICIE_MASK   0x40u
#define	I2C_C1_IICIE_SHIFT   6
#define	I2C_C1_IICEN_MASK   0x80u
#define	I2C_C1_IICEN_SHIFT   7
#define	I2C_C1_DMAEN_MASK   (0x1U)
#define	I2C_C1_DMAEN_SHIFT   (0U)
#define	I2C_C1_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
#define	I2C_C1_WUEN_MASK   (0x2U)
#define	I2C_C1_WUEN_SHIFT   (1U)
#define	I2C_C1_WUEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
#define	I2C_C1_RSTA_MASK   (0x4U)
#define	I2C_C1_RSTA_SHIFT   (2U)
#define	I2C_C1_RSTA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
#define	I2C_C1_TXAK_MASK   (0x8U)
#define	I2C_C1_TXAK_SHIFT   (3U)
#define	I2C_C1_TXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
#define	I2C_C1_TX_MASK   (0x10U)
#define	I2C_C1_TX_SHIFT   (4U)
#define	I2C_C1_TX(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
#define	I2C_C1_MST_MASK   (0x20U)
#define	I2C_C1_MST_SHIFT   (5U)
#define	I2C_C1_MST(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
#define	I2C_C1_IICIE_MASK   (0x40U)
#define	I2C_C1_IICIE_SHIFT   (6U)
#define	I2C_C1_IICIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
#define	I2C_C1_IICEN_MASK   (0x80U)
#define	I2C_C1_IICEN_SHIFT   (7U)
#define	I2C_C1_IICEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
#define	I2C_C1_DMAEN_MASK   (0x1U)
#define	I2C_C1_DMAEN_SHIFT   (0U)
#define	I2C_C1_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
#define	I2C_C1_WUEN_MASK   (0x2U)
#define	I2C_C1_WUEN_SHIFT   (1U)
#define	I2C_C1_WUEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
#define	I2C_C1_RSTA_MASK   (0x4U)
#define	I2C_C1_RSTA_SHIFT   (2U)
#define	I2C_C1_RSTA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
#define	I2C_C1_TXAK_MASK   (0x8U)
#define	I2C_C1_TXAK_SHIFT   (3U)
#define	I2C_C1_TXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
#define	I2C_C1_TX_MASK   (0x10U)
#define	I2C_C1_TX_SHIFT   (4U)
#define	I2C_C1_TX(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
#define	I2C_C1_MST_MASK   (0x20U)
#define	I2C_C1_MST_SHIFT   (5U)
#define	I2C_C1_MST(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
#define	I2C_C1_IICIE_MASK   (0x40U)
#define	I2C_C1_IICIE_SHIFT   (6U)
#define	I2C_C1_IICIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
#define	I2C_C1_IICEN_MASK   (0x80U)
#define	I2C_C1_IICEN_SHIFT   (7U)
#define	I2C_C1_IICEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
#define	I2C_C1_DMAEN_MASK   (0x1U)
#define	I2C_C1_DMAEN_SHIFT   (0U)
#define	I2C_C1_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
#define	I2C_C1_WUEN_MASK   (0x2U)
#define	I2C_C1_WUEN_SHIFT   (1U)
#define	I2C_C1_WUEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
#define	I2C_C1_RSTA_MASK   (0x4U)
#define	I2C_C1_RSTA_SHIFT   (2U)
#define	I2C_C1_RSTA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
#define	I2C_C1_TXAK_MASK   (0x8U)
#define	I2C_C1_TXAK_SHIFT   (3U)
#define	I2C_C1_TXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
#define	I2C_C1_TX_MASK   (0x10U)
#define	I2C_C1_TX_SHIFT   (4U)
#define	I2C_C1_TX(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
#define	I2C_C1_MST_MASK   (0x20U)
#define	I2C_C1_MST_SHIFT   (5U)
#define	I2C_C1_MST(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
#define	I2C_C1_IICIE_MASK   (0x40U)
#define	I2C_C1_IICIE_SHIFT   (6U)
#define	I2C_C1_IICIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
#define	I2C_C1_IICEN_MASK   (0x80U)
#define	I2C_C1_IICEN_SHIFT   (7U)
#define	I2C_C1_IICEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
#define	I2C_C1_DMAEN_MASK   (0x1U)
#define	I2C_C1_DMAEN_SHIFT   (0U)
#define	I2C_C1_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
#define	I2C_C1_WUEN_MASK   (0x2U)
#define	I2C_C1_WUEN_SHIFT   (1U)
#define	I2C_C1_WUEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
#define	I2C_C1_RSTA_MASK   (0x4U)
#define	I2C_C1_RSTA_SHIFT   (2U)
#define	I2C_C1_RSTA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
#define	I2C_C1_TXAK_MASK   (0x8U)
#define	I2C_C1_TXAK_SHIFT   (3U)
#define	I2C_C1_TXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
#define	I2C_C1_TX_MASK   (0x10U)
#define	I2C_C1_TX_SHIFT   (4U)
#define	I2C_C1_TX(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
#define	I2C_C1_MST_MASK   (0x20U)
#define	I2C_C1_MST_SHIFT   (5U)
#define	I2C_C1_MST(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
#define	I2C_C1_IICIE_MASK   (0x40U)
#define	I2C_C1_IICIE_SHIFT   (6U)
#define	I2C_C1_IICIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
#define	I2C_C1_IICEN_MASK   (0x80U)
#define	I2C_C1_IICEN_SHIFT   (7U)
#define	I2C_C1_IICEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)

S - I2C Status register
#define	I2C_S_RXAK_MASK   (0x1U)
#define	I2C_S_RXAK_SHIFT   (0U)
#define	I2C_S_RXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
#define	I2C_S_IICIF_MASK   (0x2U)
#define	I2C_S_IICIF_SHIFT   (1U)
#define	I2C_S_IICIF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
#define	I2C_S_SRW_MASK   (0x4U)
#define	I2C_S_SRW_SHIFT   (2U)
#define	I2C_S_SRW(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
#define	I2C_S_RAM_MASK   (0x8U)
#define	I2C_S_RAM_SHIFT   (3U)
#define	I2C_S_RAM(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
#define	I2C_S_ARBL_MASK   (0x10U)
#define	I2C_S_ARBL_SHIFT   (4U)
#define	I2C_S_ARBL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
#define	I2C_S_BUSY_MASK   (0x20U)
#define	I2C_S_BUSY_SHIFT   (5U)
#define	I2C_S_BUSY(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
#define	I2C_S_IAAS_MASK   (0x40U)
#define	I2C_S_IAAS_SHIFT   (6U)
#define	I2C_S_IAAS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
#define	I2C_S_TCF_MASK   (0x80U)
#define	I2C_S_TCF_SHIFT   (7U)
#define	I2C_S_TCF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
#define	I2C_S_RXAK_MASK   0x1u
#define	I2C_S_RXAK_SHIFT   0
#define	I2C_S_IICIF_MASK   0x2u
#define	I2C_S_IICIF_SHIFT   1
#define	I2C_S_SRW_MASK   0x4u
#define	I2C_S_SRW_SHIFT   2
#define	I2C_S_RAM_MASK   0x8u
#define	I2C_S_RAM_SHIFT   3
#define	I2C_S_ARBL_MASK   0x10u
#define	I2C_S_ARBL_SHIFT   4
#define	I2C_S_BUSY_MASK   0x20u
#define	I2C_S_BUSY_SHIFT   5
#define	I2C_S_IAAS_MASK   0x40u
#define	I2C_S_IAAS_SHIFT   6
#define	I2C_S_TCF_MASK   0x80u
#define	I2C_S_TCF_SHIFT   7
#define	I2C_S_RXAK_MASK   (0x1U)
#define	I2C_S_RXAK_SHIFT   (0U)
#define	I2C_S_RXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
#define	I2C_S_IICIF_MASK   (0x2U)
#define	I2C_S_IICIF_SHIFT   (1U)
#define	I2C_S_IICIF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
#define	I2C_S_SRW_MASK   (0x4U)
#define	I2C_S_SRW_SHIFT   (2U)
#define	I2C_S_SRW(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
#define	I2C_S_RAM_MASK   (0x8U)
#define	I2C_S_RAM_SHIFT   (3U)
#define	I2C_S_RAM(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
#define	I2C_S_ARBL_MASK   (0x10U)
#define	I2C_S_ARBL_SHIFT   (4U)
#define	I2C_S_ARBL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
#define	I2C_S_BUSY_MASK   (0x20U)
#define	I2C_S_BUSY_SHIFT   (5U)
#define	I2C_S_BUSY(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
#define	I2C_S_IAAS_MASK   (0x40U)
#define	I2C_S_IAAS_SHIFT   (6U)
#define	I2C_S_IAAS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
#define	I2C_S_TCF_MASK   (0x80U)
#define	I2C_S_TCF_SHIFT   (7U)
#define	I2C_S_TCF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
#define	I2C_S_RXAK_MASK   (0x1U)
#define	I2C_S_RXAK_SHIFT   (0U)
#define	I2C_S_RXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
#define	I2C_S_IICIF_MASK   (0x2U)
#define	I2C_S_IICIF_SHIFT   (1U)
#define	I2C_S_IICIF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
#define	I2C_S_SRW_MASK   (0x4U)
#define	I2C_S_SRW_SHIFT   (2U)
#define	I2C_S_SRW(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
#define	I2C_S_RAM_MASK   (0x8U)
#define	I2C_S_RAM_SHIFT   (3U)
#define	I2C_S_RAM(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
#define	I2C_S_ARBL_MASK   (0x10U)
#define	I2C_S_ARBL_SHIFT   (4U)
#define	I2C_S_ARBL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
#define	I2C_S_BUSY_MASK   (0x20U)
#define	I2C_S_BUSY_SHIFT   (5U)
#define	I2C_S_BUSY(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
#define	I2C_S_IAAS_MASK   (0x40U)
#define	I2C_S_IAAS_SHIFT   (6U)
#define	I2C_S_IAAS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
#define	I2C_S_TCF_MASK   (0x80U)
#define	I2C_S_TCF_SHIFT   (7U)
#define	I2C_S_TCF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
#define	I2C_S_RXAK_MASK   (0x1U)
#define	I2C_S_RXAK_SHIFT   (0U)
#define	I2C_S_RXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
#define	I2C_S_IICIF_MASK   (0x2U)
#define	I2C_S_IICIF_SHIFT   (1U)
#define	I2C_S_IICIF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
#define	I2C_S_SRW_MASK   (0x4U)
#define	I2C_S_SRW_SHIFT   (2U)
#define	I2C_S_SRW(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
#define	I2C_S_RAM_MASK   (0x8U)
#define	I2C_S_RAM_SHIFT   (3U)
#define	I2C_S_RAM(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
#define	I2C_S_ARBL_MASK   (0x10U)
#define	I2C_S_ARBL_SHIFT   (4U)
#define	I2C_S_ARBL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
#define	I2C_S_BUSY_MASK   (0x20U)
#define	I2C_S_BUSY_SHIFT   (5U)
#define	I2C_S_BUSY(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
#define	I2C_S_IAAS_MASK   (0x40U)
#define	I2C_S_IAAS_SHIFT   (6U)
#define	I2C_S_IAAS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
#define	I2C_S_TCF_MASK   (0x80U)
#define	I2C_S_TCF_SHIFT   (7U)
#define	I2C_S_TCF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
#define	I2C_S_RXAK_MASK   (0x1U)
#define	I2C_S_RXAK_SHIFT   (0U)
#define	I2C_S_RXAK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
#define	I2C_S_IICIF_MASK   (0x2U)
#define	I2C_S_IICIF_SHIFT   (1U)
#define	I2C_S_IICIF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
#define	I2C_S_SRW_MASK   (0x4U)
#define	I2C_S_SRW_SHIFT   (2U)
#define	I2C_S_SRW(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
#define	I2C_S_RAM_MASK   (0x8U)
#define	I2C_S_RAM_SHIFT   (3U)
#define	I2C_S_RAM(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
#define	I2C_S_ARBL_MASK   (0x10U)
#define	I2C_S_ARBL_SHIFT   (4U)
#define	I2C_S_ARBL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
#define	I2C_S_BUSY_MASK   (0x20U)
#define	I2C_S_BUSY_SHIFT   (5U)
#define	I2C_S_BUSY(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
#define	I2C_S_IAAS_MASK   (0x40U)
#define	I2C_S_IAAS_SHIFT   (6U)
#define	I2C_S_IAAS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
#define	I2C_S_TCF_MASK   (0x80U)
#define	I2C_S_TCF_SHIFT   (7U)
#define	I2C_S_TCF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)

D - I2C Data I/O register
#define	I2C_D_DATA_MASK   (0xFFU)
#define	I2C_D_DATA_SHIFT   (0U)
#define	I2C_D_DATA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
#define	I2C_D_DATA_MASK   0xFFu
#define	I2C_D_DATA_SHIFT   0
#define	I2C_D_DATA(x)   (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
#define	I2C_D_DATA_MASK   (0xFFU)
#define	I2C_D_DATA_SHIFT   (0U)
#define	I2C_D_DATA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
#define	I2C_D_DATA_MASK   (0xFFU)
#define	I2C_D_DATA_SHIFT   (0U)
#define	I2C_D_DATA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
#define	I2C_D_DATA_MASK   (0xFFU)
#define	I2C_D_DATA_SHIFT   (0U)
#define	I2C_D_DATA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
#define	I2C_D_DATA_MASK   (0xFFU)
#define	I2C_D_DATA_SHIFT   (0U)
#define	I2C_D_DATA(x)   (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)

C2 - I2C Control Register 2
#define	I2C_C2_AD_MASK   (0x7U)
#define	I2C_C2_AD_SHIFT   (0U)
#define	I2C_C2_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
#define	I2C_C2_RMEN_MASK   (0x8U)
#define	I2C_C2_RMEN_SHIFT   (3U)
#define	I2C_C2_RMEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
#define	I2C_C2_SBRC_MASK   (0x10U)
#define	I2C_C2_SBRC_SHIFT   (4U)
#define	I2C_C2_SBRC(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
#define	I2C_C2_HDRS_MASK   (0x20U)
#define	I2C_C2_HDRS_SHIFT   (5U)
#define	I2C_C2_HDRS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
#define	I2C_C2_ADEXT_MASK   (0x40U)
#define	I2C_C2_ADEXT_SHIFT   (6U)
#define	I2C_C2_ADEXT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
#define	I2C_C2_GCAEN_MASK   (0x80U)
#define	I2C_C2_GCAEN_SHIFT   (7U)
#define	I2C_C2_GCAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
#define	I2C_C2_AD_MASK   0x7u
#define	I2C_C2_AD_SHIFT   0
#define	I2C_C2_AD(x)   (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
#define	I2C_C2_RMEN_MASK   0x8u
#define	I2C_C2_RMEN_SHIFT   3
#define	I2C_C2_SBRC_MASK   0x10u
#define	I2C_C2_SBRC_SHIFT   4
#define	I2C_C2_HDRS_MASK   0x20u
#define	I2C_C2_HDRS_SHIFT   5
#define	I2C_C2_ADEXT_MASK   0x40u
#define	I2C_C2_ADEXT_SHIFT   6
#define	I2C_C2_GCAEN_MASK   0x80u
#define	I2C_C2_GCAEN_SHIFT   7
#define	I2C_C2_AD_MASK   (0x7U)
#define	I2C_C2_AD_SHIFT   (0U)
#define	I2C_C2_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
#define	I2C_C2_RMEN_MASK   (0x8U)
#define	I2C_C2_RMEN_SHIFT   (3U)
#define	I2C_C2_RMEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
#define	I2C_C2_SBRC_MASK   (0x10U)
#define	I2C_C2_SBRC_SHIFT   (4U)
#define	I2C_C2_SBRC(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
#define	I2C_C2_HDRS_MASK   (0x20U)
#define	I2C_C2_HDRS_SHIFT   (5U)
#define	I2C_C2_HDRS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
#define	I2C_C2_ADEXT_MASK   (0x40U)
#define	I2C_C2_ADEXT_SHIFT   (6U)
#define	I2C_C2_ADEXT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
#define	I2C_C2_GCAEN_MASK   (0x80U)
#define	I2C_C2_GCAEN_SHIFT   (7U)
#define	I2C_C2_GCAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
#define	I2C_C2_AD_MASK   (0x7U)
#define	I2C_C2_AD_SHIFT   (0U)
#define	I2C_C2_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
#define	I2C_C2_RMEN_MASK   (0x8U)
#define	I2C_C2_RMEN_SHIFT   (3U)
#define	I2C_C2_RMEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
#define	I2C_C2_SBRC_MASK   (0x10U)
#define	I2C_C2_SBRC_SHIFT   (4U)
#define	I2C_C2_SBRC(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
#define	I2C_C2_HDRS_MASK   (0x20U)
#define	I2C_C2_HDRS_SHIFT   (5U)
#define	I2C_C2_HDRS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
#define	I2C_C2_ADEXT_MASK   (0x40U)
#define	I2C_C2_ADEXT_SHIFT   (6U)
#define	I2C_C2_ADEXT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
#define	I2C_C2_GCAEN_MASK   (0x80U)
#define	I2C_C2_GCAEN_SHIFT   (7U)
#define	I2C_C2_GCAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
#define	I2C_C2_AD_MASK   (0x7U)
#define	I2C_C2_AD_SHIFT   (0U)
#define	I2C_C2_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
#define	I2C_C2_RMEN_MASK   (0x8U)
#define	I2C_C2_RMEN_SHIFT   (3U)
#define	I2C_C2_RMEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
#define	I2C_C2_SBRC_MASK   (0x10U)
#define	I2C_C2_SBRC_SHIFT   (4U)
#define	I2C_C2_SBRC(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
#define	I2C_C2_HDRS_MASK   (0x20U)
#define	I2C_C2_HDRS_SHIFT   (5U)
#define	I2C_C2_HDRS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
#define	I2C_C2_ADEXT_MASK   (0x40U)
#define	I2C_C2_ADEXT_SHIFT   (6U)
#define	I2C_C2_ADEXT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
#define	I2C_C2_GCAEN_MASK   (0x80U)
#define	I2C_C2_GCAEN_SHIFT   (7U)
#define	I2C_C2_GCAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
#define	I2C_C2_AD_MASK   (0x7U)
#define	I2C_C2_AD_SHIFT   (0U)
#define	I2C_C2_AD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
#define	I2C_C2_RMEN_MASK   (0x8U)
#define	I2C_C2_RMEN_SHIFT   (3U)
#define	I2C_C2_RMEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
#define	I2C_C2_SBRC_MASK   (0x10U)
#define	I2C_C2_SBRC_SHIFT   (4U)
#define	I2C_C2_SBRC(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
#define	I2C_C2_HDRS_MASK   (0x20U)
#define	I2C_C2_HDRS_SHIFT   (5U)
#define	I2C_C2_HDRS(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
#define	I2C_C2_ADEXT_MASK   (0x40U)
#define	I2C_C2_ADEXT_SHIFT   (6U)
#define	I2C_C2_ADEXT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
#define	I2C_C2_GCAEN_MASK   (0x80U)
#define	I2C_C2_GCAEN_SHIFT   (7U)
#define	I2C_C2_GCAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)

FLT - I2C Programmable Input Glitch Filter Register
#define	I2C_FLT_FLT_MASK   (0x1FU)
#define	I2C_FLT_FLT_SHIFT   (0U)
#define	I2C_FLT_FLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
#define	I2C_FLT_FLT_MASK   0x1Fu
#define	I2C_FLT_FLT_SHIFT   0
#define	I2C_FLT_FLT(x)   (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
#define	I2C_FLT_FLT_MASK   (0xFU)
#define	I2C_FLT_FLT_SHIFT   (0U)
#define	I2C_FLT_FLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
#define	I2C_FLT_STARTF_MASK   (0x10U)
#define	I2C_FLT_STARTF_SHIFT   (4U)
#define	I2C_FLT_STARTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
#define	I2C_FLT_SSIE_MASK   (0x20U)
#define	I2C_FLT_SSIE_SHIFT   (5U)
#define	I2C_FLT_SSIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
#define	I2C_FLT_STOPF_MASK   (0x40U)
#define	I2C_FLT_STOPF_SHIFT   (6U)
#define	I2C_FLT_STOPF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
#define	I2C_FLT_SHEN_MASK   (0x80U)
#define	I2C_FLT_SHEN_SHIFT   (7U)
#define	I2C_FLT_SHEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
#define	I2C_FLT_FLT_MASK   (0xFU)
#define	I2C_FLT_FLT_SHIFT   (0U)
#define	I2C_FLT_FLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
#define	I2C_FLT_STARTF_MASK   (0x10U)
#define	I2C_FLT_STARTF_SHIFT   (4U)
#define	I2C_FLT_STARTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
#define	I2C_FLT_SSIE_MASK   (0x20U)
#define	I2C_FLT_SSIE_SHIFT   (5U)
#define	I2C_FLT_SSIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
#define	I2C_FLT_STOPF_MASK   (0x40U)
#define	I2C_FLT_STOPF_SHIFT   (6U)
#define	I2C_FLT_STOPF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
#define	I2C_FLT_SHEN_MASK   (0x80U)
#define	I2C_FLT_SHEN_SHIFT   (7U)
#define	I2C_FLT_SHEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
#define	I2C_FLT_FLT_MASK   (0xFU)
#define	I2C_FLT_FLT_SHIFT   (0U)
#define	I2C_FLT_FLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
#define	I2C_FLT_STARTF_MASK   (0x10U)
#define	I2C_FLT_STARTF_SHIFT   (4U)
#define	I2C_FLT_STARTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
#define	I2C_FLT_SSIE_MASK   (0x20U)
#define	I2C_FLT_SSIE_SHIFT   (5U)
#define	I2C_FLT_SSIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
#define	I2C_FLT_STOPF_MASK   (0x40U)
#define	I2C_FLT_STOPF_SHIFT   (6U)
#define	I2C_FLT_STOPF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
#define	I2C_FLT_SHEN_MASK   (0x80U)
#define	I2C_FLT_SHEN_SHIFT   (7U)
#define	I2C_FLT_SHEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
#define	I2C_FLT_FLT_MASK   (0xFU)
#define	I2C_FLT_FLT_SHIFT   (0U)
#define	I2C_FLT_FLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
#define	I2C_FLT_STARTF_MASK   (0x10U)
#define	I2C_FLT_STARTF_SHIFT   (4U)
#define	I2C_FLT_STARTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
#define	I2C_FLT_SSIE_MASK   (0x20U)
#define	I2C_FLT_SSIE_SHIFT   (5U)
#define	I2C_FLT_SSIE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
#define	I2C_FLT_STOPF_MASK   (0x40U)
#define	I2C_FLT_STOPF_SHIFT   (6U)
#define	I2C_FLT_STOPF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
#define	I2C_FLT_SHEN_MASK   (0x80U)
#define	I2C_FLT_SHEN_SHIFT   (7U)
#define	I2C_FLT_SHEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)

RA - I2C Range Address register
#define	I2C_RA_RAD_MASK   (0xFEU)
#define	I2C_RA_RAD_SHIFT   (1U)
#define	I2C_RA_RAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
#define	I2C_RA_RAD_MASK   0xFEu
#define	I2C_RA_RAD_SHIFT   1
#define	I2C_RA_RAD(x)   (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
#define	I2C_RA_RAD_MASK   (0xFEU)
#define	I2C_RA_RAD_SHIFT   (1U)
#define	I2C_RA_RAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
#define	I2C_RA_RAD_MASK   (0xFEU)
#define	I2C_RA_RAD_SHIFT   (1U)
#define	I2C_RA_RAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
#define	I2C_RA_RAD_MASK   (0xFEU)
#define	I2C_RA_RAD_SHIFT   (1U)
#define	I2C_RA_RAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
#define	I2C_RA_RAD_MASK   (0xFEU)
#define	I2C_RA_RAD_SHIFT   (1U)
#define	I2C_RA_RAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)

SMB - I2C SMBus Control and Status register
#define	I2C_SMB_SHTF2IE_MASK   (0x1U)
#define	I2C_SMB_SHTF2IE_SHIFT   (0U)
#define	I2C_SMB_SHTF2IE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
#define	I2C_SMB_SHTF2_MASK   (0x2U)
#define	I2C_SMB_SHTF2_SHIFT   (1U)
#define	I2C_SMB_SHTF2(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
#define	I2C_SMB_SHTF1_MASK   (0x4U)
#define	I2C_SMB_SHTF1_SHIFT   (2U)
#define	I2C_SMB_SHTF1(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
#define	I2C_SMB_SLTF_MASK   (0x8U)
#define	I2C_SMB_SLTF_SHIFT   (3U)
#define	I2C_SMB_SLTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
#define	I2C_SMB_TCKSEL_MASK   (0x10U)
#define	I2C_SMB_TCKSEL_SHIFT   (4U)
#define	I2C_SMB_TCKSEL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
#define	I2C_SMB_SIICAEN_MASK   (0x20U)
#define	I2C_SMB_SIICAEN_SHIFT   (5U)
#define	I2C_SMB_SIICAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
#define	I2C_SMB_ALERTEN_MASK   (0x40U)
#define	I2C_SMB_ALERTEN_SHIFT   (6U)
#define	I2C_SMB_ALERTEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
#define	I2C_SMB_FACK_MASK   (0x80U)
#define	I2C_SMB_FACK_SHIFT   (7U)
#define	I2C_SMB_FACK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
#define	I2C_SMB_SHTF2IE_MASK   0x1u
#define	I2C_SMB_SHTF2IE_SHIFT   0
#define	I2C_SMB_SHTF2_MASK   0x2u
#define	I2C_SMB_SHTF2_SHIFT   1
#define	I2C_SMB_SHTF1_MASK   0x4u
#define	I2C_SMB_SHTF1_SHIFT   2
#define	I2C_SMB_SLTF_MASK   0x8u
#define	I2C_SMB_SLTF_SHIFT   3
#define	I2C_SMB_TCKSEL_MASK   0x10u
#define	I2C_SMB_TCKSEL_SHIFT   4
#define	I2C_SMB_SIICAEN_MASK   0x20u
#define	I2C_SMB_SIICAEN_SHIFT   5
#define	I2C_SMB_ALERTEN_MASK   0x40u
#define	I2C_SMB_ALERTEN_SHIFT   6
#define	I2C_SMB_FACK_MASK   0x80u
#define	I2C_SMB_FACK_SHIFT   7
#define	I2C_SMB_SHTF2IE_MASK   (0x1U)
#define	I2C_SMB_SHTF2IE_SHIFT   (0U)
#define	I2C_SMB_SHTF2IE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
#define	I2C_SMB_SHTF2_MASK   (0x2U)
#define	I2C_SMB_SHTF2_SHIFT   (1U)
#define	I2C_SMB_SHTF2(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
#define	I2C_SMB_SHTF1_MASK   (0x4U)
#define	I2C_SMB_SHTF1_SHIFT   (2U)
#define	I2C_SMB_SHTF1(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
#define	I2C_SMB_SLTF_MASK   (0x8U)
#define	I2C_SMB_SLTF_SHIFT   (3U)
#define	I2C_SMB_SLTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
#define	I2C_SMB_TCKSEL_MASK   (0x10U)
#define	I2C_SMB_TCKSEL_SHIFT   (4U)
#define	I2C_SMB_TCKSEL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
#define	I2C_SMB_SIICAEN_MASK   (0x20U)
#define	I2C_SMB_SIICAEN_SHIFT   (5U)
#define	I2C_SMB_SIICAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
#define	I2C_SMB_ALERTEN_MASK   (0x40U)
#define	I2C_SMB_ALERTEN_SHIFT   (6U)
#define	I2C_SMB_ALERTEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
#define	I2C_SMB_FACK_MASK   (0x80U)
#define	I2C_SMB_FACK_SHIFT   (7U)
#define	I2C_SMB_FACK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
#define	I2C_SMB_SHTF2IE_MASK   (0x1U)
#define	I2C_SMB_SHTF2IE_SHIFT   (0U)
#define	I2C_SMB_SHTF2IE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
#define	I2C_SMB_SHTF2_MASK   (0x2U)
#define	I2C_SMB_SHTF2_SHIFT   (1U)
#define	I2C_SMB_SHTF2(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
#define	I2C_SMB_SHTF1_MASK   (0x4U)
#define	I2C_SMB_SHTF1_SHIFT   (2U)
#define	I2C_SMB_SHTF1(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
#define	I2C_SMB_SLTF_MASK   (0x8U)
#define	I2C_SMB_SLTF_SHIFT   (3U)
#define	I2C_SMB_SLTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
#define	I2C_SMB_TCKSEL_MASK   (0x10U)
#define	I2C_SMB_TCKSEL_SHIFT   (4U)
#define	I2C_SMB_TCKSEL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
#define	I2C_SMB_SIICAEN_MASK   (0x20U)
#define	I2C_SMB_SIICAEN_SHIFT   (5U)
#define	I2C_SMB_SIICAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
#define	I2C_SMB_ALERTEN_MASK   (0x40U)
#define	I2C_SMB_ALERTEN_SHIFT   (6U)
#define	I2C_SMB_ALERTEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
#define	I2C_SMB_FACK_MASK   (0x80U)
#define	I2C_SMB_FACK_SHIFT   (7U)
#define	I2C_SMB_FACK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
#define	I2C_SMB_SHTF2IE_MASK   (0x1U)
#define	I2C_SMB_SHTF2IE_SHIFT   (0U)
#define	I2C_SMB_SHTF2IE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
#define	I2C_SMB_SHTF2_MASK   (0x2U)
#define	I2C_SMB_SHTF2_SHIFT   (1U)
#define	I2C_SMB_SHTF2(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
#define	I2C_SMB_SHTF1_MASK   (0x4U)
#define	I2C_SMB_SHTF1_SHIFT   (2U)
#define	I2C_SMB_SHTF1(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
#define	I2C_SMB_SLTF_MASK   (0x8U)
#define	I2C_SMB_SLTF_SHIFT   (3U)
#define	I2C_SMB_SLTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
#define	I2C_SMB_TCKSEL_MASK   (0x10U)
#define	I2C_SMB_TCKSEL_SHIFT   (4U)
#define	I2C_SMB_TCKSEL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
#define	I2C_SMB_SIICAEN_MASK   (0x20U)
#define	I2C_SMB_SIICAEN_SHIFT   (5U)
#define	I2C_SMB_SIICAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
#define	I2C_SMB_ALERTEN_MASK   (0x40U)
#define	I2C_SMB_ALERTEN_SHIFT   (6U)
#define	I2C_SMB_ALERTEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
#define	I2C_SMB_FACK_MASK   (0x80U)
#define	I2C_SMB_FACK_SHIFT   (7U)
#define	I2C_SMB_FACK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
#define	I2C_SMB_SHTF2IE_MASK   (0x1U)
#define	I2C_SMB_SHTF2IE_SHIFT   (0U)
#define	I2C_SMB_SHTF2IE(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
#define	I2C_SMB_SHTF2_MASK   (0x2U)
#define	I2C_SMB_SHTF2_SHIFT   (1U)
#define	I2C_SMB_SHTF2(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
#define	I2C_SMB_SHTF1_MASK   (0x4U)
#define	I2C_SMB_SHTF1_SHIFT   (2U)
#define	I2C_SMB_SHTF1(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
#define	I2C_SMB_SLTF_MASK   (0x8U)
#define	I2C_SMB_SLTF_SHIFT   (3U)
#define	I2C_SMB_SLTF(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
#define	I2C_SMB_TCKSEL_MASK   (0x10U)
#define	I2C_SMB_TCKSEL_SHIFT   (4U)
#define	I2C_SMB_TCKSEL(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
#define	I2C_SMB_SIICAEN_MASK   (0x20U)
#define	I2C_SMB_SIICAEN_SHIFT   (5U)
#define	I2C_SMB_SIICAEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
#define	I2C_SMB_ALERTEN_MASK   (0x40U)
#define	I2C_SMB_ALERTEN_SHIFT   (6U)
#define	I2C_SMB_ALERTEN(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
#define	I2C_SMB_FACK_MASK   (0x80U)
#define	I2C_SMB_FACK_SHIFT   (7U)
#define	I2C_SMB_FACK(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)

A2 - I2C Address Register 2
#define	I2C_A2_SAD_MASK   (0xFEU)
#define	I2C_A2_SAD_SHIFT   (1U)
#define	I2C_A2_SAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
#define	I2C_A2_SAD_MASK   0xFEu
#define	I2C_A2_SAD_SHIFT   1
#define	I2C_A2_SAD(x)   (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
#define	I2C_A2_SAD_MASK   (0xFEU)
#define	I2C_A2_SAD_SHIFT   (1U)
#define	I2C_A2_SAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
#define	I2C_A2_SAD_MASK   (0xFEU)
#define	I2C_A2_SAD_SHIFT   (1U)
#define	I2C_A2_SAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
#define	I2C_A2_SAD_MASK   (0xFEU)
#define	I2C_A2_SAD_SHIFT   (1U)
#define	I2C_A2_SAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
#define	I2C_A2_SAD_MASK   (0xFEU)
#define	I2C_A2_SAD_SHIFT   (1U)
#define	I2C_A2_SAD(x)   (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)

SLTH - I2C SCL Low Timeout Register High
#define	I2C_SLTH_SSLT_MASK   (0xFFU)
#define	I2C_SLTH_SSLT_SHIFT   (0U)
#define	I2C_SLTH_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
#define	I2C_SLTH_SSLT_MASK   0xFFu
#define	I2C_SLTH_SSLT_SHIFT   0
#define	I2C_SLTH_SSLT(x)   (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
#define	I2C_SLTH_SSLT_MASK   (0xFFU)
#define	I2C_SLTH_SSLT_SHIFT   (0U)
#define	I2C_SLTH_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
#define	I2C_SLTH_SSLT_MASK   (0xFFU)
#define	I2C_SLTH_SSLT_SHIFT   (0U)
#define	I2C_SLTH_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
#define	I2C_SLTH_SSLT_MASK   (0xFFU)
#define	I2C_SLTH_SSLT_SHIFT   (0U)
#define	I2C_SLTH_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
#define	I2C_SLTH_SSLT_MASK   (0xFFU)
#define	I2C_SLTH_SSLT_SHIFT   (0U)
#define	I2C_SLTH_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)

SLTL - I2C SCL Low Timeout Register Low
#define	I2C_SLTL_SSLT_MASK   (0xFFU)
#define	I2C_SLTL_SSLT_SHIFT   (0U)
#define	I2C_SLTL_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
#define	I2C_SLTL_SSLT_MASK   0xFFu
#define	I2C_SLTL_SSLT_SHIFT   0
#define	I2C_SLTL_SSLT(x)   (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
#define	I2C_SLTL_SSLT_MASK   (0xFFU)
#define	I2C_SLTL_SSLT_SHIFT   (0U)
#define	I2C_SLTL_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
#define	I2C_SLTL_SSLT_MASK   (0xFFU)
#define	I2C_SLTL_SSLT_SHIFT   (0U)
#define	I2C_SLTL_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
#define	I2C_SLTL_SSLT_MASK   (0xFFU)
#define	I2C_SLTL_SSLT_SHIFT   (0U)
#define	I2C_SLTL_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
#define	I2C_SLTL_SSLT_MASK   (0xFFU)
#define	I2C_SLTL_SSLT_SHIFT   (0U)
#define	I2C_SLTL_SSLT(x)   (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)

Macro Definition Documentation

I2C0

#define I2C0   ((I2C_Type *)I2C0_BASE)

Peripheral I2C0 base pointer

I2C0_BASE

#define I2C0_BASE   (0x40066000u)

Peripheral I2C0 base address

I2C1

#define I2C1   ((I2C_Type *)I2C1_BASE)

Peripheral I2C1 base pointer

I2C1_BASE

#define I2C1_BASE   (0x40067000u)

Peripheral I2C1 base address

I2C_BASE_ADDRS

#define I2C_BASE_ADDRS   { I2C0_BASE, I2C1_BASE }

Array initializer of I2C peripheral base addresses

I2C_BASE_PTRS

#define I2C_BASE_PTRS   { I2C0, I2C1 }

Array initializer of I2C peripheral base pointers

I2C_C1_DMAEN [1/5]

#define I2C_C1_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)

DMAEN - DMA Enable 0b0..All DMA signalling disabled. 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.

I2C_C1_DMAEN [2/5]

#define I2C_C1_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)

DMAEN - DMA Enable 0b0..All DMA signalling disabled. 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.

I2C_C1_DMAEN [3/5]

#define I2C_C1_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)

DMAEN - DMA Enable 0b0..All DMA signalling disabled. 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.

I2C_C1_DMAEN [4/5]

#define I2C_C1_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)

DMAEN - DMA Enable 0b0..All DMA signalling disabled. 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.

I2C_C1_DMAEN [5/5]

#define I2C_C1_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)

DMAEN - DMA Enable 0b0..All DMA signalling disabled. 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.

I2C_C1_IICEN [1/5]

#define I2C_C1_IICEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)

IICEN - I2C Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICEN [2/5]

#define I2C_C1_IICEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)

IICEN - I2C Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICEN [3/5]

#define I2C_C1_IICEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)

IICEN - I2C Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICEN [4/5]

#define I2C_C1_IICEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)

IICEN - I2C Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICEN [5/5]

#define I2C_C1_IICEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)

IICEN - I2C Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICIE [1/5]

#define I2C_C1_IICIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)

IICIE - I2C Interrupt Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICIE [2/5]

#define I2C_C1_IICIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)

IICIE - I2C Interrupt Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICIE [3/5]

#define I2C_C1_IICIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)

IICIE - I2C Interrupt Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICIE [4/5]

#define I2C_C1_IICIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)

IICIE - I2C Interrupt Enable 0b0..Disabled 0b1..Enabled

I2C_C1_IICIE [5/5]

#define I2C_C1_IICIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)

IICIE - I2C Interrupt Enable 0b0..Disabled 0b1..Enabled

I2C_C1_MST [1/5]

#define I2C_C1_MST

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)

MST - Master Mode Select 0b0..Slave mode 0b1..Master mode

I2C_C1_MST [2/5]

#define I2C_C1_MST

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)

MST - Master Mode Select 0b0..Slave mode 0b1..Master mode

I2C_C1_MST [3/5]

#define I2C_C1_MST

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)

MST - Master Mode Select 0b0..Slave mode 0b1..Master mode

I2C_C1_MST [4/5]

#define I2C_C1_MST

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)

MST - Master Mode Select 0b0..Slave mode 0b1..Master mode

I2C_C1_MST [5/5]

#define I2C_C1_MST

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)

MST - Master Mode Select 0b0..Slave mode 0b1..Master mode

I2C_C1_TX [1/5]

#define I2C_C1_TX

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)

TX - Transmit Mode Select 0b0..Receive 0b1..Transmit

I2C_C1_TX [2/5]

#define I2C_C1_TX

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)

TX - Transmit Mode Select 0b0..Receive 0b1..Transmit

I2C_C1_TX [3/5]

#define I2C_C1_TX

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)

TX - Transmit Mode Select 0b0..Receive 0b1..Transmit

I2C_C1_TX [4/5]

#define I2C_C1_TX

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)

TX - Transmit Mode Select 0b0..Receive 0b1..Transmit

I2C_C1_TX [5/5]

#define I2C_C1_TX

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)

TX - Transmit Mode Select 0b0..Receive 0b1..Transmit

I2C_C1_TXAK [1/5]

#define I2C_C1_TXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)

TXAK - Transmit Acknowledge Enable 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).

I2C_C1_TXAK [2/5]

#define I2C_C1_TXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)

TXAK - Transmit Acknowledge Enable 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).

I2C_C1_TXAK [3/5]

#define I2C_C1_TXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)

TXAK - Transmit Acknowledge Enable 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).

I2C_C1_TXAK [4/5]

#define I2C_C1_TXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)

TXAK - Transmit Acknowledge Enable 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).

I2C_C1_TXAK [5/5]

#define I2C_C1_TXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)

TXAK - Transmit Acknowledge Enable 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).

I2C_C1_WUEN [1/5]

#define I2C_C1_WUEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)

WUEN - Wakeup Enable 0b0..Normal operation. No interrupt generated when address matching in low power mode. 0b1..Enables the wakeup function in low power mode.

I2C_C1_WUEN [2/5]

#define I2C_C1_WUEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)

WUEN - Wakeup Enable 0b0..Normal operation. No interrupt generated when address matching in low power mode. 0b1..Enables the wakeup function in low power mode.

I2C_C1_WUEN [3/5]

#define I2C_C1_WUEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)

WUEN - Wakeup Enable 0b0..Normal operation. No interrupt generated when address matching in low power mode. 0b1..Enables the wakeup function in low power mode.

I2C_C1_WUEN [4/5]

#define I2C_C1_WUEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)

WUEN - Wakeup Enable 0b0..Normal operation. No interrupt generated when address matching in low power mode. 0b1..Enables the wakeup function in low power mode.

I2C_C1_WUEN [5/5]

#define I2C_C1_WUEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)

WUEN - Wakeup Enable 0b0..Normal operation. No interrupt generated when address matching in low power mode. 0b1..Enables the wakeup function in low power mode.

I2C_C2_ADEXT [1/5]

#define I2C_C2_ADEXT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)

ADEXT - Address Extension 0b0..7-bit address scheme 0b1..10-bit address scheme

I2C_C2_ADEXT [2/5]

#define I2C_C2_ADEXT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)

ADEXT - Address Extension 0b0..7-bit address scheme 0b1..10-bit address scheme

I2C_C2_ADEXT [3/5]

#define I2C_C2_ADEXT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)

ADEXT - Address Extension 0b0..7-bit address scheme 0b1..10-bit address scheme

I2C_C2_ADEXT [4/5]

#define I2C_C2_ADEXT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)

ADEXT - Address Extension 0b0..7-bit address scheme 0b1..10-bit address scheme

I2C_C2_ADEXT [5/5]

#define I2C_C2_ADEXT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)

ADEXT - Address Extension 0b0..7-bit address scheme 0b1..10-bit address scheme

I2C_C2_GCAEN [1/5]

#define I2C_C2_GCAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)

GCAEN - General Call Address Enable 0b0..Disabled 0b1..Enabled

I2C_C2_GCAEN [2/5]

#define I2C_C2_GCAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)

GCAEN - General Call Address Enable 0b0..Disabled 0b1..Enabled

I2C_C2_GCAEN [3/5]

#define I2C_C2_GCAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)

GCAEN - General Call Address Enable 0b0..Disabled 0b1..Enabled

I2C_C2_GCAEN [4/5]

#define I2C_C2_GCAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)

GCAEN - General Call Address Enable 0b0..Disabled 0b1..Enabled

I2C_C2_GCAEN [5/5]

#define I2C_C2_GCAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)

GCAEN - General Call Address Enable 0b0..Disabled 0b1..Enabled

I2C_C2_HDRS [1/5]

#define I2C_C2_HDRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)

HDRS - High Drive Select 0b0..Normal drive mode 0b1..High drive mode

I2C_C2_HDRS [2/5]

#define I2C_C2_HDRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)

HDRS - High Drive Select 0b0..Normal drive mode 0b1..High drive mode

I2C_C2_HDRS [3/5]

#define I2C_C2_HDRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)

HDRS - High Drive Select 0b0..Normal drive mode 0b1..High drive mode

I2C_C2_HDRS [4/5]

#define I2C_C2_HDRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)

HDRS - High Drive Select 0b0..Normal drive mode 0b1..High drive mode

I2C_C2_HDRS [5/5]

#define I2C_C2_HDRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)

HDRS - High Drive Select 0b0..Normal drive mode 0b1..High drive mode

I2C_C2_RMEN [1/5]

#define I2C_C2_RMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)

RMEN - Range Address Matching Enable 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.

I2C_C2_RMEN [2/5]

#define I2C_C2_RMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)

RMEN - Range Address Matching Enable 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.

I2C_C2_RMEN [3/5]

#define I2C_C2_RMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)

RMEN - Range Address Matching Enable 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.

I2C_C2_RMEN [4/5]

#define I2C_C2_RMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)

RMEN - Range Address Matching Enable 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.

I2C_C2_RMEN [5/5]

#define I2C_C2_RMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)

RMEN - Range Address Matching Enable 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.

I2C_C2_SBRC [1/5]

#define I2C_C2_SBRC

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)

SBRC - Slave Baud Rate Control 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 0b1..Slave baud rate is independent of the master baud rate

I2C_C2_SBRC [2/5]

#define I2C_C2_SBRC

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)

SBRC - Slave Baud Rate Control 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 0b1..Slave baud rate is independent of the master baud rate

I2C_C2_SBRC [3/5]

#define I2C_C2_SBRC

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)

SBRC - Slave Baud Rate Control 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 0b1..Slave baud rate is independent of the master baud rate

I2C_C2_SBRC [4/5]

#define I2C_C2_SBRC

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)

SBRC - Slave Baud Rate Control 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 0b1..Slave baud rate is independent of the master baud rate

I2C_C2_SBRC [5/5]

#define I2C_C2_SBRC

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)

SBRC - Slave Baud Rate Control 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 0b1..Slave baud rate is independent of the master baud rate

I2C_F_MULT [1/6]

#define I2C_F_MULT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)

MULT - Multiplier Factor 0b00..mul = 1 0b01..mul = 2 0b10..mul = 4 0b11..Reserved

I2C_F_MULT [2/6]

#define I2C_F_MULT

(

x

)

(((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)

MULT - Multiplier Factor 0b00..mul = 1 0b01..mul = 2 0b10..mul = 4 0b11..Reserved

I2C_F_MULT [3/6]

#define I2C_F_MULT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)

MULT - Multiplier Factor 0b00..mul = 1 0b01..mul = 2 0b10..mul = 4 0b11..Reserved

I2C_F_MULT [4/6]

#define I2C_F_MULT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)

MULT - Multiplier Factor 0b00..mul = 1 0b01..mul = 2 0b10..mul = 4 0b11..Reserved

I2C_F_MULT [5/6]

#define I2C_F_MULT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)

MULT - Multiplier Factor 0b00..mul = 1 0b01..mul = 2 0b10..mul = 4 0b11..Reserved

I2C_F_MULT [6/6]

#define I2C_F_MULT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)

MULT - Multiplier Factor 0b00..mul = 1 0b01..mul = 2 0b10..mul = 4 0b11..Reserved

I2C_FLT_FLT [1/6]

#define I2C_FLT_FLT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)

FLT - I2C Programmable Filter Factor 0b0000..No filter/bypass

I2C_FLT_FLT [2/6]

#define I2C_FLT_FLT

(

x

)

(((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)

FLT - I2C Programmable Filter Factor 0b0000..No filter/bypass

I2C_FLT_FLT [3/6]

#define I2C_FLT_FLT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)

FLT - I2C Programmable Filter Factor 0b0000..No filter/bypass

I2C_FLT_FLT [4/6]

#define I2C_FLT_FLT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)

FLT - I2C Programmable Filter Factor 0b0000..No filter/bypass

I2C_FLT_FLT [5/6]

#define I2C_FLT_FLT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)

FLT - I2C Programmable Filter Factor 0b0000..No filter/bypass

I2C_FLT_FLT [6/6]

#define I2C_FLT_FLT

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)

FLT - I2C Programmable Filter Factor 0b0000..No filter/bypass

I2C_FLT_SHEN [1/4]

#define I2C_FLT_SHEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)

SHEN - Stop Hold Enable 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 0b1..Stop holdoff is enabled.

I2C_FLT_SHEN [2/4]

#define I2C_FLT_SHEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)

SHEN - Stop Hold Enable 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 0b1..Stop holdoff is enabled.

I2C_FLT_SHEN [3/4]

#define I2C_FLT_SHEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)

SHEN - Stop Hold Enable 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 0b1..Stop holdoff is enabled.

I2C_FLT_SHEN [4/4]

#define I2C_FLT_SHEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)

SHEN - Stop Hold Enable 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 0b1..Stop holdoff is enabled.

I2C_FLT_SSIE [1/4]

#define I2C_FLT_SSIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)

SSIE - I2C Bus Stop or Start Interrupt Enable 0b0..Stop or start detection interrupt is disabled 0b1..Stop or start detection interrupt is enabled

I2C_FLT_SSIE [2/4]

#define I2C_FLT_SSIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)

SSIE - I2C Bus Stop or Start Interrupt Enable 0b0..Stop or start detection interrupt is disabled 0b1..Stop or start detection interrupt is enabled

I2C_FLT_SSIE [3/4]

#define I2C_FLT_SSIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)

SSIE - I2C Bus Stop or Start Interrupt Enable 0b0..Stop or start detection interrupt is disabled 0b1..Stop or start detection interrupt is enabled

I2C_FLT_SSIE [4/4]

#define I2C_FLT_SSIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)

SSIE - I2C Bus Stop or Start Interrupt Enable 0b0..Stop or start detection interrupt is disabled 0b1..Stop or start detection interrupt is enabled

I2C_FLT_STARTF [1/4]

#define I2C_FLT_STARTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)

STARTF - I2C Bus Start Detect Flag 0b0..No start happens on I2C bus 0b1..Start detected on I2C bus

I2C_FLT_STARTF [2/4]

#define I2C_FLT_STARTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)

STARTF - I2C Bus Start Detect Flag 0b0..No start happens on I2C bus 0b1..Start detected on I2C bus

I2C_FLT_STARTF [3/4]

#define I2C_FLT_STARTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)

STARTF - I2C Bus Start Detect Flag 0b0..No start happens on I2C bus 0b1..Start detected on I2C bus

I2C_FLT_STARTF [4/4]

#define I2C_FLT_STARTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)

STARTF - I2C Bus Start Detect Flag 0b0..No start happens on I2C bus 0b1..Start detected on I2C bus

I2C_FLT_STOPF [1/4]

#define I2C_FLT_STOPF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)

STOPF - I2C Bus Stop Detect Flag 0b0..No stop happens on I2C bus 0b1..Stop detected on I2C bus

I2C_FLT_STOPF [2/4]

#define I2C_FLT_STOPF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)

STOPF - I2C Bus Stop Detect Flag 0b0..No stop happens on I2C bus 0b1..Stop detected on I2C bus

I2C_FLT_STOPF [3/4]

#define I2C_FLT_STOPF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)

STOPF - I2C Bus Stop Detect Flag 0b0..No stop happens on I2C bus 0b1..Stop detected on I2C bus

I2C_FLT_STOPF [4/4]

#define I2C_FLT_STOPF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)

STOPF - I2C Bus Stop Detect Flag 0b0..No stop happens on I2C bus 0b1..Stop detected on I2C bus

I2C_IRQS

#define I2C_IRQS   { I2C0_IRQn, I2C1_IRQn }

Interrupt vectors for the I2C peripheral type

I2C_S_ARBL [1/5]

#define I2C_S_ARBL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)

ARBL - Arbitration Lost 0b0..Standard bus operation. 0b1..Loss of arbitration.

I2C_S_ARBL [2/5]

#define I2C_S_ARBL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)

ARBL - Arbitration Lost 0b0..Standard bus operation. 0b1..Loss of arbitration.

I2C_S_ARBL [3/5]

#define I2C_S_ARBL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)

ARBL - Arbitration Lost 0b0..Standard bus operation. 0b1..Loss of arbitration.

I2C_S_ARBL [4/5]

#define I2C_S_ARBL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)

ARBL - Arbitration Lost 0b0..Standard bus operation. 0b1..Loss of arbitration.

I2C_S_ARBL [5/5]

#define I2C_S_ARBL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)

ARBL - Arbitration Lost 0b0..Standard bus operation. 0b1..Loss of arbitration.

I2C_S_BUSY [1/5]

#define I2C_S_BUSY

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)

BUSY - Bus Busy 0b0..Bus is idle 0b1..Bus is busy

I2C_S_BUSY [2/5]

#define I2C_S_BUSY

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)

BUSY - Bus Busy 0b0..Bus is idle 0b1..Bus is busy

I2C_S_BUSY [3/5]

#define I2C_S_BUSY

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)

BUSY - Bus Busy 0b0..Bus is idle 0b1..Bus is busy

I2C_S_BUSY [4/5]

#define I2C_S_BUSY

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)

BUSY - Bus Busy 0b0..Bus is idle 0b1..Bus is busy

I2C_S_BUSY [5/5]

#define I2C_S_BUSY

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)

BUSY - Bus Busy 0b0..Bus is idle 0b1..Bus is busy

I2C_S_IAAS [1/5]

#define I2C_S_IAAS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)

IAAS - Addressed As A Slave 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_IAAS [2/5]

#define I2C_S_IAAS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)

IAAS - Addressed As A Slave 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_IAAS [3/5]

#define I2C_S_IAAS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)

IAAS - Addressed As A Slave 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_IAAS [4/5]

#define I2C_S_IAAS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)

IAAS - Addressed As A Slave 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_IAAS [5/5]

#define I2C_S_IAAS

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)

IAAS - Addressed As A Slave 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_IICIF [1/5]

#define I2C_S_IICIF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)

IICIF - Interrupt Flag 0b0..No interrupt pending 0b1..Interrupt pending

I2C_S_IICIF [2/5]

#define I2C_S_IICIF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)

IICIF - Interrupt Flag 0b0..No interrupt pending 0b1..Interrupt pending

I2C_S_IICIF [3/5]

#define I2C_S_IICIF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)

IICIF - Interrupt Flag 0b0..No interrupt pending 0b1..Interrupt pending

I2C_S_IICIF [4/5]

#define I2C_S_IICIF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)

IICIF - Interrupt Flag 0b0..No interrupt pending 0b1..Interrupt pending

I2C_S_IICIF [5/5]

#define I2C_S_IICIF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)

IICIF - Interrupt Flag 0b0..No interrupt pending 0b1..Interrupt pending

I2C_S_RAM [1/5]

#define I2C_S_RAM

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)

RAM - Range Address Match 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_RAM [2/5]

#define I2C_S_RAM

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)

RAM - Range Address Match 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_RAM [3/5]

#define I2C_S_RAM

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)

RAM - Range Address Match 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_RAM [4/5]

#define I2C_S_RAM

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)

RAM - Range Address Match 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_RAM [5/5]

#define I2C_S_RAM

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)

RAM - Range Address Match 0b0..Not addressed 0b1..Addressed as a slave

I2C_S_RXAK [1/5]

#define I2C_S_RXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)

RXAK - Receive Acknowledge 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 0b1..No acknowledge signal detected

I2C_S_RXAK [2/5]

#define I2C_S_RXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)

RXAK - Receive Acknowledge 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 0b1..No acknowledge signal detected

I2C_S_RXAK [3/5]

#define I2C_S_RXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)

RXAK - Receive Acknowledge 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 0b1..No acknowledge signal detected

I2C_S_RXAK [4/5]

#define I2C_S_RXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)

RXAK - Receive Acknowledge 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 0b1..No acknowledge signal detected

I2C_S_RXAK [5/5]

#define I2C_S_RXAK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)

RXAK - Receive Acknowledge 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 0b1..No acknowledge signal detected

I2C_S_SRW [1/5]

#define I2C_S_SRW

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)

SRW - Slave Read/Write 0b0..Slave receive, master writing to slave 0b1..Slave transmit, master reading from slave

I2C_S_SRW [2/5]

#define I2C_S_SRW

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)

SRW - Slave Read/Write 0b0..Slave receive, master writing to slave 0b1..Slave transmit, master reading from slave

I2C_S_SRW [3/5]

#define I2C_S_SRW

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)

SRW - Slave Read/Write 0b0..Slave receive, master writing to slave 0b1..Slave transmit, master reading from slave

I2C_S_SRW [4/5]

#define I2C_S_SRW

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)

SRW - Slave Read/Write 0b0..Slave receive, master writing to slave 0b1..Slave transmit, master reading from slave

I2C_S_SRW [5/5]

#define I2C_S_SRW

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)

SRW - Slave Read/Write 0b0..Slave receive, master writing to slave 0b1..Slave transmit, master reading from slave

I2C_S_TCF [1/5]

#define I2C_S_TCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer in progress 0b1..Transfer complete

I2C_S_TCF [2/5]

#define I2C_S_TCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer in progress 0b1..Transfer complete

I2C_S_TCF [3/5]

#define I2C_S_TCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer in progress 0b1..Transfer complete

I2C_S_TCF [4/5]

#define I2C_S_TCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer in progress 0b1..Transfer complete

I2C_S_TCF [5/5]

#define I2C_S_TCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer in progress 0b1..Transfer complete

I2C_SMB_ALERTEN [1/5]

#define I2C_SMB_ALERTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)

ALERTEN - SMBus Alert Response Address Enable 0b0..SMBus alert response address matching is disabled 0b1..SMBus alert response address matching is enabled

I2C_SMB_ALERTEN [2/5]

#define I2C_SMB_ALERTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)

ALERTEN - SMBus Alert Response Address Enable 0b0..SMBus alert response address matching is disabled 0b1..SMBus alert response address matching is enabled

I2C_SMB_ALERTEN [3/5]

#define I2C_SMB_ALERTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)

ALERTEN - SMBus Alert Response Address Enable 0b0..SMBus alert response address matching is disabled 0b1..SMBus alert response address matching is enabled

I2C_SMB_ALERTEN [4/5]

#define I2C_SMB_ALERTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)

ALERTEN - SMBus Alert Response Address Enable 0b0..SMBus alert response address matching is disabled 0b1..SMBus alert response address matching is enabled

I2C_SMB_ALERTEN [5/5]

#define I2C_SMB_ALERTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)

ALERTEN - SMBus Alert Response Address Enable 0b0..SMBus alert response address matching is disabled 0b1..SMBus alert response address matching is enabled

I2C_SMB_FACK [1/5]

#define I2C_SMB_FACK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)

FACK - Fast NACK/ACK Enable 0b0..An ACK or NACK is sent on the following receiving data byte 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

I2C_SMB_FACK [2/5]

#define I2C_SMB_FACK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)

FACK - Fast NACK/ACK Enable 0b0..An ACK or NACK is sent on the following receiving data byte 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

I2C_SMB_FACK [3/5]

#define I2C_SMB_FACK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)

FACK - Fast NACK/ACK Enable 0b0..An ACK or NACK is sent on the following receiving data byte 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

I2C_SMB_FACK [4/5]

#define I2C_SMB_FACK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)

FACK - Fast NACK/ACK Enable 0b0..An ACK or NACK is sent on the following receiving data byte 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

I2C_SMB_FACK [5/5]

#define I2C_SMB_FACK

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)

FACK - Fast NACK/ACK Enable 0b0..An ACK or NACK is sent on the following receiving data byte 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

I2C_SMB_SHTF1 [1/5]

#define I2C_SMB_SHTF1

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)

SHTF1 - SCL High Timeout Flag 1 0b0..No SCL high and SDA high timeout occurs 0b1..SCL high and SDA high timeout occurs

I2C_SMB_SHTF1 [2/5]

#define I2C_SMB_SHTF1

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)

SHTF1 - SCL High Timeout Flag 1 0b0..No SCL high and SDA high timeout occurs 0b1..SCL high and SDA high timeout occurs

I2C_SMB_SHTF1 [3/5]

#define I2C_SMB_SHTF1

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)

SHTF1 - SCL High Timeout Flag 1 0b0..No SCL high and SDA high timeout occurs 0b1..SCL high and SDA high timeout occurs

I2C_SMB_SHTF1 [4/5]

#define I2C_SMB_SHTF1

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)

SHTF1 - SCL High Timeout Flag 1 0b0..No SCL high and SDA high timeout occurs 0b1..SCL high and SDA high timeout occurs

I2C_SMB_SHTF1 [5/5]

#define I2C_SMB_SHTF1

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)

SHTF1 - SCL High Timeout Flag 1 0b0..No SCL high and SDA high timeout occurs 0b1..SCL high and SDA high timeout occurs

I2C_SMB_SHTF2 [1/5]

#define I2C_SMB_SHTF2

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)

SHTF2 - SCL High Timeout Flag 2 0b0..No SCL high and SDA low timeout occurs 0b1..SCL high and SDA low timeout occurs

I2C_SMB_SHTF2 [2/5]

#define I2C_SMB_SHTF2

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)

SHTF2 - SCL High Timeout Flag 2 0b0..No SCL high and SDA low timeout occurs 0b1..SCL high and SDA low timeout occurs

I2C_SMB_SHTF2 [3/5]

#define I2C_SMB_SHTF2

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)

SHTF2 - SCL High Timeout Flag 2 0b0..No SCL high and SDA low timeout occurs 0b1..SCL high and SDA low timeout occurs

I2C_SMB_SHTF2 [4/5]

#define I2C_SMB_SHTF2

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)

SHTF2 - SCL High Timeout Flag 2 0b0..No SCL high and SDA low timeout occurs 0b1..SCL high and SDA low timeout occurs

I2C_SMB_SHTF2 [5/5]

#define I2C_SMB_SHTF2

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)

SHTF2 - SCL High Timeout Flag 2 0b0..No SCL high and SDA low timeout occurs 0b1..SCL high and SDA low timeout occurs

I2C_SMB_SHTF2IE [1/5]

#define I2C_SMB_SHTF2IE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)

SHTF2IE - SHTF2 Interrupt Enable 0b0..SHTF2 interrupt is disabled 0b1..SHTF2 interrupt is enabled

I2C_SMB_SHTF2IE [2/5]

#define I2C_SMB_SHTF2IE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)

SHTF2IE - SHTF2 Interrupt Enable 0b0..SHTF2 interrupt is disabled 0b1..SHTF2 interrupt is enabled

I2C_SMB_SHTF2IE [3/5]

#define I2C_SMB_SHTF2IE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)

SHTF2IE - SHTF2 Interrupt Enable 0b0..SHTF2 interrupt is disabled 0b1..SHTF2 interrupt is enabled

I2C_SMB_SHTF2IE [4/5]

#define I2C_SMB_SHTF2IE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)

SHTF2IE - SHTF2 Interrupt Enable 0b0..SHTF2 interrupt is disabled 0b1..SHTF2 interrupt is enabled

I2C_SMB_SHTF2IE [5/5]

#define I2C_SMB_SHTF2IE

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)

SHTF2IE - SHTF2 Interrupt Enable 0b0..SHTF2 interrupt is disabled 0b1..SHTF2 interrupt is enabled

I2C_SMB_SIICAEN [1/5]

#define I2C_SMB_SIICAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)

SIICAEN - Second I2C Address Enable 0b0..I2C address register 2 matching is disabled 0b1..I2C address register 2 matching is enabled

I2C_SMB_SIICAEN [2/5]

#define I2C_SMB_SIICAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)

SIICAEN - Second I2C Address Enable 0b0..I2C address register 2 matching is disabled 0b1..I2C address register 2 matching is enabled

I2C_SMB_SIICAEN [3/5]

#define I2C_SMB_SIICAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)

SIICAEN - Second I2C Address Enable 0b0..I2C address register 2 matching is disabled 0b1..I2C address register 2 matching is enabled

I2C_SMB_SIICAEN [4/5]

#define I2C_SMB_SIICAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)

SIICAEN - Second I2C Address Enable 0b0..I2C address register 2 matching is disabled 0b1..I2C address register 2 matching is enabled

I2C_SMB_SIICAEN [5/5]

#define I2C_SMB_SIICAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)

SIICAEN - Second I2C Address Enable 0b0..I2C address register 2 matching is disabled 0b1..I2C address register 2 matching is enabled

I2C_SMB_SLTF [1/5]

#define I2C_SMB_SLTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)

SLTF - SCL Low Timeout Flag 0b0..No low timeout occurs 0b1..Low timeout occurs

I2C_SMB_SLTF [2/5]

#define I2C_SMB_SLTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)

SLTF - SCL Low Timeout Flag 0b0..No low timeout occurs 0b1..Low timeout occurs

I2C_SMB_SLTF [3/5]

#define I2C_SMB_SLTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)

SLTF - SCL Low Timeout Flag 0b0..No low timeout occurs 0b1..Low timeout occurs

I2C_SMB_SLTF [4/5]

#define I2C_SMB_SLTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)

SLTF - SCL Low Timeout Flag 0b0..No low timeout occurs 0b1..Low timeout occurs

I2C_SMB_SLTF [5/5]

#define I2C_SMB_SLTF

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)

SLTF - SCL Low Timeout Flag 0b0..No low timeout occurs 0b1..Low timeout occurs

I2C_SMB_TCKSEL [1/5]

#define I2C_SMB_TCKSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)

TCKSEL - Timeout Counter Clock Select 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 0b1..Timeout counter counts at the frequency of the I2C module clock

I2C_SMB_TCKSEL [2/5]

#define I2C_SMB_TCKSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)

TCKSEL - Timeout Counter Clock Select 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 0b1..Timeout counter counts at the frequency of the I2C module clock

I2C_SMB_TCKSEL [3/5]

#define I2C_SMB_TCKSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)

TCKSEL - Timeout Counter Clock Select 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 0b1..Timeout counter counts at the frequency of the I2C module clock

I2C_SMB_TCKSEL [4/5]

#define I2C_SMB_TCKSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)

TCKSEL - Timeout Counter Clock Select 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 0b1..Timeout counter counts at the frequency of the I2C module clock

I2C_SMB_TCKSEL [5/5]

#define I2C_SMB_TCKSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)

TCKSEL - Timeout Counter Clock Select 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 0b1..Timeout counter counts at the frequency of the I2C module clock