I2S Register Masks

Macros
#define	I2S0_BASE   (0x4002F000u)
#define	I2S0   ((I2S_Type *)I2S0_BASE)
#define	I2S_BASE_ADDRS   { I2S0_BASE }
#define	I2S_BASE_PTRS   { I2S0 }
#define	I2S_RX_IRQS   { I2S0_Rx_IRQn }
#define	I2S_TX_IRQS   { I2S0_Tx_IRQn }
#define	I2S_TX0_TX0_MASK   0xFFFFFFFFu
#define	I2S_TX0_TX0_SHIFT   0
#define	I2S_TX0_TX0(x)   (((uint32_t)(((uint32_t)(x))<<I2S_TX0_TX0_SHIFT))&I2S_TX0_TX0_MASK)
#define	I2S_TX1_TX1_MASK   0xFFFFFFFFu
#define	I2S_TX1_TX1_SHIFT   0
#define	I2S_TX1_TX1(x)   (((uint32_t)(((uint32_t)(x))<<I2S_TX1_TX1_SHIFT))&I2S_TX1_TX1_MASK)
#define	I2S_RX0_RX0_MASK   0xFFFFFFFFu
#define	I2S_RX0_RX0_SHIFT   0
#define	I2S_RX0_RX0(x)   (((uint32_t)(((uint32_t)(x))<<I2S_RX0_RX0_SHIFT))&I2S_RX0_RX0_MASK)
#define	I2S_RX1_RX1_MASK   0xFFFFFFFFu
#define	I2S_RX1_RX1_SHIFT   0
#define	I2S_RX1_RX1(x)   (((uint32_t)(((uint32_t)(x))<<I2S_RX1_RX1_SHIFT))&I2S_RX1_RX1_MASK)
#define	I2S_CR_SSIEN_MASK   0x1u
#define	I2S_CR_SSIEN_SHIFT   0
#define	I2S_CR_TE_MASK   0x2u
#define	I2S_CR_TE_SHIFT   1
#define	I2S_CR_RE_MASK   0x4u
#define	I2S_CR_RE_SHIFT   2
#define	I2S_CR_NET_MASK   0x8u
#define	I2S_CR_NET_SHIFT   3
#define	I2S_CR_SYN_MASK   0x10u
#define	I2S_CR_SYN_SHIFT   4
#define	I2S_CR_I2SMODE_MASK   0x60u
#define	I2S_CR_I2SMODE_SHIFT   5
#define	I2S_CR_I2SMODE(x)   (((uint32_t)(((uint32_t)(x))<<I2S_CR_I2SMODE_SHIFT))&I2S_CR_I2SMODE_MASK)
#define	I2S_CR_SYSCLKEN_MASK   0x80u
#define	I2S_CR_SYSCLKEN_SHIFT   7
#define	I2S_CR_TCHEN_MASK   0x100u
#define	I2S_CR_TCHEN_SHIFT   8
#define	I2S_CR_CLKIST_MASK   0x200u
#define	I2S_CR_CLKIST_SHIFT   9
#define	I2S_CR_TFRCLKDIS_MASK   0x400u
#define	I2S_CR_TFRCLKDIS_SHIFT   10
#define	I2S_CR_RFRCLKDIS_MASK   0x800u
#define	I2S_CR_RFRCLKDIS_SHIFT   11
#define	I2S_CR_SYNCTXFS_MASK   0x1000u
#define	I2S_CR_SYNCTXFS_SHIFT   12
#define	I2S_ISR_TFE0_MASK   0x1u
#define	I2S_ISR_TFE0_SHIFT   0
#define	I2S_ISR_TFE1_MASK   0x2u
#define	I2S_ISR_TFE1_SHIFT   1
#define	I2S_ISR_RFF0_MASK   0x4u
#define	I2S_ISR_RFF0_SHIFT   2
#define	I2S_ISR_RFF1_MASK   0x8u
#define	I2S_ISR_RFF1_SHIFT   3
#define	I2S_ISR_RLS_MASK   0x10u
#define	I2S_ISR_RLS_SHIFT   4
#define	I2S_ISR_TLS_MASK   0x20u
#define	I2S_ISR_TLS_SHIFT   5
#define	I2S_ISR_RFS_MASK   0x40u
#define	I2S_ISR_RFS_SHIFT   6
#define	I2S_ISR_TFS_MASK   0x80u
#define	I2S_ISR_TFS_SHIFT   7
#define	I2S_ISR_TUE0_MASK   0x100u
#define	I2S_ISR_TUE0_SHIFT   8
#define	I2S_ISR_TUE1_MASK   0x200u
#define	I2S_ISR_TUE1_SHIFT   9
#define	I2S_ISR_ROE0_MASK   0x400u
#define	I2S_ISR_ROE0_SHIFT   10
#define	I2S_ISR_ROE1_MASK   0x800u
#define	I2S_ISR_ROE1_SHIFT   11
#define	I2S_ISR_TDE0_MASK   0x1000u
#define	I2S_ISR_TDE0_SHIFT   12
#define	I2S_ISR_TDE1_MASK   0x2000u
#define	I2S_ISR_TDE1_SHIFT   13
#define	I2S_ISR_RDR0_MASK   0x4000u
#define	I2S_ISR_RDR0_SHIFT   14
#define	I2S_ISR_RDR1_MASK   0x8000u
#define	I2S_ISR_RDR1_SHIFT   15
#define	I2S_ISR_RXT_MASK   0x10000u
#define	I2S_ISR_RXT_SHIFT   16
#define	I2S_ISR_CMDDU_MASK   0x20000u
#define	I2S_ISR_CMDDU_SHIFT   17
#define	I2S_ISR_CMDAU_MASK   0x40000u
#define	I2S_ISR_CMDAU_SHIFT   18
#define	I2S_ISR_TRFC_MASK   0x800000u
#define	I2S_ISR_TRFC_SHIFT   23
#define	I2S_ISR_RFRC_MASK   0x1000000u
#define	I2S_ISR_RFRC_SHIFT   24
#define	I2S_IER_TFE0EN_MASK   0x1u
#define	I2S_IER_TFE0EN_SHIFT   0
#define	I2S_IER_TFE1EN_MASK   0x2u
#define	I2S_IER_TFE1EN_SHIFT   1
#define	I2S_IER_RFF0EN_MASK   0x4u
#define	I2S_IER_RFF0EN_SHIFT   2
#define	I2S_IER_RFF1EN_MASK   0x8u
#define	I2S_IER_RFF1EN_SHIFT   3
#define	I2S_IER_RLSEN_MASK   0x10u
#define	I2S_IER_RLSEN_SHIFT   4
#define	I2S_IER_TLSEN_MASK   0x20u
#define	I2S_IER_TLSEN_SHIFT   5
#define	I2S_IER_RFSEN_MASK   0x40u
#define	I2S_IER_RFSEN_SHIFT   6
#define	I2S_IER_TFSEN_MASK   0x80u
#define	I2S_IER_TFSEN_SHIFT   7
#define	I2S_IER_TUE0EN_MASK   0x100u
#define	I2S_IER_TUE0EN_SHIFT   8
#define	I2S_IER_TUE1EN_MASK   0x200u
#define	I2S_IER_TUE1EN_SHIFT   9
#define	I2S_IER_ROE0EN_MASK   0x400u
#define	I2S_IER_ROE0EN_SHIFT   10
#define	I2S_IER_ROE1EN_MASK   0x800u
#define	I2S_IER_ROE1EN_SHIFT   11
#define	I2S_IER_TDE0EN_MASK   0x1000u
#define	I2S_IER_TDE0EN_SHIFT   12
#define	I2S_IER_TDE1EN_MASK   0x2000u
#define	I2S_IER_TDE1EN_SHIFT   13
#define	I2S_IER_RDR0EN_MASK   0x4000u
#define	I2S_IER_RDR0EN_SHIFT   14
#define	I2S_IER_RDR1EN_MASK   0x8000u
#define	I2S_IER_RDR1EN_SHIFT   15
#define	I2S_IER_RXTEN_MASK   0x10000u
#define	I2S_IER_RXTEN_SHIFT   16
#define	I2S_IER_CMDDUEN_MASK   0x20000u
#define	I2S_IER_CMDDUEN_SHIFT   17
#define	I2S_IER_CMDAUEN_MASK   0x40000u
#define	I2S_IER_CMDAUEN_SHIFT   18
#define	I2S_IER_TIE_MASK   0x80000u
#define	I2S_IER_TIE_SHIFT   19
#define	I2S_IER_TDMAE_MASK   0x100000u
#define	I2S_IER_TDMAE_SHIFT   20
#define	I2S_IER_RIE_MASK   0x200000u
#define	I2S_IER_RIE_SHIFT   21
#define	I2S_IER_RDMAE_MASK   0x400000u
#define	I2S_IER_RDMAE_SHIFT   22
#define	I2S_IER_TFRC_EN_MASK   0x800000u
#define	I2S_IER_TFRC_EN_SHIFT   23
#define	I2S_IER_RFRC_EN_MASK   0x1000000u
#define	I2S_IER_RFRC_EN_SHIFT   24
#define	I2S_TCR_TEFS_MASK   0x1u
#define	I2S_TCR_TEFS_SHIFT   0
#define	I2S_TCR_TFSL_MASK   0x2u
#define	I2S_TCR_TFSL_SHIFT   1
#define	I2S_TCR_TFSI_MASK   0x4u
#define	I2S_TCR_TFSI_SHIFT   2
#define	I2S_TCR_TSCKP_MASK   0x8u
#define	I2S_TCR_TSCKP_SHIFT   3
#define	I2S_TCR_TSHFD_MASK   0x10u
#define	I2S_TCR_TSHFD_SHIFT   4
#define	I2S_TCR_TXDIR_MASK   0x20u
#define	I2S_TCR_TXDIR_SHIFT   5
#define	I2S_TCR_TFDIR_MASK   0x40u
#define	I2S_TCR_TFDIR_SHIFT   6
#define	I2S_TCR_TFEN0_MASK   0x80u
#define	I2S_TCR_TFEN0_SHIFT   7
#define	I2S_TCR_TFEN1_MASK   0x100u
#define	I2S_TCR_TFEN1_SHIFT   8
#define	I2S_TCR_TXBIT0_MASK   0x200u
#define	I2S_TCR_TXBIT0_SHIFT   9
#define	I2S_RCR_REFS_MASK   0x1u
#define	I2S_RCR_REFS_SHIFT   0
#define	I2S_RCR_RFSL_MASK   0x2u
#define	I2S_RCR_RFSL_SHIFT   1
#define	I2S_RCR_RFSI_MASK   0x4u
#define	I2S_RCR_RFSI_SHIFT   2
#define	I2S_RCR_RSCKP_MASK   0x8u
#define	I2S_RCR_RSCKP_SHIFT   3
#define	I2S_RCR_RSHFD_MASK   0x10u
#define	I2S_RCR_RSHFD_SHIFT   4
#define	I2S_RCR_RXDIR_MASK   0x20u
#define	I2S_RCR_RXDIR_SHIFT   5
#define	I2S_RCR_RFDIR_MASK   0x40u
#define	I2S_RCR_RFDIR_SHIFT   6
#define	I2S_RCR_RFEN0_MASK   0x80u
#define	I2S_RCR_RFEN0_SHIFT   7
#define	I2S_RCR_RFEN1_MASK   0x100u
#define	I2S_RCR_RFEN1_SHIFT   8
#define	I2S_RCR_RXBIT0_MASK   0x200u
#define	I2S_RCR_RXBIT0_SHIFT   9
#define	I2S_RCR_RXEXT_MASK   0x400u
#define	I2S_RCR_RXEXT_SHIFT   10
#define	I2S_TCCR_PM_MASK   0xFFu
#define	I2S_TCCR_PM_SHIFT   0
#define	I2S_TCCR_PM(x)   (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_PM_SHIFT))&I2S_TCCR_PM_MASK)
#define	I2S_TCCR_DC_MASK   0x1F00u
#define	I2S_TCCR_DC_SHIFT   8
#define	I2S_TCCR_DC(x)   (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_DC_SHIFT))&I2S_TCCR_DC_MASK)
#define	I2S_TCCR_WL_MASK   0x1E000u
#define	I2S_TCCR_WL_SHIFT   13
#define	I2S_TCCR_WL(x)   (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_WL_SHIFT))&I2S_TCCR_WL_MASK)
#define	I2S_TCCR_PSR_MASK   0x20000u
#define	I2S_TCCR_PSR_SHIFT   17
#define	I2S_TCCR_DIV2_MASK   0x40000u
#define	I2S_TCCR_DIV2_SHIFT   18
#define	I2S_RCCR_PM_MASK   0xFFu
#define	I2S_RCCR_PM_SHIFT   0
#define	I2S_RCCR_PM(x)   (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_PM_SHIFT))&I2S_RCCR_PM_MASK)
#define	I2S_RCCR_DC_MASK   0x1F00u
#define	I2S_RCCR_DC_SHIFT   8
#define	I2S_RCCR_DC(x)   (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_DC_SHIFT))&I2S_RCCR_DC_MASK)
#define	I2S_RCCR_WL_MASK   0x1E000u
#define	I2S_RCCR_WL_SHIFT   13
#define	I2S_RCCR_WL(x)   (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_WL_SHIFT))&I2S_RCCR_WL_MASK)
#define	I2S_RCCR_PSR_MASK   0x20000u
#define	I2S_RCCR_PSR_SHIFT   17
#define	I2S_RCCR_DIV2_MASK   0x40000u
#define	I2S_RCCR_DIV2_SHIFT   18
#define	I2S_FCSR_TFWM0_MASK   0xFu
#define	I2S_FCSR_TFWM0_SHIFT   0
#define	I2S_FCSR_TFWM0(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM0_SHIFT))&I2S_FCSR_TFWM0_MASK)
#define	I2S_FCSR_RFWM0_MASK   0xF0u
#define	I2S_FCSR_RFWM0_SHIFT   4
#define	I2S_FCSR_RFWM0(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM0_SHIFT))&I2S_FCSR_RFWM0_MASK)
#define	I2S_FCSR_TFCNT0_MASK   0xF00u
#define	I2S_FCSR_TFCNT0_SHIFT   8
#define	I2S_FCSR_TFCNT0(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT0_SHIFT))&I2S_FCSR_TFCNT0_MASK)
#define	I2S_FCSR_RFCNT0_MASK   0xF000u
#define	I2S_FCSR_RFCNT0_SHIFT   12
#define	I2S_FCSR_RFCNT0(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT0_SHIFT))&I2S_FCSR_RFCNT0_MASK)
#define	I2S_FCSR_TFWM1_MASK   0xF0000u
#define	I2S_FCSR_TFWM1_SHIFT   16
#define	I2S_FCSR_TFWM1(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM1_SHIFT))&I2S_FCSR_TFWM1_MASK)
#define	I2S_FCSR_RFWM1_MASK   0xF00000u
#define	I2S_FCSR_RFWM1_SHIFT   20
#define	I2S_FCSR_RFWM1(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM1_SHIFT))&I2S_FCSR_RFWM1_MASK)
#define	I2S_FCSR_TFCNT1_MASK   0xF000000u
#define	I2S_FCSR_TFCNT1_SHIFT   24
#define	I2S_FCSR_TFCNT1(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT1_SHIFT))&I2S_FCSR_TFCNT1_MASK)
#define	I2S_FCSR_RFCNT1_MASK   0xF0000000u
#define	I2S_FCSR_RFCNT1_SHIFT   28
#define	I2S_FCSR_RFCNT1(x)   (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT1_SHIFT))&I2S_FCSR_RFCNT1_MASK)
#define	I2S_ACNT_AC97EN_MASK   0x1u
#define	I2S_ACNT_AC97EN_SHIFT   0
#define	I2S_ACNT_FV_MASK   0x2u
#define	I2S_ACNT_FV_SHIFT   1
#define	I2S_ACNT_TIF_MASK   0x4u
#define	I2S_ACNT_TIF_SHIFT   2
#define	I2S_ACNT_RD_MASK   0x8u
#define	I2S_ACNT_RD_SHIFT   3
#define	I2S_ACNT_WR_MASK   0x10u
#define	I2S_ACNT_WR_SHIFT   4
#define	I2S_ACNT_FRDIV_MASK   0x7E0u
#define	I2S_ACNT_FRDIV_SHIFT   5
#define	I2S_ACNT_FRDIV(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ACNT_FRDIV_SHIFT))&I2S_ACNT_FRDIV_MASK)
#define	I2S_ACADD_ACADD_MASK   0x7FFFFu
#define	I2S_ACADD_ACADD_SHIFT   0
#define	I2S_ACADD_ACADD(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ACADD_ACADD_SHIFT))&I2S_ACADD_ACADD_MASK)
#define	I2S_ACDAT_ACDAT_MASK   0xFFFFFu
#define	I2S_ACDAT_ACDAT_SHIFT   0
#define	I2S_ACDAT_ACDAT(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ACDAT_ACDAT_SHIFT))&I2S_ACDAT_ACDAT_MASK)
#define	I2S_ATAG_ATAG_MASK   0xFFFFu
#define	I2S_ATAG_ATAG_SHIFT   0
#define	I2S_ATAG_ATAG(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ATAG_ATAG_SHIFT))&I2S_ATAG_ATAG_MASK)
#define	I2S_TMSK_TMSK_MASK   0xFFFFFFFFu
#define	I2S_TMSK_TMSK_SHIFT   0
#define	I2S_TMSK_TMSK(x)   (((uint32_t)(((uint32_t)(x))<<I2S_TMSK_TMSK_SHIFT))&I2S_TMSK_TMSK_MASK)
#define	I2S_RMSK_RMSK_MASK   0xFFFFFFFFu
#define	I2S_RMSK_RMSK_SHIFT   0
#define	I2S_RMSK_RMSK(x)   (((uint32_t)(((uint32_t)(x))<<I2S_RMSK_RMSK_SHIFT))&I2S_RMSK_RMSK_MASK)
#define	I2S_ACCST_ACCST_MASK   0x3FFu
#define	I2S_ACCST_ACCST_SHIFT   0
#define	I2S_ACCST_ACCST(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ACCST_ACCST_SHIFT))&I2S_ACCST_ACCST_MASK)
#define	I2S_ACCEN_ACCEN_MASK   0x3FFu
#define	I2S_ACCEN_ACCEN_SHIFT   0
#define	I2S_ACCEN_ACCEN(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ACCEN_ACCEN_SHIFT))&I2S_ACCEN_ACCEN_MASK)
#define	I2S_ACCDIS_ACCDIS_MASK   0x3FFu
#define	I2S_ACCDIS_ACCDIS_SHIFT   0
#define	I2S_ACCDIS_ACCDIS(x)   (((uint32_t)(((uint32_t)(x))<<I2S_ACCDIS_ACCDIS_SHIFT))&I2S_ACCDIS_ACCDIS_MASK)
#define	I2S_TDR_COUNT   (2U)
#define	I2S_TFR_COUNT   (2U)
#define	I2S_RDR_COUNT   (2U)
#define	I2S_RFR_COUNT   (2U)
#define	I2S_TDR_COUNT   (2U)
#define	I2S_TFR_COUNT   (2U)
#define	I2S_RDR_COUNT   (2U)
#define	I2S_RFR_COUNT   (2U)
#define	I2S_TDR_COUNT   (2U)
#define	I2S_TFR_COUNT   (2U)
#define	I2S_RDR_COUNT   (2U)
#define	I2S_RFR_COUNT   (2U)

TCSR - SAI Transmit Control Register
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TCR1 - SAI Transmit Configuration 1 Register
#define	I2S_TCR1_TFW_MASK   (0x7U)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
#define	I2S_TCR1_TFW_MASK   (0x7U)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
#define	I2S_TCR1_TFW_MASK   (0x7U)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
#define	I2S_TCR1_TFW_MASK   (0x7U)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TCR2 - SAI Transmit Configuration 2 Register
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

TCR3 - SAI Transmit Configuration 3 Register
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0x30000U)
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0x30000U)
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0x30000U)
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
#define	I2S_TCR3_CFR_MASK   (0x3000000U)
#define	I2S_TCR3_CFR_SHIFT   (24U)
#define	I2S_TCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0x30000U)
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
#define	I2S_TCR3_CFR_MASK   (0x3000000U)
#define	I2S_TCR3_CFR_SHIFT   (24U)
#define	I2S_TCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

TCR4 - SAI Transmit Configuration 4 Register
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_ONDEM_MASK   (0x4U)
#define	I2S_TCR4_ONDEM_SHIFT   (2U)
#define	I2S_TCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FPACK_MASK   (0x3000000U)
#define	I2S_TCR4_FPACK_SHIFT   (24U)
#define	I2S_TCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define	I2S_TCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_TCR4_FCOMB_SHIFT   (26U)
#define	I2S_TCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define	I2S_TCR4_FCONT_MASK   (0x10000000U)
#define	I2S_TCR4_FCONT_SHIFT   (28U)
#define	I2S_TCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_ONDEM_MASK   (0x4U)
#define	I2S_TCR4_ONDEM_SHIFT   (2U)
#define	I2S_TCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FPACK_MASK   (0x3000000U)
#define	I2S_TCR4_FPACK_SHIFT   (24U)
#define	I2S_TCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define	I2S_TCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_TCR4_FCOMB_SHIFT   (26U)
#define	I2S_TCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define	I2S_TCR4_FCONT_MASK   (0x10000000U)
#define	I2S_TCR4_FCONT_SHIFT   (28U)
#define	I2S_TCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

TCR5 - SAI Transmit Configuration 5 Register
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

TDR - SAI Transmit Data Register
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)

TDR - SAI Transmit Data Register
#define	I2S_TDR_COUNT   (2U)

TFR - SAI Transmit FIFO Register
#define	I2S_TFR_RFP_MASK   (0xFU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0xF0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_RFP_MASK   (0xFU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0xF0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_RFP_MASK   (0xFU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0xF0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_WCP_MASK   (0x80000000U)
#define	I2S_TFR_WCP_SHIFT   (31U)
#define	I2S_TFR_WCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
#define	I2S_TFR_RFP_MASK   (0xFU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0xF0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_WCP_MASK   (0x80000000U)
#define	I2S_TFR_WCP_SHIFT   (31U)
#define	I2S_TFR_WCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

TFR - SAI Transmit FIFO Register
#define	I2S_TFR_COUNT   (2U)

TMR - SAI Transmit Mask Register
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

RCSR - SAI Receive Control Register
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RCR1 - SAI Receive Configuration 1 Register
#define	I2S_RCR1_RFW_MASK   (0x7U)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
#define	I2S_RCR1_RFW_MASK   (0x7U)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
#define	I2S_RCR1_RFW_MASK   (0x7U)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
#define	I2S_RCR1_RFW_MASK   (0x7U)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RCR2 - SAI Receive Configuration 2 Register
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0xC0000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

RCR3 - SAI Receive Configuration 3 Register
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0x30000U)
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0x30000U)
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0x30000U)
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
#define	I2S_RCR3_CFR_MASK   (0x3000000U)
#define	I2S_RCR3_CFR_SHIFT   (24U)
#define	I2S_RCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0x30000U)
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
#define	I2S_RCR3_CFR_MASK   (0x3000000U)
#define	I2S_RCR3_CFR_SHIFT   (24U)
#define	I2S_RCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

RCR4 - SAI Receive Configuration 4 Register
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_ONDEM_MASK   (0x4U)
#define	I2S_RCR4_ONDEM_SHIFT   (2U)
#define	I2S_RCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FPACK_MASK   (0x3000000U)
#define	I2S_RCR4_FPACK_SHIFT   (24U)
#define	I2S_RCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define	I2S_RCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_RCR4_FCOMB_SHIFT   (26U)
#define	I2S_RCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define	I2S_RCR4_FCONT_MASK   (0x10000000U)
#define	I2S_RCR4_FCONT_SHIFT   (28U)
#define	I2S_RCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_ONDEM_MASK   (0x4U)
#define	I2S_RCR4_ONDEM_SHIFT   (2U)
#define	I2S_RCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FPACK_MASK   (0x3000000U)
#define	I2S_RCR4_FPACK_SHIFT   (24U)
#define	I2S_RCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define	I2S_RCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_RCR4_FCOMB_SHIFT   (26U)
#define	I2S_RCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define	I2S_RCR4_FCONT_MASK   (0x10000000U)
#define	I2S_RCR4_FCONT_SHIFT   (28U)
#define	I2S_RCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

RCR5 - SAI Receive Configuration 5 Register
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

RDR - SAI Receive Data Register
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)

RDR - SAI Receive Data Register
#define	I2S_RDR_COUNT   (2U)

RFR - SAI Receive FIFO Register
#define	I2S_RFR_RFP_MASK   (0xFU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_WFP_MASK   (0xF0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
#define	I2S_RFR_RFP_MASK   (0xFU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_WFP_MASK   (0xF0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
#define	I2S_RFR_RFP_MASK   (0xFU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_RCP_MASK   (0x8000U)
#define	I2S_RFR_RCP_SHIFT   (15U)
#define	I2S_RFR_RCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define	I2S_RFR_WFP_MASK   (0xF0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
#define	I2S_RFR_RFP_MASK   (0xFU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_RCP_MASK   (0x8000U)
#define	I2S_RFR_RCP_SHIFT   (15U)
#define	I2S_RFR_RCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define	I2S_RFR_WFP_MASK   (0xF0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

RFR - SAI Receive FIFO Register
#define	I2S_RFR_COUNT   (2U)

RMR - SAI Receive Mask Register
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

MCR - SAI MCLK Control Register
#define	I2S_MCR_MICS_MASK   (0x3000000U)
#define	I2S_MCR_MICS_SHIFT   (24U)
#define	I2S_MCR_MICS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
#define	I2S_MCR_MOE_MASK   (0x40000000U)
#define	I2S_MCR_MOE_SHIFT   (30U)
#define	I2S_MCR_MOE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
#define	I2S_MCR_DUF_MASK   (0x80000000U)
#define	I2S_MCR_DUF_SHIFT   (31U)
#define	I2S_MCR_DUF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
#define	I2S_MCR_MICS_MASK   (0x3000000U)
#define	I2S_MCR_MICS_SHIFT   (24U)
#define	I2S_MCR_MICS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
#define	I2S_MCR_MOE_MASK   (0x40000000U)
#define	I2S_MCR_MOE_SHIFT   (30U)
#define	I2S_MCR_MOE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
#define	I2S_MCR_DUF_MASK   (0x80000000U)
#define	I2S_MCR_DUF_SHIFT   (31U)
#define	I2S_MCR_DUF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
#define	I2S_MCR_MICS_MASK   (0x3000000U)
#define	I2S_MCR_MICS_SHIFT   (24U)
#define	I2S_MCR_MICS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
#define	I2S_MCR_MOE_MASK   (0x40000000U)
#define	I2S_MCR_MOE_SHIFT   (30U)
#define	I2S_MCR_MOE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
#define	I2S_MCR_DUF_MASK   (0x80000000U)
#define	I2S_MCR_DUF_SHIFT   (31U)
#define	I2S_MCR_DUF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
#define	I2S_MCR_MICS_MASK   (0x3000000U)
#define	I2S_MCR_MICS_SHIFT   (24U)
#define	I2S_MCR_MICS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
#define	I2S_MCR_MOE_MASK   (0x40000000U)
#define	I2S_MCR_MOE_SHIFT   (30U)
#define	I2S_MCR_MOE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
#define	I2S_MCR_DUF_MASK   (0x80000000U)
#define	I2S_MCR_DUF_SHIFT   (31U)
#define	I2S_MCR_DUF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)

MDR - SAI MCLK Divide Register
#define	I2S_MDR_DIVIDE_MASK   (0xFFFU)
#define	I2S_MDR_DIVIDE_SHIFT   (0U)
#define	I2S_MDR_DIVIDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
#define	I2S_MDR_FRACT_MASK   (0xFF000U)
#define	I2S_MDR_FRACT_SHIFT   (12U)
#define	I2S_MDR_FRACT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
#define	I2S_MDR_DIVIDE_MASK   (0xFFFU)
#define	I2S_MDR_DIVIDE_SHIFT   (0U)
#define	I2S_MDR_DIVIDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
#define	I2S_MDR_FRACT_MASK   (0xFF000U)
#define	I2S_MDR_FRACT_SHIFT   (12U)
#define	I2S_MDR_FRACT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
#define	I2S_MDR_DIVIDE_MASK   (0xFFFU)
#define	I2S_MDR_DIVIDE_SHIFT   (0U)
#define	I2S_MDR_DIVIDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
#define	I2S_MDR_FRACT_MASK   (0xFF000U)
#define	I2S_MDR_FRACT_SHIFT   (12U)
#define	I2S_MDR_FRACT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
#define	I2S_MDR_DIVIDE_MASK   (0xFFFU)
#define	I2S_MDR_DIVIDE_SHIFT   (0U)
#define	I2S_MDR_DIVIDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
#define	I2S_MDR_FRACT_MASK   (0xFF000U)
#define	I2S_MDR_FRACT_SHIFT   (12U)
#define	I2S_MDR_FRACT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)

Macro Definition Documentation

I2S0

#define I2S0   ((I2S_Type *)I2S0_BASE)

Peripheral I2S0 base pointer

I2S0_BASE

#define I2S0_BASE   (0x4002F000u)

Peripheral I2S0 base address

I2S_BASE_ADDRS

#define I2S_BASE_ADDRS   { I2S0_BASE }

Array initializer of I2S peripheral base addresses

I2S_BASE_PTRS

#define I2S_BASE_PTRS   { I2S0 }

Array initializer of I2S peripheral base pointers

I2S_MCR_DUF [1/4]

#define I2S_MCR_DUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)

DUF - Divider Update Flag 0b0..MCLK divider ratio is not being updated currently. 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.

I2S_MCR_DUF [2/4]

#define I2S_MCR_DUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)

DUF - Divider Update Flag 0b0..MCLK divider ratio is not being updated currently. 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.

I2S_MCR_DUF [3/4]

#define I2S_MCR_DUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)

DUF - Divider Update Flag 0b0..MCLK divider ratio is not being updated currently. 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.

I2S_MCR_DUF [4/4]

#define I2S_MCR_DUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)

DUF - Divider Update Flag 0b0..MCLK divider ratio is not being updated currently. 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.

I2S_MCR_MICS [1/4]

#define I2S_MCR_MICS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)

MICS - MCLK Input Clock Select 0b00..MCLK divider input clock 0 selected. 0b01..MCLK divider input clock 1 selected. 0b10..MCLK divider input clock 2 selected. 0b11..MCLK divider input clock 3 selected.

MICS - MCLK Input Clock Select 0b00..MCLK divider input clock 0 is selected. 0b01..MCLK divider input clock 1 is selected. 0b10..MCLK divider input clock 2 is selected. 0b11..MCLK divider input clock 3 is selected.

I2S_MCR_MICS [2/4]

#define I2S_MCR_MICS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)

MICS - MCLK Input Clock Select 0b00..MCLK divider input clock 0 selected. 0b01..MCLK divider input clock 1 selected. 0b10..MCLK divider input clock 2 selected. 0b11..MCLK divider input clock 3 selected.

MICS - MCLK Input Clock Select 0b00..MCLK divider input clock 0 is selected. 0b01..MCLK divider input clock 1 is selected. 0b10..MCLK divider input clock 2 is selected. 0b11..MCLK divider input clock 3 is selected.

I2S_MCR_MICS [3/4]

#define I2S_MCR_MICS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)

MICS - MCLK Input Clock Select 0b00..MCLK divider input clock 0 is selected. 0b01..MCLK divider input clock 1 is selected. 0b10..MCLK divider input clock 2 is selected. 0b11..MCLK divider input clock 3 is selected.

I2S_MCR_MICS [4/4]

#define I2S_MCR_MICS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)

MICS - MCLK Input Clock Select 0b00..MCLK divider input clock 0 is selected. 0b01..MCLK divider input clock 1 is selected. 0b10..MCLK divider input clock 2 is selected. 0b11..MCLK divider input clock 3 is selected.

I2S_MCR_MOE [1/4]

#define I2S_MCR_MOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)

MOE - MCLK Output Enable 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider. 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.

I2S_MCR_MOE [2/4]

#define I2S_MCR_MOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)

MOE - MCLK Output Enable 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider. 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.

I2S_MCR_MOE [3/4]

#define I2S_MCR_MOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)

MOE - MCLK Output Enable 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider. 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.

I2S_MCR_MOE [4/4]

#define I2S_MCR_MOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)

MOE - MCLK Output Enable 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider. 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.

I2S_RCR2_BCD [1/4]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCD [2/4]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCD [3/4]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCD [4/4]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCI [1/4]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCI [2/4]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCI [3/4]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCI [4/4]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCP [1/4]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCP [2/4]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCP [3/4]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCP [4/4]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCS [1/4]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_BCS [2/4]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_BCS [3/4]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_BCS [4/4]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_MSEL [1/4]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_MSEL [2/4]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_MSEL [3/4]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_MSEL [4/4]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_SYNC [1/4]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with transmitter. 0b10..Synchronous with another SAI receiver. 0b11..Synchronous with another SAI transmitter.

I2S_RCR2_SYNC [2/4]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with transmitter. 0b10..Synchronous with another SAI receiver. 0b11..Synchronous with another SAI transmitter.

I2S_RCR2_SYNC [3/4]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with transmitter. 0b10..Synchronous with another SAI receiver. 0b11..Synchronous with another SAI transmitter.

I2S_RCR2_SYNC [4/4]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with transmitter. 0b10..Synchronous with another SAI receiver. 0b11..Synchronous with another SAI transmitter.

I2S_RCR3_CFR [1/2]

#define I2S_RCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

CFR - Channel FIFO Reset 0b00..No effect. 0b01..Receive data channel N FIFO is reset.

I2S_RCR3_CFR [2/2]

#define I2S_RCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

CFR - Channel FIFO Reset 0b00..No effect. 0b01..Receive data channel N FIFO is reset.

I2S_RCR3_RCE [1/4]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)

RCE - Receive Channel Enable 0b00..Receive data channel N is disabled. 0b01..Receive data channel N is enabled.

I2S_RCR3_RCE [2/4]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)

RCE - Receive Channel Enable 0b00..Receive data channel N is disabled. 0b01..Receive data channel N is enabled.

I2S_RCR3_RCE [3/4]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)

RCE - Receive Channel Enable 0b00..Receive data channel N is disabled. 0b01..Receive data channel N is enabled.

I2S_RCR3_RCE [4/4]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)

RCE - Receive Channel Enable 0b00..Receive data channel N is disabled. 0b01..Receive data channel N is enabled.

I2S_RCR4_FCOMB [1/2]

#define I2S_RCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). 0b10..FIFO combine mode enabled on FIFO reads (by software). 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).

I2S_RCR4_FCOMB [2/2]

#define I2S_RCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). 0b10..FIFO combine mode enabled on FIFO reads (by software). 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).

I2S_RCR4_FCONT [1/2]

#define I2S_RCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_RCR4_FCONT [2/2]

#define I2S_RCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_RCR4_FPACK [1/2]

#define I2S_RCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved. 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_RCR4_FPACK [2/2]

#define I2S_RCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved. 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_RCR4_FSD [1/4]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSD [2/4]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSD [3/4]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSD [4/4]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSE [1/4]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSE [2/4]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSE [3/4]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSE [4/4]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSP [1/4]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_FSP [2/4]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_FSP [3/4]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_FSP [4/4]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_MF [1/4]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_MF [2/4]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_MF [3/4]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_MF [4/4]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_ONDEM [1/2]

#define I2S_RCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_RCR4_ONDEM [2/2]

#define I2S_RCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_RCSR_BCE [1/4]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_BCE [2/4]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_BCE [3/4]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_BCE [4/4]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_DBGE [1/4]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_DBGE [2/4]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_DBGE [3/4]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_DBGE [4/4]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_FEF [1/4]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEF [2/4]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEF [3/4]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEF [4/4]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEIE [1/4]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FEIE [2/4]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FEIE [3/4]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FEIE [4/4]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FR [1/4]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FR [2/4]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FR [3/4]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FR [4/4]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FRDE [1/4]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRDE [2/4]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRDE [3/4]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRDE [4/4]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRF [1/4]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRF [2/4]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRF [3/4]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRF [4/4]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRIE [1/4]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FRIE [2/4]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FRIE [3/4]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FRIE [4/4]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWDE [1/4]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWDE [2/4]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWDE [3/4]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWDE [4/4]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWF [1/4]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWF [2/4]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWF [3/4]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWF [4/4]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWIE [1/4]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWIE [2/4]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWIE [3/4]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWIE [4/4]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_RE [1/4]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_RE [2/4]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_RE [3/4]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_RE [4/4]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_SEF [1/4]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEF [2/4]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEF [3/4]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEF [4/4]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEIE [1/4]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SEIE [2/4]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SEIE [3/4]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SEIE [4/4]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SR [1/4]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_SR [2/4]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_SR [3/4]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_SR [4/4]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_STOPE [1/4]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_STOPE [2/4]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_STOPE [3/4]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_STOPE [4/4]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_WSF [1/4]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSF [2/4]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSF [3/4]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSF [4/4]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSIE [1/4]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_WSIE [2/4]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_WSIE [3/4]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_WSIE [4/4]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RFR_RCP [1/2]

#define I2S_RFR_RCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)

RCP - Receive Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.

I2S_RFR_RCP [2/2]

#define I2S_RFR_RCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)

RCP - Receive Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.

I2S_RMR_RWM [1/4]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_RMR_RWM [2/4]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_RMR_RWM [3/4]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_RMR_RWM [4/4]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_RX_IRQS

#define I2S_RX_IRQS   { I2S0_Rx_IRQn }

Interrupt vectors for the I2S peripheral type

I2S_TCR2_BCD [1/4]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCD [2/4]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCD [3/4]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCD [4/4]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCI [1/4]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCI [2/4]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCI [3/4]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCI [4/4]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCP [1/4]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCP [2/4]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCP [3/4]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCP [4/4]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCS [1/4]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_BCS [2/4]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_BCS [3/4]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_BCS [4/4]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_MSEL [1/4]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_MSEL [2/4]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_MSEL [3/4]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_MSEL [4/4]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_SYNC [1/4]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with receiver. 0b10..Synchronous with another SAI transmitter. 0b11..Synchronous with another SAI receiver.

I2S_TCR2_SYNC [2/4]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with receiver. 0b10..Synchronous with another SAI transmitter. 0b11..Synchronous with another SAI receiver.

I2S_TCR2_SYNC [3/4]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with receiver. 0b10..Synchronous with another SAI transmitter. 0b11..Synchronous with another SAI receiver.

I2S_TCR2_SYNC [4/4]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with receiver. 0b10..Synchronous with another SAI transmitter. 0b11..Synchronous with another SAI receiver.

I2S_TCR3_CFR [1/2]

#define I2S_TCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

CFR - Channel FIFO Reset 0b00..No effect. 0b01..Transmit data channel N FIFO is reset.

I2S_TCR3_CFR [2/2]

#define I2S_TCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

CFR - Channel FIFO Reset 0b00..No effect. 0b01..Transmit data channel N FIFO is reset.

I2S_TCR3_TCE [1/4]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)

TCE - Transmit Channel Enable 0b00..Transmit data channel N is disabled. 0b01..Transmit data channel N is enabled.

I2S_TCR3_TCE [2/4]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)

TCE - Transmit Channel Enable 0b00..Transmit data channel N is disabled. 0b01..Transmit data channel N is enabled.

I2S_TCR3_TCE [3/4]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)

TCE - Transmit Channel Enable 0b00..Transmit data channel N is disabled. 0b01..Transmit data channel N is enabled.

I2S_TCR3_TCE [4/4]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)

TCE - Transmit Channel Enable 0b00..Transmit data channel N is disabled. 0b01..Transmit data channel N is enabled.

I2S_TCR4_FCOMB [1/2]

#define I2S_TCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0b10..FIFO combine mode enabled on FIFO writes (by software). 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).

I2S_TCR4_FCOMB [2/2]

#define I2S_TCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0b10..FIFO combine mode enabled on FIFO writes (by software). 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).

I2S_TCR4_FCONT [1/2]

#define I2S_TCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_TCR4_FCONT [2/2]

#define I2S_TCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_TCR4_FPACK [1/2]

#define I2S_TCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_TCR4_FPACK [2/2]

#define I2S_TCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_TCR4_FSD [1/4]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSD [2/4]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSD [3/4]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSD [4/4]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSE [1/4]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSE [2/4]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSE [3/4]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSE [4/4]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSP [1/4]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_FSP [2/4]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_FSP [3/4]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_FSP [4/4]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_MF [1/4]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_MF [2/4]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_MF [3/4]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_MF [4/4]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_ONDEM [1/2]

#define I2S_TCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_TCR4_ONDEM [2/2]

#define I2S_TCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_TCSR_BCE [1/4]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_BCE [2/4]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_BCE [3/4]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_BCE [4/4]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_DBGE [1/4]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_DBGE [2/4]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_DBGE [3/4]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_DBGE [4/4]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_FEF [1/4]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEF [2/4]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEF [3/4]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEF [4/4]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEIE [1/4]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FEIE [2/4]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FEIE [3/4]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FEIE [4/4]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FR [1/4]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FR [2/4]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FR [3/4]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FR [4/4]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FRDE [1/4]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRDE [2/4]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRDE [3/4]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRDE [4/4]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRF [1/4]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRF [2/4]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRF [3/4]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRF [4/4]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRIE [1/4]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FRIE [2/4]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FRIE [3/4]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FRIE [4/4]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWDE [1/4]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWDE [2/4]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWDE [3/4]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWDE [4/4]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWF [1/4]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWF [2/4]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWF [3/4]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWF [4/4]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWIE [1/4]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWIE [2/4]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWIE [3/4]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWIE [4/4]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_SEF [1/4]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEF [2/4]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEF [3/4]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEF [4/4]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEIE [1/4]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SEIE [2/4]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SEIE [3/4]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SEIE [4/4]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SR [1/4]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_SR [2/4]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_SR [3/4]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_SR [4/4]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_STOPE [1/4]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_STOPE [2/4]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_STOPE [3/4]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_STOPE [4/4]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_TE [1/4]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_TE [2/4]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_TE [3/4]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_TE [4/4]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_WSF [1/4]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSF [2/4]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSF [3/4]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSF [4/4]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSIE [1/4]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_WSIE [2/4]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_WSIE [3/4]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_WSIE [4/4]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TFR_WCP [1/2]

#define I2S_TFR_WCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

WCP - Write Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.

I2S_TFR_WCP [2/2]

#define I2S_TFR_WCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

WCP - Write Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.

I2S_TMR_TWM [1/4]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.

I2S_TMR_TWM [2/4]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.

I2S_TMR_TWM [3/4]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.

I2S_TMR_TWM [4/4]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.