LPTMR Register Masks

Macros
#define	LPTMR0_BASE   (0x40040000u)
#define	LPTMR0   ((LPTMR_Type *)LPTMR0_BASE)
#define	LPTMR_BASE_ADDRS   { LPTMR0_BASE }
#define	LPTMR_BASE_PTRS   { LPTMR0 }
#define	LPTMR_IRQS   { LPTMR0_IRQn }

CSR - Low Power Timer Control Status Register
#define	LPTMR_CSR_TEN_MASK   (0x1U)
#define	LPTMR_CSR_TEN_SHIFT   (0U)
#define	LPTMR_CSR_TEN(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define	LPTMR_CSR_TMS_MASK   (0x2U)
#define	LPTMR_CSR_TMS_SHIFT   (1U)
#define	LPTMR_CSR_TMS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define	LPTMR_CSR_TFC_MASK   (0x4U)
#define	LPTMR_CSR_TFC_SHIFT   (2U)
#define	LPTMR_CSR_TFC(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define	LPTMR_CSR_TPP_MASK   (0x8U)
#define	LPTMR_CSR_TPP_SHIFT   (3U)
#define	LPTMR_CSR_TPP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define	LPTMR_CSR_TPS_MASK   (0x30U)
#define	LPTMR_CSR_TPS_SHIFT   (4U)
#define	LPTMR_CSR_TPS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define	LPTMR_CSR_TIE_MASK   (0x40U)
#define	LPTMR_CSR_TIE_SHIFT   (6U)
#define	LPTMR_CSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define	LPTMR_CSR_TCF_MASK   (0x80U)
#define	LPTMR_CSR_TCF_SHIFT   (7U)
#define	LPTMR_CSR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
#define	LPTMR_CSR_TEN_MASK   0x1u
#define	LPTMR_CSR_TEN_SHIFT   0
#define	LPTMR_CSR_TMS_MASK   0x2u
#define	LPTMR_CSR_TMS_SHIFT   1
#define	LPTMR_CSR_TFC_MASK   0x4u
#define	LPTMR_CSR_TFC_SHIFT   2
#define	LPTMR_CSR_TPP_MASK   0x8u
#define	LPTMR_CSR_TPP_SHIFT   3
#define	LPTMR_CSR_TPS_MASK   0x30u
#define	LPTMR_CSR_TPS_SHIFT   4
#define	LPTMR_CSR_TPS(x)   (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
#define	LPTMR_CSR_TIE_MASK   0x40u
#define	LPTMR_CSR_TIE_SHIFT   6
#define	LPTMR_CSR_TCF_MASK   0x80u
#define	LPTMR_CSR_TCF_SHIFT   7
#define	LPTMR_CSR_TEN_MASK   (0x1U)
#define	LPTMR_CSR_TEN_SHIFT   (0U)
#define	LPTMR_CSR_TEN(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define	LPTMR_CSR_TMS_MASK   (0x2U)
#define	LPTMR_CSR_TMS_SHIFT   (1U)
#define	LPTMR_CSR_TMS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define	LPTMR_CSR_TFC_MASK   (0x4U)
#define	LPTMR_CSR_TFC_SHIFT   (2U)
#define	LPTMR_CSR_TFC(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define	LPTMR_CSR_TPP_MASK   (0x8U)
#define	LPTMR_CSR_TPP_SHIFT   (3U)
#define	LPTMR_CSR_TPP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define	LPTMR_CSR_TPS_MASK   (0x30U)
#define	LPTMR_CSR_TPS_SHIFT   (4U)
#define	LPTMR_CSR_TPS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define	LPTMR_CSR_TIE_MASK   (0x40U)
#define	LPTMR_CSR_TIE_SHIFT   (6U)
#define	LPTMR_CSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define	LPTMR_CSR_TCF_MASK   (0x80U)
#define	LPTMR_CSR_TCF_SHIFT   (7U)
#define	LPTMR_CSR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
#define	LPTMR_CSR_TEN_MASK   (0x1U)
#define	LPTMR_CSR_TEN_SHIFT   (0U)
#define	LPTMR_CSR_TEN(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define	LPTMR_CSR_TMS_MASK   (0x2U)
#define	LPTMR_CSR_TMS_SHIFT   (1U)
#define	LPTMR_CSR_TMS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define	LPTMR_CSR_TFC_MASK   (0x4U)
#define	LPTMR_CSR_TFC_SHIFT   (2U)
#define	LPTMR_CSR_TFC(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define	LPTMR_CSR_TPP_MASK   (0x8U)
#define	LPTMR_CSR_TPP_SHIFT   (3U)
#define	LPTMR_CSR_TPP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define	LPTMR_CSR_TPS_MASK   (0x30U)
#define	LPTMR_CSR_TPS_SHIFT   (4U)
#define	LPTMR_CSR_TPS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define	LPTMR_CSR_TIE_MASK   (0x40U)
#define	LPTMR_CSR_TIE_SHIFT   (6U)
#define	LPTMR_CSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define	LPTMR_CSR_TCF_MASK   (0x80U)
#define	LPTMR_CSR_TCF_SHIFT   (7U)
#define	LPTMR_CSR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
#define	LPTMR_CSR_TEN_MASK   (0x1U)
#define	LPTMR_CSR_TEN_SHIFT   (0U)
#define	LPTMR_CSR_TEN(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define	LPTMR_CSR_TMS_MASK   (0x2U)
#define	LPTMR_CSR_TMS_SHIFT   (1U)
#define	LPTMR_CSR_TMS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define	LPTMR_CSR_TFC_MASK   (0x4U)
#define	LPTMR_CSR_TFC_SHIFT   (2U)
#define	LPTMR_CSR_TFC(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define	LPTMR_CSR_TPP_MASK   (0x8U)
#define	LPTMR_CSR_TPP_SHIFT   (3U)
#define	LPTMR_CSR_TPP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define	LPTMR_CSR_TPS_MASK   (0x30U)
#define	LPTMR_CSR_TPS_SHIFT   (4U)
#define	LPTMR_CSR_TPS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define	LPTMR_CSR_TIE_MASK   (0x40U)
#define	LPTMR_CSR_TIE_SHIFT   (6U)
#define	LPTMR_CSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define	LPTMR_CSR_TCF_MASK   (0x80U)
#define	LPTMR_CSR_TCF_SHIFT   (7U)
#define	LPTMR_CSR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
#define	LPTMR_CSR_TEN_MASK   (0x1U)
#define	LPTMR_CSR_TEN_SHIFT   (0U)
#define	LPTMR_CSR_TEN(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define	LPTMR_CSR_TMS_MASK   (0x2U)
#define	LPTMR_CSR_TMS_SHIFT   (1U)
#define	LPTMR_CSR_TMS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define	LPTMR_CSR_TFC_MASK   (0x4U)
#define	LPTMR_CSR_TFC_SHIFT   (2U)
#define	LPTMR_CSR_TFC(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define	LPTMR_CSR_TPP_MASK   (0x8U)
#define	LPTMR_CSR_TPP_SHIFT   (3U)
#define	LPTMR_CSR_TPP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define	LPTMR_CSR_TPS_MASK   (0x30U)
#define	LPTMR_CSR_TPS_SHIFT   (4U)
#define	LPTMR_CSR_TPS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define	LPTMR_CSR_TIE_MASK   (0x40U)
#define	LPTMR_CSR_TIE_SHIFT   (6U)
#define	LPTMR_CSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define	LPTMR_CSR_TCF_MASK   (0x80U)
#define	LPTMR_CSR_TCF_SHIFT   (7U)
#define	LPTMR_CSR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

PSR - Low Power Timer Prescale Register
#define	LPTMR_PSR_PCS_MASK   (0x3U)
#define	LPTMR_PSR_PCS_SHIFT   (0U)
#define	LPTMR_PSR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define	LPTMR_PSR_PBYP_MASK   (0x4U)
#define	LPTMR_PSR_PBYP_SHIFT   (2U)
#define	LPTMR_PSR_PBYP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define	LPTMR_PSR_PRESCALE_MASK   (0x78U)
#define	LPTMR_PSR_PRESCALE_SHIFT   (3U)
#define	LPTMR_PSR_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
#define	LPTMR_PSR_PCS_MASK   0x3u
#define	LPTMR_PSR_PCS_SHIFT   0
#define	LPTMR_PSR_PCS(x)   (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
#define	LPTMR_PSR_PBYP_MASK   0x4u
#define	LPTMR_PSR_PBYP_SHIFT   2
#define	LPTMR_PSR_PRESCALE_MASK   0x78u
#define	LPTMR_PSR_PRESCALE_SHIFT   3
#define	LPTMR_PSR_PRESCALE(x)   (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
#define	LPTMR_PSR_PCS_MASK   (0x3U)
#define	LPTMR_PSR_PCS_SHIFT   (0U)
#define	LPTMR_PSR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define	LPTMR_PSR_PBYP_MASK   (0x4U)
#define	LPTMR_PSR_PBYP_SHIFT   (2U)
#define	LPTMR_PSR_PBYP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define	LPTMR_PSR_PRESCALE_MASK   (0x78U)
#define	LPTMR_PSR_PRESCALE_SHIFT   (3U)
#define	LPTMR_PSR_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
#define	LPTMR_PSR_PCS_MASK   (0x3U)
#define	LPTMR_PSR_PCS_SHIFT   (0U)
#define	LPTMR_PSR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define	LPTMR_PSR_PBYP_MASK   (0x4U)
#define	LPTMR_PSR_PBYP_SHIFT   (2U)
#define	LPTMR_PSR_PBYP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define	LPTMR_PSR_PRESCALE_MASK   (0x78U)
#define	LPTMR_PSR_PRESCALE_SHIFT   (3U)
#define	LPTMR_PSR_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
#define	LPTMR_PSR_PCS_MASK   (0x3U)
#define	LPTMR_PSR_PCS_SHIFT   (0U)
#define	LPTMR_PSR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define	LPTMR_PSR_PBYP_MASK   (0x4U)
#define	LPTMR_PSR_PBYP_SHIFT   (2U)
#define	LPTMR_PSR_PBYP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define	LPTMR_PSR_PRESCALE_MASK   (0x78U)
#define	LPTMR_PSR_PRESCALE_SHIFT   (3U)
#define	LPTMR_PSR_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
#define	LPTMR_PSR_PCS_MASK   (0x3U)
#define	LPTMR_PSR_PCS_SHIFT   (0U)
#define	LPTMR_PSR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define	LPTMR_PSR_PBYP_MASK   (0x4U)
#define	LPTMR_PSR_PBYP_SHIFT   (2U)
#define	LPTMR_PSR_PBYP(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define	LPTMR_PSR_PRESCALE_MASK   (0x78U)
#define	LPTMR_PSR_PRESCALE_SHIFT   (3U)
#define	LPTMR_PSR_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)

CMR - Low Power Timer Compare Register
#define	LPTMR_CMR_COMPARE_MASK   (0xFFFFU)
#define	LPTMR_CMR_COMPARE_SHIFT   (0U)
#define	LPTMR_CMR_COMPARE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
#define	LPTMR_CMR_COMPARE_MASK   0xFFFFu
#define	LPTMR_CMR_COMPARE_SHIFT   0
#define	LPTMR_CMR_COMPARE(x)   (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
#define	LPTMR_CMR_COMPARE_MASK   (0xFFFFU)
#define	LPTMR_CMR_COMPARE_SHIFT   (0U)
#define	LPTMR_CMR_COMPARE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
#define	LPTMR_CMR_COMPARE_MASK   (0xFFFFU)
#define	LPTMR_CMR_COMPARE_SHIFT   (0U)
#define	LPTMR_CMR_COMPARE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
#define	LPTMR_CMR_COMPARE_MASK   (0xFFFFU)
#define	LPTMR_CMR_COMPARE_SHIFT   (0U)
#define	LPTMR_CMR_COMPARE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
#define	LPTMR_CMR_COMPARE_MASK   (0xFFFFU)
#define	LPTMR_CMR_COMPARE_SHIFT   (0U)
#define	LPTMR_CMR_COMPARE(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)

CNR - Low Power Timer Counter Register
#define	LPTMR_CNR_COUNTER_MASK   (0xFFFFU)
#define	LPTMR_CNR_COUNTER_SHIFT   (0U)
#define	LPTMR_CNR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
#define	LPTMR_CNR_COUNTER_MASK   0xFFFFu
#define	LPTMR_CNR_COUNTER_SHIFT   0
#define	LPTMR_CNR_COUNTER(x)   (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
#define	LPTMR_CNR_COUNTER_MASK   (0xFFFFU)
#define	LPTMR_CNR_COUNTER_SHIFT   (0U)
#define	LPTMR_CNR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
#define	LPTMR_CNR_COUNTER_MASK   (0xFFFFU)
#define	LPTMR_CNR_COUNTER_SHIFT   (0U)
#define	LPTMR_CNR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
#define	LPTMR_CNR_COUNTER_MASK   (0xFFFFU)
#define	LPTMR_CNR_COUNTER_SHIFT   (0U)
#define	LPTMR_CNR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
#define	LPTMR_CNR_COUNTER_MASK   (0xFFFFU)
#define	LPTMR_CNR_COUNTER_SHIFT   (0U)
#define	LPTMR_CNR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)

Macro Definition Documentation

LPTMR0

#define LPTMR0   ((LPTMR_Type *)LPTMR0_BASE)

Peripheral LPTMR0 base pointer

LPTMR0_BASE

#define LPTMR0_BASE   (0x40040000u)

Peripheral LPTMR0 base address

LPTMR_BASE_ADDRS

#define LPTMR_BASE_ADDRS   { LPTMR0_BASE }

Array initializer of LPTMR peripheral base addresses

LPTMR_BASE_PTRS

#define LPTMR_BASE_PTRS   { LPTMR0 }

Array initializer of LPTMR peripheral base pointers

LPTMR_CSR_TCF [1/5]

#define LPTMR_CSR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

TCF - Timer Compare Flag 0b0..The value of CNR is not equal to CMR and increments. 0b1..The value of CNR is equal to CMR and increments.

LPTMR_CSR_TCF [2/5]

#define LPTMR_CSR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

TCF - Timer Compare Flag 0b0..The value of CNR is not equal to CMR and increments. 0b1..The value of CNR is equal to CMR and increments.

LPTMR_CSR_TCF [3/5]

#define LPTMR_CSR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

TCF - Timer Compare Flag 0b0..The value of CNR is not equal to CMR and increments. 0b1..The value of CNR is equal to CMR and increments.

LPTMR_CSR_TCF [4/5]

#define LPTMR_CSR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

TCF - Timer Compare Flag 0b0..The value of CNR is not equal to CMR and increments. 0b1..The value of CNR is equal to CMR and increments.

LPTMR_CSR_TCF [5/5]

#define LPTMR_CSR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

TCF - Timer Compare Flag 0b0..The value of CNR is not equal to CMR and increments. 0b1..The value of CNR is equal to CMR and increments.

LPTMR_CSR_TEN [1/5]

#define LPTMR_CSR_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

TEN - Timer Enable 0b0..LPTMR is disabled and internal logic is reset. 0b1..LPTMR is enabled.

LPTMR_CSR_TEN [2/5]

#define LPTMR_CSR_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

TEN - Timer Enable 0b0..LPTMR is disabled and internal logic is reset. 0b1..LPTMR is enabled.

LPTMR_CSR_TEN [3/5]

#define LPTMR_CSR_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

TEN - Timer Enable 0b0..LPTMR is disabled and internal logic is reset. 0b1..LPTMR is enabled.

LPTMR_CSR_TEN [4/5]

#define LPTMR_CSR_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

TEN - Timer Enable 0b0..LPTMR is disabled and internal logic is reset. 0b1..LPTMR is enabled.

LPTMR_CSR_TEN [5/5]

#define LPTMR_CSR_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

TEN - Timer Enable 0b0..LPTMR is disabled and internal logic is reset. 0b1..LPTMR is enabled.

LPTMR_CSR_TFC [1/5]

#define LPTMR_CSR_TFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

TFC - Timer Free-Running Counter 0b0..CNR is reset whenever TCF is set. 0b1..CNR is reset on overflow.

LPTMR_CSR_TFC [2/5]

#define LPTMR_CSR_TFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

TFC - Timer Free-Running Counter 0b0..CNR is reset whenever TCF is set. 0b1..CNR is reset on overflow.

LPTMR_CSR_TFC [3/5]

#define LPTMR_CSR_TFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

TFC - Timer Free-Running Counter 0b0..CNR is reset whenever TCF is set. 0b1..CNR is reset on overflow.

LPTMR_CSR_TFC [4/5]

#define LPTMR_CSR_TFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

TFC - Timer Free-Running Counter 0b0..CNR is reset whenever TCF is set. 0b1..CNR is reset on overflow.

LPTMR_CSR_TFC [5/5]

#define LPTMR_CSR_TFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

TFC - Timer Free-Running Counter 0b0..CNR is reset whenever TCF is set. 0b1..CNR is reset on overflow.

LPTMR_CSR_TIE [1/5]

#define LPTMR_CSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Timer interrupt disabled. 0b1..Timer interrupt enabled.

LPTMR_CSR_TIE [2/5]

#define LPTMR_CSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Timer interrupt disabled. 0b1..Timer interrupt enabled.

LPTMR_CSR_TIE [3/5]

#define LPTMR_CSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Timer interrupt disabled. 0b1..Timer interrupt enabled.

LPTMR_CSR_TIE [4/5]

#define LPTMR_CSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Timer interrupt disabled. 0b1..Timer interrupt enabled.

LPTMR_CSR_TIE [5/5]

#define LPTMR_CSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Timer interrupt disabled. 0b1..Timer interrupt enabled.

LPTMR_CSR_TMS [1/5]

#define LPTMR_CSR_TMS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

TMS - Timer Mode Select 0b0..Time Counter mode. 0b1..Pulse Counter mode.

LPTMR_CSR_TMS [2/5]

#define LPTMR_CSR_TMS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

TMS - Timer Mode Select 0b0..Time Counter mode. 0b1..Pulse Counter mode.

LPTMR_CSR_TMS [3/5]

#define LPTMR_CSR_TMS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

TMS - Timer Mode Select 0b0..Time Counter mode. 0b1..Pulse Counter mode.

LPTMR_CSR_TMS [4/5]

#define LPTMR_CSR_TMS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

TMS - Timer Mode Select 0b0..Time Counter mode. 0b1..Pulse Counter mode.

LPTMR_CSR_TMS [5/5]

#define LPTMR_CSR_TMS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

TMS - Timer Mode Select 0b0..Time Counter mode. 0b1..Pulse Counter mode.

LPTMR_CSR_TPP [1/5]

#define LPTMR_CSR_TPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

TPP - Timer Pin Polarity 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.

LPTMR_CSR_TPP [2/5]

#define LPTMR_CSR_TPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

TPP - Timer Pin Polarity 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.

LPTMR_CSR_TPP [3/5]

#define LPTMR_CSR_TPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

TPP - Timer Pin Polarity 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.

LPTMR_CSR_TPP [4/5]

#define LPTMR_CSR_TPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

TPP - Timer Pin Polarity 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.

LPTMR_CSR_TPP [5/5]

#define LPTMR_CSR_TPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

TPP - Timer Pin Polarity 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.

LPTMR_CSR_TPS [1/6]

#define LPTMR_CSR_TPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

TPS - Timer Pin Select 0b00..Pulse counter input 0 is selected. 0b01..Pulse counter input 1 is selected. 0b10..Pulse counter input 2 is selected. 0b11..Pulse counter input 3 is selected.

LPTMR_CSR_TPS [2/6]

#define LPTMR_CSR_TPS

(

x

)

(((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)

TPS - Timer Pin Select 0b00..Pulse counter input 0 is selected. 0b01..Pulse counter input 1 is selected. 0b10..Pulse counter input 2 is selected. 0b11..Pulse counter input 3 is selected.

LPTMR_CSR_TPS [3/6]

#define LPTMR_CSR_TPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

TPS - Timer Pin Select 0b00..Pulse counter input 0 is selected. 0b01..Pulse counter input 1 is selected. 0b10..Pulse counter input 2 is selected. 0b11..Pulse counter input 3 is selected.

LPTMR_CSR_TPS [4/6]

#define LPTMR_CSR_TPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

TPS - Timer Pin Select 0b00..Pulse counter input 0 is selected. 0b01..Pulse counter input 1 is selected. 0b10..Pulse counter input 2 is selected. 0b11..Pulse counter input 3 is selected.

LPTMR_CSR_TPS [5/6]

#define LPTMR_CSR_TPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

TPS - Timer Pin Select 0b00..Pulse counter input 0 is selected. 0b01..Pulse counter input 1 is selected. 0b10..Pulse counter input 2 is selected. 0b11..Pulse counter input 3 is selected.

LPTMR_CSR_TPS [6/6]

#define LPTMR_CSR_TPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

TPS - Timer Pin Select 0b00..Pulse counter input 0 is selected. 0b01..Pulse counter input 1 is selected. 0b10..Pulse counter input 2 is selected. 0b11..Pulse counter input 3 is selected.

LPTMR_IRQS

#define LPTMR_IRQS   { LPTMR0_IRQn }

Interrupt vectors for the LPTMR peripheral type

LPTMR_PSR_PBYP [1/5]

#define LPTMR_PSR_PBYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

PBYP - Prescaler Bypass 0b0..Prescaler/glitch filter is enabled. 0b1..Prescaler/glitch filter is bypassed.

LPTMR_PSR_PBYP [2/5]

#define LPTMR_PSR_PBYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

PBYP - Prescaler Bypass 0b0..Prescaler/glitch filter is enabled. 0b1..Prescaler/glitch filter is bypassed.

LPTMR_PSR_PBYP [3/5]

#define LPTMR_PSR_PBYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

PBYP - Prescaler Bypass 0b0..Prescaler/glitch filter is enabled. 0b1..Prescaler/glitch filter is bypassed.

LPTMR_PSR_PBYP [4/5]

#define LPTMR_PSR_PBYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

PBYP - Prescaler Bypass 0b0..Prescaler/glitch filter is enabled. 0b1..Prescaler/glitch filter is bypassed.

LPTMR_PSR_PBYP [5/5]

#define LPTMR_PSR_PBYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

PBYP - Prescaler Bypass 0b0..Prescaler/glitch filter is enabled. 0b1..Prescaler/glitch filter is bypassed.

LPTMR_PSR_PCS [1/6]

#define LPTMR_PSR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

PCS - Prescaler Clock Select 0b00..Prescaler/glitch filter clock 0 selected. 0b01..Prescaler/glitch filter clock 1 selected. 0b10..Prescaler/glitch filter clock 2 selected. 0b11..Prescaler/glitch filter clock 3 selected.

LPTMR_PSR_PCS [2/6]

#define LPTMR_PSR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)

PCS - Prescaler Clock Select 0b00..Prescaler/glitch filter clock 0 selected. 0b01..Prescaler/glitch filter clock 1 selected. 0b10..Prescaler/glitch filter clock 2 selected. 0b11..Prescaler/glitch filter clock 3 selected.

LPTMR_PSR_PCS [3/6]

#define LPTMR_PSR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

PCS - Prescaler Clock Select 0b00..Prescaler/glitch filter clock 0 selected. 0b01..Prescaler/glitch filter clock 1 selected. 0b10..Prescaler/glitch filter clock 2 selected. 0b11..Prescaler/glitch filter clock 3 selected.

LPTMR_PSR_PCS [4/6]

#define LPTMR_PSR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

PCS - Prescaler Clock Select 0b00..Prescaler/glitch filter clock 0 selected. 0b01..Prescaler/glitch filter clock 1 selected. 0b10..Prescaler/glitch filter clock 2 selected. 0b11..Prescaler/glitch filter clock 3 selected.

LPTMR_PSR_PCS [5/6]

#define LPTMR_PSR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

PCS - Prescaler Clock Select 0b00..Prescaler/glitch filter clock 0 selected. 0b01..Prescaler/glitch filter clock 1 selected. 0b10..Prescaler/glitch filter clock 2 selected. 0b11..Prescaler/glitch filter clock 3 selected.

LPTMR_PSR_PCS [6/6]

#define LPTMR_PSR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

PCS - Prescaler Clock Select 0b00..Prescaler/glitch filter clock 0 selected. 0b01..Prescaler/glitch filter clock 1 selected. 0b10..Prescaler/glitch filter clock 2 selected. 0b11..Prescaler/glitch filter clock 3 selected.

LPTMR_PSR_PRESCALE [1/6]

#define LPTMR_PSR_PRESCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)

PRESCALE - Prescale Value 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

LPTMR_PSR_PRESCALE [2/6]

#define LPTMR_PSR_PRESCALE

(

x

)

(((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)

PRESCALE - Prescale Value 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

LPTMR_PSR_PRESCALE [3/6]

#define LPTMR_PSR_PRESCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)

PRESCALE - Prescale Value 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

LPTMR_PSR_PRESCALE [4/6]

#define LPTMR_PSR_PRESCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)

PRESCALE - Prescale Value 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

LPTMR_PSR_PRESCALE [5/6]

#define LPTMR_PSR_PRESCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)

PRESCALE - Prescale Value 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

LPTMR_PSR_PRESCALE [6/6]

#define LPTMR_PSR_PRESCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)

PRESCALE - Prescale Value 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.