MCG Register Masks

Macros
#define	MCG_BASE   (0x40064000u)
#define	MCG   ((MCG_Type *)MCG_BASE)
#define	MCG_BASE_ADDRS   { MCG_BASE }
#define	MCG_BASE_PTRS   { MCG }
#define	MCG_IRQS   { MCG_IRQn }
#define	MCG_C2_EREFS_WIDTH   (MCG_C2_EREFS0_WIDTH)
#define	MCG_C2_HGO_WIDTH   (MCG_C2_HGO0_WIDTH)
#define	MCG_C2_RANGE_WIDTH   (MCG_C2_RANGE0_WIDTH)
#define	MCG_S_LOLS0_WIDTH   (MCG_S_LOLS_WIDTH)
#define	MCG_C6_CME_MASK   0x20u
#define	MCG_C6_CME_SHIFT   5
#define	MCG_C6_LOLIE_MASK   0x80u
#define	MCG_C6_LOLIE_SHIFT   7
#define	MCG_S_OSCINIT_MASK   0x2u
#define	MCG_S_OSCINIT_SHIFT   1
#define	MCG_S_LOCK_MASK   0x40u
#define	MCG_S_LOCK_SHIFT   6
#define	MCG_S_LOLS_MASK   0x80u
#define	MCG_S_LOLS_SHIFT   7
#define	MCG_ATC_ATMF_MASK   0x20u
#define	MCG_ATC_ATMF_SHIFT   5
#define	MCG_ATC_ATMS_MASK   0x40u
#define	MCG_ATC_ATMS_SHIFT   6
#define	MCG_ATC_ATME_MASK   0x80u
#define	MCG_ATC_ATME_SHIFT   7

C1 - MCG Control 1 Register
#define	MCG_C1_IREFSTEN_MASK   (0x1U)
#define	MCG_C1_IREFSTEN_SHIFT   (0U)
#define	MCG_C1_IREFSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
#define	MCG_C1_IRCLKEN_MASK   (0x2U)
#define	MCG_C1_IRCLKEN_SHIFT   (1U)
#define	MCG_C1_IRCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
#define	MCG_C1_IREFS_MASK   (0x4U)
#define	MCG_C1_IREFS_SHIFT   (2U)
#define	MCG_C1_IREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
#define	MCG_C1_FRDIV_MASK   (0x38U)
#define	MCG_C1_FRDIV_SHIFT   (3U)
#define	MCG_C1_FRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
#define	MCG_C1_CLKS_MASK   (0xC0U)
#define	MCG_C1_CLKS_SHIFT   (6U)
#define	MCG_C1_CLKS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
#define	MCG_C1_IREFSTEN_MASK   0x1u
#define	MCG_C1_IREFSTEN_SHIFT   0
#define	MCG_C1_IRCLKEN_MASK   0x2u
#define	MCG_C1_IRCLKEN_SHIFT   1
#define	MCG_C1_IREFS_MASK   0x4u
#define	MCG_C1_IREFS_SHIFT   2
#define	MCG_C1_FRDIV_MASK   0x38u
#define	MCG_C1_FRDIV_SHIFT   3
#define	MCG_C1_FRDIV(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
#define	MCG_C1_CLKS_MASK   0xC0u
#define	MCG_C1_CLKS_SHIFT   6
#define	MCG_C1_CLKS(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
#define	MCG_C1_IREFSTEN_MASK   (0x1U)
#define	MCG_C1_IREFSTEN_SHIFT   (0U)
#define	MCG_C1_IREFSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
#define	MCG_C1_IRCLKEN_MASK   (0x2U)
#define	MCG_C1_IRCLKEN_SHIFT   (1U)
#define	MCG_C1_IRCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
#define	MCG_C1_IREFS_MASK   (0x4U)
#define	MCG_C1_IREFS_SHIFT   (2U)
#define	MCG_C1_IREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
#define	MCG_C1_FRDIV_MASK   (0x38U)
#define	MCG_C1_FRDIV_SHIFT   (3U)
#define	MCG_C1_FRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
#define	MCG_C1_CLKS_MASK   (0xC0U)
#define	MCG_C1_CLKS_SHIFT   (6U)
#define	MCG_C1_CLKS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
#define	MCG_C1_IREFSTEN_MASK   (0x1U)
#define	MCG_C1_IREFSTEN_SHIFT   (0U)
#define	MCG_C1_IREFSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
#define	MCG_C1_IRCLKEN_MASK   (0x2U)
#define	MCG_C1_IRCLKEN_SHIFT   (1U)
#define	MCG_C1_IRCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
#define	MCG_C1_IREFS_MASK   (0x4U)
#define	MCG_C1_IREFS_SHIFT   (2U)
#define	MCG_C1_IREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
#define	MCG_C1_FRDIV_MASK   (0x38U)
#define	MCG_C1_FRDIV_SHIFT   (3U)
#define	MCG_C1_FRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
#define	MCG_C1_CLKS_MASK   (0xC0U)
#define	MCG_C1_CLKS_SHIFT   (6U)
#define	MCG_C1_CLKS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
#define	MCG_C1_IREFSTEN_MASK   (0x1U)
#define	MCG_C1_IREFSTEN_SHIFT   (0U)
#define	MCG_C1_IREFSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
#define	MCG_C1_IRCLKEN_MASK   (0x2U)
#define	MCG_C1_IRCLKEN_SHIFT   (1U)
#define	MCG_C1_IRCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
#define	MCG_C1_IREFS_MASK   (0x4U)
#define	MCG_C1_IREFS_SHIFT   (2U)
#define	MCG_C1_IREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
#define	MCG_C1_FRDIV_MASK   (0x38U)
#define	MCG_C1_FRDIV_SHIFT   (3U)
#define	MCG_C1_FRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
#define	MCG_C1_CLKS_MASK   (0xC0U)
#define	MCG_C1_CLKS_SHIFT   (6U)
#define	MCG_C1_CLKS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
#define	MCG_C1_IREFSTEN_MASK   (0x1U)
#define	MCG_C1_IREFSTEN_SHIFT   (0U)
#define	MCG_C1_IREFSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
#define	MCG_C1_IRCLKEN_MASK   (0x2U)
#define	MCG_C1_IRCLKEN_SHIFT   (1U)
#define	MCG_C1_IRCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
#define	MCG_C1_IREFS_MASK   (0x4U)
#define	MCG_C1_IREFS_SHIFT   (2U)
#define	MCG_C1_IREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
#define	MCG_C1_FRDIV_MASK   (0x38U)
#define	MCG_C1_FRDIV_SHIFT   (3U)
#define	MCG_C1_FRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
#define	MCG_C1_CLKS_MASK   (0xC0U)
#define	MCG_C1_CLKS_SHIFT   (6U)
#define	MCG_C1_CLKS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)

C2 - MCG Control 2 Register
#define	MCG_C2_IRCS_MASK   (0x1U)
#define	MCG_C2_IRCS_SHIFT   (0U)
#define	MCG_C2_IRCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
#define	MCG_C2_LP_MASK   (0x2U)
#define	MCG_C2_LP_SHIFT   (1U)
#define	MCG_C2_LP(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
#define	MCG_C2_LOCRE0_MASK   (0x80U)
#define	MCG_C2_LOCRE0_SHIFT   (7U)
#define	MCG_C2_LOCRE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
#define	MCG_C2_EREFS_MASK   (MCG_C2_EREFS0_MASK)
#define	MCG_C2_EREFS_SHIFT   (MCG_C2_EREFS0_SHIFT)
#define	MCG_C2_EREFS(x)   (MCG_C2_EREFS0(x))
#define	MCG_C2_HGO_MASK   (MCG_C2_HGO0_MASK)
#define	MCG_C2_HGO_SHIFT   (MCG_C2_HGO0_SHIFT)
#define	MCG_C2_HGO(x)   (MCG_C2_HGO0(x))
#define	MCG_C2_RANGE_MASK   (MCG_C2_RANGE0_MASK)
#define	MCG_C2_RANGE_SHIFT   (MCG_C2_RANGE0_SHIFT)
#define	MCG_C2_RANGE(x)   (MCG_C2_RANGE0(x))
#define	MCG_C2_IRCS_MASK   0x1u
#define	MCG_C2_IRCS_SHIFT   0
#define	MCG_C2_LP_MASK   0x2u
#define	MCG_C2_LP_SHIFT   1
#define	MCG_C2_EREFS_MASK   0x4u
#define	MCG_C2_EREFS_SHIFT   2
#define	MCG_C2_HGO_MASK   0x8u
#define	MCG_C2_HGO_SHIFT   3
#define	MCG_C2_RANGE_MASK   0x30u
#define	MCG_C2_RANGE_SHIFT   4
#define	MCG_C2_RANGE(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
#define	MCG_C2_IRCS_MASK   (0x1U)
#define	MCG_C2_IRCS_SHIFT   (0U)
#define	MCG_C2_IRCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
#define	MCG_C2_LP_MASK   (0x2U)
#define	MCG_C2_LP_SHIFT   (1U)
#define	MCG_C2_LP(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
#define	MCG_C2_EREFS_MASK   (0x4U)
#define	MCG_C2_EREFS_SHIFT   (2U)
#define	MCG_C2_EREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
#define	MCG_C2_HGO_MASK   (0x8U)
#define	MCG_C2_HGO_SHIFT   (3U)
#define	MCG_C2_HGO(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
#define	MCG_C2_RANGE_MASK   (0x30U)
#define	MCG_C2_RANGE_SHIFT   (4U)
#define	MCG_C2_RANGE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
#define	MCG_C2_FCFTRIM_MASK   (0x40U)
#define	MCG_C2_FCFTRIM_SHIFT   (6U)
#define	MCG_C2_FCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
#define	MCG_C2_LOCRE0_MASK   (0x80U)
#define	MCG_C2_LOCRE0_SHIFT   (7U)
#define	MCG_C2_LOCRE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
#define	MCG_C2_IRCS_MASK   (0x1U)
#define	MCG_C2_IRCS_SHIFT   (0U)
#define	MCG_C2_IRCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
#define	MCG_C2_LP_MASK   (0x2U)
#define	MCG_C2_LP_SHIFT   (1U)
#define	MCG_C2_LP(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
#define	MCG_C2_EREFS_MASK   (0x4U)
#define	MCG_C2_EREFS_SHIFT   (2U)
#define	MCG_C2_EREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
#define	MCG_C2_HGO_MASK   (0x8U)
#define	MCG_C2_HGO_SHIFT   (3U)
#define	MCG_C2_HGO(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
#define	MCG_C2_RANGE_MASK   (0x30U)
#define	MCG_C2_RANGE_SHIFT   (4U)
#define	MCG_C2_RANGE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
#define	MCG_C2_FCFTRIM_MASK   (0x40U)
#define	MCG_C2_FCFTRIM_SHIFT   (6U)
#define	MCG_C2_FCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
#define	MCG_C2_LOCRE0_MASK   (0x80U)
#define	MCG_C2_LOCRE0_SHIFT   (7U)
#define	MCG_C2_LOCRE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
#define	MCG_C2_IRCS_MASK   (0x1U)
#define	MCG_C2_IRCS_SHIFT   (0U)
#define	MCG_C2_IRCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
#define	MCG_C2_LP_MASK   (0x2U)
#define	MCG_C2_LP_SHIFT   (1U)
#define	MCG_C2_LP(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
#define	MCG_C2_EREFS_MASK   (0x4U)
#define	MCG_C2_EREFS_SHIFT   (2U)
#define	MCG_C2_EREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
#define	MCG_C2_HGO_MASK   (0x8U)
#define	MCG_C2_HGO_SHIFT   (3U)
#define	MCG_C2_HGO(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
#define	MCG_C2_RANGE_MASK   (0x30U)
#define	MCG_C2_RANGE_SHIFT   (4U)
#define	MCG_C2_RANGE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
#define	MCG_C2_FCFTRIM_MASK   (0x40U)
#define	MCG_C2_FCFTRIM_SHIFT   (6U)
#define	MCG_C2_FCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
#define	MCG_C2_LOCRE0_MASK   (0x80U)
#define	MCG_C2_LOCRE0_SHIFT   (7U)
#define	MCG_C2_LOCRE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
#define	MCG_C2_IRCS_MASK   (0x1U)
#define	MCG_C2_IRCS_SHIFT   (0U)
#define	MCG_C2_IRCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
#define	MCG_C2_LP_MASK   (0x2U)
#define	MCG_C2_LP_SHIFT   (1U)
#define	MCG_C2_LP(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
#define	MCG_C2_EREFS_MASK   (0x4U)
#define	MCG_C2_EREFS_SHIFT   (2U)
#define	MCG_C2_EREFS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
#define	MCG_C2_HGO_MASK   (0x8U)
#define	MCG_C2_HGO_SHIFT   (3U)
#define	MCG_C2_HGO(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
#define	MCG_C2_RANGE_MASK   (0x30U)
#define	MCG_C2_RANGE_SHIFT   (4U)
#define	MCG_C2_RANGE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
#define	MCG_C2_FCFTRIM_MASK   (0x40U)
#define	MCG_C2_FCFTRIM_SHIFT   (6U)
#define	MCG_C2_FCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
#define	MCG_C2_LOCRE0_MASK   (0x80U)
#define	MCG_C2_LOCRE0_SHIFT   (7U)
#define	MCG_C2_LOCRE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)

C2 - MCG Control 2 Register
#define	MCG_C2_EREFS0_MASK   (0x4U)
#define	MCG_C2_EREFS0_SHIFT   (2U)
#define	MCG_C2_EREFS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
#define	MCG_C2_HGO0_MASK   (0x8U)
#define	MCG_C2_HGO0_SHIFT   (3U)
#define	MCG_C2_HGO0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
#define	MCG_C2_RANGE0_MASK   (0x30U)
#define	MCG_C2_RANGE0_SHIFT   (4U)
#define	MCG_C2_RANGE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)

C3 - MCG Control 3 Register
#define	MCG_C3_SCTRIM_MASK   (0xFFU)
#define	MCG_C3_SCTRIM_SHIFT   (0U)
#define	MCG_C3_SCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
#define	MCG_C3_SCTRIM_MASK   0xFFu
#define	MCG_C3_SCTRIM_SHIFT   0
#define	MCG_C3_SCTRIM(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
#define	MCG_C3_SCTRIM_MASK   (0xFFU)
#define	MCG_C3_SCTRIM_SHIFT   (0U)
#define	MCG_C3_SCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
#define	MCG_C3_SCTRIM_MASK   (0xFFU)
#define	MCG_C3_SCTRIM_SHIFT   (0U)
#define	MCG_C3_SCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
#define	MCG_C3_SCTRIM_MASK   (0xFFU)
#define	MCG_C3_SCTRIM_SHIFT   (0U)
#define	MCG_C3_SCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
#define	MCG_C3_SCTRIM_MASK   (0xFFU)
#define	MCG_C3_SCTRIM_SHIFT   (0U)
#define	MCG_C3_SCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)

C4 - MCG Control 4 Register
#define	MCG_C4_SCFTRIM_MASK   (0x1U)
#define	MCG_C4_SCFTRIM_SHIFT   (0U)
#define	MCG_C4_SCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
#define	MCG_C4_FCTRIM_MASK   (0x1EU)
#define	MCG_C4_FCTRIM_SHIFT   (1U)
#define	MCG_C4_FCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
#define	MCG_C4_DRST_DRS_MASK   (0x60U)
#define	MCG_C4_DRST_DRS_SHIFT   (5U)
#define	MCG_C4_DRST_DRS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
#define	MCG_C4_DMX32_MASK   (0x80U)
#define	MCG_C4_DMX32_SHIFT   (7U)
#define	MCG_C4_DMX32(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
#define	MCG_C4_SCFTRIM_MASK   0x1u
#define	MCG_C4_SCFTRIM_SHIFT   0
#define	MCG_C4_FCTRIM_MASK   0x1Eu
#define	MCG_C4_FCTRIM_SHIFT   1
#define	MCG_C4_FCTRIM(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
#define	MCG_C4_DRST_DRS_MASK   0x60u
#define	MCG_C4_DRST_DRS_SHIFT   5
#define	MCG_C4_DRST_DRS(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
#define	MCG_C4_DMX32_MASK   0x80u
#define	MCG_C4_DMX32_SHIFT   7
#define	MCG_C4_SCFTRIM_MASK   (0x1U)
#define	MCG_C4_SCFTRIM_SHIFT   (0U)
#define	MCG_C4_SCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
#define	MCG_C4_FCTRIM_MASK   (0x1EU)
#define	MCG_C4_FCTRIM_SHIFT   (1U)
#define	MCG_C4_FCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
#define	MCG_C4_DRST_DRS_MASK   (0x60U)
#define	MCG_C4_DRST_DRS_SHIFT   (5U)
#define	MCG_C4_DRST_DRS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
#define	MCG_C4_DMX32_MASK   (0x80U)
#define	MCG_C4_DMX32_SHIFT   (7U)
#define	MCG_C4_DMX32(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
#define	MCG_C4_SCFTRIM_MASK   (0x1U)
#define	MCG_C4_SCFTRIM_SHIFT   (0U)
#define	MCG_C4_SCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
#define	MCG_C4_FCTRIM_MASK   (0x1EU)
#define	MCG_C4_FCTRIM_SHIFT   (1U)
#define	MCG_C4_FCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
#define	MCG_C4_DRST_DRS_MASK   (0x60U)
#define	MCG_C4_DRST_DRS_SHIFT   (5U)
#define	MCG_C4_DRST_DRS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
#define	MCG_C4_DMX32_MASK   (0x80U)
#define	MCG_C4_DMX32_SHIFT   (7U)
#define	MCG_C4_DMX32(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
#define	MCG_C4_SCFTRIM_MASK   (0x1U)
#define	MCG_C4_SCFTRIM_SHIFT   (0U)
#define	MCG_C4_SCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
#define	MCG_C4_FCTRIM_MASK   (0x1EU)
#define	MCG_C4_FCTRIM_SHIFT   (1U)
#define	MCG_C4_FCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
#define	MCG_C4_DRST_DRS_MASK   (0x60U)
#define	MCG_C4_DRST_DRS_SHIFT   (5U)
#define	MCG_C4_DRST_DRS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
#define	MCG_C4_DMX32_MASK   (0x80U)
#define	MCG_C4_DMX32_SHIFT   (7U)
#define	MCG_C4_DMX32(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
#define	MCG_C4_SCFTRIM_MASK   (0x1U)
#define	MCG_C4_SCFTRIM_SHIFT   (0U)
#define	MCG_C4_SCFTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
#define	MCG_C4_FCTRIM_MASK   (0x1EU)
#define	MCG_C4_FCTRIM_SHIFT   (1U)
#define	MCG_C4_FCTRIM(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
#define	MCG_C4_DRST_DRS_MASK   (0x60U)
#define	MCG_C4_DRST_DRS_SHIFT   (5U)
#define	MCG_C4_DRST_DRS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
#define	MCG_C4_DMX32_MASK   (0x80U)
#define	MCG_C4_DMX32_SHIFT   (7U)
#define	MCG_C4_DMX32(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)

C5 - MCG Control 5 Register
#define	MCG_C5_PRDIV0_MASK   (0x1FU)
#define	MCG_C5_PRDIV0_SHIFT   (0U)
#define	MCG_C5_PRDIV0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
#define	MCG_C5_PLLSTEN0_MASK   (0x20U)
#define	MCG_C5_PLLSTEN0_SHIFT   (5U)
#define	MCG_C5_PLLSTEN0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
#define	MCG_C5_PLLCLKEN0_MASK   (0x40U)
#define	MCG_C5_PLLCLKEN0_SHIFT   (6U)
#define	MCG_C5_PLLCLKEN0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
#define	MCG_C5_PRDIV0_MASK   (0x1FU)
#define	MCG_C5_PRDIV0_SHIFT   (0U)
#define	MCG_C5_PRDIV0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
#define	MCG_C5_PLLSTEN0_MASK   (0x20U)
#define	MCG_C5_PLLSTEN0_SHIFT   (5U)
#define	MCG_C5_PLLSTEN0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
#define	MCG_C5_PLLCLKEN0_MASK   (0x40U)
#define	MCG_C5_PLLCLKEN0_SHIFT   (6U)
#define	MCG_C5_PLLCLKEN0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)

C6 - MCG Control 6 Register
#define	MCG_C6_VDIV0_MASK   (0x1FU)
#define	MCG_C6_VDIV0_SHIFT   (0U)
#define	MCG_C6_VDIV0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
#define	MCG_C6_VDIV0_MASK   (0x1FU)
#define	MCG_C6_VDIV0_SHIFT   (0U)
#define	MCG_C6_VDIV0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)

C6 - MCG Control 6 Register
#define	MCG_C6_CME0_MASK   (0x20U)
#define	MCG_C6_CME0_SHIFT   (5U)
#define	MCG_C6_CME0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
#define	MCG_C6_PLLS_MASK   (0x40U)
#define	MCG_C6_PLLS_SHIFT   (6U)
#define	MCG_C6_PLLS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
#define	MCG_C6_LOLIE0_MASK   (0x80U)
#define	MCG_C6_LOLIE0_SHIFT   (7U)
#define	MCG_C6_LOLIE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
#define	MCG_C6_VDIV_MASK   0x1Fu
#define	MCG_C6_VDIV_SHIFT   0
#define	MCG_C6_VDIV(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV_SHIFT))&MCG_C6_VDIV_MASK)
#define	MCG_C6_PLLS_MASK   0x40u
#define	MCG_C6_PLLS_SHIFT   6
#define	MCG_C6_CME0_MASK   (0x20U)
#define	MCG_C6_CME0_SHIFT   (5U)
#define	MCG_C6_CME0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
#define	MCG_C6_PLLS_MASK   (0x40U)
#define	MCG_C6_PLLS_SHIFT   (6U)
#define	MCG_C6_PLLS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
#define	MCG_C6_LOLIE0_MASK   (0x80U)
#define	MCG_C6_LOLIE0_SHIFT   (7U)
#define	MCG_C6_LOLIE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
#define	MCG_C6_VDIV_MASK   (0x1FU)
#define	MCG_C6_VDIV_SHIFT   (0U)
#define	MCG_C6_VDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
#define	MCG_C6_CME0_MASK   (0x20U)
#define	MCG_C6_CME0_SHIFT   (5U)
#define	MCG_C6_CME0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
#define	MCG_C6_PLLS_MASK   (0x40U)
#define	MCG_C6_PLLS_SHIFT   (6U)
#define	MCG_C6_PLLS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
#define	MCG_C6_LOLIE0_MASK   (0x80U)
#define	MCG_C6_LOLIE0_SHIFT   (7U)
#define	MCG_C6_LOLIE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
#define	MCG_C6_VDIV_MASK   (0x1FU)
#define	MCG_C6_VDIV_SHIFT   (0U)
#define	MCG_C6_VDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
#define	MCG_C6_CME0_MASK   (0x20U)
#define	MCG_C6_CME0_SHIFT   (5U)
#define	MCG_C6_CME0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
#define	MCG_C6_PLLS_MASK   (0x40U)
#define	MCG_C6_PLLS_SHIFT   (6U)
#define	MCG_C6_PLLS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
#define	MCG_C6_LOLIE0_MASK   (0x80U)
#define	MCG_C6_LOLIE0_SHIFT   (7U)
#define	MCG_C6_LOLIE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
#define	MCG_C6_VDIV_MASK   (0x1FU)
#define	MCG_C6_VDIV_SHIFT   (0U)
#define	MCG_C6_VDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
#define	MCG_C6_CME0_MASK   (0x20U)
#define	MCG_C6_CME0_SHIFT   (5U)
#define	MCG_C6_CME0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
#define	MCG_C6_PLLS_MASK   (0x40U)
#define	MCG_C6_PLLS_SHIFT   (6U)
#define	MCG_C6_PLLS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
#define	MCG_C6_LOLIE0_MASK   (0x80U)
#define	MCG_C6_LOLIE0_SHIFT   (7U)
#define	MCG_C6_LOLIE0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)

S - MCG Status Register
#define	MCG_S_IRCST_MASK   (0x1U)
#define	MCG_S_IRCST_SHIFT   (0U)
#define	MCG_S_IRCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
#define	MCG_S_OSCINIT0_MASK   (0x2U)
#define	MCG_S_OSCINIT0_SHIFT   (1U)
#define	MCG_S_OSCINIT0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
#define	MCG_S_CLKST_MASK   (0xCU)
#define	MCG_S_CLKST_SHIFT   (2U)
#define	MCG_S_CLKST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
#define	MCG_S_IREFST_MASK   (0x10U)
#define	MCG_S_IREFST_SHIFT   (4U)
#define	MCG_S_IREFST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
#define	MCG_S_PLLST_MASK   (0x20U)
#define	MCG_S_PLLST_SHIFT   (5U)
#define	MCG_S_PLLST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
#define	MCG_S_LOCK0_MASK   (0x40U)
#define	MCG_S_LOCK0_SHIFT   (6U)
#define	MCG_S_LOCK0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
#define	MCG_S_LOLS0_MASK   (MCG_S_LOLS_MASK)
#define	MCG_S_LOLS0_SHIFT   (MCG_S_LOLS_SHIFT)
#define	MCG_S_LOLS0(x)   (MCG_S_LOLS(x))
#define	MCG_S_IRCST_MASK   0x1u
#define	MCG_S_IRCST_SHIFT   0
#define	MCG_S_CLKST_MASK   0xCu
#define	MCG_S_CLKST_SHIFT   2
#define	MCG_S_CLKST(x)   (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
#define	MCG_S_IREFST_MASK   0x10u
#define	MCG_S_IREFST_SHIFT   4
#define	MCG_S_PLLST_MASK   0x20u
#define	MCG_S_PLLST_SHIFT   5
#define	MCG_S_IRCST_MASK   (0x1U)
#define	MCG_S_IRCST_SHIFT   (0U)
#define	MCG_S_IRCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
#define	MCG_S_OSCINIT0_MASK   (0x2U)
#define	MCG_S_OSCINIT0_SHIFT   (1U)
#define	MCG_S_OSCINIT0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
#define	MCG_S_CLKST_MASK   (0xCU)
#define	MCG_S_CLKST_SHIFT   (2U)
#define	MCG_S_CLKST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
#define	MCG_S_IREFST_MASK   (0x10U)
#define	MCG_S_IREFST_SHIFT   (4U)
#define	MCG_S_IREFST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
#define	MCG_S_PLLST_MASK   (0x20U)
#define	MCG_S_PLLST_SHIFT   (5U)
#define	MCG_S_PLLST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
#define	MCG_S_LOCK0_MASK   (0x40U)
#define	MCG_S_LOCK0_SHIFT   (6U)
#define	MCG_S_LOCK0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
#define	MCG_S_LOLS0_MASK   (0x80U)
#define	MCG_S_LOLS0_SHIFT   (7U)
#define	MCG_S_LOLS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
#define	MCG_S_IRCST_MASK   (0x1U)
#define	MCG_S_IRCST_SHIFT   (0U)
#define	MCG_S_IRCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
#define	MCG_S_OSCINIT0_MASK   (0x2U)
#define	MCG_S_OSCINIT0_SHIFT   (1U)
#define	MCG_S_OSCINIT0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
#define	MCG_S_CLKST_MASK   (0xCU)
#define	MCG_S_CLKST_SHIFT   (2U)
#define	MCG_S_CLKST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
#define	MCG_S_IREFST_MASK   (0x10U)
#define	MCG_S_IREFST_SHIFT   (4U)
#define	MCG_S_IREFST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
#define	MCG_S_PLLST_MASK   (0x20U)
#define	MCG_S_PLLST_SHIFT   (5U)
#define	MCG_S_PLLST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
#define	MCG_S_LOCK0_MASK   (0x40U)
#define	MCG_S_LOCK0_SHIFT   (6U)
#define	MCG_S_LOCK0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
#define	MCG_S_LOLS0_MASK   (0x80U)
#define	MCG_S_LOLS0_SHIFT   (7U)
#define	MCG_S_LOLS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
#define	MCG_S_IRCST_MASK   (0x1U)
#define	MCG_S_IRCST_SHIFT   (0U)
#define	MCG_S_IRCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
#define	MCG_S_OSCINIT0_MASK   (0x2U)
#define	MCG_S_OSCINIT0_SHIFT   (1U)
#define	MCG_S_OSCINIT0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
#define	MCG_S_CLKST_MASK   (0xCU)
#define	MCG_S_CLKST_SHIFT   (2U)
#define	MCG_S_CLKST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
#define	MCG_S_IREFST_MASK   (0x10U)
#define	MCG_S_IREFST_SHIFT   (4U)
#define	MCG_S_IREFST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
#define	MCG_S_PLLST_MASK   (0x20U)
#define	MCG_S_PLLST_SHIFT   (5U)
#define	MCG_S_PLLST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
#define	MCG_S_LOCK0_MASK   (0x40U)
#define	MCG_S_LOCK0_SHIFT   (6U)
#define	MCG_S_LOCK0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
#define	MCG_S_LOLS0_MASK   (0x80U)
#define	MCG_S_LOLS0_SHIFT   (7U)
#define	MCG_S_LOLS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
#define	MCG_S_IRCST_MASK   (0x1U)
#define	MCG_S_IRCST_SHIFT   (0U)
#define	MCG_S_IRCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
#define	MCG_S_OSCINIT0_MASK   (0x2U)
#define	MCG_S_OSCINIT0_SHIFT   (1U)
#define	MCG_S_OSCINIT0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
#define	MCG_S_CLKST_MASK   (0xCU)
#define	MCG_S_CLKST_SHIFT   (2U)
#define	MCG_S_CLKST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
#define	MCG_S_IREFST_MASK   (0x10U)
#define	MCG_S_IREFST_SHIFT   (4U)
#define	MCG_S_IREFST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
#define	MCG_S_PLLST_MASK   (0x20U)
#define	MCG_S_PLLST_SHIFT   (5U)
#define	MCG_S_PLLST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
#define	MCG_S_LOCK0_MASK   (0x40U)
#define	MCG_S_LOCK0_SHIFT   (6U)
#define	MCG_S_LOCK0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
#define	MCG_S_LOLS0_MASK   (0x80U)
#define	MCG_S_LOLS0_SHIFT   (7U)
#define	MCG_S_LOLS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)

S - MCG Status Register
#define	MCG_S_LOLS_MASK   (0x80U)
#define	MCG_S_LOLS_SHIFT   (7U)
#define	MCG_S_LOLS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS_SHIFT)) & MCG_S_LOLS_MASK)

SC - MCG Status and Control Register
#define	MCG_SC_LOCS0_MASK   (0x1U)
#define	MCG_SC_LOCS0_SHIFT   (0U)
#define	MCG_SC_LOCS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
#define	MCG_SC_FCRDIV_MASK   (0xEU)
#define	MCG_SC_FCRDIV_SHIFT   (1U)
#define	MCG_SC_FCRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
#define	MCG_SC_FLTPRSRV_MASK   (0x10U)
#define	MCG_SC_FLTPRSRV_SHIFT   (4U)
#define	MCG_SC_FLTPRSRV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
#define	MCG_SC_ATMF_MASK   (0x20U)
#define	MCG_SC_ATMF_SHIFT   (5U)
#define	MCG_SC_ATMF(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
#define	MCG_SC_ATMS_MASK   (0x40U)
#define	MCG_SC_ATMS_SHIFT   (6U)
#define	MCG_SC_ATMS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
#define	MCG_SC_ATME_MASK   (0x80U)
#define	MCG_SC_ATME_SHIFT   (7U)
#define	MCG_SC_ATME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
#define	MCG_SC_LOCS0_MASK   (0x1U)
#define	MCG_SC_LOCS0_SHIFT   (0U)
#define	MCG_SC_LOCS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
#define	MCG_SC_FCRDIV_MASK   (0xEU)
#define	MCG_SC_FCRDIV_SHIFT   (1U)
#define	MCG_SC_FCRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
#define	MCG_SC_FLTPRSRV_MASK   (0x10U)
#define	MCG_SC_FLTPRSRV_SHIFT   (4U)
#define	MCG_SC_FLTPRSRV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
#define	MCG_SC_ATMF_MASK   (0x20U)
#define	MCG_SC_ATMF_SHIFT   (5U)
#define	MCG_SC_ATMF(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
#define	MCG_SC_ATMS_MASK   (0x40U)
#define	MCG_SC_ATMS_SHIFT   (6U)
#define	MCG_SC_ATMS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
#define	MCG_SC_ATME_MASK   (0x80U)
#define	MCG_SC_ATME_SHIFT   (7U)
#define	MCG_SC_ATME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
#define	MCG_SC_LOCS0_MASK   (0x1U)
#define	MCG_SC_LOCS0_SHIFT   (0U)
#define	MCG_SC_LOCS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
#define	MCG_SC_FCRDIV_MASK   (0xEU)
#define	MCG_SC_FCRDIV_SHIFT   (1U)
#define	MCG_SC_FCRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
#define	MCG_SC_FLTPRSRV_MASK   (0x10U)
#define	MCG_SC_FLTPRSRV_SHIFT   (4U)
#define	MCG_SC_FLTPRSRV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
#define	MCG_SC_ATMF_MASK   (0x20U)
#define	MCG_SC_ATMF_SHIFT   (5U)
#define	MCG_SC_ATMF(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
#define	MCG_SC_ATMS_MASK   (0x40U)
#define	MCG_SC_ATMS_SHIFT   (6U)
#define	MCG_SC_ATMS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
#define	MCG_SC_ATME_MASK   (0x80U)
#define	MCG_SC_ATME_SHIFT   (7U)
#define	MCG_SC_ATME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
#define	MCG_SC_LOCS0_MASK   (0x1U)
#define	MCG_SC_LOCS0_SHIFT   (0U)
#define	MCG_SC_LOCS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
#define	MCG_SC_FCRDIV_MASK   (0xEU)
#define	MCG_SC_FCRDIV_SHIFT   (1U)
#define	MCG_SC_FCRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
#define	MCG_SC_FLTPRSRV_MASK   (0x10U)
#define	MCG_SC_FLTPRSRV_SHIFT   (4U)
#define	MCG_SC_FLTPRSRV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
#define	MCG_SC_ATMF_MASK   (0x20U)
#define	MCG_SC_ATMF_SHIFT   (5U)
#define	MCG_SC_ATMF(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
#define	MCG_SC_ATMS_MASK   (0x40U)
#define	MCG_SC_ATMS_SHIFT   (6U)
#define	MCG_SC_ATMS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
#define	MCG_SC_ATME_MASK   (0x80U)
#define	MCG_SC_ATME_SHIFT   (7U)
#define	MCG_SC_ATME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
#define	MCG_SC_LOCS0_MASK   (0x1U)
#define	MCG_SC_LOCS0_SHIFT   (0U)
#define	MCG_SC_LOCS0(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
#define	MCG_SC_FCRDIV_MASK   (0xEU)
#define	MCG_SC_FCRDIV_SHIFT   (1U)
#define	MCG_SC_FCRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
#define	MCG_SC_FLTPRSRV_MASK   (0x10U)
#define	MCG_SC_FLTPRSRV_SHIFT   (4U)
#define	MCG_SC_FLTPRSRV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
#define	MCG_SC_ATMF_MASK   (0x20U)
#define	MCG_SC_ATMF_SHIFT   (5U)
#define	MCG_SC_ATMF(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
#define	MCG_SC_ATMS_MASK   (0x40U)
#define	MCG_SC_ATMS_SHIFT   (6U)
#define	MCG_SC_ATMS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
#define	MCG_SC_ATME_MASK   (0x80U)
#define	MCG_SC_ATME_SHIFT   (7U)
#define	MCG_SC_ATME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)

ATCVH - MCG Auto Trim Compare Value High Register
#define	MCG_ATCVH_ATCVH_MASK   (0xFFU)
#define	MCG_ATCVH_ATCVH_SHIFT   (0U)
#define	MCG_ATCVH_ATCVH(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
#define	MCG_ATCVH_ATCVH_MASK   0xFFu
#define	MCG_ATCVH_ATCVH_SHIFT   0
#define	MCG_ATCVH_ATCVH(x)   (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
#define	MCG_ATCVH_ATCVH_MASK   (0xFFU)
#define	MCG_ATCVH_ATCVH_SHIFT   (0U)
#define	MCG_ATCVH_ATCVH(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
#define	MCG_ATCVH_ATCVH_MASK   (0xFFU)
#define	MCG_ATCVH_ATCVH_SHIFT   (0U)
#define	MCG_ATCVH_ATCVH(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
#define	MCG_ATCVH_ATCVH_MASK   (0xFFU)
#define	MCG_ATCVH_ATCVH_SHIFT   (0U)
#define	MCG_ATCVH_ATCVH(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
#define	MCG_ATCVH_ATCVH_MASK   (0xFFU)
#define	MCG_ATCVH_ATCVH_SHIFT   (0U)
#define	MCG_ATCVH_ATCVH(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)

ATCVL - MCG Auto Trim Compare Value Low Register
#define	MCG_ATCVL_ATCVL_MASK   (0xFFU)
#define	MCG_ATCVL_ATCVL_SHIFT   (0U)
#define	MCG_ATCVL_ATCVL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
#define	MCG_ATCVL_ATCVL_MASK   0xFFu
#define	MCG_ATCVL_ATCVL_SHIFT   0
#define	MCG_ATCVL_ATCVL(x)   (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
#define	MCG_ATCVL_ATCVL_MASK   (0xFFU)
#define	MCG_ATCVL_ATCVL_SHIFT   (0U)
#define	MCG_ATCVL_ATCVL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
#define	MCG_ATCVL_ATCVL_MASK   (0xFFU)
#define	MCG_ATCVL_ATCVL_SHIFT   (0U)
#define	MCG_ATCVL_ATCVL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
#define	MCG_ATCVL_ATCVL_MASK   (0xFFU)
#define	MCG_ATCVL_ATCVL_SHIFT   (0U)
#define	MCG_ATCVL_ATCVL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
#define	MCG_ATCVL_ATCVL_MASK   (0xFFU)
#define	MCG_ATCVL_ATCVL_SHIFT   (0U)
#define	MCG_ATCVL_ATCVL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)

C7 - MCG Control 7 Register
#define	MCG_C7_OSCSEL_MASK   (0x1U)
#define	MCG_C7_OSCSEL_SHIFT   (0U)
#define	MCG_C7_OSCSEL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
#define	MCG_C7_OSCSEL_MASK   (0x3U)
#define	MCG_C7_OSCSEL_SHIFT   (0U)
#define	MCG_C7_OSCSEL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
#define	MCG_C7_OSCSEL_MASK   (0x3U)
#define	MCG_C7_OSCSEL_SHIFT   (0U)
#define	MCG_C7_OSCSEL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
#define	MCG_C7_OSCSEL_MASK   (0x3U)
#define	MCG_C7_OSCSEL_SHIFT   (0U)
#define	MCG_C7_OSCSEL(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)

C8 - MCG Control 8 Register
#define	MCG_C8_LOCS1_MASK   (0x1U)
#define	MCG_C8_LOCS1_SHIFT   (0U)
#define	MCG_C8_LOCS1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
#define	MCG_C8_CME1_MASK   (0x20U)
#define	MCG_C8_CME1_SHIFT   (5U)
#define	MCG_C8_CME1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
#define	MCG_C8_LOCRE1_MASK   (0x80U)
#define	MCG_C8_LOCRE1_SHIFT   (7U)
#define	MCG_C8_LOCRE1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
#define	MCG_C8_LOCS1_MASK   (0x1U)
#define	MCG_C8_LOCS1_SHIFT   (0U)
#define	MCG_C8_LOCS1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
#define	MCG_C8_CME1_MASK   (0x20U)
#define	MCG_C8_CME1_SHIFT   (5U)
#define	MCG_C8_CME1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
#define	MCG_C8_LOCRE1_MASK   (0x80U)
#define	MCG_C8_LOCRE1_SHIFT   (7U)
#define	MCG_C8_LOCRE1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
#define	MCG_C8_LOCS1_MASK   (0x1U)
#define	MCG_C8_LOCS1_SHIFT   (0U)
#define	MCG_C8_LOCS1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
#define	MCG_C8_CME1_MASK   (0x20U)
#define	MCG_C8_CME1_SHIFT   (5U)
#define	MCG_C8_CME1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
#define	MCG_C8_LOCRE1_MASK   (0x80U)
#define	MCG_C8_LOCRE1_SHIFT   (7U)
#define	MCG_C8_LOCRE1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
#define	MCG_C8_LOCS1_MASK   (0x1U)
#define	MCG_C8_LOCS1_SHIFT   (0U)
#define	MCG_C8_LOCS1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
#define	MCG_C8_CME1_MASK   (0x20U)
#define	MCG_C8_CME1_SHIFT   (5U)
#define	MCG_C8_CME1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
#define	MCG_C8_LOCRE1_MASK   (0x80U)
#define	MCG_C8_LOCRE1_SHIFT   (7U)
#define	MCG_C8_LOCRE1(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)

C8 - MCG Control 8 Register
#define	MCG_C8_LOLRE_MASK   (0x40U)
#define	MCG_C8_LOLRE_SHIFT   (6U)
#define	MCG_C8_LOLRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
#define	MCG_C8_LOLRE_MASK   (0x40U)
#define	MCG_C8_LOLRE_SHIFT   (6U)
#define	MCG_C8_LOLRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
#define	MCG_C8_LOLRE_MASK   (0x40U)
#define	MCG_C8_LOLRE_SHIFT   (6U)
#define	MCG_C8_LOLRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
#define	MCG_C8_LOLRE_MASK   (0x40U)
#define	MCG_C8_LOLRE_SHIFT   (6U)
#define	MCG_C8_LOLRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
#define	MCG_C8_LOLRE_MASK   (0x40U)
#define	MCG_C8_LOLRE_SHIFT   (6U)
#define	MCG_C8_LOLRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)

C5 - MCG Control 5 Register
#define	MCG_C5_PRDIV_MASK   0x1Fu
#define	MCG_C5_PRDIV_SHIFT   0
#define	MCG_C5_PRDIV(x)   (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV_SHIFT))&MCG_C5_PRDIV_MASK)
#define	MCG_C5_PLLSTEN_MASK   0x20u
#define	MCG_C5_PLLSTEN_SHIFT   5
#define	MCG_C5_PLLCLKEN_MASK   0x40u
#define	MCG_C5_PLLCLKEN_SHIFT   6
#define	MCG_C5_PRDIV_MASK   (0x7U)
#define	MCG_C5_PRDIV_SHIFT   (0U)
#define	MCG_C5_PRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
#define	MCG_C5_PLLSTEN_MASK   (0x20U)
#define	MCG_C5_PLLSTEN_SHIFT   (5U)
#define	MCG_C5_PLLSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
#define	MCG_C5_PLLCLKEN_MASK   (0x40U)
#define	MCG_C5_PLLCLKEN_SHIFT   (6U)
#define	MCG_C5_PLLCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
#define	MCG_C5_PRDIV_MASK   (0x7U)
#define	MCG_C5_PRDIV_SHIFT   (0U)
#define	MCG_C5_PRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
#define	MCG_C5_PLLSTEN_MASK   (0x20U)
#define	MCG_C5_PLLSTEN_SHIFT   (5U)
#define	MCG_C5_PLLSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
#define	MCG_C5_PLLCLKEN_MASK   (0x40U)
#define	MCG_C5_PLLCLKEN_SHIFT   (6U)
#define	MCG_C5_PLLCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
#define	MCG_C5_PRDIV_MASK   (0x7U)
#define	MCG_C5_PRDIV_SHIFT   (0U)
#define	MCG_C5_PRDIV(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
#define	MCG_C5_PLLSTEN_MASK   (0x20U)
#define	MCG_C5_PLLSTEN_SHIFT   (5U)
#define	MCG_C5_PLLSTEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
#define	MCG_C5_PLLCLKEN_MASK   (0x40U)
#define	MCG_C5_PLLCLKEN_SHIFT   (6U)
#define	MCG_C5_PLLCLKEN(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)

C9 - MCG Control 9 Register
#define	MCG_C9_EXT_PLL_LOCS_MASK   (0x1U)
#define	MCG_C9_EXT_PLL_LOCS_SHIFT   (0U)
#define	MCG_C9_EXT_PLL_LOCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
#define	MCG_C9_PLL_LOCRE_MASK   (0x10U)
#define	MCG_C9_PLL_LOCRE_SHIFT   (4U)
#define	MCG_C9_PLL_LOCRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
#define	MCG_C9_PLL_CME_MASK   (0x20U)
#define	MCG_C9_PLL_CME_SHIFT   (5U)
#define	MCG_C9_PLL_CME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
#define	MCG_C9_EXT_PLL_LOCS_MASK   (0x1U)
#define	MCG_C9_EXT_PLL_LOCS_SHIFT   (0U)
#define	MCG_C9_EXT_PLL_LOCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
#define	MCG_C9_PLL_LOCRE_MASK   (0x10U)
#define	MCG_C9_PLL_LOCRE_SHIFT   (4U)
#define	MCG_C9_PLL_LOCRE(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
#define	MCG_C9_PLL_CME_MASK   (0x20U)
#define	MCG_C9_PLL_CME_SHIFT   (5U)
#define	MCG_C9_PLL_CME(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)

C11 - MCG Control 11 Register
#define	MCG_C11_PLLCS_MASK   (0x10U)
#define	MCG_C11_PLLCS_SHIFT   (4U)
#define	MCG_C11_PLLCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
#define	MCG_C11_PLLCS_MASK   (0x10U)
#define	MCG_C11_PLLCS_SHIFT   (4U)
#define	MCG_C11_PLLCS(x)   (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)

S2 - MCG Status 2 Register
#define	MCG_S2_PLLCST_MASK   (0x10U)
#define	MCG_S2_PLLCST_SHIFT   (4U)
#define	MCG_S2_PLLCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
#define	MCG_S2_PLLCST_MASK   (0x10U)
#define	MCG_S2_PLLCST_SHIFT   (4U)
#define	MCG_S2_PLLCST(x)   (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)

Macro Definition Documentation

MCG

#define MCG   ((MCG_Type *)MCG_BASE)

Peripheral MCG base pointer

MCG_BASE

#define MCG_BASE   (0x40064000u)

Peripheral MCG base address

MCG_BASE_ADDRS

#define MCG_BASE_ADDRS   { MCG_BASE }

Array initializer of MCG peripheral base addresses

MCG_BASE_PTRS

#define MCG_BASE_PTRS   { MCG }

Array initializer of MCG peripheral base pointers

MCG_C11_PLLCS [1/2]

#define MCG_C11_PLLCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)

PLLCS - PLL Clock Select 0b0..PLL0 output clock is selected. 0b1..External PLL clock is selected.

MCG_C11_PLLCS [2/2]

#define MCG_C11_PLLCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)

PLLCS - PLL Clock Select 0b0..PLL0 output clock is selected. 0b1..External PLL clock is selected.

MCG_C1_CLKS [1/6]

#define MCG_C1_CLKS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

MCG_C1_CLKS [2/6]

#define MCG_C1_CLKS

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

MCG_C1_CLKS [3/6]

#define MCG_C1_CLKS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

MCG_C1_CLKS [4/6]

#define MCG_C1_CLKS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

MCG_C1_CLKS [5/6]

#define MCG_C1_CLKS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

MCG_C1_CLKS [6/6]

#define MCG_C1_CLKS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)

CLKS - Clock Source Select 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Reserved.

MCG_C1_FRDIV [1/6]

#define MCG_C1_FRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

MCG_C1_FRDIV [2/6]

#define MCG_C1_FRDIV

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

MCG_C1_FRDIV [3/6]

#define MCG_C1_FRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

MCG_C1_FRDIV [4/6]

#define MCG_C1_FRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

MCG_C1_FRDIV [5/6]

#define MCG_C1_FRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

MCG_C1_FRDIV [6/6]

#define MCG_C1_FRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)

FRDIV - FLL External Reference Divider 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .

MCG_C1_IRCLKEN [1/5]

#define MCG_C1_IRCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)

IRCLKEN - Internal Reference Clock Enable 0b0..MCGIRCLK inactive. 0b1..MCGIRCLK active.

MCG_C1_IRCLKEN [2/5]

#define MCG_C1_IRCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)

IRCLKEN - Internal Reference Clock Enable 0b0..MCGIRCLK inactive. 0b1..MCGIRCLK active.

MCG_C1_IRCLKEN [3/5]

#define MCG_C1_IRCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)

IRCLKEN - Internal Reference Clock Enable 0b0..MCGIRCLK inactive. 0b1..MCGIRCLK active.

MCG_C1_IRCLKEN [4/5]

#define MCG_C1_IRCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)

IRCLKEN - Internal Reference Clock Enable 0b0..MCGIRCLK inactive. 0b1..MCGIRCLK active.

MCG_C1_IRCLKEN [5/5]

#define MCG_C1_IRCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)

IRCLKEN - Internal Reference Clock Enable 0b0..MCGIRCLK inactive. 0b1..MCGIRCLK active.

MCG_C1_IREFS [1/5]

#define MCG_C1_IREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)

IREFS - Internal Reference Select 0b0..External reference clock is selected. 0b1..The slow internal reference clock is selected.

MCG_C1_IREFS [2/5]

#define MCG_C1_IREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)

IREFS - Internal Reference Select 0b0..External reference clock is selected. 0b1..The slow internal reference clock is selected.

MCG_C1_IREFS [3/5]

#define MCG_C1_IREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)

IREFS - Internal Reference Select 0b0..External reference clock is selected. 0b1..The slow internal reference clock is selected.

MCG_C1_IREFS [4/5]

#define MCG_C1_IREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)

IREFS - Internal Reference Select 0b0..External reference clock is selected. 0b1..The slow internal reference clock is selected.

MCG_C1_IREFS [5/5]

#define MCG_C1_IREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)

IREFS - Internal Reference Select 0b0..External reference clock is selected. 0b1..The slow internal reference clock is selected.

MCG_C1_IREFSTEN [1/5]

#define MCG_C1_IREFSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)

IREFSTEN - Internal Reference Stop Enable 0b0..Internal reference clock is disabled in Stop mode. 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.

MCG_C1_IREFSTEN [2/5]

#define MCG_C1_IREFSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)

IREFSTEN - Internal Reference Stop Enable 0b0..Internal reference clock is disabled in Stop mode. 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.

MCG_C1_IREFSTEN [3/5]

#define MCG_C1_IREFSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)

IREFSTEN - Internal Reference Stop Enable 0b0..Internal reference clock is disabled in Stop mode. 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.

MCG_C1_IREFSTEN [4/5]

#define MCG_C1_IREFSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)

IREFSTEN - Internal Reference Stop Enable 0b0..Internal reference clock is disabled in Stop mode. 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.

MCG_C1_IREFSTEN [5/5]

#define MCG_C1_IREFSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)

IREFSTEN - Internal Reference Stop Enable 0b0..Internal reference clock is disabled in Stop mode. 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.

MCG_C2_EREFS [1/5]

#define MCG_C2_EREFS

(

x

)

(MCG_C2_EREFS0(x))

EREFS - External Reference Select 0b0..External reference clock requested. 0b1..Oscillator requested.

MCG_C2_EREFS [2/5]

#define MCG_C2_EREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)

EREFS - External Reference Select 0b0..External reference clock requested. 0b1..Oscillator requested.

MCG_C2_EREFS [3/5]

#define MCG_C2_EREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)

EREFS - External Reference Select 0b0..External reference clock requested. 0b1..Oscillator requested.

MCG_C2_EREFS [4/5]

#define MCG_C2_EREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)

EREFS - External Reference Select 0b0..External reference clock requested. 0b1..Oscillator requested.

MCG_C2_EREFS [5/5]

#define MCG_C2_EREFS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)

EREFS - External Reference Select 0b0..External reference clock requested. 0b1..Oscillator requested.

MCG_C2_HGO [1/5]

#define MCG_C2_HGO

(

x

)

(MCG_C2_HGO0(x))

HGO - High Gain Oscillator Select 0b0..Configure crystal oscillator for low-power operation. 0b1..Configure crystal oscillator for high-gain operation.

MCG_C2_HGO [2/5]

#define MCG_C2_HGO

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)

HGO - High Gain Oscillator Select 0b0..Configure crystal oscillator for low-power operation. 0b1..Configure crystal oscillator for high-gain operation.

MCG_C2_HGO [3/5]

#define MCG_C2_HGO

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)

HGO - High Gain Oscillator Select 0b0..Configure crystal oscillator for low-power operation. 0b1..Configure crystal oscillator for high-gain operation.

MCG_C2_HGO [4/5]

#define MCG_C2_HGO

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)

HGO - High Gain Oscillator Select 0b0..Configure crystal oscillator for low-power operation. 0b1..Configure crystal oscillator for high-gain operation.

MCG_C2_HGO [5/5]

#define MCG_C2_HGO

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)

HGO - High Gain Oscillator Select 0b0..Configure crystal oscillator for low-power operation. 0b1..Configure crystal oscillator for high-gain operation.

MCG_C2_IRCS [1/5]

#define MCG_C2_IRCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)

IRCS - Internal Reference Clock Select 0b0..Slow internal reference clock selected. 0b1..Fast internal reference clock selected.

MCG_C2_IRCS [2/5]

#define MCG_C2_IRCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)

IRCS - Internal Reference Clock Select 0b0..Slow internal reference clock selected. 0b1..Fast internal reference clock selected.

MCG_C2_IRCS [3/5]

#define MCG_C2_IRCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)

IRCS - Internal Reference Clock Select 0b0..Slow internal reference clock selected. 0b1..Fast internal reference clock selected.

MCG_C2_IRCS [4/5]

#define MCG_C2_IRCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)

IRCS - Internal Reference Clock Select 0b0..Slow internal reference clock selected. 0b1..Fast internal reference clock selected.

MCG_C2_IRCS [5/5]

#define MCG_C2_IRCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)

IRCS - Internal Reference Clock Select 0b0..Slow internal reference clock selected. 0b1..Fast internal reference clock selected.

MCG_C2_LOCRE0 [1/5]

#define MCG_C2_LOCRE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)

LOCRE0 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. 0b1..Generate a reset request on a loss of OSC0 external reference clock.

MCG_C2_LOCRE0 [2/5]

#define MCG_C2_LOCRE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)

LOCRE0 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. 0b1..Generate a reset request on a loss of OSC0 external reference clock.

MCG_C2_LOCRE0 [3/5]

#define MCG_C2_LOCRE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)

LOCRE0 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. 0b1..Generate a reset request on a loss of OSC0 external reference clock.

MCG_C2_LOCRE0 [4/5]

#define MCG_C2_LOCRE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)

LOCRE0 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. 0b1..Generate a reset request on a loss of OSC0 external reference clock.

MCG_C2_LOCRE0 [5/5]

#define MCG_C2_LOCRE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)

LOCRE0 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. 0b1..Generate a reset request on a loss of OSC0 external reference clock.

MCG_C2_LP [1/5]

#define MCG_C2_LP

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)

LP - Low Power Select 0b0..FLL or PLL is not disabled in bypass modes. 0b1..FLL or PLL is disabled in bypass modes (lower power)

MCG_C2_LP [2/5]

#define MCG_C2_LP

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)

LP - Low Power Select 0b0..FLL or PLL is not disabled in bypass modes. 0b1..FLL or PLL is disabled in bypass modes (lower power)

MCG_C2_LP [3/5]

#define MCG_C2_LP

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)

LP - Low Power Select 0b0..FLL or PLL is not disabled in bypass modes. 0b1..FLL or PLL is disabled in bypass modes (lower power)

MCG_C2_LP [4/5]

#define MCG_C2_LP

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)

LP - Low Power Select 0b0..FLL or PLL is not disabled in bypass modes. 0b1..FLL or PLL is disabled in bypass modes (lower power)

MCG_C2_LP [5/5]

#define MCG_C2_LP

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)

LP - Low Power Select 0b0..FLL or PLL is not disabled in bypass modes. 0b1..FLL or PLL is disabled in bypass modes (lower power)

MCG_C2_RANGE [1/6]

#define MCG_C2_RANGE

(

x

)

(MCG_C2_RANGE0(x))

RANGE - Frequency Range Select 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .

MCG_C2_RANGE [2/6]

#define MCG_C2_RANGE

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)

RANGE - Frequency Range Select 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .

MCG_C2_RANGE [3/6]

#define MCG_C2_RANGE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)

RANGE - Frequency Range Select 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .

MCG_C2_RANGE [4/6]

#define MCG_C2_RANGE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)

RANGE - Frequency Range Select 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .

MCG_C2_RANGE [5/6]

#define MCG_C2_RANGE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)

RANGE - Frequency Range Select 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .

MCG_C2_RANGE [6/6]

#define MCG_C2_RANGE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)

RANGE - Frequency Range Select 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .

MCG_C4_DMX32 [1/5]

#define MCG_C4_DMX32

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)

DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 0b0..DCO has a default range of 25%. 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

MCG_C4_DMX32 [2/5]

#define MCG_C4_DMX32

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)

DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 0b0..DCO has a default range of 25%. 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

MCG_C4_DMX32 [3/5]

#define MCG_C4_DMX32

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)

DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 0b0..DCO has a default range of 25%. 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

MCG_C4_DMX32 [4/5]

#define MCG_C4_DMX32

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)

DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 0b0..DCO has a default range of 25%. 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

MCG_C4_DMX32 [5/5]

#define MCG_C4_DMX32

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)

DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 0b0..DCO has a default range of 25%. 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

MCG_C4_DRST_DRS [1/6]

#define MCG_C4_DRST_DRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)

DRST_DRS - DCO Range Select 0b00..Encoding 0 - Low range (reset default). 0b01..Encoding 1 - Mid range. 0b10..Encoding 2 - Mid-high range. 0b11..Encoding 3 - High range.

MCG_C4_DRST_DRS [2/6]

#define MCG_C4_DRST_DRS

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)

DRST_DRS - DCO Range Select 0b00..Encoding 0 - Low range (reset default). 0b01..Encoding 1 - Mid range. 0b10..Encoding 2 - Mid-high range. 0b11..Encoding 3 - High range.

MCG_C4_DRST_DRS [3/6]

#define MCG_C4_DRST_DRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)

DRST_DRS - DCO Range Select 0b00..Encoding 0 - Low range (reset default). 0b01..Encoding 1 - Mid range. 0b10..Encoding 2 - Mid-high range. 0b11..Encoding 3 - High range.

MCG_C4_DRST_DRS [4/6]

#define MCG_C4_DRST_DRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)

DRST_DRS - DCO Range Select 0b00..Encoding 0 - Low range (reset default). 0b01..Encoding 1 - Mid range. 0b10..Encoding 2 - Mid-high range. 0b11..Encoding 3 - High range.

MCG_C4_DRST_DRS [5/6]

#define MCG_C4_DRST_DRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)

DRST_DRS - DCO Range Select 0b00..Encoding 0 - Low range (reset default). 0b01..Encoding 1 - Mid range. 0b10..Encoding 2 - Mid-high range. 0b11..Encoding 3 - High range.

MCG_C4_DRST_DRS [6/6]

#define MCG_C4_DRST_DRS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)

DRST_DRS - DCO Range Select 0b00..Encoding 0 - Low range (reset default). 0b01..Encoding 1 - Mid range. 0b10..Encoding 2 - Mid-high range. 0b11..Encoding 3 - High range.

MCG_C5_PLLCLKEN [1/3]

#define MCG_C5_PLLCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)

PLLCLKEN - PLL Clock Enable 0b0..MCGPLLCLK is inactive. 0b1..MCGPLLCLK is active.

MCG_C5_PLLCLKEN [2/3]

#define MCG_C5_PLLCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)

PLLCLKEN - PLL Clock Enable 0b0..MCGPLLCLK is inactive. 0b1..MCGPLLCLK is active.

MCG_C5_PLLCLKEN [3/3]

#define MCG_C5_PLLCLKEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)

PLLCLKEN - PLL Clock Enable 0b0..MCGPLLCLK is inactive. 0b1..MCGPLLCLK is active.

MCG_C5_PLLCLKEN0 [1/2]

#define MCG_C5_PLLCLKEN0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)

PLLCLKEN0 - PLL Clock Enable 0b0..MCGPLLCLK is inactive. 0b1..MCGPLLCLK is active.

MCG_C5_PLLCLKEN0 [2/2]

#define MCG_C5_PLLCLKEN0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)

PLLCLKEN0 - PLL Clock Enable 0b0..MCGPLLCLK is inactive. 0b1..MCGPLLCLK is active.

MCG_C5_PLLSTEN [1/3]

#define MCG_C5_PLLSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)

PLLSTEN - PLL Stop Enable 0b0..MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes. 0b1..MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode.

MCG_C5_PLLSTEN [2/3]

#define MCG_C5_PLLSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)

PLLSTEN - PLL Stop Enable 0b0..MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes. 0b1..MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode.

MCG_C5_PLLSTEN [3/3]

#define MCG_C5_PLLSTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)

PLLSTEN - PLL Stop Enable 0b0..MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes. 0b1..MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode.

MCG_C5_PLLSTEN0 [1/2]

#define MCG_C5_PLLSTEN0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)

PLLSTEN0 - PLL Stop Enable 0b0..MCGPLLCLK is disabled in any of the Stop modes. 0b1..MCGPLLCLK is enabled if system is in Normal Stop mode.

MCG_C5_PLLSTEN0 [2/2]

#define MCG_C5_PLLSTEN0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)

PLLSTEN0 - PLL Stop Enable 0b0..MCGPLLCLK is disabled in any of the Stop modes. 0b1..MCGPLLCLK is enabled if system is in Normal Stop mode.

MCG_C5_PRDIV [1/4]

#define MCG_C5_PRDIV

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV_SHIFT))&MCG_C5_PRDIV_MASK)

PRDIV - PLL External Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2 0b010..Divide Factor is 3 0b011..Divide Factor is 4 0b100..Divide Factor is 5 0b101..Divide Factor is 6 0b110..Divide Factor is 7 0b111..Divide Factor is 8

MCG_C5_PRDIV [2/4]

#define MCG_C5_PRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)

PRDIV - PLL External Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2 0b010..Divide Factor is 3 0b011..Divide Factor is 4 0b100..Divide Factor is 5 0b101..Divide Factor is 6 0b110..Divide Factor is 7 0b111..Divide Factor is 8

MCG_C5_PRDIV [3/4]

#define MCG_C5_PRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)

PRDIV - PLL External Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2 0b010..Divide Factor is 3 0b011..Divide Factor is 4 0b100..Divide Factor is 5 0b101..Divide Factor is 6 0b110..Divide Factor is 7 0b111..Divide Factor is 8

MCG_C5_PRDIV [4/4]

#define MCG_C5_PRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)

PRDIV - PLL External Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2 0b010..Divide Factor is 3 0b011..Divide Factor is 4 0b100..Divide Factor is 5 0b101..Divide Factor is 6 0b110..Divide Factor is 7 0b111..Divide Factor is 8

MCG_C5_PRDIV0 [1/2]

#define MCG_C5_PRDIV0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)

PRDIV0 - PLL External Reference Divider 0b00000..Divide Factor is 1 0b00001..Divide Factor is 2 0b00010..Divide Factor is 3 0b00011..Divide Factor is 4 0b00100..Divide Factor is 5 0b00101..Divide Factor is 6 0b00110..Divide Factor is 7 0b00111..Divide Factor is 8 0b01000..Divide Factor is 9 0b01001..Divide Factor is 10 0b01010..Divide Factor is 11 0b01011..Divide Factor is 12 0b01100..Divide Factor is 13 0b01101..Divide Factor is 14 0b01110..Divide Factor is 15 0b01111..Divide Factor is 16 0b10000..Divide Factor is 17 0b10001..Divide Factor is 18 0b10010..Divide Factor is 19 0b10011..Divide Factor is 20 0b10100..Divide Factor is 21 0b10101..Divide Factor is 22 0b10110..Divide Factor is 23 0b10111..Divide Factor is 24 0b11000..Divide Factor is 25 0b11001..Divide Factor is 26 0b11010..Divide Factor is 27 0b11011..Divide Factor is 28 0b11100..Divide Factor is 29 0b11101..Divide Factor is 30 0b11110..Divide Factor is 31 0b11111..Divide Factor is 32

MCG_C5_PRDIV0 [2/2]

#define MCG_C5_PRDIV0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)

PRDIV0 - PLL External Reference Divider 0b00000..Divide Factor is 1 0b00001..Divide Factor is 2 0b00010..Divide Factor is 3 0b00011..Divide Factor is 4 0b00100..Divide Factor is 5 0b00101..Divide Factor is 6 0b00110..Divide Factor is 7 0b00111..Divide Factor is 8 0b01000..Divide Factor is 9 0b01001..Divide Factor is 10 0b01010..Divide Factor is 11 0b01011..Divide Factor is 12 0b01100..Divide Factor is 13 0b01101..Divide Factor is 14 0b01110..Divide Factor is 15 0b01111..Divide Factor is 16 0b10000..Divide Factor is 17 0b10001..Divide Factor is 18 0b10010..Divide Factor is 19 0b10011..Divide Factor is 20 0b10100..Divide Factor is 21 0b10101..Divide Factor is 22 0b10110..Divide Factor is 23 0b10111..Divide Factor is 24 0b11000..Divide Factor is 25 0b11001..Divide Factor is 26 0b11010..Divide Factor is 27 0b11011..Divide Factor is 28 0b11100..Divide Factor is 29 0b11101..Divide Factor is 30 0b11110..Divide Factor is 31 0b11111..Divide Factor is 32

MCG_C6_CME0 [1/5]

#define MCG_C6_CME0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)

CME0 - Clock Monitor Enable 0b0..External clock monitor is disabled for OSC0. 0b1..External clock monitor is enabled for OSC0.

MCG_C6_CME0 [2/5]

#define MCG_C6_CME0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)

CME0 - Clock Monitor Enable 0b0..External clock monitor is disabled for OSC0. 0b1..External clock monitor is enabled for OSC0.

MCG_C6_CME0 [3/5]

#define MCG_C6_CME0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)

CME0 - Clock Monitor Enable 0b0..External clock monitor is disabled for OSC0. 0b1..External clock monitor is enabled for OSC0.

MCG_C6_CME0 [4/5]

#define MCG_C6_CME0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)

CME0 - Clock Monitor Enable 0b0..External clock monitor is disabled for OSC0. 0b1..External clock monitor is enabled for OSC0.

MCG_C6_CME0 [5/5]

#define MCG_C6_CME0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)

CME0 - Clock Monitor Enable 0b0..External clock monitor is disabled for OSC0. 0b1..External clock monitor is enabled for OSC0.

MCG_C6_LOLIE0 [1/5]

#define MCG_C6_LOLIE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)

LOLIE0 - Loss of Lock Interrrupt Enable 0b0..No interrupt request is generated on loss of lock. 0b1..Generate an interrupt request on loss of lock.

MCG_C6_LOLIE0 [2/5]

#define MCG_C6_LOLIE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)

LOLIE0 - Loss of Lock Interrrupt Enable 0b0..No interrupt request is generated on loss of lock. 0b1..Generate an interrupt request on loss of lock.

MCG_C6_LOLIE0 [3/5]

#define MCG_C6_LOLIE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)

LOLIE0 - Loss of Lock Interrrupt Enable 0b0..No interrupt request is generated on loss of lock. 0b1..Generate an interrupt request on loss of lock.

MCG_C6_LOLIE0 [4/5]

#define MCG_C6_LOLIE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)

LOLIE0 - Loss of Lock Interrrupt Enable 0b0..No interrupt request is generated on loss of lock. 0b1..Generate an interrupt request on loss of lock.

MCG_C6_LOLIE0 [5/5]

#define MCG_C6_LOLIE0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)

LOLIE0 - Loss of Lock Interrrupt Enable 0b0..No interrupt request is generated on loss of lock. 0b1..Generate an interrupt request on loss of lock.

MCG_C6_PLLS [1/5]

#define MCG_C6_PLLS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLLCS output clock is selected (PRDIV0 bits of PLL in the C5 register need to be programmed to the correct divider to generate a PLL reference clock in the range specified in the data sheet (fpll_ref) prior to setting the PLLS bit).

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit).

MCG_C6_PLLS [2/5]

#define MCG_C6_PLLS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLLCS output clock is selected (PRDIV0 bits of PLL in the C5 register need to be programmed to the correct divider to generate a PLL reference clock in the range specified in the data sheet (fpll_ref) prior to setting the PLLS bit).

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit).

MCG_C6_PLLS [3/5]

#define MCG_C6_PLLS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLLCS output clock is selected (PRDIV0 bits of PLL in the C5 register need to be programmed to the correct divider to generate a PLL reference clock in the range specified in the data sheet (fpll_ref) prior to setting the PLLS bit).

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit).

MCG_C6_PLLS [4/5]

#define MCG_C6_PLLS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLLCS output clock is selected (PRDIV0 bits of PLL in the C5 register need to be programmed to the correct divider to generate a PLL reference clock in the range specified in the data sheet (fpll_ref) prior to setting the PLLS bit).

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit).

MCG_C6_PLLS [5/5]

#define MCG_C6_PLLS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)

PLLS - PLL Select 0b0..FLL is selected. 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit).

MCG_C6_VDIV [1/4]

#define MCG_C6_VDIV

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV_SHIFT))&MCG_C6_VDIV_MASK)

VDIV - VCO Divider 0b00000..Multiply Factor is 16 0b00001..Multiply Factor is 17 0b00010..Multiply Factor is 18 0b00011..Multiply Factor is 19 0b00100..Multiply Factor is 20 0b00101..Multiply Factor is 21 0b00110..Multiply Factor is 22 0b00111..Multiply Factor is 23 0b01000..Multiply Factor is 24 0b01001..Multiply Factor is 25 0b01010..Multiply Factor is 26 0b01011..Multiply Factor is 27 0b01100..Multiply Factor is 28 0b01101..Multiply Factor is 29 0b01110..Multiply Factor is 30 0b01111..Multiply Factor is 31 0b10000..Multiply Factor is 32 0b10001..Multiply Factor is 33 0b10010..Multiply Factor is 34 0b10011..Multiply Factor is 35 0b10100..Multiply Factor is 36 0b10101..Multiply Factor is 37 0b10110..Multiply Factor is 38 0b10111..Multiply Factor is 39 0b11000..Multiply Factor is 40 0b11001..Multiply Factor is 41 0b11010..Multiply Factor is 42 0b11011..Multiply Factor is 43 0b11100..Multiply Factor is 44 0b11101..Multiply Factor is 45 0b11110..Multiply Factor is 46 0b11111..Multiply Factor is 47

MCG_C6_VDIV [2/4]

#define MCG_C6_VDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)

VDIV - VCO Divider 0b00000..Multiply Factor is 16 0b00001..Multiply Factor is 17 0b00010..Multiply Factor is 18 0b00011..Multiply Factor is 19 0b00100..Multiply Factor is 20 0b00101..Multiply Factor is 21 0b00110..Multiply Factor is 22 0b00111..Multiply Factor is 23 0b01000..Multiply Factor is 24 0b01001..Multiply Factor is 25 0b01010..Multiply Factor is 26 0b01011..Multiply Factor is 27 0b01100..Multiply Factor is 28 0b01101..Multiply Factor is 29 0b01110..Multiply Factor is 30 0b01111..Multiply Factor is 31 0b10000..Multiply Factor is 32 0b10001..Multiply Factor is 33 0b10010..Multiply Factor is 34 0b10011..Multiply Factor is 35 0b10100..Multiply Factor is 36 0b10101..Multiply Factor is 37 0b10110..Multiply Factor is 38 0b10111..Multiply Factor is 39 0b11000..Multiply Factor is 40 0b11001..Multiply Factor is 41 0b11010..Multiply Factor is 42 0b11011..Multiply Factor is 43 0b11100..Multiply Factor is 44 0b11101..Multiply Factor is 45 0b11110..Multiply Factor is 46 0b11111..Multiply Factor is 47

MCG_C6_VDIV [3/4]

#define MCG_C6_VDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)

VDIV - VCO Divider 0b00000..Multiply Factor is 16 0b00001..Multiply Factor is 17 0b00010..Multiply Factor is 18 0b00011..Multiply Factor is 19 0b00100..Multiply Factor is 20 0b00101..Multiply Factor is 21 0b00110..Multiply Factor is 22 0b00111..Multiply Factor is 23 0b01000..Multiply Factor is 24 0b01001..Multiply Factor is 25 0b01010..Multiply Factor is 26 0b01011..Multiply Factor is 27 0b01100..Multiply Factor is 28 0b01101..Multiply Factor is 29 0b01110..Multiply Factor is 30 0b01111..Multiply Factor is 31 0b10000..Multiply Factor is 32 0b10001..Multiply Factor is 33 0b10010..Multiply Factor is 34 0b10011..Multiply Factor is 35 0b10100..Multiply Factor is 36 0b10101..Multiply Factor is 37 0b10110..Multiply Factor is 38 0b10111..Multiply Factor is 39 0b11000..Multiply Factor is 40 0b11001..Multiply Factor is 41 0b11010..Multiply Factor is 42 0b11011..Multiply Factor is 43 0b11100..Multiply Factor is 44 0b11101..Multiply Factor is 45 0b11110..Multiply Factor is 46 0b11111..Multiply Factor is 47

MCG_C6_VDIV [4/4]

#define MCG_C6_VDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)

VDIV - VCO Divider 0b00000..Multiply Factor is 16 0b00001..Multiply Factor is 17 0b00010..Multiply Factor is 18 0b00011..Multiply Factor is 19 0b00100..Multiply Factor is 20 0b00101..Multiply Factor is 21 0b00110..Multiply Factor is 22 0b00111..Multiply Factor is 23 0b01000..Multiply Factor is 24 0b01001..Multiply Factor is 25 0b01010..Multiply Factor is 26 0b01011..Multiply Factor is 27 0b01100..Multiply Factor is 28 0b01101..Multiply Factor is 29 0b01110..Multiply Factor is 30 0b01111..Multiply Factor is 31 0b10000..Multiply Factor is 32 0b10001..Multiply Factor is 33 0b10010..Multiply Factor is 34 0b10011..Multiply Factor is 35 0b10100..Multiply Factor is 36 0b10101..Multiply Factor is 37 0b10110..Multiply Factor is 38 0b10111..Multiply Factor is 39 0b11000..Multiply Factor is 40 0b11001..Multiply Factor is 41 0b11010..Multiply Factor is 42 0b11011..Multiply Factor is 43 0b11100..Multiply Factor is 44 0b11101..Multiply Factor is 45 0b11110..Multiply Factor is 46 0b11111..Multiply Factor is 47

MCG_C6_VDIV0 [1/2]

#define MCG_C6_VDIV0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)

VDIV0 - VCO 0 Divider 0b00000..Multiply Factor is 24 0b00001..Multiply Factor is 25 0b00010..Multiply Factor is 26 0b00011..Multiply Factor is 27 0b00100..Multiply Factor is 28 0b00101..Multiply Factor is 29 0b00110..Multiply Factor is 30 0b00111..Multiply Factor is 31 0b01000..Multiply Factor is 32 0b01001..Multiply Factor is 33 0b01010..Multiply Factor is 34 0b01011..Multiply Factor is 35 0b01100..Multiply Factor is 36 0b01101..Multiply Factor is 37 0b01110..Multiply Factor is 38 0b01111..Multiply Factor is 39 0b10000..Multiply Factor is 40 0b10001..Multiply Factor is 41 0b10010..Multiply Factor is 42 0b10011..Multiply Factor is 43 0b10100..Multiply Factor is 44 0b10101..Multiply Factor is 45 0b10110..Multiply Factor is 46 0b10111..Multiply Factor is 47 0b11000..Multiply Factor is 48 0b11001..Multiply Factor is 49 0b11010..Multiply Factor is 50 0b11011..Multiply Factor is 51 0b11100..Multiply Factor is 52 0b11101..Multiply Factor is 53 0b11110..Multiply Factor is 54 0b11111..Multiply Factor is 55

MCG_C6_VDIV0 [2/2]

#define MCG_C6_VDIV0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)

VDIV0 - VCO 0 Divider 0b00000..Multiply Factor is 24 0b00001..Multiply Factor is 25 0b00010..Multiply Factor is 26 0b00011..Multiply Factor is 27 0b00100..Multiply Factor is 28 0b00101..Multiply Factor is 29 0b00110..Multiply Factor is 30 0b00111..Multiply Factor is 31 0b01000..Multiply Factor is 32 0b01001..Multiply Factor is 33 0b01010..Multiply Factor is 34 0b01011..Multiply Factor is 35 0b01100..Multiply Factor is 36 0b01101..Multiply Factor is 37 0b01110..Multiply Factor is 38 0b01111..Multiply Factor is 39 0b10000..Multiply Factor is 40 0b10001..Multiply Factor is 41 0b10010..Multiply Factor is 42 0b10011..Multiply Factor is 43 0b10100..Multiply Factor is 44 0b10101..Multiply Factor is 45 0b10110..Multiply Factor is 46 0b10111..Multiply Factor is 47 0b11000..Multiply Factor is 48 0b11001..Multiply Factor is 49 0b11010..Multiply Factor is 50 0b11011..Multiply Factor is 51 0b11100..Multiply Factor is 52 0b11101..Multiply Factor is 53 0b11110..Multiply Factor is 54 0b11111..Multiply Factor is 55

MCG_C7_OSCSEL [1/4]

#define MCG_C7_OSCSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)

OSCSEL - MCG OSC Clock Select 0b00..Selects Oscillator (OSCCLK0). 0b01..Selects 32 kHz RTC Oscillator. 0b10..Selects Oscillator (OSCCLK1). 0b11..RESERVED

MCG_C7_OSCSEL [2/4]

#define MCG_C7_OSCSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)

OSCSEL - MCG OSC Clock Select 0b00..Selects Oscillator (OSCCLK0). 0b01..Selects 32 kHz RTC Oscillator. 0b10..Selects Oscillator (OSCCLK1). 0b11..RESERVED

MCG_C7_OSCSEL [3/4]

#define MCG_C7_OSCSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)

OSCSEL - MCG OSC Clock Select 0b00..Selects Oscillator (OSCCLK0). 0b01..Selects 32 kHz RTC Oscillator. 0b10..Selects Oscillator (OSCCLK1). 0b11..RESERVED

MCG_C7_OSCSEL [4/4]

#define MCG_C7_OSCSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)

OSCSEL - MCG OSC Clock Select 0b00..Selects Oscillator (OSCCLK0). 0b01..Selects 32 kHz RTC Oscillator. 0b10..Selects Oscillator (OSCCLK1). 0b11..RESERVED

MCG_C8_CME1 [1/4]

#define MCG_C8_CME1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)

CME1 - Clock Monitor Enable1 0b0..External clock monitor is disabled for RTC clock. 0b1..External clock monitor is enabled for RTC clock.

MCG_C8_CME1 [2/4]

#define MCG_C8_CME1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)

CME1 - Clock Monitor Enable1 0b0..External clock monitor is disabled for RTC clock. 0b1..External clock monitor is enabled for RTC clock.

MCG_C8_CME1 [3/4]

#define MCG_C8_CME1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)

CME1 - Clock Monitor Enable1 0b0..External clock monitor is disabled for RTC clock. 0b1..External clock monitor is enabled for RTC clock.

MCG_C8_CME1 [4/4]

#define MCG_C8_CME1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)

CME1 - Clock Monitor Enable1 0b0..External clock monitor is disabled for RTC clock. 0b1..External clock monitor is enabled for RTC clock.

MCG_C8_LOCRE1 [1/4]

#define MCG_C8_LOCRE1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)

LOCRE1 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of RTC external reference clock. 0b1..Generate a reset request on a loss of RTC external reference clock

MCG_C8_LOCRE1 [2/4]

#define MCG_C8_LOCRE1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)

LOCRE1 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of RTC external reference clock. 0b1..Generate a reset request on a loss of RTC external reference clock

MCG_C8_LOCRE1 [3/4]

#define MCG_C8_LOCRE1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)

LOCRE1 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of RTC external reference clock. 0b1..Generate a reset request on a loss of RTC external reference clock

MCG_C8_LOCRE1 [4/4]

#define MCG_C8_LOCRE1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)

LOCRE1 - Loss of Clock Reset Enable 0b0..Interrupt request is generated on a loss of RTC external reference clock. 0b1..Generate a reset request on a loss of RTC external reference clock

MCG_C8_LOCS1 [1/4]

#define MCG_C8_LOCS1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)

LOCS1 - RTC Loss of Clock Status 0b0..Loss of RTC has not occur. 0b1..Loss of RTC has occur

MCG_C8_LOCS1 [2/4]

#define MCG_C8_LOCS1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)

LOCS1 - RTC Loss of Clock Status 0b0..Loss of RTC has not occur. 0b1..Loss of RTC has occur

MCG_C8_LOCS1 [3/4]

#define MCG_C8_LOCS1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)

LOCS1 - RTC Loss of Clock Status 0b0..Loss of RTC has not occur. 0b1..Loss of RTC has occur

MCG_C8_LOCS1 [4/4]

#define MCG_C8_LOCS1

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)

LOCS1 - RTC Loss of Clock Status 0b0..Loss of RTC has not occur. 0b1..Loss of RTC has occur

MCG_C8_LOLRE [1/5]

#define MCG_C8_LOLRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)

LOLRE - PLL Loss of Lock Reset Enable 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. 0b1..Generate a reset request on a PLL loss of lock indication.

MCG_C8_LOLRE [2/5]

#define MCG_C8_LOLRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)

LOLRE - PLL Loss of Lock Reset Enable 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. 0b1..Generate a reset request on a PLL loss of lock indication.

MCG_C8_LOLRE [3/5]

#define MCG_C8_LOLRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)

LOLRE - PLL Loss of Lock Reset Enable 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. 0b1..Generate a reset request on a PLL loss of lock indication.

MCG_C8_LOLRE [4/5]

#define MCG_C8_LOLRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)

LOLRE - PLL Loss of Lock Reset Enable 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. 0b1..Generate a reset request on a PLL loss of lock indication.

MCG_C8_LOLRE [5/5]

#define MCG_C8_LOLRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)

LOLRE - PLL Loss of Lock Reset Enable 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. 0b1..Generate a reset request on a PLL loss of lock indication.

MCG_C9_EXT_PLL_LOCS [1/2]

#define MCG_C9_EXT_PLL_LOCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)

EXT_PLL_LOCS - External PLL Loss of Clock Status 0b0..Loss of MCG EXT_PLL has not occurred. 0b1..Loss of MCG EXT_PLL has occurred.

MCG_C9_EXT_PLL_LOCS [2/2]

#define MCG_C9_EXT_PLL_LOCS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)

EXT_PLL_LOCS - External PLL Loss of Clock Status 0b0..Loss of MCG EXT_PLL has not occurred. 0b1..Loss of MCG EXT_PLL has occurred.

MCG_C9_PLL_CME [1/2]

#define MCG_C9_PLL_CME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)

PLL_CME - MCG External PLL Clock Monitor Enable 0b0..External clock monitor is disabled for EXT_PLL clock. 0b1..External clock monitor is enabled for EXT_PLL clock.

MCG_C9_PLL_CME [2/2]

#define MCG_C9_PLL_CME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)

PLL_CME - MCG External PLL Clock Monitor Enable 0b0..External clock monitor is disabled for EXT_PLL clock. 0b1..External clock monitor is enabled for EXT_PLL clock.

MCG_C9_PLL_LOCRE [1/2]

#define MCG_C9_PLL_LOCRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)

PLL_LOCRE - MCG External PLL Loss of Clock Reset Enable 0b0..Interrupt request is generated on a invalid or loss of the MCG external PLL clock. 0b1..Generates a system reset request on a invalid or loss of the MCG external PLL clock.

MCG_C9_PLL_LOCRE [2/2]

#define MCG_C9_PLL_LOCRE

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)

PLL_LOCRE - MCG External PLL Loss of Clock Reset Enable 0b0..Interrupt request is generated on a invalid or loss of the MCG external PLL clock. 0b1..Generates a system reset request on a invalid or loss of the MCG external PLL clock.

MCG_IRQS

#define MCG_IRQS   { MCG_IRQn }

Interrupt vectors for the MCG peripheral type

MCG_S2_PLLCST [1/2]

#define MCG_S2_PLLCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)

PLLCST - PLL Clock Select Status 0b0..Source of PLLCS is PLL clock. 0b1..Source of PLLCS is EXT_PLL clock.

MCG_S2_PLLCST [2/2]

#define MCG_S2_PLLCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)

PLLCST - PLL Clock Select Status 0b0..Source of PLLCS is PLL clock. 0b1..Source of PLLCS is EXT_PLL clock.

MCG_S_CLKST [1/6]

#define MCG_S_CLKST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)

CLKST - Clock Mode Status 0b00..Encoding 0 - Output of the FLL is selected (reset default). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Output of the PLL is selected.

MCG_S_CLKST [2/6]

#define MCG_S_CLKST

(

x

)

(((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)

CLKST - Clock Mode Status 0b00..Encoding 0 - Output of the FLL is selected (reset default). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Output of the PLL is selected.

MCG_S_CLKST [3/6]

#define MCG_S_CLKST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)

CLKST - Clock Mode Status 0b00..Encoding 0 - Output of the FLL is selected (reset default). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Output of the PLL is selected.

MCG_S_CLKST [4/6]

#define MCG_S_CLKST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)

CLKST - Clock Mode Status 0b00..Encoding 0 - Output of the FLL is selected (reset default). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Output of the PLL is selected.

MCG_S_CLKST [5/6]

#define MCG_S_CLKST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)

CLKST - Clock Mode Status 0b00..Encoding 0 - Output of the FLL is selected (reset default). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Output of the PLL is selected.

MCG_S_CLKST [6/6]

#define MCG_S_CLKST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)

CLKST - Clock Mode Status 0b00..Encoding 0 - Output of the FLL is selected (reset default). 0b01..Encoding 1 - Internal reference clock is selected. 0b10..Encoding 2 - External reference clock is selected. 0b11..Encoding 3 - Output of the PLL is selected.

MCG_S_IRCST [1/5]

#define MCG_S_IRCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)

IRCST - Internal Reference Clock Status 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).

MCG_S_IRCST [2/5]

#define MCG_S_IRCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)

IRCST - Internal Reference Clock Status 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).

MCG_S_IRCST [3/5]

#define MCG_S_IRCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)

IRCST - Internal Reference Clock Status 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).

MCG_S_IRCST [4/5]

#define MCG_S_IRCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)

IRCST - Internal Reference Clock Status 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).

MCG_S_IRCST [5/5]

#define MCG_S_IRCST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)

IRCST - Internal Reference Clock Status 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).

MCG_S_IREFST [1/5]

#define MCG_S_IREFST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)

IREFST - Internal Reference Status 0b0..Source of FLL reference clock is the external reference clock. 0b1..Source of FLL reference clock is the internal reference clock.

MCG_S_IREFST [2/5]

#define MCG_S_IREFST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)

IREFST - Internal Reference Status 0b0..Source of FLL reference clock is the external reference clock. 0b1..Source of FLL reference clock is the internal reference clock.

MCG_S_IREFST [3/5]

#define MCG_S_IREFST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)

IREFST - Internal Reference Status 0b0..Source of FLL reference clock is the external reference clock. 0b1..Source of FLL reference clock is the internal reference clock.

MCG_S_IREFST [4/5]

#define MCG_S_IREFST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)

IREFST - Internal Reference Status 0b0..Source of FLL reference clock is the external reference clock. 0b1..Source of FLL reference clock is the internal reference clock.

MCG_S_IREFST [5/5]

#define MCG_S_IREFST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)

IREFST - Internal Reference Status 0b0..Source of FLL reference clock is the external reference clock. 0b1..Source of FLL reference clock is the internal reference clock.

MCG_S_LOCK0 [1/5]

#define MCG_S_LOCK0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)

LOCK0 - Lock Status 0b0..PLL is currently unlocked. 0b1..PLL is currently locked.

MCG_S_LOCK0 [2/5]

#define MCG_S_LOCK0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)

LOCK0 - Lock Status 0b0..PLL is currently unlocked. 0b1..PLL is currently locked.

MCG_S_LOCK0 [3/5]

#define MCG_S_LOCK0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)

LOCK0 - Lock Status 0b0..PLL is currently unlocked. 0b1..PLL is currently locked.

MCG_S_LOCK0 [4/5]

#define MCG_S_LOCK0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)

LOCK0 - Lock Status 0b0..PLL is currently unlocked. 0b1..PLL is currently locked.

MCG_S_LOCK0 [5/5]

#define MCG_S_LOCK0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)

LOCK0 - Lock Status 0b0..PLL is currently unlocked. 0b1..PLL is currently locked.

MCG_S_LOLS0 [1/5]

#define MCG_S_LOLS0

(

x

)

(MCG_S_LOLS(x))

LOLS0 - Loss of Lock Status 0b0..PLL has not lost lock since LOLS 0 was last cleared. 0b1..PLL has lost lock since LOLS 0 was last cleared.

MCG_S_LOLS0 [2/5]

#define MCG_S_LOLS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)

LOLS0 - Loss of Lock Status 0b0..PLL has not lost lock since LOLS 0 was last cleared. 0b1..PLL has lost lock since LOLS 0 was last cleared.

MCG_S_LOLS0 [3/5]

#define MCG_S_LOLS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)

LOLS0 - Loss of Lock Status 0b0..PLL has not lost lock since LOLS 0 was last cleared. 0b1..PLL has lost lock since LOLS 0 was last cleared.

MCG_S_LOLS0 [4/5]

#define MCG_S_LOLS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)

LOLS0 - Loss of Lock Status 0b0..PLL has not lost lock since LOLS 0 was last cleared. 0b1..PLL has lost lock since LOLS 0 was last cleared.

MCG_S_LOLS0 [5/5]

#define MCG_S_LOLS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)

LOLS0 - Loss of Lock Status 0b0..PLL has not lost lock since LOLS 0 was last cleared. 0b1..PLL has lost lock since LOLS 0 was last cleared.

MCG_S_PLLST [1/5]

#define MCG_S_PLLST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLL output clock.

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLLCS output clock.

MCG_S_PLLST [2/5]

#define MCG_S_PLLST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLL output clock.

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLLCS output clock.

MCG_S_PLLST [3/5]

#define MCG_S_PLLST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLLCS output clock.

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLL output clock.

MCG_S_PLLST [4/5]

#define MCG_S_PLLST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLLCS output clock.

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLL output clock.

MCG_S_PLLST [5/5]

#define MCG_S_PLLST

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)

PLLST - PLL Select Status 0b0..Source of PLLS clock is FLL clock. 0b1..Source of PLLS clock is PLL output clock.

MCG_SC_ATME [1/5]

#define MCG_SC_ATME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)

ATME - Automatic Trim Machine Enable 0b0..Auto Trim Machine disabled. 0b1..Auto Trim Machine enabled.

MCG_SC_ATME [2/5]

#define MCG_SC_ATME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)

ATME - Automatic Trim Machine Enable 0b0..Auto Trim Machine disabled. 0b1..Auto Trim Machine enabled.

MCG_SC_ATME [3/5]

#define MCG_SC_ATME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)

ATME - Automatic Trim Machine Enable 0b0..Auto Trim Machine disabled. 0b1..Auto Trim Machine enabled.

MCG_SC_ATME [4/5]

#define MCG_SC_ATME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)

ATME - Automatic Trim Machine Enable 0b0..Auto Trim Machine disabled. 0b1..Auto Trim Machine enabled.

MCG_SC_ATME [5/5]

#define MCG_SC_ATME

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)

ATME - Automatic Trim Machine Enable 0b0..Auto Trim Machine disabled. 0b1..Auto Trim Machine enabled.

MCG_SC_ATMF [1/5]

#define MCG_SC_ATMF

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)

ATMF - Automatic Trim Machine Fail Flag 0b0..Automatic Trim Machine completed normally. 0b1..Automatic Trim Machine failed.

MCG_SC_ATMF [2/5]

#define MCG_SC_ATMF

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)

ATMF - Automatic Trim Machine Fail Flag 0b0..Automatic Trim Machine completed normally. 0b1..Automatic Trim Machine failed.

MCG_SC_ATMF [3/5]

#define MCG_SC_ATMF

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)

ATMF - Automatic Trim Machine Fail Flag 0b0..Automatic Trim Machine completed normally. 0b1..Automatic Trim Machine failed.

MCG_SC_ATMF [4/5]

#define MCG_SC_ATMF

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)

ATMF - Automatic Trim Machine Fail Flag 0b0..Automatic Trim Machine completed normally. 0b1..Automatic Trim Machine failed.

MCG_SC_ATMF [5/5]

#define MCG_SC_ATMF

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)

ATMF - Automatic Trim Machine Fail Flag 0b0..Automatic Trim Machine completed normally. 0b1..Automatic Trim Machine failed.

MCG_SC_ATMS [1/5]

#define MCG_SC_ATMS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)

ATMS - Automatic Trim Machine Select 0b0..32 kHz Internal Reference Clock selected. 0b1..4 MHz Internal Reference Clock selected.

MCG_SC_ATMS [2/5]

#define MCG_SC_ATMS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)

ATMS - Automatic Trim Machine Select 0b0..32 kHz Internal Reference Clock selected. 0b1..4 MHz Internal Reference Clock selected.

MCG_SC_ATMS [3/5]

#define MCG_SC_ATMS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)

ATMS - Automatic Trim Machine Select 0b0..32 kHz Internal Reference Clock selected. 0b1..4 MHz Internal Reference Clock selected.

MCG_SC_ATMS [4/5]

#define MCG_SC_ATMS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)

ATMS - Automatic Trim Machine Select 0b0..32 kHz Internal Reference Clock selected. 0b1..4 MHz Internal Reference Clock selected.

MCG_SC_ATMS [5/5]

#define MCG_SC_ATMS

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)

ATMS - Automatic Trim Machine Select 0b0..32 kHz Internal Reference Clock selected. 0b1..4 MHz Internal Reference Clock selected.

MCG_SC_FCRDIV [1/5]

#define MCG_SC_FCRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)

FCRDIV - Fast Clock Internal Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2. 0b010..Divide Factor is 4. 0b011..Divide Factor is 8. 0b100..Divide Factor is 16 0b101..Divide Factor is 32 0b110..Divide Factor is 64 0b111..Divide Factor is 128.

MCG_SC_FCRDIV [2/5]

#define MCG_SC_FCRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)

FCRDIV - Fast Clock Internal Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2. 0b010..Divide Factor is 4. 0b011..Divide Factor is 8. 0b100..Divide Factor is 16 0b101..Divide Factor is 32 0b110..Divide Factor is 64 0b111..Divide Factor is 128.

MCG_SC_FCRDIV [3/5]

#define MCG_SC_FCRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)

FCRDIV - Fast Clock Internal Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2. 0b010..Divide Factor is 4. 0b011..Divide Factor is 8. 0b100..Divide Factor is 16 0b101..Divide Factor is 32 0b110..Divide Factor is 64 0b111..Divide Factor is 128.

MCG_SC_FCRDIV [4/5]

#define MCG_SC_FCRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)

FCRDIV - Fast Clock Internal Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2. 0b010..Divide Factor is 4. 0b011..Divide Factor is 8. 0b100..Divide Factor is 16 0b101..Divide Factor is 32 0b110..Divide Factor is 64 0b111..Divide Factor is 128.

MCG_SC_FCRDIV [5/5]

#define MCG_SC_FCRDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)

FCRDIV - Fast Clock Internal Reference Divider 0b000..Divide Factor is 1 0b001..Divide Factor is 2. 0b010..Divide Factor is 4. 0b011..Divide Factor is 8. 0b100..Divide Factor is 16 0b101..Divide Factor is 32 0b110..Divide Factor is 64 0b111..Divide Factor is 128.

MCG_SC_FLTPRSRV [1/5]

#define MCG_SC_FLTPRSRV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)

FLTPRSRV - FLL Filter Preserve Enable 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.

MCG_SC_FLTPRSRV [2/5]

#define MCG_SC_FLTPRSRV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)

FLTPRSRV - FLL Filter Preserve Enable 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.

MCG_SC_FLTPRSRV [3/5]

#define MCG_SC_FLTPRSRV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)

FLTPRSRV - FLL Filter Preserve Enable 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.

MCG_SC_FLTPRSRV [4/5]

#define MCG_SC_FLTPRSRV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)

FLTPRSRV - FLL Filter Preserve Enable 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.

MCG_SC_FLTPRSRV [5/5]

#define MCG_SC_FLTPRSRV

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)

FLTPRSRV - FLL Filter Preserve Enable 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.

MCG_SC_LOCS0 [1/5]

#define MCG_SC_LOCS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)

LOCS0 - OSC0 Loss of Clock Status 0b0..Loss of OSC0 has not occurred. 0b1..Loss of OSC0 has occurred.

MCG_SC_LOCS0 [2/5]

#define MCG_SC_LOCS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)

LOCS0 - OSC0 Loss of Clock Status 0b0..Loss of OSC0 has not occurred. 0b1..Loss of OSC0 has occurred.

MCG_SC_LOCS0 [3/5]

#define MCG_SC_LOCS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)

LOCS0 - OSC0 Loss of Clock Status 0b0..Loss of OSC0 has not occurred. 0b1..Loss of OSC0 has occurred.

MCG_SC_LOCS0 [4/5]

#define MCG_SC_LOCS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)

LOCS0 - OSC0 Loss of Clock Status 0b0..Loss of OSC0 has not occurred. 0b1..Loss of OSC0 has occurred.

MCG_SC_LOCS0 [5/5]

#define MCG_SC_LOCS0

(

x

)

(((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)

LOCS0 - OSC0 Loss of Clock Status 0b0..Loss of OSC0 has not occurred. 0b1..Loss of OSC0 has occurred.