MCM Register Masks

Macros
#define	MCM_BASE   (0xE0080000u)
#define	MCM   ((MCM_Type *)MCM_BASE)
#define	MCM_BASE_ADDRS   { MCM_BASE }
#define	MCM_BASE_PTRS   { MCM }
#define	MCM_IRQS   { MCM_IRQn }
#define	MCM_SRAMAP_SRAMUAP_MASK   0x3000000u
#define	MCM_SRAMAP_SRAMUAP_SHIFT   24
#define	MCM_SRAMAP_SRAMUAP(x)   (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMUAP_SHIFT))&MCM_SRAMAP_SRAMUAP_MASK)
#define	MCM_SRAMAP_SRAMUWP_MASK   0x4000000u
#define	MCM_SRAMAP_SRAMUWP_SHIFT   26
#define	MCM_SRAMAP_SRAMLAP_MASK   0x30000000u
#define	MCM_SRAMAP_SRAMLAP_SHIFT   28
#define	MCM_SRAMAP_SRAMLAP(x)   (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMLAP_SHIFT))&MCM_SRAMAP_SRAMLAP_MASK)
#define	MCM_SRAMAP_SRAMLWP_MASK   0x40000000u
#define	MCM_SRAMAP_SRAMLWP_SHIFT   30
#define	MCM_ISR_IRQ_MASK   0x2u
#define	MCM_ISR_IRQ_SHIFT   1
#define	MCM_ISR_NMI_MASK   0x4u
#define	MCM_ISR_NMI_SHIFT   2
#define	MCM_LMEM_COUNT   (5U)

PLASC - Crossbar Switch (AXBS) Slave Configuration
#define	MCM_PLASC_ASC_MASK   (0xFFU)
#define	MCM_PLASC_ASC_SHIFT   (0U)
#define	MCM_PLASC_ASC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
#define	MCM_PLASC_ASC_MASK   0xFFu
#define	MCM_PLASC_ASC_SHIFT   0
#define	MCM_PLASC_ASC(x)   (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
#define	MCM_PLASC_ASC_MASK   (0xFFU)
#define	MCM_PLASC_ASC_SHIFT   (0U)
#define	MCM_PLASC_ASC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
#define	MCM_PLASC_ASC_MASK   (0xFFU)
#define	MCM_PLASC_ASC_SHIFT   (0U)
#define	MCM_PLASC_ASC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
#define	MCM_PLASC_ASC_MASK   (0xFFU)
#define	MCM_PLASC_ASC_SHIFT   (0U)
#define	MCM_PLASC_ASC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

PLAMC - Crossbar Switch (AXBS) Master Configuration
#define	MCM_PLAMC_AMC_MASK   (0xFFU)
#define	MCM_PLAMC_AMC_SHIFT   (0U)
#define	MCM_PLAMC_AMC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
#define	MCM_PLAMC_AMC_MASK   0xFFu
#define	MCM_PLAMC_AMC_SHIFT   0
#define	MCM_PLAMC_AMC(x)   (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
#define	MCM_PLAMC_AMC_MASK   (0xFFU)
#define	MCM_PLAMC_AMC_SHIFT   (0U)
#define	MCM_PLAMC_AMC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
#define	MCM_PLAMC_AMC_MASK   (0xFFU)
#define	MCM_PLAMC_AMC_SHIFT   (0U)
#define	MCM_PLAMC_AMC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
#define	MCM_PLAMC_AMC_MASK   (0xFFU)
#define	MCM_PLAMC_AMC_SHIFT   (0U)
#define	MCM_PLAMC_AMC(x)   (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

CR - Control Register
#define	MCM_CR_SRAMUAP_MASK   (0x3000000U)
#define	MCM_CR_SRAMUAP_SHIFT   (24U)
#define	MCM_CR_SRAMUAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
#define	MCM_CR_SRAMUWP_MASK   (0x4000000U)
#define	MCM_CR_SRAMUWP_SHIFT   (26U)
#define	MCM_CR_SRAMUWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
#define	MCM_CR_SRAMLAP_MASK   (0x30000000U)
#define	MCM_CR_SRAMLAP_SHIFT   (28U)
#define	MCM_CR_SRAMLAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
#define	MCM_CR_SRAMLWP_MASK   (0x40000000U)
#define	MCM_CR_SRAMLWP_SHIFT   (30U)
#define	MCM_CR_SRAMLWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
#define	MCM_CR_SRAMUAP_MASK   (0x3000000U)
#define	MCM_CR_SRAMUAP_SHIFT   (24U)
#define	MCM_CR_SRAMUAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
#define	MCM_CR_SRAMUWP_MASK   (0x4000000U)
#define	MCM_CR_SRAMUWP_SHIFT   (26U)
#define	MCM_CR_SRAMUWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
#define	MCM_CR_SRAMLAP_MASK   (0x30000000U)
#define	MCM_CR_SRAMLAP_SHIFT   (28U)
#define	MCM_CR_SRAMLAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
#define	MCM_CR_SRAMLWP_MASK   (0x40000000U)
#define	MCM_CR_SRAMLWP_SHIFT   (30U)
#define	MCM_CR_SRAMLWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
#define	MCM_CR_SRAMUAP_MASK   (0x3000000U)
#define	MCM_CR_SRAMUAP_SHIFT   (24U)
#define	MCM_CR_SRAMUAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
#define	MCM_CR_SRAMUWP_MASK   (0x4000000U)
#define	MCM_CR_SRAMUWP_SHIFT   (26U)
#define	MCM_CR_SRAMUWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
#define	MCM_CR_SRAMLAP_MASK   (0x30000000U)
#define	MCM_CR_SRAMLAP_SHIFT   (28U)
#define	MCM_CR_SRAMLAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
#define	MCM_CR_SRAMLWP_MASK   (0x40000000U)
#define	MCM_CR_SRAMLWP_SHIFT   (30U)
#define	MCM_CR_SRAMLWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
#define	MCM_CR_SRAMUAP_MASK   (0x3000000U)
#define	MCM_CR_SRAMUAP_SHIFT   (24U)
#define	MCM_CR_SRAMUAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
#define	MCM_CR_SRAMUWP_MASK   (0x4000000U)
#define	MCM_CR_SRAMUWP_SHIFT   (26U)
#define	MCM_CR_SRAMUWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
#define	MCM_CR_SRAMLAP_MASK   (0x30000000U)
#define	MCM_CR_SRAMLAP_SHIFT   (28U)
#define	MCM_CR_SRAMLAP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
#define	MCM_CR_SRAMLWP_MASK   (0x40000000U)
#define	MCM_CR_SRAMLWP_SHIFT   (30U)
#define	MCM_CR_SRAMLWP(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)

ISR - Interrupt Status Register
#define	MCM_ISR_IRQ_MASK   (0x2U)
#define	MCM_ISR_IRQ_SHIFT   (1U)
#define	MCM_ISR_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISR_IRQ_SHIFT)) & MCM_ISR_IRQ_MASK)
#define	MCM_ISR_NMI_MASK   (0x4U)
#define	MCM_ISR_NMI_SHIFT   (2U)
#define	MCM_ISR_NMI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISR_NMI_SHIFT)) & MCM_ISR_NMI_MASK)
#define	MCM_ISR_DHREQ_MASK   (0x8U)
#define	MCM_ISR_DHREQ_SHIFT   (3U)
#define	MCM_ISR_DHREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISR_DHREQ_SHIFT)) & MCM_ISR_DHREQ_MASK)

ETBCC - ETB Counter Control register
#define	MCM_ETBCC_CNTEN_MASK   (0x1U)
#define	MCM_ETBCC_CNTEN_SHIFT   (0U)
#define	MCM_ETBCC_CNTEN(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
#define	MCM_ETBCC_RSPT_MASK   (0x6U)
#define	MCM_ETBCC_RSPT_SHIFT   (1U)
#define	MCM_ETBCC_RSPT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
#define	MCM_ETBCC_RLRQ_MASK   (0x8U)
#define	MCM_ETBCC_RLRQ_SHIFT   (3U)
#define	MCM_ETBCC_RLRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
#define	MCM_ETBCC_ETDIS_MASK   (0x10U)
#define	MCM_ETBCC_ETDIS_SHIFT   (4U)
#define	MCM_ETBCC_ETDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
#define	MCM_ETBCC_ITDIS_MASK   (0x20U)
#define	MCM_ETBCC_ITDIS_SHIFT   (5U)
#define	MCM_ETBCC_ITDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
#define	MCM_ETBCC_CNTEN_MASK   0x1u
#define	MCM_ETBCC_CNTEN_SHIFT   0
#define	MCM_ETBCC_RSPT_MASK   0x6u
#define	MCM_ETBCC_RSPT_SHIFT   1
#define	MCM_ETBCC_RSPT(x)   (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
#define	MCM_ETBCC_RLRQ_MASK   0x8u
#define	MCM_ETBCC_RLRQ_SHIFT   3
#define	MCM_ETBCC_ETDIS_MASK   0x10u
#define	MCM_ETBCC_ETDIS_SHIFT   4
#define	MCM_ETBCC_ITDIS_MASK   0x20u
#define	MCM_ETBCC_ITDIS_SHIFT   5
#define	MCM_ETBCC_CNTEN_MASK   (0x1U)
#define	MCM_ETBCC_CNTEN_SHIFT   (0U)
#define	MCM_ETBCC_CNTEN(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
#define	MCM_ETBCC_RSPT_MASK   (0x6U)
#define	MCM_ETBCC_RSPT_SHIFT   (1U)
#define	MCM_ETBCC_RSPT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
#define	MCM_ETBCC_RLRQ_MASK   (0x8U)
#define	MCM_ETBCC_RLRQ_SHIFT   (3U)
#define	MCM_ETBCC_RLRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
#define	MCM_ETBCC_ETDIS_MASK   (0x10U)
#define	MCM_ETBCC_ETDIS_SHIFT   (4U)
#define	MCM_ETBCC_ETDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
#define	MCM_ETBCC_ITDIS_MASK   (0x20U)
#define	MCM_ETBCC_ITDIS_SHIFT   (5U)
#define	MCM_ETBCC_ITDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
#define	MCM_ETBCC_CNTEN_MASK   (0x1U)
#define	MCM_ETBCC_CNTEN_SHIFT   (0U)
#define	MCM_ETBCC_CNTEN(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
#define	MCM_ETBCC_RSPT_MASK   (0x6U)
#define	MCM_ETBCC_RSPT_SHIFT   (1U)
#define	MCM_ETBCC_RSPT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
#define	MCM_ETBCC_RLRQ_MASK   (0x8U)
#define	MCM_ETBCC_RLRQ_SHIFT   (3U)
#define	MCM_ETBCC_RLRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
#define	MCM_ETBCC_ETDIS_MASK   (0x10U)
#define	MCM_ETBCC_ETDIS_SHIFT   (4U)
#define	MCM_ETBCC_ETDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
#define	MCM_ETBCC_ITDIS_MASK   (0x20U)
#define	MCM_ETBCC_ITDIS_SHIFT   (5U)
#define	MCM_ETBCC_ITDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
#define	MCM_ETBCC_CNTEN_MASK   (0x1U)
#define	MCM_ETBCC_CNTEN_SHIFT   (0U)
#define	MCM_ETBCC_CNTEN(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
#define	MCM_ETBCC_RSPT_MASK   (0x6U)
#define	MCM_ETBCC_RSPT_SHIFT   (1U)
#define	MCM_ETBCC_RSPT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
#define	MCM_ETBCC_RLRQ_MASK   (0x8U)
#define	MCM_ETBCC_RLRQ_SHIFT   (3U)
#define	MCM_ETBCC_RLRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
#define	MCM_ETBCC_ETDIS_MASK   (0x10U)
#define	MCM_ETBCC_ETDIS_SHIFT   (4U)
#define	MCM_ETBCC_ETDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
#define	MCM_ETBCC_ITDIS_MASK   (0x20U)
#define	MCM_ETBCC_ITDIS_SHIFT   (5U)
#define	MCM_ETBCC_ITDIS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)

ETBRL - ETB Reload register
#define	MCM_ETBRL_RELOAD_MASK   (0x7FFU)
#define	MCM_ETBRL_RELOAD_SHIFT   (0U)
#define	MCM_ETBRL_RELOAD(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
#define	MCM_ETBRL_RELOAD_MASK   0x7FFu
#define	MCM_ETBRL_RELOAD_SHIFT   0
#define	MCM_ETBRL_RELOAD(x)   (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
#define	MCM_ETBRL_RELOAD_MASK   (0x7FFU)
#define	MCM_ETBRL_RELOAD_SHIFT   (0U)
#define	MCM_ETBRL_RELOAD(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
#define	MCM_ETBRL_RELOAD_MASK   (0x7FFU)
#define	MCM_ETBRL_RELOAD_SHIFT   (0U)
#define	MCM_ETBRL_RELOAD(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
#define	MCM_ETBRL_RELOAD_MASK   (0x7FFU)
#define	MCM_ETBRL_RELOAD_SHIFT   (0U)
#define	MCM_ETBRL_RELOAD(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)

ETBCNT - ETB Counter Value register
#define	MCM_ETBCNT_COUNTER_MASK   (0x7FFU)
#define	MCM_ETBCNT_COUNTER_SHIFT   (0U)
#define	MCM_ETBCNT_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
#define	MCM_ETBCNT_COUNTER_MASK   0x7FFu
#define	MCM_ETBCNT_COUNTER_SHIFT   0
#define	MCM_ETBCNT_COUNTER(x)   (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
#define	MCM_ETBCNT_COUNTER_MASK   (0x7FFU)
#define	MCM_ETBCNT_COUNTER_SHIFT   (0U)
#define	MCM_ETBCNT_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
#define	MCM_ETBCNT_COUNTER_MASK   (0x7FFU)
#define	MCM_ETBCNT_COUNTER_SHIFT   (0U)
#define	MCM_ETBCNT_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
#define	MCM_ETBCNT_COUNTER_MASK   (0x7FFU)
#define	MCM_ETBCNT_COUNTER_SHIFT   (0U)
#define	MCM_ETBCNT_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)

PID - Process ID register
#define	MCM_PID_PID_MASK   (0xFFU)
#define	MCM_PID_PID_SHIFT   (0U)
#define	MCM_PID_PID(x)   (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
#define	MCM_PID_PID_MASK   (0xFFU)
#define	MCM_PID_PID_SHIFT   (0U)
#define	MCM_PID_PID(x)   (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
#define	MCM_PID_PID_MASK   (0xFFU)
#define	MCM_PID_PID_SHIFT   (0U)
#define	MCM_PID_PID(x)   (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
#define	MCM_PID_PID_MASK   (0xFFU)
#define	MCM_PID_PID_SHIFT   (0U)
#define	MCM_PID_PID(x)   (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)

ISCR - Interrupt Status Register
#define	MCM_ISCR_IRQ_MASK   (0x2U)
#define	MCM_ISCR_IRQ_SHIFT   (1U)
#define	MCM_ISCR_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
#define	MCM_ISCR_NMI_MASK   (0x4U)
#define	MCM_ISCR_NMI_SHIFT   (2U)
#define	MCM_ISCR_NMI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
#define	MCM_ISCR_DHREQ_MASK   (0x8U)
#define	MCM_ISCR_DHREQ_SHIFT   (3U)
#define	MCM_ISCR_DHREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
#define	MCM_ISCR_IRQ_MASK   (0x2U)
#define	MCM_ISCR_IRQ_SHIFT   (1U)
#define	MCM_ISCR_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
#define	MCM_ISCR_NMI_MASK   (0x4U)
#define	MCM_ISCR_NMI_SHIFT   (2U)
#define	MCM_ISCR_NMI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
#define	MCM_ISCR_DHREQ_MASK   (0x8U)
#define	MCM_ISCR_DHREQ_SHIFT   (3U)
#define	MCM_ISCR_DHREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
#define	MCM_ISCR_IRQ_MASK   (0x2U)
#define	MCM_ISCR_IRQ_SHIFT   (1U)
#define	MCM_ISCR_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
#define	MCM_ISCR_NMI_MASK   (0x4U)
#define	MCM_ISCR_NMI_SHIFT   (2U)
#define	MCM_ISCR_NMI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
#define	MCM_ISCR_DHREQ_MASK   (0x8U)
#define	MCM_ISCR_DHREQ_SHIFT   (3U)
#define	MCM_ISCR_DHREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)

ISCR - Interrupt Status and Control Register
#define	MCM_ISCR_FIOC_MASK   (0x100U)
#define	MCM_ISCR_FIOC_SHIFT   (8U)
#define	MCM_ISCR_FIOC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
#define	MCM_ISCR_FDZC_MASK   (0x200U)
#define	MCM_ISCR_FDZC_SHIFT   (9U)
#define	MCM_ISCR_FDZC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
#define	MCM_ISCR_FOFC_MASK   (0x400U)
#define	MCM_ISCR_FOFC_SHIFT   (10U)
#define	MCM_ISCR_FOFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
#define	MCM_ISCR_FUFC_MASK   (0x800U)
#define	MCM_ISCR_FUFC_SHIFT   (11U)
#define	MCM_ISCR_FUFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
#define	MCM_ISCR_FIXC_MASK   (0x1000U)
#define	MCM_ISCR_FIXC_SHIFT   (12U)
#define	MCM_ISCR_FIXC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
#define	MCM_ISCR_FIDC_MASK   (0x8000U)
#define	MCM_ISCR_FIDC_SHIFT   (15U)
#define	MCM_ISCR_FIDC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
#define	MCM_ISCR_FIOCE_MASK   (0x1000000U)
#define	MCM_ISCR_FIOCE_SHIFT   (24U)
#define	MCM_ISCR_FIOCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
#define	MCM_ISCR_FDZCE_MASK   (0x2000000U)
#define	MCM_ISCR_FDZCE_SHIFT   (25U)
#define	MCM_ISCR_FDZCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
#define	MCM_ISCR_FOFCE_MASK   (0x4000000U)
#define	MCM_ISCR_FOFCE_SHIFT   (26U)
#define	MCM_ISCR_FOFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
#define	MCM_ISCR_FUFCE_MASK   (0x8000000U)
#define	MCM_ISCR_FUFCE_SHIFT   (27U)
#define	MCM_ISCR_FUFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
#define	MCM_ISCR_FIXCE_MASK   (0x10000000U)
#define	MCM_ISCR_FIXCE_SHIFT   (28U)
#define	MCM_ISCR_FIXCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
#define	MCM_ISCR_FIDCE_MASK   (0x80000000U)
#define	MCM_ISCR_FIDCE_SHIFT   (31U)
#define	MCM_ISCR_FIDCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
#define	MCM_ISCR_FIOC_MASK   (0x100U)
#define	MCM_ISCR_FIOC_SHIFT   (8U)
#define	MCM_ISCR_FIOC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
#define	MCM_ISCR_FDZC_MASK   (0x200U)
#define	MCM_ISCR_FDZC_SHIFT   (9U)
#define	MCM_ISCR_FDZC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
#define	MCM_ISCR_FOFC_MASK   (0x400U)
#define	MCM_ISCR_FOFC_SHIFT   (10U)
#define	MCM_ISCR_FOFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
#define	MCM_ISCR_FUFC_MASK   (0x800U)
#define	MCM_ISCR_FUFC_SHIFT   (11U)
#define	MCM_ISCR_FUFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
#define	MCM_ISCR_FIXC_MASK   (0x1000U)
#define	MCM_ISCR_FIXC_SHIFT   (12U)
#define	MCM_ISCR_FIXC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
#define	MCM_ISCR_FIDC_MASK   (0x8000U)
#define	MCM_ISCR_FIDC_SHIFT   (15U)
#define	MCM_ISCR_FIDC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
#define	MCM_ISCR_FIOCE_MASK   (0x1000000U)
#define	MCM_ISCR_FIOCE_SHIFT   (24U)
#define	MCM_ISCR_FIOCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
#define	MCM_ISCR_FDZCE_MASK   (0x2000000U)
#define	MCM_ISCR_FDZCE_SHIFT   (25U)
#define	MCM_ISCR_FDZCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
#define	MCM_ISCR_FOFCE_MASK   (0x4000000U)
#define	MCM_ISCR_FOFCE_SHIFT   (26U)
#define	MCM_ISCR_FOFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
#define	MCM_ISCR_FUFCE_MASK   (0x8000000U)
#define	MCM_ISCR_FUFCE_SHIFT   (27U)
#define	MCM_ISCR_FUFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
#define	MCM_ISCR_FIXCE_MASK   (0x10000000U)
#define	MCM_ISCR_FIXCE_SHIFT   (28U)
#define	MCM_ISCR_FIXCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
#define	MCM_ISCR_FIDCE_MASK   (0x80000000U)
#define	MCM_ISCR_FIDCE_SHIFT   (31U)
#define	MCM_ISCR_FIDCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
#define	MCM_ISCR_FIOC_MASK   (0x100U)
#define	MCM_ISCR_FIOC_SHIFT   (8U)
#define	MCM_ISCR_FIOC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
#define	MCM_ISCR_FDZC_MASK   (0x200U)
#define	MCM_ISCR_FDZC_SHIFT   (9U)
#define	MCM_ISCR_FDZC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
#define	MCM_ISCR_FOFC_MASK   (0x400U)
#define	MCM_ISCR_FOFC_SHIFT   (10U)
#define	MCM_ISCR_FOFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
#define	MCM_ISCR_FUFC_MASK   (0x800U)
#define	MCM_ISCR_FUFC_SHIFT   (11U)
#define	MCM_ISCR_FUFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
#define	MCM_ISCR_FIXC_MASK   (0x1000U)
#define	MCM_ISCR_FIXC_SHIFT   (12U)
#define	MCM_ISCR_FIXC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
#define	MCM_ISCR_FIDC_MASK   (0x8000U)
#define	MCM_ISCR_FIDC_SHIFT   (15U)
#define	MCM_ISCR_FIDC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
#define	MCM_ISCR_FIOCE_MASK   (0x1000000U)
#define	MCM_ISCR_FIOCE_SHIFT   (24U)
#define	MCM_ISCR_FIOCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
#define	MCM_ISCR_FDZCE_MASK   (0x2000000U)
#define	MCM_ISCR_FDZCE_SHIFT   (25U)
#define	MCM_ISCR_FDZCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
#define	MCM_ISCR_FOFCE_MASK   (0x4000000U)
#define	MCM_ISCR_FOFCE_SHIFT   (26U)
#define	MCM_ISCR_FOFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
#define	MCM_ISCR_FUFCE_MASK   (0x8000000U)
#define	MCM_ISCR_FUFCE_SHIFT   (27U)
#define	MCM_ISCR_FUFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
#define	MCM_ISCR_FIXCE_MASK   (0x10000000U)
#define	MCM_ISCR_FIXCE_SHIFT   (28U)
#define	MCM_ISCR_FIXCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
#define	MCM_ISCR_FIDCE_MASK   (0x80000000U)
#define	MCM_ISCR_FIDCE_SHIFT   (31U)
#define	MCM_ISCR_FIDCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
#define	MCM_ISCR_FIOC_MASK   (0x100U)
#define	MCM_ISCR_FIOC_SHIFT   (8U)
#define	MCM_ISCR_FIOC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
#define	MCM_ISCR_FDZC_MASK   (0x200U)
#define	MCM_ISCR_FDZC_SHIFT   (9U)
#define	MCM_ISCR_FDZC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
#define	MCM_ISCR_FOFC_MASK   (0x400U)
#define	MCM_ISCR_FOFC_SHIFT   (10U)
#define	MCM_ISCR_FOFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
#define	MCM_ISCR_FUFC_MASK   (0x800U)
#define	MCM_ISCR_FUFC_SHIFT   (11U)
#define	MCM_ISCR_FUFC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
#define	MCM_ISCR_FIXC_MASK   (0x1000U)
#define	MCM_ISCR_FIXC_SHIFT   (12U)
#define	MCM_ISCR_FIXC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
#define	MCM_ISCR_FIDC_MASK   (0x8000U)
#define	MCM_ISCR_FIDC_SHIFT   (15U)
#define	MCM_ISCR_FIDC(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
#define	MCM_ISCR_FIOCE_MASK   (0x1000000U)
#define	MCM_ISCR_FIOCE_SHIFT   (24U)
#define	MCM_ISCR_FIOCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
#define	MCM_ISCR_FDZCE_MASK   (0x2000000U)
#define	MCM_ISCR_FDZCE_SHIFT   (25U)
#define	MCM_ISCR_FDZCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
#define	MCM_ISCR_FOFCE_MASK   (0x4000000U)
#define	MCM_ISCR_FOFCE_SHIFT   (26U)
#define	MCM_ISCR_FOFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
#define	MCM_ISCR_FUFCE_MASK   (0x8000000U)
#define	MCM_ISCR_FUFCE_SHIFT   (27U)
#define	MCM_ISCR_FUFCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
#define	MCM_ISCR_FIXCE_MASK   (0x10000000U)
#define	MCM_ISCR_FIXCE_SHIFT   (28U)
#define	MCM_ISCR_FIXCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
#define	MCM_ISCR_FIDCE_MASK   (0x80000000U)
#define	MCM_ISCR_FIDCE_SHIFT   (31U)
#define	MCM_ISCR_FIDCE(x)   (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FADR - Fault address register
#define	MCM_FADR_ADDRESS_MASK   (0xFFFFFFFFU)
#define	MCM_FADR_ADDRESS_SHIFT   (0U)
#define	MCM_FADR_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
#define	MCM_FADR_ADDRESS_MASK   (0xFFFFFFFFU)
#define	MCM_FADR_ADDRESS_SHIFT   (0U)
#define	MCM_FADR_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)

FATR - Fault attributes register
#define	MCM_FATR_BEDA_MASK   (0x1U)
#define	MCM_FATR_BEDA_SHIFT   (0U)
#define	MCM_FATR_BEDA(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
#define	MCM_FATR_BEMD_MASK   (0x2U)
#define	MCM_FATR_BEMD_SHIFT   (1U)
#define	MCM_FATR_BEMD(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
#define	MCM_FATR_BESZ_MASK   (0x30U)
#define	MCM_FATR_BESZ_SHIFT   (4U)
#define	MCM_FATR_BESZ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
#define	MCM_FATR_BEWT_MASK   (0x80U)
#define	MCM_FATR_BEWT_SHIFT   (7U)
#define	MCM_FATR_BEWT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
#define	MCM_FATR_BEMN_MASK   (0xF00U)
#define	MCM_FATR_BEMN_SHIFT   (8U)
#define	MCM_FATR_BEMN(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
#define	MCM_FATR_BEOVR_MASK   (0x80000000U)
#define	MCM_FATR_BEOVR_SHIFT   (31U)
#define	MCM_FATR_BEOVR(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
#define	MCM_FATR_BEDA_MASK   (0x1U)
#define	MCM_FATR_BEDA_SHIFT   (0U)
#define	MCM_FATR_BEDA(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
#define	MCM_FATR_BEMD_MASK   (0x2U)
#define	MCM_FATR_BEMD_SHIFT   (1U)
#define	MCM_FATR_BEMD(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
#define	MCM_FATR_BESZ_MASK   (0x30U)
#define	MCM_FATR_BESZ_SHIFT   (4U)
#define	MCM_FATR_BESZ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
#define	MCM_FATR_BEWT_MASK   (0x80U)
#define	MCM_FATR_BEWT_SHIFT   (7U)
#define	MCM_FATR_BEWT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
#define	MCM_FATR_BEMN_MASK   (0xF00U)
#define	MCM_FATR_BEMN_SHIFT   (8U)
#define	MCM_FATR_BEMN(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
#define	MCM_FATR_BEOVR_MASK   (0x80000000U)
#define	MCM_FATR_BEOVR_SHIFT   (31U)
#define	MCM_FATR_BEOVR(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)

FDR - Fault data register
#define	MCM_FDR_DATA_MASK   (0xFFFFFFFFU)
#define	MCM_FDR_DATA_SHIFT   (0U)
#define	MCM_FDR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
#define	MCM_FDR_DATA_MASK   (0xFFFFFFFFU)
#define	MCM_FDR_DATA_SHIFT   (0U)
#define	MCM_FDR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)

CPO - Compute Only Operation Control Register
#define	MCM_CPO_CPOREQ_MASK   (0x1U)
#define	MCM_CPO_CPOREQ_SHIFT   (0U)
#define	MCM_CPO_CPOREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
#define	MCM_CPO_CPOACK_MASK   (0x2U)
#define	MCM_CPO_CPOACK_SHIFT   (1U)
#define	MCM_CPO_CPOACK(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
#define	MCM_CPO_CPOREQ_MASK   (0x1U)
#define	MCM_CPO_CPOREQ_SHIFT   (0U)
#define	MCM_CPO_CPOREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
#define	MCM_CPO_CPOACK_MASK   (0x2U)
#define	MCM_CPO_CPOACK_SHIFT   (1U)
#define	MCM_CPO_CPOACK(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
#define	MCM_CPO_CPOREQ_MASK   (0x1U)
#define	MCM_CPO_CPOREQ_SHIFT   (0U)
#define	MCM_CPO_CPOREQ(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
#define	MCM_CPO_CPOACK_MASK   (0x2U)
#define	MCM_CPO_CPOACK_SHIFT   (1U)
#define	MCM_CPO_CPOACK(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)

CPO - Compute Operation Control Register
#define	MCM_CPO_CPOWOI_MASK   (0x4U)
#define	MCM_CPO_CPOWOI_SHIFT   (2U)
#define	MCM_CPO_CPOWOI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
#define	MCM_CPO_CPOWOI_MASK   (0x4U)
#define	MCM_CPO_CPOWOI_SHIFT   (2U)
#define	MCM_CPO_CPOWOI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)

PCT - Processor core type
#define	MCM_PCT_PLREV_MASK   (0xFFFFU)
#define	MCM_PCT_PLREV_SHIFT   (0U)
#define	MCM_PCT_PLREV(x)   (((uint32_t)(((uint32_t)(x)) << MCM_PCT_PLREV_SHIFT)) & MCM_PCT_PLREV_MASK)
#define	MCM_PCT_PCT_MASK   (0xFFFF0000U)
#define	MCM_PCT_PCT_SHIFT   (16U)
#define	MCM_PCT_PCT(x)   (((uint32_t)(((uint32_t)(x)) << MCM_PCT_PCT_SHIFT)) & MCM_PCT_PCT_MASK)

CR - Control Register
#define	MCM_CR_AHBSPRI_MASK   (0x8000000U)
#define	MCM_CR_AHBSPRI_SHIFT   (27U)
#define	MCM_CR_AHBSPRI(x)   (((uint32_t)(((uint32_t)(x)) << MCM_CR_AHBSPRI_SHIFT)) & MCM_CR_AHBSPRI_MASK)

LMEM - Local Memory General Descriptor Register
#define	MCM_LMEM_LMEM_Type_MASK   (0xE000U)
#define	MCM_LMEM_LMEM_Type_SHIFT   (13U)
#define	MCM_LMEM_LMEM_Type(x)   (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Type_SHIFT)) & MCM_LMEM_LMEM_Type_MASK)
#define	MCM_LMEM_LMEM_Width_MASK   (0xE0000U)
#define	MCM_LMEM_LMEM_Width_SHIFT   (17U)
#define	MCM_LMEM_LMEM_Width(x)   (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Width_SHIFT)) & MCM_LMEM_LMEM_Width_MASK)
#define	MCM_LMEM_LMEM_Ways_MASK   (0xF00000U)
#define	MCM_LMEM_LMEM_Ways_SHIFT   (20U)
#define	MCM_LMEM_LMEM_Ways(x)   (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Ways_SHIFT)) & MCM_LMEM_LMEM_Ways_MASK)
#define	MCM_LMEM_LMEM_Size_MASK   (0xF000000U)
#define	MCM_LMEM_LMEM_Size_SHIFT   (24U)
#define	MCM_LMEM_LMEM_Size(x)   (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Size_SHIFT)) & MCM_LMEM_LMEM_Size_MASK)
#define	MCM_LMEM_LMEM_Valid_MASK   (0x80000000U)
#define	MCM_LMEM_LMEM_Valid_SHIFT   (31U)
#define	MCM_LMEM_LMEM_Valid(x)   (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Valid_SHIFT)) & MCM_LMEM_LMEM_Valid_MASK)

Macro Definition Documentation

MCM

#define MCM   ((MCM_Type *)MCM_BASE)

Peripheral MCM base pointer

MCM_BASE

#define MCM_BASE   (0xE0080000u)

Peripheral MCM base address

MCM_BASE_ADDRS

#define MCM_BASE_ADDRS   { MCM_BASE }

Array initializer of MCM peripheral base addresses

MCM_BASE_PTRS

#define MCM_BASE_PTRS   { MCM }

Array initializer of MCM peripheral base pointers

MCM_CPO_CPOACK [1/3]

#define MCM_CPO_CPOACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)

CPOACK - Compute Operation acknowledge 0b0..Compute operation entry has not completed or compute operation exit has completed. 0b1..Compute operation entry has completed or compute operation exit has not completed.

CPOACK - Compute Only Operation acknowledge 0b0..Compute only operation entry has not completed or compute only operation exit has completed. 0b1..Compute only operation entry has completed or compute only operation exit has not completed.

MCM_CPO_CPOACK [2/3]

#define MCM_CPO_CPOACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)

CPOACK - Compute Operation acknowledge 0b0..Compute operation entry has not completed or compute operation exit has completed. 0b1..Compute operation entry has completed or compute operation exit has not completed.

CPOACK - Compute Only Operation acknowledge 0b0..Compute only operation entry has not completed or compute only operation exit has completed. 0b1..Compute only operation entry has completed or compute only operation exit has not completed.

MCM_CPO_CPOACK [3/3]

#define MCM_CPO_CPOACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)

CPOACK - Compute Only Operation acknowledge 0b0..Compute only operation entry has not completed or compute only operation exit has completed. 0b1..Compute only operation entry has completed or compute only operation exit has not completed.

MCM_CPO_CPOREQ [1/3]

#define MCM_CPO_CPOREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)

CPOREQ - Compute Operation request 0b0..Request is cleared. 0b1..Request Compute Operation.

CPOREQ - Compute Only Operation request 0b0..Request is cleared. 0b1..Request Compute Only Operation.

MCM_CPO_CPOREQ [2/3]

#define MCM_CPO_CPOREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)

CPOREQ - Compute Operation request 0b0..Request is cleared. 0b1..Request Compute Operation.

CPOREQ - Compute Only Operation request 0b0..Request is cleared. 0b1..Request Compute Only Operation.

MCM_CPO_CPOREQ [3/3]

#define MCM_CPO_CPOREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)

CPOREQ - Compute Only Operation request 0b0..Request is cleared. 0b1..Request Compute Only Operation.

MCM_CPO_CPOWOI [1/2]

#define MCM_CPO_CPOWOI

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)

CPOWOI - Compute Operation wakeup on interrupt 0b0..No effect. 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.

MCM_CPO_CPOWOI [2/2]

#define MCM_CPO_CPOWOI

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)

CPOWOI - Compute Operation wakeup on interrupt 0b0..No effect. 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.

MCM_CR_AHBSPRI

#define MCM_CR_AHBSPRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_AHBSPRI_SHIFT)) & MCM_CR_AHBSPRI_MASK)

AHBSPRI - AHB Slave Interface Priority 0b0..SW accesses take priority over AHBS accesses 0b1..AHBS accesses take priority over SW accesses

MCM_CR_SRAMLAP [1/4]

#define MCM_CR_SRAMLAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)

SRAMLAP - SRAM_L arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMLAP [2/4]

#define MCM_CR_SRAMLAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)

SRAMLAP - SRAM_L arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMLAP [3/4]

#define MCM_CR_SRAMLAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)

SRAMLAP - SRAM_L arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMLAP [4/4]

#define MCM_CR_SRAMLAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)

SRAMLAP - SRAM_L arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMUAP [1/4]

#define MCM_CR_SRAMUAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)

SRAMUAP - SRAM_U arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMUAP [2/4]

#define MCM_CR_SRAMUAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)

SRAMUAP - SRAM_U arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMUAP [3/4]

#define MCM_CR_SRAMUAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)

SRAMUAP - SRAM_U arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_CR_SRAMUAP [4/4]

#define MCM_CR_SRAMUAP

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)

SRAMUAP - SRAM_U arbitration priority 0b00..Round robin 0b01..Special round robin (favors SRAM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

MCM_ETBCC_CNTEN [1/4]

#define MCM_ETBCC_CNTEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)

CNTEN - Counter Enable 0b0..ETB counter disabled 0b1..ETB counter enabled

MCM_ETBCC_CNTEN [2/4]

#define MCM_ETBCC_CNTEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)

CNTEN - Counter Enable 0b0..ETB counter disabled 0b1..ETB counter enabled

MCM_ETBCC_CNTEN [3/4]

#define MCM_ETBCC_CNTEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)

CNTEN - Counter Enable 0b0..ETB counter disabled 0b1..ETB counter enabled

MCM_ETBCC_CNTEN [4/4]

#define MCM_ETBCC_CNTEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)

CNTEN - Counter Enable 0b0..ETB counter disabled 0b1..ETB counter enabled

MCM_ETBCC_ETDIS [1/4]

#define MCM_ETBCC_ETDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)

ETDIS - ETM-To-TPIU Disable 0b0..ETM-to-TPIU trace path enabled 0b1..ETM-to-TPIU trace path disabled

MCM_ETBCC_ETDIS [2/4]

#define MCM_ETBCC_ETDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)

ETDIS - ETM-To-TPIU Disable 0b0..ETM-to-TPIU trace path enabled 0b1..ETM-to-TPIU trace path disabled

MCM_ETBCC_ETDIS [3/4]

#define MCM_ETBCC_ETDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)

ETDIS - ETM-To-TPIU Disable 0b0..ETM-to-TPIU trace path enabled 0b1..ETM-to-TPIU trace path disabled

MCM_ETBCC_ETDIS [4/4]

#define MCM_ETBCC_ETDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)

ETDIS - ETM-To-TPIU Disable 0b0..ETM-to-TPIU trace path enabled 0b1..ETM-to-TPIU trace path disabled

MCM_ETBCC_ITDIS [1/4]

#define MCM_ETBCC_ITDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)

ITDIS - ITM-To-TPIU Disable 0b0..ITM-to-TPIU trace path enabled 0b1..ITM-to-TPIU trace path disabled

MCM_ETBCC_ITDIS [2/4]

#define MCM_ETBCC_ITDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)

ITDIS - ITM-To-TPIU Disable 0b0..ITM-to-TPIU trace path enabled 0b1..ITM-to-TPIU trace path disabled

MCM_ETBCC_ITDIS [3/4]

#define MCM_ETBCC_ITDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)

ITDIS - ITM-To-TPIU Disable 0b0..ITM-to-TPIU trace path enabled 0b1..ITM-to-TPIU trace path disabled

MCM_ETBCC_ITDIS [4/4]

#define MCM_ETBCC_ITDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)

ITDIS - ITM-To-TPIU Disable 0b0..ITM-to-TPIU trace path enabled 0b1..ITM-to-TPIU trace path disabled

MCM_ETBCC_RLRQ [1/4]

#define MCM_ETBCC_RLRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)

RLRQ - Reload Request 0b0..No effect 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests

MCM_ETBCC_RLRQ [2/4]

#define MCM_ETBCC_RLRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)

RLRQ - Reload Request 0b0..No effect 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests

MCM_ETBCC_RLRQ [3/4]

#define MCM_ETBCC_RLRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)

RLRQ - Reload Request 0b0..No effect 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests

MCM_ETBCC_RLRQ [4/4]

#define MCM_ETBCC_RLRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)

RLRQ - Reload Request 0b0..No effect 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests

MCM_ETBCC_RSPT [1/5]

#define MCM_ETBCC_RSPT

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)

RSPT - Response Type 0b00..No response when the ETB count expires 0b01..Generate a normal interrupt when the ETB count expires 0b10..Generate an NMI when the ETB count expires 0b11..Generate a debug halt when the ETB count expires

MCM_ETBCC_RSPT [2/5]

#define MCM_ETBCC_RSPT

(

x

)

(((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)

RSPT - Response Type 0b00..No response when the ETB count expires 0b01..Generate a normal interrupt when the ETB count expires 0b10..Generate an NMI when the ETB count expires 0b11..Generate a debug halt when the ETB count expires

MCM_ETBCC_RSPT [3/5]

#define MCM_ETBCC_RSPT

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)

RSPT - Response Type 0b00..No response when the ETB count expires 0b01..Generate a normal interrupt when the ETB count expires 0b10..Generate an NMI when the ETB count expires 0b11..Generate a debug halt when the ETB count expires

MCM_ETBCC_RSPT [4/5]

#define MCM_ETBCC_RSPT

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)

RSPT - Response Type 0b00..No response when the ETB count expires 0b01..Generate a normal interrupt when the ETB count expires 0b10..Generate an NMI when the ETB count expires 0b11..Generate a debug halt when the ETB count expires

MCM_ETBCC_RSPT [5/5]

#define MCM_ETBCC_RSPT

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)

RSPT - Response Type 0b00..No response when the ETB count expires 0b01..Generate a normal interrupt when the ETB count expires 0b10..Generate an NMI when the ETB count expires 0b11..Generate a debug halt when the ETB count expires

MCM_FATR_BEDA [1/2]

#define MCM_FATR_BEDA

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)

BEDA - Bus error access type 0b0..Instruction 0b1..Data

MCM_FATR_BEDA [2/2]

#define MCM_FATR_BEDA

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)

BEDA - Bus error access type 0b0..Instruction 0b1..Data

MCM_FATR_BEMD [1/2]

#define MCM_FATR_BEMD

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)

BEMD - Bus error privilege level 0b0..User mode 0b1..Supervisor/privileged mode

MCM_FATR_BEMD [2/2]

#define MCM_FATR_BEMD

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)

BEMD - Bus error privilege level 0b0..User mode 0b1..Supervisor/privileged mode

MCM_FATR_BEOVR [1/2]

#define MCM_FATR_BEOVR

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)

BEOVR - Bus error overrun 0b0..No bus error overrun 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.

MCM_FATR_BEOVR [2/2]

#define MCM_FATR_BEOVR

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)

BEOVR - Bus error overrun 0b0..No bus error overrun 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.

MCM_FATR_BESZ [1/2]

#define MCM_FATR_BESZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)

BESZ - Bus error size 0b00..8-bit access 0b01..16-bit access 0b10..32-bit access 0b11..Reserved

MCM_FATR_BESZ [2/2]

#define MCM_FATR_BESZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)

BESZ - Bus error size 0b00..8-bit access 0b01..16-bit access 0b10..32-bit access 0b11..Reserved

MCM_FATR_BEWT [1/2]

#define MCM_FATR_BEWT

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)

BEWT - Bus error write 0b0..Read access 0b1..Write access

MCM_FATR_BEWT [2/2]

#define MCM_FATR_BEWT

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)

BEWT - Bus error write 0b0..Read access 0b1..Write access

MCM_IRQS

#define MCM_IRQS   { MCM_IRQn }

Interrupt vectors for the MCM peripheral type

MCM_ISCR_DHREQ [1/3]

#define MCM_ISCR_DHREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)

DHREQ - Debug Halt Request Indicator 0b0..No debug halt request 0b1..Debug halt request initiated

MCM_ISCR_DHREQ [2/3]

#define MCM_ISCR_DHREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)

DHREQ - Debug Halt Request Indicator 0b0..No debug halt request 0b1..Debug halt request initiated

MCM_ISCR_DHREQ [3/3]

#define MCM_ISCR_DHREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)

DHREQ - Debug Halt Request Indicator 0b0..No debug halt request 0b1..Debug halt request initiated

MCM_ISCR_FDZC [1/4]

#define MCM_ISCR_FDZC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FDZC [2/4]

#define MCM_ISCR_FDZC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FDZC [3/4]

#define MCM_ISCR_FDZC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FDZC [4/4]

#define MCM_ISCR_FDZC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FDZCE [1/4]

#define MCM_ISCR_FDZCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

FDZCE - FPU divide-by-zero interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FDZCE [2/4]

#define MCM_ISCR_FDZCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

FDZCE - FPU divide-by-zero interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FDZCE [3/4]

#define MCM_ISCR_FDZCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

FDZCE - FPU divide-by-zero interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FDZCE [4/4]

#define MCM_ISCR_FDZCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

FDZCE - FPU divide-by-zero interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIDC [1/4]

#define MCM_ISCR_FIDC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIDC [2/4]

#define MCM_ISCR_FIDC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIDC [3/4]

#define MCM_ISCR_FIDC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIDC [4/4]

#define MCM_ISCR_FIDC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIDCE [1/4]

#define MCM_ISCR_FIDCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FIDCE - FPU input denormal interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIDCE [2/4]

#define MCM_ISCR_FIDCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FIDCE - FPU input denormal interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIDCE [3/4]

#define MCM_ISCR_FIDCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FIDCE - FPU input denormal interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIDCE [4/4]

#define MCM_ISCR_FIDCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FIDCE - FPU input denormal interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIOC [1/4]

#define MCM_ISCR_FIOC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FIOC [2/4]

#define MCM_ISCR_FIOC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FIOC [3/4]

#define MCM_ISCR_FIOC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FIOC [4/4]

#define MCM_ISCR_FIOC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FIOCE [1/4]

#define MCM_ISCR_FIOCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

FIOCE - FPU invalid operation interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIOCE [2/4]

#define MCM_ISCR_FIOCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

FIOCE - FPU invalid operation interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIOCE [3/4]

#define MCM_ISCR_FIOCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

FIOCE - FPU invalid operation interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIOCE [4/4]

#define MCM_ISCR_FIOCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

FIOCE - FPU invalid operation interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIXC [1/4]

#define MCM_ISCR_FIXC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIXC [2/4]

#define MCM_ISCR_FIXC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIXC [3/4]

#define MCM_ISCR_FIXC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIXC [4/4]

#define MCM_ISCR_FIXC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt has occured

MCM_ISCR_FIXCE [1/4]

#define MCM_ISCR_FIXCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

FIXCE - FPU inexact interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIXCE [2/4]

#define MCM_ISCR_FIXCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

FIXCE - FPU inexact interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIXCE [3/4]

#define MCM_ISCR_FIXCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

FIXCE - FPU inexact interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FIXCE [4/4]

#define MCM_ISCR_FIXCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

FIXCE - FPU inexact interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FOFC [1/4]

#define MCM_ISCR_FOFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FOFC [2/4]

#define MCM_ISCR_FOFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FOFC [3/4]

#define MCM_ISCR_FOFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FOFC [4/4]

#define MCM_ISCR_FOFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FOFCE [1/4]

#define MCM_ISCR_FOFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

FOFCE - FPU overflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FOFCE [2/4]

#define MCM_ISCR_FOFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

FOFCE - FPU overflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FOFCE [3/4]

#define MCM_ISCR_FOFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

FOFCE - FPU overflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FOFCE [4/4]

#define MCM_ISCR_FOFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

FOFCE - FPU overflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FUFC [1/4]

#define MCM_ISCR_FUFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FUFC [2/4]

#define MCM_ISCR_FUFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FUFC [3/4]

#define MCM_ISCR_FUFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FUFC [4/4]

#define MCM_ISCR_FUFC

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt has occurred

MCM_ISCR_FUFCE [1/4]

#define MCM_ISCR_FUFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

FUFCE - FPU underflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FUFCE [2/4]

#define MCM_ISCR_FUFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

FUFCE - FPU underflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FUFCE [3/4]

#define MCM_ISCR_FUFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

FUFCE - FPU underflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_FUFCE [4/4]

#define MCM_ISCR_FUFCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

FUFCE - FPU underflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

MCM_ISCR_IRQ [1/3]

#define MCM_ISCR_IRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)

IRQ - Normal Interrupt Pending 0b0..No pending interrupt 0b1..Due to the ETB counter expiring, a normal interrupt is pending

MCM_ISCR_IRQ [2/3]

#define MCM_ISCR_IRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)

IRQ - Normal Interrupt Pending 0b0..No pending interrupt 0b1..Due to the ETB counter expiring, a normal interrupt is pending

MCM_ISCR_IRQ [3/3]

#define MCM_ISCR_IRQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)

IRQ - Normal Interrupt Pending 0b0..No pending interrupt 0b1..Due to the ETB counter expiring, a normal interrupt is pending

MCM_ISCR_NMI [1/3]

#define MCM_ISCR_NMI

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)

NMI - Non-maskable Interrupt Pending 0b0..No pending NMI 0b1..Due to the ETB counter expiring, an NMI is pending

MCM_ISCR_NMI [2/3]

#define MCM_ISCR_NMI

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)

NMI - Non-maskable Interrupt Pending 0b0..No pending NMI 0b1..Due to the ETB counter expiring, an NMI is pending

MCM_ISCR_NMI [3/3]

#define MCM_ISCR_NMI

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)

NMI - Non-maskable Interrupt Pending 0b0..No pending NMI 0b1..Due to the ETB counter expiring, an NMI is pending

MCM_LMEM_LMEM_Size

#define MCM_LMEM_LMEM_Size

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Size_SHIFT)) & MCM_LMEM_LMEM_Size_MASK)

LMEM_Size 0b0100..8KB 0b0101..16KB 0b0111..64KB

MCM_LMEM_LMEM_Type

#define MCM_LMEM_LMEM_Type

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Type_SHIFT)) & MCM_LMEM_LMEM_Type_MASK)

LMEM_Type 0b000..ITCM (Instruction Tightly Coupled Memory) 0b001..DTCM (Data Tightly Coupled Memory) 0b010..Instruction Cache 0b011..Data Cache

MCM_LMEM_LMEM_Valid

#define MCM_LMEM_LMEM_Valid

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Valid_SHIFT)) & MCM_LMEM_LMEM_Valid_MASK)

LMEM_Valid 0b0..Local memory not present 0b1..Local memory present

MCM_LMEM_LMEM_Ways

#define MCM_LMEM_LMEM_Ways

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Ways_SHIFT)) & MCM_LMEM_LMEM_Ways_MASK)

LMEM_Ways 0b0000..Reserved (not applicable) 0b0010..2-way set associative 0b0100..4-way set associative

MCM_LMEM_LMEM_Width

#define MCM_LMEM_LMEM_Width

(

x

)

(((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Width_SHIFT)) & MCM_LMEM_LMEM_Width_MASK)

LMEM_Width 0b010..32-bits 0b011..64-bits

MCM_PLAMC_AMC [1/5]

#define MCM_PLAMC_AMC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0b00000000..A bus master connection to AXBS input port n is absent 0b00000001..A bus master connection to AXBS input port n is present

MCM_PLAMC_AMC [2/5]

#define MCM_PLAMC_AMC

(

x

)

(((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)

AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0b00000000..A bus master connection to AXBS input port n is absent 0b00000001..A bus master connection to AXBS input port n is present

MCM_PLAMC_AMC [3/5]

#define MCM_PLAMC_AMC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0b00000000..A bus master connection to AXBS input port n is absent 0b00000001..A bus master connection to AXBS input port n is present

MCM_PLAMC_AMC [4/5]

#define MCM_PLAMC_AMC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0b00000000..A bus master connection to AXBS input port n is absent 0b00000001..A bus master connection to AXBS input port n is present

MCM_PLAMC_AMC [5/5]

#define MCM_PLAMC_AMC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0b00000000..A bus master connection to AXBS input port n is absent 0b00000001..A bus master connection to AXBS input port n is present

MCM_PLASC_ASC [1/5]

#define MCM_PLASC_ASC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0b00000000..A bus slave connection to AXBS input port n is absent 0b00000001..A bus slave connection to AXBS input port n is present

MCM_PLASC_ASC [2/5]

#define MCM_PLASC_ASC

(

x

)

(((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)

ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0b00000000..A bus slave connection to AXBS input port n is absent 0b00000001..A bus slave connection to AXBS input port n is present

MCM_PLASC_ASC [3/5]

#define MCM_PLASC_ASC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0b00000000..A bus slave connection to AXBS input port n is absent 0b00000001..A bus slave connection to AXBS input port n is present

MCM_PLASC_ASC [4/5]

#define MCM_PLASC_ASC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0b00000000..A bus slave connection to AXBS input port n is absent 0b00000001..A bus slave connection to AXBS input port n is present

MCM_PLASC_ASC [5/5]

#define MCM_PLASC_ASC

(

x

)

(((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0b00000000..A bus slave connection to AXBS input port n is absent 0b00000001..A bus slave connection to AXBS input port n is present