mikroSDK Reference Manual
Macros
PIT Register Masks
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Macros

#define PIT_BASE   (0x40037000u)
 
#define PIT   ((PIT_Type *)PIT_BASE)
 
#define PIT_BASE_ADDRS   { PIT_BASE }
 
#define PIT_BASE_PTRS   { PIT }
 
#define PIT_IRQS   { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
 
#define PIT_LDVAL_COUNT   (4U)
 
#define PIT_CVAL_COUNT   (4U)
 
#define PIT_TCTRL_COUNT   (4U)
 
#define PIT_TFLG_COUNT   (4U)
 
#define PIT_LDVAL_COUNT   (4U)
 
#define PIT_CVAL_COUNT   (4U)
 
#define PIT_TCTRL_COUNT   (4U)
 
#define PIT_TFLG_COUNT   (4U)
 
#define PIT_LDVAL_COUNT   (4U)
 
#define PIT_CVAL_COUNT   (4U)
 
#define PIT_TCTRL_COUNT   (4U)
 
#define PIT_TFLG_COUNT   (4U)
 
#define PIT_LDVAL_COUNT   (4U)
 
#define PIT_CVAL_COUNT   (4U)
 
#define PIT_TCTRL_COUNT   (4U)
 
#define PIT_TFLG_COUNT   (4U)
 

MCR - PIT Module Control Register

#define PIT_MCR_FRZ_MASK   (0x1U)
 
#define PIT_MCR_FRZ_SHIFT   (0U)
 
#define PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
 
#define PIT_MCR_MDIS_MASK   (0x2U)
 
#define PIT_MCR_MDIS_SHIFT   (1U)
 
#define PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 
#define PIT_MCR_FRZ_MASK   0x1u
 
#define PIT_MCR_FRZ_SHIFT   0
 
#define PIT_MCR_MDIS_MASK   0x2u
 
#define PIT_MCR_MDIS_SHIFT   1
 
#define PIT_MCR_FRZ_MASK   (0x1U)
 
#define PIT_MCR_FRZ_SHIFT   (0U)
 
#define PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
 
#define PIT_MCR_MDIS_MASK   (0x2U)
 
#define PIT_MCR_MDIS_SHIFT   (1U)
 
#define PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 
#define PIT_MCR_FRZ_MASK   (0x1U)
 
#define PIT_MCR_FRZ_SHIFT   (0U)
 
#define PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
 
#define PIT_MCR_MDIS_MASK   (0x2U)
 
#define PIT_MCR_MDIS_SHIFT   (1U)
 
#define PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 
#define PIT_MCR_FRZ_MASK   (0x1U)
 
#define PIT_MCR_FRZ_SHIFT   (0U)
 
#define PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
 
#define PIT_MCR_MDIS_MASK   (0x2U)
 
#define PIT_MCR_MDIS_SHIFT   (1U)
 
#define PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 
#define PIT_MCR_FRZ_MASK   (0x1U)
 
#define PIT_MCR_FRZ_SHIFT   (0U)
 
#define PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
 
#define PIT_MCR_MDIS_MASK   (0x2U)
 
#define PIT_MCR_MDIS_SHIFT   (1U)
 
#define PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 

LDVAL - Timer Load Value Register

#define PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
 
#define PIT_LDVAL_TSV_SHIFT   (0U)
 
#define PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
 
#define PIT_LDVAL_TSV_MASK   0xFFFFFFFFu
 
#define PIT_LDVAL_TSV_SHIFT   0
 
#define PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
 
#define PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
 
#define PIT_LDVAL_TSV_SHIFT   (0U)
 
#define PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
 
#define PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
 
#define PIT_LDVAL_TSV_SHIFT   (0U)
 
#define PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
 
#define PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
 
#define PIT_LDVAL_TSV_SHIFT   (0U)
 
#define PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
 
#define PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
 
#define PIT_LDVAL_TSV_SHIFT   (0U)
 
#define PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
 

LDVAL - Timer Load Value Register

#define PIT_LDVAL_COUNT   (4U)
 

CVAL - Current Timer Value Register

#define PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
 
#define PIT_CVAL_TVL_SHIFT   (0U)
 
#define PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
 
#define PIT_CVAL_TVL_MASK   0xFFFFFFFFu
 
#define PIT_CVAL_TVL_SHIFT   0
 
#define PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
 
#define PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
 
#define PIT_CVAL_TVL_SHIFT   (0U)
 
#define PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
 
#define PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
 
#define PIT_CVAL_TVL_SHIFT   (0U)
 
#define PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
 
#define PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
 
#define PIT_CVAL_TVL_SHIFT   (0U)
 
#define PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
 
#define PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
 
#define PIT_CVAL_TVL_SHIFT   (0U)
 
#define PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
 

CVAL - Current Timer Value Register

#define PIT_CVAL_COUNT   (4U)
 

TCTRL - Timer Control Register

#define PIT_TCTRL_TEN_MASK   (0x1U)
 
#define PIT_TCTRL_TEN_SHIFT   (0U)
 
#define PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
 
#define PIT_TCTRL_TIE_MASK   (0x2U)
 
#define PIT_TCTRL_TIE_SHIFT   (1U)
 
#define PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
 
#define PIT_TCTRL_CHN_MASK   (0x4U)
 
#define PIT_TCTRL_CHN_SHIFT   (2U)
 
#define PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
 
#define PIT_TCTRL_TEN_MASK   0x1u
 
#define PIT_TCTRL_TEN_SHIFT   0
 
#define PIT_TCTRL_TIE_MASK   0x2u
 
#define PIT_TCTRL_TIE_SHIFT   1
 
#define PIT_TCTRL_TEN_MASK   (0x1U)
 
#define PIT_TCTRL_TEN_SHIFT   (0U)
 
#define PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
 
#define PIT_TCTRL_TIE_MASK   (0x2U)
 
#define PIT_TCTRL_TIE_SHIFT   (1U)
 
#define PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
 
#define PIT_TCTRL_CHN_MASK   (0x4U)
 
#define PIT_TCTRL_CHN_SHIFT   (2U)
 
#define PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
 
#define PIT_TCTRL_TEN_MASK   (0x1U)
 
#define PIT_TCTRL_TEN_SHIFT   (0U)
 
#define PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
 
#define PIT_TCTRL_TIE_MASK   (0x2U)
 
#define PIT_TCTRL_TIE_SHIFT   (1U)
 
#define PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
 
#define PIT_TCTRL_CHN_MASK   (0x4U)
 
#define PIT_TCTRL_CHN_SHIFT   (2U)
 
#define PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
 
#define PIT_TCTRL_TEN_MASK   (0x1U)
 
#define PIT_TCTRL_TEN_SHIFT   (0U)
 
#define PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
 
#define PIT_TCTRL_TIE_MASK   (0x2U)
 
#define PIT_TCTRL_TIE_SHIFT   (1U)
 
#define PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
 
#define PIT_TCTRL_CHN_MASK   (0x4U)
 
#define PIT_TCTRL_CHN_SHIFT   (2U)
 
#define PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
 
#define PIT_TCTRL_TEN_MASK   (0x1U)
 
#define PIT_TCTRL_TEN_SHIFT   (0U)
 
#define PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
 
#define PIT_TCTRL_TIE_MASK   (0x2U)
 
#define PIT_TCTRL_TIE_SHIFT   (1U)
 
#define PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
 
#define PIT_TCTRL_CHN_MASK   (0x4U)
 
#define PIT_TCTRL_CHN_SHIFT   (2U)
 
#define PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
 

TCTRL - Timer Control Register

#define PIT_TCTRL_COUNT   (4U)
 

TFLG - Timer Flag Register

#define PIT_TFLG_TIF_MASK   (0x1U)
 
#define PIT_TFLG_TIF_SHIFT   (0U)
 
#define PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
 
#define PIT_TFLG_TIF_MASK   0x1u
 
#define PIT_TFLG_TIF_SHIFT   0
 
#define PIT_TFLG_TIF_MASK   (0x1U)
 
#define PIT_TFLG_TIF_SHIFT   (0U)
 
#define PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
 
#define PIT_TFLG_TIF_MASK   (0x1U)
 
#define PIT_TFLG_TIF_SHIFT   (0U)
 
#define PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
 
#define PIT_TFLG_TIF_MASK   (0x1U)
 
#define PIT_TFLG_TIF_SHIFT   (0U)
 
#define PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
 
#define PIT_TFLG_TIF_MASK   (0x1U)
 
#define PIT_TFLG_TIF_SHIFT   (0U)
 
#define PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
 

TFLG - Timer Flag Register

#define PIT_TFLG_COUNT   (4U)
 

LTMR64H - PIT Upper Lifetime Timer Register

#define PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
 
#define PIT_LTMR64H_LTH_SHIFT   (0U)
 
#define PIT_LTMR64H_LTH(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
 
#define PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
 
#define PIT_LTMR64H_LTH_SHIFT   (0U)
 
#define PIT_LTMR64H_LTH(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
 
#define PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
 
#define PIT_LTMR64H_LTH_SHIFT   (0U)
 
#define PIT_LTMR64H_LTH(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
 

LTMR64L - PIT Lower Lifetime Timer Register

#define PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
 
#define PIT_LTMR64L_LTL_SHIFT   (0U)
 
#define PIT_LTMR64L_LTL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
 
#define PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
 
#define PIT_LTMR64L_LTL_SHIFT   (0U)
 
#define PIT_LTMR64L_LTL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
 
#define PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
 
#define PIT_LTMR64L_LTL_SHIFT   (0U)
 
#define PIT_LTMR64L_LTL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
 

Macro Definition Documentation

◆ PIT

#define PIT   ((PIT_Type *)PIT_BASE)

Peripheral PIT base pointer

◆ PIT_BASE

#define PIT_BASE   (0x40037000u)

Peripheral PIT base address

◆ PIT_BASE_ADDRS

#define PIT_BASE_ADDRS   { PIT_BASE }

Array initializer of PIT peripheral base addresses

◆ PIT_BASE_PTRS

#define PIT_BASE_PTRS   { PIT }

Array initializer of PIT peripheral base pointers

◆ PIT_IRQS

#define PIT_IRQS   { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }

Interrupt vectors for the PIT peripheral type

◆ PIT_MCR_FRZ [1/5]

#define PIT_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

◆ PIT_MCR_FRZ [2/5]

#define PIT_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

◆ PIT_MCR_FRZ [3/5]

#define PIT_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

◆ PIT_MCR_FRZ [4/5]

#define PIT_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

◆ PIT_MCR_FRZ [5/5]

#define PIT_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

◆ PIT_MCR_MDIS [1/5]

#define PIT_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable - (PIT section) 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

◆ PIT_MCR_MDIS [2/5]

#define PIT_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable - (PIT section) 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

◆ PIT_MCR_MDIS [3/5]

#define PIT_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable - (PIT section) 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

◆ PIT_MCR_MDIS [4/5]

#define PIT_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable - (PIT section) 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

◆ PIT_MCR_MDIS [5/5]

#define PIT_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable - (PIT section) 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

◆ PIT_TCTRL_CHN [1/5]

#define PIT_TCTRL_CHN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

◆ PIT_TCTRL_CHN [2/5]

#define PIT_TCTRL_CHN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

◆ PIT_TCTRL_CHN [3/5]

#define PIT_TCTRL_CHN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

◆ PIT_TCTRL_CHN [4/5]

#define PIT_TCTRL_CHN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

◆ PIT_TCTRL_CHN [5/5]

#define PIT_TCTRL_CHN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

◆ PIT_TCTRL_TEN [1/5]

#define PIT_TCTRL_TEN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

◆ PIT_TCTRL_TEN [2/5]

#define PIT_TCTRL_TEN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

◆ PIT_TCTRL_TEN [3/5]

#define PIT_TCTRL_TEN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

◆ PIT_TCTRL_TEN [4/5]

#define PIT_TCTRL_TEN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

◆ PIT_TCTRL_TEN [5/5]

#define PIT_TCTRL_TEN ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

◆ PIT_TCTRL_TIE [1/5]

#define PIT_TCTRL_TIE ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt will be requested whenever TIF is set.

◆ PIT_TCTRL_TIE [2/5]

#define PIT_TCTRL_TIE ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt will be requested whenever TIF is set.

◆ PIT_TCTRL_TIE [3/5]

#define PIT_TCTRL_TIE ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt will be requested whenever TIF is set.

◆ PIT_TCTRL_TIE [4/5]

#define PIT_TCTRL_TIE ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt will be requested whenever TIF is set.

◆ PIT_TCTRL_TIE [5/5]

#define PIT_TCTRL_TIE ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt will be requested whenever TIF is set.

◆ PIT_TFLG_TIF [1/5]

#define PIT_TFLG_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.

◆ PIT_TFLG_TIF [2/5]

#define PIT_TFLG_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.

◆ PIT_TFLG_TIF [3/5]

#define PIT_TFLG_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.

◆ PIT_TFLG_TIF [4/5]

#define PIT_TFLG_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.

◆ PIT_TFLG_TIF [5/5]

#define PIT_TFLG_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.