RNG Register Masks

Macros
#define	RNG_BASE   (0x400A0000u)
#define	RNG   ((RNG_Type *)RNG_BASE)
#define	RNG_BASE_ADDRS   { RNG_BASE }
#define	RNG_BASE_PTRS   { RNG }
#define	RNG_IRQS   { RNG_IRQn }
#define	RNG_VER_MINOR_MASK   0xFFu
#define	RNG_VER_MINOR_SHIFT   0
#define	RNG_VER_MINOR(x)   (((uint32_t)(((uint32_t)(x))<<RNG_VER_MINOR_SHIFT))&RNG_VER_MINOR_MASK)
#define	RNG_VER_MAJOR_MASK   0xFF00u
#define	RNG_VER_MAJOR_SHIFT   8
#define	RNG_VER_MAJOR(x)   (((uint32_t)(((uint32_t)(x))<<RNG_VER_MAJOR_SHIFT))&RNG_VER_MAJOR_MASK)
#define	RNG_VER_TYPE_MASK   0xF0000000u
#define	RNG_VER_TYPE_SHIFT   28
#define	RNG_VER_TYPE(x)   (((uint32_t)(((uint32_t)(x))<<RNG_VER_TYPE_SHIFT))&RNG_VER_TYPE_MASK)
#define	RNG_CMD_ST_MASK   0x1u
#define	RNG_CMD_ST_SHIFT   0
#define	RNG_CMD_GS_MASK   0x2u
#define	RNG_CMD_GS_SHIFT   1
#define	RNG_CMD_CI_MASK   0x10u
#define	RNG_CMD_CI_SHIFT   4
#define	RNG_CMD_CE_MASK   0x20u
#define	RNG_CMD_CE_SHIFT   5
#define	RNG_CMD_SR_MASK   0x40u
#define	RNG_CMD_SR_SHIFT   6
#define	RNG_CR_FUFMOD_MASK   0x3u
#define	RNG_CR_FUFMOD_SHIFT   0
#define	RNG_CR_FUFMOD(x)   (((uint32_t)(((uint32_t)(x))<<RNG_CR_FUFMOD_SHIFT))&RNG_CR_FUFMOD_MASK)
#define	RNG_CR_AR_MASK   0x10u
#define	RNG_CR_AR_SHIFT   4
#define	RNG_CR_MASKDONE_MASK   0x20u
#define	RNG_CR_MASKDONE_SHIFT   5
#define	RNG_CR_MASKERR_MASK   0x40u
#define	RNG_CR_MASKERR_SHIFT   6
#define	RNG_SR_BUSY_MASK   0x2u
#define	RNG_SR_BUSY_SHIFT   1
#define	RNG_SR_RS_MASK   0x8u
#define	RNG_SR_RS_SHIFT   3
#define	RNG_SR_STDN_MASK   0x10u
#define	RNG_SR_STDN_SHIFT   4
#define	RNG_SR_SDN_MASK   0x20u
#define	RNG_SR_SDN_SHIFT   5
#define	RNG_SR_NSDN_MASK   0x40u
#define	RNG_SR_NSDN_SHIFT   6
#define	RNG_SR_FIFO_LVL_MASK   0xF00u
#define	RNG_SR_FIFO_LVL_SHIFT   8
#define	RNG_SR_FIFO_LVL(x)   (((uint32_t)(((uint32_t)(x))<<RNG_SR_FIFO_LVL_SHIFT))&RNG_SR_FIFO_LVL_MASK)
#define	RNG_SR_FIFO_SIZE_MASK   0xF000u
#define	RNG_SR_FIFO_SIZE_SHIFT   12
#define	RNG_SR_FIFO_SIZE(x)   (((uint32_t)(((uint32_t)(x))<<RNG_SR_FIFO_SIZE_SHIFT))&RNG_SR_FIFO_SIZE_MASK)
#define	RNG_SR_ERR_MASK   0x10000u
#define	RNG_SR_ERR_SHIFT   16
#define	RNG_SR_ST_PF_MASK   0xE00000u
#define	RNG_SR_ST_PF_SHIFT   21
#define	RNG_SR_ST_PF(x)   (((uint32_t)(((uint32_t)(x))<<RNG_SR_ST_PF_SHIFT))&RNG_SR_ST_PF_MASK)
#define	RNG_SR_STATPF_MASK   0xFF000000u
#define	RNG_SR_STATPF_SHIFT   24
#define	RNG_SR_STATPF(x)   (((uint32_t)(((uint32_t)(x))<<RNG_SR_STATPF_SHIFT))&RNG_SR_STATPF_MASK)
#define	RNG_ESR_LFE_MASK   0x1u
#define	RNG_ESR_LFE_SHIFT   0
#define	RNG_ESR_OSCE_MASK   0x2u
#define	RNG_ESR_OSCE_SHIFT   1
#define	RNG_ESR_STE_MASK   0x4u
#define	RNG_ESR_STE_SHIFT   2
#define	RNG_ESR_SATE_MASK   0x8u
#define	RNG_ESR_SATE_SHIFT   3
#define	RNG_ESR_FUFE_MASK   0x10u
#define	RNG_ESR_FUFE_SHIFT   4
#define	RNG_OUT_RANDOUT_MASK   0xFFFFFFFFu
#define	RNG_OUT_RANDOUT_SHIFT   0
#define	RNG_OUT_RANDOUT(x)   (((uint32_t)(((uint32_t)(x))<<RNG_OUT_RANDOUT_SHIFT))&RNG_OUT_RANDOUT_MASK)

CR - RNGA Control Register
#define	RNG_CR_GO_MASK   (0x1U)
#define	RNG_CR_GO_SHIFT   (0U)
#define	RNG_CR_GO(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
#define	RNG_CR_HA_MASK   (0x2U)
#define	RNG_CR_HA_SHIFT   (1U)
#define	RNG_CR_HA(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
#define	RNG_CR_INTM_MASK   (0x4U)
#define	RNG_CR_INTM_SHIFT   (2U)
#define	RNG_CR_INTM(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
#define	RNG_CR_CLRI_MASK   (0x8U)
#define	RNG_CR_CLRI_SHIFT   (3U)
#define	RNG_CR_CLRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
#define	RNG_CR_SLP_MASK   (0x10U)
#define	RNG_CR_SLP_SHIFT   (4U)
#define	RNG_CR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
#define	RNG_CR_GO_MASK   (0x1U)
#define	RNG_CR_GO_SHIFT   (0U)
#define	RNG_CR_GO(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
#define	RNG_CR_HA_MASK   (0x2U)
#define	RNG_CR_HA_SHIFT   (1U)
#define	RNG_CR_HA(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
#define	RNG_CR_INTM_MASK   (0x4U)
#define	RNG_CR_INTM_SHIFT   (2U)
#define	RNG_CR_INTM(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
#define	RNG_CR_CLRI_MASK   (0x8U)
#define	RNG_CR_CLRI_SHIFT   (3U)
#define	RNG_CR_CLRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
#define	RNG_CR_SLP_MASK   (0x10U)
#define	RNG_CR_SLP_SHIFT   (4U)
#define	RNG_CR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
#define	RNG_CR_GO_MASK   (0x1U)
#define	RNG_CR_GO_SHIFT   (0U)
#define	RNG_CR_GO(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
#define	RNG_CR_HA_MASK   (0x2U)
#define	RNG_CR_HA_SHIFT   (1U)
#define	RNG_CR_HA(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
#define	RNG_CR_INTM_MASK   (0x4U)
#define	RNG_CR_INTM_SHIFT   (2U)
#define	RNG_CR_INTM(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
#define	RNG_CR_CLRI_MASK   (0x8U)
#define	RNG_CR_CLRI_SHIFT   (3U)
#define	RNG_CR_CLRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
#define	RNG_CR_SLP_MASK   (0x10U)
#define	RNG_CR_SLP_SHIFT   (4U)
#define	RNG_CR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
#define	RNG_CR_GO_MASK   (0x1U)
#define	RNG_CR_GO_SHIFT   (0U)
#define	RNG_CR_GO(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
#define	RNG_CR_HA_MASK   (0x2U)
#define	RNG_CR_HA_SHIFT   (1U)
#define	RNG_CR_HA(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
#define	RNG_CR_INTM_MASK   (0x4U)
#define	RNG_CR_INTM_SHIFT   (2U)
#define	RNG_CR_INTM(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
#define	RNG_CR_CLRI_MASK   (0x8U)
#define	RNG_CR_CLRI_SHIFT   (3U)
#define	RNG_CR_CLRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
#define	RNG_CR_SLP_MASK   (0x10U)
#define	RNG_CR_SLP_SHIFT   (4U)
#define	RNG_CR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)

SR - RNGA Status Register
#define	RNG_SR_SECV_MASK   (0x1U)
#define	RNG_SR_SECV_SHIFT   (0U)
#define	RNG_SR_SECV(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
#define	RNG_SR_LRS_MASK   (0x2U)
#define	RNG_SR_LRS_SHIFT   (1U)
#define	RNG_SR_LRS(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
#define	RNG_SR_ORU_MASK   (0x4U)
#define	RNG_SR_ORU_SHIFT   (2U)
#define	RNG_SR_ORU(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
#define	RNG_SR_ERRI_MASK   (0x8U)
#define	RNG_SR_ERRI_SHIFT   (3U)
#define	RNG_SR_ERRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
#define	RNG_SR_SLP_MASK   (0x10U)
#define	RNG_SR_SLP_SHIFT   (4U)
#define	RNG_SR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
#define	RNG_SR_OREG_LVL_MASK   (0xFF00U)
#define	RNG_SR_OREG_LVL_SHIFT   (8U)
#define	RNG_SR_OREG_LVL(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
#define	RNG_SR_OREG_SIZE_MASK   (0xFF0000U)
#define	RNG_SR_OREG_SIZE_SHIFT   (16U)
#define	RNG_SR_OREG_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
#define	RNG_SR_SLP_MASK   0x4u
#define	RNG_SR_SLP_SHIFT   2
#define	RNG_SR_SECV_MASK   (0x1U)
#define	RNG_SR_SECV_SHIFT   (0U)
#define	RNG_SR_SECV(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
#define	RNG_SR_LRS_MASK   (0x2U)
#define	RNG_SR_LRS_SHIFT   (1U)
#define	RNG_SR_LRS(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
#define	RNG_SR_ORU_MASK   (0x4U)
#define	RNG_SR_ORU_SHIFT   (2U)
#define	RNG_SR_ORU(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
#define	RNG_SR_ERRI_MASK   (0x8U)
#define	RNG_SR_ERRI_SHIFT   (3U)
#define	RNG_SR_ERRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
#define	RNG_SR_SLP_MASK   (0x10U)
#define	RNG_SR_SLP_SHIFT   (4U)
#define	RNG_SR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
#define	RNG_SR_OREG_LVL_MASK   (0xFF00U)
#define	RNG_SR_OREG_LVL_SHIFT   (8U)
#define	RNG_SR_OREG_LVL(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
#define	RNG_SR_OREG_SIZE_MASK   (0xFF0000U)
#define	RNG_SR_OREG_SIZE_SHIFT   (16U)
#define	RNG_SR_OREG_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
#define	RNG_SR_SECV_MASK   (0x1U)
#define	RNG_SR_SECV_SHIFT   (0U)
#define	RNG_SR_SECV(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
#define	RNG_SR_LRS_MASK   (0x2U)
#define	RNG_SR_LRS_SHIFT   (1U)
#define	RNG_SR_LRS(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
#define	RNG_SR_ORU_MASK   (0x4U)
#define	RNG_SR_ORU_SHIFT   (2U)
#define	RNG_SR_ORU(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
#define	RNG_SR_ERRI_MASK   (0x8U)
#define	RNG_SR_ERRI_SHIFT   (3U)
#define	RNG_SR_ERRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
#define	RNG_SR_SLP_MASK   (0x10U)
#define	RNG_SR_SLP_SHIFT   (4U)
#define	RNG_SR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
#define	RNG_SR_OREG_LVL_MASK   (0xFF00U)
#define	RNG_SR_OREG_LVL_SHIFT   (8U)
#define	RNG_SR_OREG_LVL(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
#define	RNG_SR_OREG_SIZE_MASK   (0xFF0000U)
#define	RNG_SR_OREG_SIZE_SHIFT   (16U)
#define	RNG_SR_OREG_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
#define	RNG_SR_SECV_MASK   (0x1U)
#define	RNG_SR_SECV_SHIFT   (0U)
#define	RNG_SR_SECV(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
#define	RNG_SR_LRS_MASK   (0x2U)
#define	RNG_SR_LRS_SHIFT   (1U)
#define	RNG_SR_LRS(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
#define	RNG_SR_ORU_MASK   (0x4U)
#define	RNG_SR_ORU_SHIFT   (2U)
#define	RNG_SR_ORU(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
#define	RNG_SR_ERRI_MASK   (0x8U)
#define	RNG_SR_ERRI_SHIFT   (3U)
#define	RNG_SR_ERRI(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
#define	RNG_SR_SLP_MASK   (0x10U)
#define	RNG_SR_SLP_SHIFT   (4U)
#define	RNG_SR_SLP(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
#define	RNG_SR_OREG_LVL_MASK   (0xFF00U)
#define	RNG_SR_OREG_LVL_SHIFT   (8U)
#define	RNG_SR_OREG_LVL(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
#define	RNG_SR_OREG_SIZE_MASK   (0xFF0000U)
#define	RNG_SR_OREG_SIZE_SHIFT   (16U)
#define	RNG_SR_OREG_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)

ER - RNGA Entropy Register
#define	RNG_ER_EXT_ENT_MASK   (0xFFFFFFFFU)
#define	RNG_ER_EXT_ENT_SHIFT   (0U)
#define	RNG_ER_EXT_ENT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
#define	RNG_ER_EXT_ENT_MASK   (0xFFFFFFFFU)
#define	RNG_ER_EXT_ENT_SHIFT   (0U)
#define	RNG_ER_EXT_ENT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
#define	RNG_ER_EXT_ENT_MASK   (0xFFFFFFFFU)
#define	RNG_ER_EXT_ENT_SHIFT   (0U)
#define	RNG_ER_EXT_ENT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
#define	RNG_ER_EXT_ENT_MASK   (0xFFFFFFFFU)
#define	RNG_ER_EXT_ENT_SHIFT   (0U)
#define	RNG_ER_EXT_ENT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)

OR - RNGA Output Register
#define	RNG_OR_RANDOUT_MASK   (0xFFFFFFFFU)
#define	RNG_OR_RANDOUT_SHIFT   (0U)
#define	RNG_OR_RANDOUT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
#define	RNG_OR_RANDOUT_MASK   (0xFFFFFFFFU)
#define	RNG_OR_RANDOUT_SHIFT   (0U)
#define	RNG_OR_RANDOUT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
#define	RNG_OR_RANDOUT_MASK   (0xFFFFFFFFU)
#define	RNG_OR_RANDOUT_SHIFT   (0U)
#define	RNG_OR_RANDOUT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
#define	RNG_OR_RANDOUT_MASK   (0xFFFFFFFFU)
#define	RNG_OR_RANDOUT_SHIFT   (0U)
#define	RNG_OR_RANDOUT(x)   (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)

Macro Definition Documentation

RNG

#define RNG   ((RNG_Type *)RNG_BASE)

Peripheral RNG base pointer

RNG_BASE

#define RNG_BASE   (0x400A0000u)

Peripheral RNG base address

RNG_BASE_ADDRS

#define RNG_BASE_ADDRS   { RNG_BASE }

Array initializer of RNG peripheral base addresses

RNG_BASE_PTRS

#define RNG_BASE_PTRS   { RNG }

Array initializer of RNG peripheral base pointers

RNG_CR_CLRI [1/4]

#define RNG_CR_CLRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)

CLRI - Clear Interrupt 0b0..Do not clear the interrupt. 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.

RNG_CR_CLRI [2/4]

#define RNG_CR_CLRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)

CLRI - Clear Interrupt 0b0..Do not clear the interrupt. 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.

RNG_CR_CLRI [3/4]

#define RNG_CR_CLRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)

CLRI - Clear Interrupt 0b0..Do not clear the interrupt. 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.

RNG_CR_CLRI [4/4]

#define RNG_CR_CLRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)

CLRI - Clear Interrupt 0b0..Do not clear the interrupt. 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.

RNG_CR_GO [1/4]

#define RNG_CR_GO

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)

GO - Go 0b0..Disabled 0b1..Enabled

RNG_CR_GO [2/4]

#define RNG_CR_GO

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)

GO - Go 0b0..Disabled 0b1..Enabled

RNG_CR_GO [3/4]

#define RNG_CR_GO

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)

GO - Go 0b0..Disabled 0b1..Enabled

RNG_CR_GO [4/4]

#define RNG_CR_GO

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)

GO - Go 0b0..Disabled 0b1..Enabled

RNG_CR_HA [1/4]

#define RNG_CR_HA

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)

HA - High Assurance 0b0..Disabled 0b1..Enabled

RNG_CR_HA [2/4]

#define RNG_CR_HA

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)

HA - High Assurance 0b0..Disabled 0b1..Enabled

RNG_CR_HA [3/4]

#define RNG_CR_HA

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)

HA - High Assurance 0b0..Disabled 0b1..Enabled

RNG_CR_HA [4/4]

#define RNG_CR_HA

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)

HA - High Assurance 0b0..Disabled 0b1..Enabled

RNG_CR_INTM [1/4]

#define RNG_CR_INTM

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)

INTM - Interrupt Mask 0b0..Not masked 0b1..Masked

RNG_CR_INTM [2/4]

#define RNG_CR_INTM

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)

INTM - Interrupt Mask 0b0..Not masked 0b1..Masked

RNG_CR_INTM [3/4]

#define RNG_CR_INTM

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)

INTM - Interrupt Mask 0b0..Not masked 0b1..Masked

RNG_CR_INTM [4/4]

#define RNG_CR_INTM

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)

INTM - Interrupt Mask 0b0..Not masked 0b1..Masked

RNG_CR_SLP [1/4]

#define RNG_CR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_CR_SLP [2/4]

#define RNG_CR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_CR_SLP [3/4]

#define RNG_CR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_CR_SLP [4/4]

#define RNG_CR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_IRQS

#define RNG_IRQS   { RNG_IRQn }

Interrupt vectors for the RNG peripheral type

RNG_OR_RANDOUT [1/4]

#define RNG_OR_RANDOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)

RANDOUT - Random Output 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).

RNG_OR_RANDOUT [2/4]

#define RNG_OR_RANDOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)

RANDOUT - Random Output 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).

RNG_OR_RANDOUT [3/4]

#define RNG_OR_RANDOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)

RANDOUT - Random Output 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).

RNG_OR_RANDOUT [4/4]

#define RNG_OR_RANDOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)

RANDOUT - Random Output 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).

RNG_SR_ERRI [1/4]

#define RNG_SR_ERRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)

ERRI - Error Interrupt 0b0..No underflow 0b1..Underflow

RNG_SR_ERRI [2/4]

#define RNG_SR_ERRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)

ERRI - Error Interrupt 0b0..No underflow 0b1..Underflow

RNG_SR_ERRI [3/4]

#define RNG_SR_ERRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)

ERRI - Error Interrupt 0b0..No underflow 0b1..Underflow

RNG_SR_ERRI [4/4]

#define RNG_SR_ERRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)

ERRI - Error Interrupt 0b0..No underflow 0b1..Underflow

RNG_SR_LRS [1/4]

#define RNG_SR_LRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)

LRS - Last Read Status 0b0..No underflow 0b1..Underflow

RNG_SR_LRS [2/4]

#define RNG_SR_LRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)

LRS - Last Read Status 0b0..No underflow 0b1..Underflow

RNG_SR_LRS [3/4]

#define RNG_SR_LRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)

LRS - Last Read Status 0b0..No underflow 0b1..Underflow

RNG_SR_LRS [4/4]

#define RNG_SR_LRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)

LRS - Last Read Status 0b0..No underflow 0b1..Underflow

RNG_SR_OREG_LVL [1/4]

#define RNG_SR_OREG_LVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)

OREG_LVL - Output Register Level 0b00000000..No words (empty) 0b00000001..One word (valid)

RNG_SR_OREG_LVL [2/4]

#define RNG_SR_OREG_LVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)

OREG_LVL - Output Register Level 0b00000000..No words (empty) 0b00000001..One word (valid)

RNG_SR_OREG_LVL [3/4]

#define RNG_SR_OREG_LVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)

OREG_LVL - Output Register Level 0b00000000..No words (empty) 0b00000001..One word (valid)

RNG_SR_OREG_LVL [4/4]

#define RNG_SR_OREG_LVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)

OREG_LVL - Output Register Level 0b00000000..No words (empty) 0b00000001..One word (valid)

RNG_SR_OREG_SIZE [1/4]

#define RNG_SR_OREG_SIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)

OREG_SIZE - Output Register Size 0b00000001..One word (this value is fixed)

RNG_SR_OREG_SIZE [2/4]

#define RNG_SR_OREG_SIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)

OREG_SIZE - Output Register Size 0b00000001..One word (this value is fixed)

RNG_SR_OREG_SIZE [3/4]

#define RNG_SR_OREG_SIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)

OREG_SIZE - Output Register Size 0b00000001..One word (this value is fixed)

RNG_SR_OREG_SIZE [4/4]

#define RNG_SR_OREG_SIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)

OREG_SIZE - Output Register Size 0b00000001..One word (this value is fixed)

RNG_SR_ORU [1/4]

#define RNG_SR_ORU

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)

ORU - Output Register Underflow 0b0..No underflow 0b1..Underflow

RNG_SR_ORU [2/4]

#define RNG_SR_ORU

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)

ORU - Output Register Underflow 0b0..No underflow 0b1..Underflow

RNG_SR_ORU [3/4]

#define RNG_SR_ORU

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)

ORU - Output Register Underflow 0b0..No underflow 0b1..Underflow

RNG_SR_ORU [4/4]

#define RNG_SR_ORU

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)

ORU - Output Register Underflow 0b0..No underflow 0b1..Underflow

RNG_SR_SECV [1/4]

#define RNG_SR_SECV

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)

SECV - Security Violation 0b0..No security violation 0b1..Security violation

RNG_SR_SECV [2/4]

#define RNG_SR_SECV

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)

SECV - Security Violation 0b0..No security violation 0b1..Security violation

RNG_SR_SECV [3/4]

#define RNG_SR_SECV

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)

SECV - Security Violation 0b0..No security violation 0b1..Security violation

RNG_SR_SECV [4/4]

#define RNG_SR_SECV

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)

SECV - Security Violation 0b0..No security violation 0b1..Security violation

RNG_SR_SLP [1/4]

#define RNG_SR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_SR_SLP [2/4]

#define RNG_SR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_SR_SLP [3/4]

#define RNG_SR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode

RNG_SR_SLP [4/4]

#define RNG_SR_SLP

(

x

)

(((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)

SLP - Sleep 0b0..Normal mode 0b1..Sleep (low-power) mode