mikroSDK Reference Manual
Macros
RTC Register Masks
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Macros

#define RTC_BASE   (0x4003D000u)
 
#define RTC   ((RTC_Type *)RTC_BASE)
 
#define RTC_BASE_ADDRS   { RTC_BASE }
 
#define RTC_BASE_PTRS   { RTC }
 
#define RTC_IRQS   { RTC_IRQn }
 
#define RTC_SECONDS_IRQS   { RTC_Seconds_IRQn }
 
#define RTC_CCR_CONFIG_MASK   0xFFu
 
#define RTC_CCR_CONFIG_SHIFT   0
 
#define RTC_CCR_CONFIG(x)   (((uint32_t)(((uint32_t)(x))<<RTC_CCR_CONFIG_SHIFT))&RTC_CCR_CONFIG_MASK)
 
#define RTC_WAR_CCRW_MASK   0x80u
 
#define RTC_WAR_CCRW_SHIFT   7
 
#define RTC_RAR_CCRR_MASK   0x80u
 
#define RTC_RAR_CCRR_SHIFT   7
 

TSR - RTC Time Seconds Register

#define RTC_TSR_TSR_MASK   (0xFFFFFFFFU)
 
#define RTC_TSR_TSR_SHIFT   (0U)
 
#define RTC_TSR_TSR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
 
#define RTC_TSR_TSR_MASK   0xFFFFFFFFu
 
#define RTC_TSR_TSR_SHIFT   0
 
#define RTC_TSR_TSR(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
 
#define RTC_TSR_TSR_MASK   (0xFFFFFFFFU)
 
#define RTC_TSR_TSR_SHIFT   (0U)
 
#define RTC_TSR_TSR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
 
#define RTC_TSR_TSR_MASK   (0xFFFFFFFFU)
 
#define RTC_TSR_TSR_SHIFT   (0U)
 
#define RTC_TSR_TSR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
 
#define RTC_TSR_TSR_MASK   (0xFFFFFFFFU)
 
#define RTC_TSR_TSR_SHIFT   (0U)
 
#define RTC_TSR_TSR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
 

TPR - RTC Time Prescaler Register

#define RTC_TPR_TPR_MASK   (0xFFFFU)
 
#define RTC_TPR_TPR_SHIFT   (0U)
 
#define RTC_TPR_TPR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
 
#define RTC_TPR_TPR_MASK   0xFFFFu
 
#define RTC_TPR_TPR_SHIFT   0
 
#define RTC_TPR_TPR(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
 
#define RTC_TPR_TPR_MASK   (0xFFFFU)
 
#define RTC_TPR_TPR_SHIFT   (0U)
 
#define RTC_TPR_TPR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
 
#define RTC_TPR_TPR_MASK   (0xFFFFU)
 
#define RTC_TPR_TPR_SHIFT   (0U)
 
#define RTC_TPR_TPR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
 
#define RTC_TPR_TPR_MASK   (0xFFFFU)
 
#define RTC_TPR_TPR_SHIFT   (0U)
 
#define RTC_TPR_TPR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
 

TAR - RTC Time Alarm Register

#define RTC_TAR_TAR_MASK   (0xFFFFFFFFU)
 
#define RTC_TAR_TAR_SHIFT   (0U)
 
#define RTC_TAR_TAR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
 
#define RTC_TAR_TAR_MASK   0xFFFFFFFFu
 
#define RTC_TAR_TAR_SHIFT   0
 
#define RTC_TAR_TAR(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
 
#define RTC_TAR_TAR_MASK   (0xFFFFFFFFU)
 
#define RTC_TAR_TAR_SHIFT   (0U)
 
#define RTC_TAR_TAR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
 
#define RTC_TAR_TAR_MASK   (0xFFFFFFFFU)
 
#define RTC_TAR_TAR_SHIFT   (0U)
 
#define RTC_TAR_TAR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
 
#define RTC_TAR_TAR_MASK   (0xFFFFFFFFU)
 
#define RTC_TAR_TAR_SHIFT   (0U)
 
#define RTC_TAR_TAR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
 

TCR - RTC Time Compensation Register

#define RTC_TCR_TCR_MASK   (0xFFU)
 
#define RTC_TCR_TCR_SHIFT   (0U)
 
#define RTC_TCR_TCR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
 
#define RTC_TCR_CIR_MASK   (0xFF00U)
 
#define RTC_TCR_CIR_SHIFT   (8U)
 
#define RTC_TCR_CIR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
 
#define RTC_TCR_TCV_MASK   (0xFF0000U)
 
#define RTC_TCR_TCV_SHIFT   (16U)
 
#define RTC_TCR_TCV(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
 
#define RTC_TCR_CIC_MASK   (0xFF000000U)
 
#define RTC_TCR_CIC_SHIFT   (24U)
 
#define RTC_TCR_CIC(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
 
#define RTC_TCR_TCR_MASK   0xFFu
 
#define RTC_TCR_TCR_SHIFT   0
 
#define RTC_TCR_TCR(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
 
#define RTC_TCR_CIR_MASK   0xFF00u
 
#define RTC_TCR_CIR_SHIFT   8
 
#define RTC_TCR_CIR(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
 
#define RTC_TCR_TCV_MASK   0xFF0000u
 
#define RTC_TCR_TCV_SHIFT   16
 
#define RTC_TCR_TCV(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
 
#define RTC_TCR_CIC_MASK   0xFF000000u
 
#define RTC_TCR_CIC_SHIFT   24
 
#define RTC_TCR_CIC(x)   (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
 
#define RTC_TCR_TCR_MASK   (0xFFU)
 
#define RTC_TCR_TCR_SHIFT   (0U)
 
#define RTC_TCR_TCR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
 
#define RTC_TCR_CIR_MASK   (0xFF00U)
 
#define RTC_TCR_CIR_SHIFT   (8U)
 
#define RTC_TCR_CIR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
 
#define RTC_TCR_TCV_MASK   (0xFF0000U)
 
#define RTC_TCR_TCV_SHIFT   (16U)
 
#define RTC_TCR_TCV(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
 
#define RTC_TCR_CIC_MASK   (0xFF000000U)
 
#define RTC_TCR_CIC_SHIFT   (24U)
 
#define RTC_TCR_CIC(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
 
#define RTC_TCR_TCR_MASK   (0xFFU)
 
#define RTC_TCR_TCR_SHIFT   (0U)
 
#define RTC_TCR_TCR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
 
#define RTC_TCR_CIR_MASK   (0xFF00U)
 
#define RTC_TCR_CIR_SHIFT   (8U)
 
#define RTC_TCR_CIR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
 
#define RTC_TCR_TCV_MASK   (0xFF0000U)
 
#define RTC_TCR_TCV_SHIFT   (16U)
 
#define RTC_TCR_TCV(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
 
#define RTC_TCR_CIC_MASK   (0xFF000000U)
 
#define RTC_TCR_CIC_SHIFT   (24U)
 
#define RTC_TCR_CIC(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
 
#define RTC_TCR_TCR_MASK   (0xFFU)
 
#define RTC_TCR_TCR_SHIFT   (0U)
 
#define RTC_TCR_TCR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
 
#define RTC_TCR_CIR_MASK   (0xFF00U)
 
#define RTC_TCR_CIR_SHIFT   (8U)
 
#define RTC_TCR_CIR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
 
#define RTC_TCR_TCV_MASK   (0xFF0000U)
 
#define RTC_TCR_TCV_SHIFT   (16U)
 
#define RTC_TCR_TCV(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
 
#define RTC_TCR_CIC_MASK   (0xFF000000U)
 
#define RTC_TCR_CIC_SHIFT   (24U)
 
#define RTC_TCR_CIC(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
 

CR - RTC Control Register

#define RTC_CR_SWR_MASK   (0x1U)
 
#define RTC_CR_SWR_SHIFT   (0U)
 
#define RTC_CR_SWR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
 
#define RTC_CR_WPE_MASK   (0x2U)
 
#define RTC_CR_WPE_SHIFT   (1U)
 
#define RTC_CR_WPE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
 
#define RTC_CR_SUP_MASK   (0x4U)
 
#define RTC_CR_SUP_SHIFT   (2U)
 
#define RTC_CR_SUP(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
 
#define RTC_CR_UM_MASK   (0x8U)
 
#define RTC_CR_UM_SHIFT   (3U)
 
#define RTC_CR_UM(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
 
#define RTC_CR_OSCE_MASK   (0x100U)
 
#define RTC_CR_OSCE_SHIFT   (8U)
 
#define RTC_CR_OSCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
 
#define RTC_CR_CLKO_MASK   (0x200U)
 
#define RTC_CR_CLKO_SHIFT   (9U)
 
#define RTC_CR_CLKO(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
 
#define RTC_CR_SC16P_MASK   (0x400U)
 
#define RTC_CR_SC16P_SHIFT   (10U)
 
#define RTC_CR_SC16P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
 
#define RTC_CR_SC8P_MASK   (0x800U)
 
#define RTC_CR_SC8P_SHIFT   (11U)
 
#define RTC_CR_SC8P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
 
#define RTC_CR_SC4P_MASK   (0x1000U)
 
#define RTC_CR_SC4P_SHIFT   (12U)
 
#define RTC_CR_SC4P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
 
#define RTC_CR_SC2P_MASK   (0x2000U)
 
#define RTC_CR_SC2P_SHIFT   (13U)
 
#define RTC_CR_SC2P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
 
#define RTC_CR_SWR_MASK   0x1u
 
#define RTC_CR_SWR_SHIFT   0
 
#define RTC_CR_WPE_MASK   0x2u
 
#define RTC_CR_WPE_SHIFT   1
 
#define RTC_CR_SUP_MASK   0x4u
 
#define RTC_CR_SUP_SHIFT   2
 
#define RTC_CR_UM_MASK   0x8u
 
#define RTC_CR_UM_SHIFT   3
 
#define RTC_CR_OSCE_MASK   0x100u
 
#define RTC_CR_OSCE_SHIFT   8
 
#define RTC_CR_CLKO_MASK   0x200u
 
#define RTC_CR_CLKO_SHIFT   9
 
#define RTC_CR_SC16P_MASK   0x400u
 
#define RTC_CR_SC16P_SHIFT   10
 
#define RTC_CR_SC8P_MASK   0x800u
 
#define RTC_CR_SC8P_SHIFT   11
 
#define RTC_CR_SC4P_MASK   0x1000u
 
#define RTC_CR_SC4P_SHIFT   12
 
#define RTC_CR_SC2P_MASK   0x2000u
 
#define RTC_CR_SC2P_SHIFT   13
 
#define RTC_CR_SWR_MASK   (0x1U)
 
#define RTC_CR_SWR_SHIFT   (0U)
 
#define RTC_CR_SWR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
 
#define RTC_CR_WPE_MASK   (0x2U)
 
#define RTC_CR_WPE_SHIFT   (1U)
 
#define RTC_CR_WPE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
 
#define RTC_CR_SUP_MASK   (0x4U)
 
#define RTC_CR_SUP_SHIFT   (2U)
 
#define RTC_CR_SUP(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
 
#define RTC_CR_UM_MASK   (0x8U)
 
#define RTC_CR_UM_SHIFT   (3U)
 
#define RTC_CR_UM(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
 
#define RTC_CR_WPS_MASK   (0x10U)
 
#define RTC_CR_WPS_SHIFT   (4U)
 
#define RTC_CR_WPS(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
 
#define RTC_CR_OSCE_MASK   (0x100U)
 
#define RTC_CR_OSCE_SHIFT   (8U)
 
#define RTC_CR_OSCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
 
#define RTC_CR_CLKO_MASK   (0x200U)
 
#define RTC_CR_CLKO_SHIFT   (9U)
 
#define RTC_CR_CLKO(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
 
#define RTC_CR_SC16P_MASK   (0x400U)
 
#define RTC_CR_SC16P_SHIFT   (10U)
 
#define RTC_CR_SC16P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
 
#define RTC_CR_SC8P_MASK   (0x800U)
 
#define RTC_CR_SC8P_SHIFT   (11U)
 
#define RTC_CR_SC8P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
 
#define RTC_CR_SC4P_MASK   (0x1000U)
 
#define RTC_CR_SC4P_SHIFT   (12U)
 
#define RTC_CR_SC4P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
 
#define RTC_CR_SC2P_MASK   (0x2000U)
 
#define RTC_CR_SC2P_SHIFT   (13U)
 
#define RTC_CR_SC2P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
 
#define RTC_CR_SWR_MASK   (0x1U)
 
#define RTC_CR_SWR_SHIFT   (0U)
 
#define RTC_CR_SWR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
 
#define RTC_CR_WPE_MASK   (0x2U)
 
#define RTC_CR_WPE_SHIFT   (1U)
 
#define RTC_CR_WPE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
 
#define RTC_CR_SUP_MASK   (0x4U)
 
#define RTC_CR_SUP_SHIFT   (2U)
 
#define RTC_CR_SUP(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
 
#define RTC_CR_UM_MASK   (0x8U)
 
#define RTC_CR_UM_SHIFT   (3U)
 
#define RTC_CR_UM(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
 
#define RTC_CR_WPS_MASK   (0x10U)
 
#define RTC_CR_WPS_SHIFT   (4U)
 
#define RTC_CR_WPS(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
 
#define RTC_CR_OSCE_MASK   (0x100U)
 
#define RTC_CR_OSCE_SHIFT   (8U)
 
#define RTC_CR_OSCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
 
#define RTC_CR_CLKO_MASK   (0x200U)
 
#define RTC_CR_CLKO_SHIFT   (9U)
 
#define RTC_CR_CLKO(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
 
#define RTC_CR_SC16P_MASK   (0x400U)
 
#define RTC_CR_SC16P_SHIFT   (10U)
 
#define RTC_CR_SC16P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
 
#define RTC_CR_SC8P_MASK   (0x800U)
 
#define RTC_CR_SC8P_SHIFT   (11U)
 
#define RTC_CR_SC8P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
 
#define RTC_CR_SC4P_MASK   (0x1000U)
 
#define RTC_CR_SC4P_SHIFT   (12U)
 
#define RTC_CR_SC4P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
 
#define RTC_CR_SC2P_MASK   (0x2000U)
 
#define RTC_CR_SC2P_SHIFT   (13U)
 
#define RTC_CR_SC2P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
 
#define RTC_CR_SWR_MASK   (0x1U)
 
#define RTC_CR_SWR_SHIFT   (0U)
 
#define RTC_CR_SWR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
 
#define RTC_CR_WPE_MASK   (0x2U)
 
#define RTC_CR_WPE_SHIFT   (1U)
 
#define RTC_CR_WPE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
 
#define RTC_CR_SUP_MASK   (0x4U)
 
#define RTC_CR_SUP_SHIFT   (2U)
 
#define RTC_CR_SUP(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
 
#define RTC_CR_UM_MASK   (0x8U)
 
#define RTC_CR_UM_SHIFT   (3U)
 
#define RTC_CR_UM(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
 
#define RTC_CR_WPS_MASK   (0x10U)
 
#define RTC_CR_WPS_SHIFT   (4U)
 
#define RTC_CR_WPS(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
 
#define RTC_CR_OSCE_MASK   (0x100U)
 
#define RTC_CR_OSCE_SHIFT   (8U)
 
#define RTC_CR_OSCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
 
#define RTC_CR_CLKO_MASK   (0x200U)
 
#define RTC_CR_CLKO_SHIFT   (9U)
 
#define RTC_CR_CLKO(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
 
#define RTC_CR_SC16P_MASK   (0x400U)
 
#define RTC_CR_SC16P_SHIFT   (10U)
 
#define RTC_CR_SC16P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
 
#define RTC_CR_SC8P_MASK   (0x800U)
 
#define RTC_CR_SC8P_SHIFT   (11U)
 
#define RTC_CR_SC8P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
 
#define RTC_CR_SC4P_MASK   (0x1000U)
 
#define RTC_CR_SC4P_SHIFT   (12U)
 
#define RTC_CR_SC4P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
 
#define RTC_CR_SC2P_MASK   (0x2000U)
 
#define RTC_CR_SC2P_SHIFT   (13U)
 
#define RTC_CR_SC2P(x)   (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
 

SR - RTC Status Register

#define RTC_SR_TIF_MASK   (0x1U)
 
#define RTC_SR_TIF_SHIFT   (0U)
 
#define RTC_SR_TIF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
 
#define RTC_SR_TOF_MASK   (0x2U)
 
#define RTC_SR_TOF_SHIFT   (1U)
 
#define RTC_SR_TOF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
 
#define RTC_SR_TAF_MASK   (0x4U)
 
#define RTC_SR_TAF_SHIFT   (2U)
 
#define RTC_SR_TAF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
 
#define RTC_SR_TCE_MASK   (0x10U)
 
#define RTC_SR_TCE_SHIFT   (4U)
 
#define RTC_SR_TCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
 
#define RTC_SR_TIF_MASK   0x1u
 
#define RTC_SR_TIF_SHIFT   0
 
#define RTC_SR_TOF_MASK   0x2u
 
#define RTC_SR_TOF_SHIFT   1
 
#define RTC_SR_TAF_MASK   0x4u
 
#define RTC_SR_TAF_SHIFT   2
 
#define RTC_SR_TCE_MASK   0x10u
 
#define RTC_SR_TCE_SHIFT   4
 
#define RTC_SR_TIF_MASK   (0x1U)
 
#define RTC_SR_TIF_SHIFT   (0U)
 
#define RTC_SR_TIF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
 
#define RTC_SR_TOF_MASK   (0x2U)
 
#define RTC_SR_TOF_SHIFT   (1U)
 
#define RTC_SR_TOF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
 
#define RTC_SR_TAF_MASK   (0x4U)
 
#define RTC_SR_TAF_SHIFT   (2U)
 
#define RTC_SR_TAF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
 
#define RTC_SR_TCE_MASK   (0x10U)
 
#define RTC_SR_TCE_SHIFT   (4U)
 
#define RTC_SR_TCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
 
#define RTC_SR_TIF_MASK   (0x1U)
 
#define RTC_SR_TIF_SHIFT   (0U)
 
#define RTC_SR_TIF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
 
#define RTC_SR_TOF_MASK   (0x2U)
 
#define RTC_SR_TOF_SHIFT   (1U)
 
#define RTC_SR_TOF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
 
#define RTC_SR_TAF_MASK   (0x4U)
 
#define RTC_SR_TAF_SHIFT   (2U)
 
#define RTC_SR_TAF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
 
#define RTC_SR_MOF_MASK   (0x8U)
 
#define RTC_SR_MOF_SHIFT   (3U)
 
#define RTC_SR_MOF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
 
#define RTC_SR_TCE_MASK   (0x10U)
 
#define RTC_SR_TCE_SHIFT   (4U)
 
#define RTC_SR_TCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
 
#define RTC_SR_TIF_MASK   (0x1U)
 
#define RTC_SR_TIF_SHIFT   (0U)
 
#define RTC_SR_TIF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
 
#define RTC_SR_TOF_MASK   (0x2U)
 
#define RTC_SR_TOF_SHIFT   (1U)
 
#define RTC_SR_TOF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
 
#define RTC_SR_TAF_MASK   (0x4U)
 
#define RTC_SR_TAF_SHIFT   (2U)
 
#define RTC_SR_TAF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
 
#define RTC_SR_MOF_MASK   (0x8U)
 
#define RTC_SR_MOF_SHIFT   (3U)
 
#define RTC_SR_MOF(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
 
#define RTC_SR_TCE_MASK   (0x10U)
 
#define RTC_SR_TCE_SHIFT   (4U)
 
#define RTC_SR_TCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
 

LR - RTC Lock Register

#define RTC_LR_TCL_MASK   (0x8U)
 
#define RTC_LR_TCL_SHIFT   (3U)
 
#define RTC_LR_TCL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
 
#define RTC_LR_CRL_MASK   (0x10U)
 
#define RTC_LR_CRL_SHIFT   (4U)
 
#define RTC_LR_CRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
 
#define RTC_LR_SRL_MASK   (0x20U)
 
#define RTC_LR_SRL_SHIFT   (5U)
 
#define RTC_LR_SRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
 
#define RTC_LR_LRL_MASK   (0x40U)
 
#define RTC_LR_LRL_SHIFT   (6U)
 
#define RTC_LR_LRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
 
#define RTC_LR_TCL_MASK   0x8u
 
#define RTC_LR_TCL_SHIFT   3
 
#define RTC_LR_CRL_MASK   0x10u
 
#define RTC_LR_CRL_SHIFT   4
 
#define RTC_LR_SRL_MASK   0x20u
 
#define RTC_LR_SRL_SHIFT   5
 
#define RTC_LR_TCL_MASK   (0x8U)
 
#define RTC_LR_TCL_SHIFT   (3U)
 
#define RTC_LR_TCL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
 
#define RTC_LR_CRL_MASK   (0x10U)
 
#define RTC_LR_CRL_SHIFT   (4U)
 
#define RTC_LR_CRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
 
#define RTC_LR_SRL_MASK   (0x20U)
 
#define RTC_LR_SRL_SHIFT   (5U)
 
#define RTC_LR_SRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
 
#define RTC_LR_LRL_MASK   (0x40U)
 
#define RTC_LR_LRL_SHIFT   (6U)
 
#define RTC_LR_LRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
 
#define RTC_LR_TCL_MASK   (0x8U)
 
#define RTC_LR_TCL_SHIFT   (3U)
 
#define RTC_LR_TCL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
 
#define RTC_LR_CRL_MASK   (0x10U)
 
#define RTC_LR_CRL_SHIFT   (4U)
 
#define RTC_LR_CRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
 
#define RTC_LR_SRL_MASK   (0x20U)
 
#define RTC_LR_SRL_SHIFT   (5U)
 
#define RTC_LR_SRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
 
#define RTC_LR_LRL_MASK   (0x40U)
 
#define RTC_LR_LRL_SHIFT   (6U)
 
#define RTC_LR_LRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
 
#define RTC_LR_TTSL_MASK   (0x100U)
 
#define RTC_LR_TTSL_SHIFT   (8U)
 
#define RTC_LR_TTSL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
 
#define RTC_LR_MEL_MASK   (0x200U)
 
#define RTC_LR_MEL_SHIFT   (9U)
 
#define RTC_LR_MEL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
 
#define RTC_LR_MCLL_MASK   (0x400U)
 
#define RTC_LR_MCLL_SHIFT   (10U)
 
#define RTC_LR_MCLL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
 
#define RTC_LR_MCHL_MASK   (0x800U)
 
#define RTC_LR_MCHL_SHIFT   (11U)
 
#define RTC_LR_MCHL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
 
#define RTC_LR_TCL_MASK   (0x8U)
 
#define RTC_LR_TCL_SHIFT   (3U)
 
#define RTC_LR_TCL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
 
#define RTC_LR_CRL_MASK   (0x10U)
 
#define RTC_LR_CRL_SHIFT   (4U)
 
#define RTC_LR_CRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
 
#define RTC_LR_SRL_MASK   (0x20U)
 
#define RTC_LR_SRL_SHIFT   (5U)
 
#define RTC_LR_SRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
 
#define RTC_LR_LRL_MASK   (0x40U)
 
#define RTC_LR_LRL_SHIFT   (6U)
 
#define RTC_LR_LRL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
 
#define RTC_LR_TTSL_MASK   (0x100U)
 
#define RTC_LR_TTSL_SHIFT   (8U)
 
#define RTC_LR_TTSL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
 
#define RTC_LR_MEL_MASK   (0x200U)
 
#define RTC_LR_MEL_SHIFT   (9U)
 
#define RTC_LR_MEL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
 
#define RTC_LR_MCLL_MASK   (0x400U)
 
#define RTC_LR_MCLL_SHIFT   (10U)
 
#define RTC_LR_MCLL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
 
#define RTC_LR_MCHL_MASK   (0x800U)
 
#define RTC_LR_MCHL_SHIFT   (11U)
 
#define RTC_LR_MCHL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
 

IER - RTC Interrupt Enable Register

#define RTC_IER_TIIE_MASK   (0x1U)
 
#define RTC_IER_TIIE_SHIFT   (0U)
 
#define RTC_IER_TIIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
 
#define RTC_IER_TOIE_MASK   (0x2U)
 
#define RTC_IER_TOIE_SHIFT   (1U)
 
#define RTC_IER_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
 
#define RTC_IER_TAIE_MASK   (0x4U)
 
#define RTC_IER_TAIE_SHIFT   (2U)
 
#define RTC_IER_TAIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
 
#define RTC_IER_TSIE_MASK   (0x10U)
 
#define RTC_IER_TSIE_SHIFT   (4U)
 
#define RTC_IER_TSIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
 
#define RTC_IER_WPON_MASK   (0x80U)
 
#define RTC_IER_WPON_SHIFT   (7U)
 
#define RTC_IER_WPON(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
 
#define RTC_IER_TIIE_MASK   (0x1U)
 
#define RTC_IER_TIIE_SHIFT   (0U)
 
#define RTC_IER_TIIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
 
#define RTC_IER_TOIE_MASK   (0x2U)
 
#define RTC_IER_TOIE_SHIFT   (1U)
 
#define RTC_IER_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
 
#define RTC_IER_TAIE_MASK   (0x4U)
 
#define RTC_IER_TAIE_SHIFT   (2U)
 
#define RTC_IER_TAIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
 
#define RTC_IER_TSIE_MASK   (0x10U)
 
#define RTC_IER_TSIE_SHIFT   (4U)
 
#define RTC_IER_TSIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
 
#define RTC_IER_WPON_MASK   (0x80U)
 
#define RTC_IER_WPON_SHIFT   (7U)
 
#define RTC_IER_WPON(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
 
#define RTC_IER_TIIE_MASK   (0x1U)
 
#define RTC_IER_TIIE_SHIFT   (0U)
 
#define RTC_IER_TIIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
 
#define RTC_IER_TOIE_MASK   (0x2U)
 
#define RTC_IER_TOIE_SHIFT   (1U)
 
#define RTC_IER_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
 
#define RTC_IER_TAIE_MASK   (0x4U)
 
#define RTC_IER_TAIE_SHIFT   (2U)
 
#define RTC_IER_TAIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
 
#define RTC_IER_MOIE_MASK   (0x8U)
 
#define RTC_IER_MOIE_SHIFT   (3U)
 
#define RTC_IER_MOIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
 
#define RTC_IER_TSIE_MASK   (0x10U)
 
#define RTC_IER_TSIE_SHIFT   (4U)
 
#define RTC_IER_TSIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
 
#define RTC_IER_WPON_MASK   (0x80U)
 
#define RTC_IER_WPON_SHIFT   (7U)
 
#define RTC_IER_WPON(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
 
#define RTC_IER_TIIE_MASK   (0x1U)
 
#define RTC_IER_TIIE_SHIFT   (0U)
 
#define RTC_IER_TIIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
 
#define RTC_IER_TOIE_MASK   (0x2U)
 
#define RTC_IER_TOIE_SHIFT   (1U)
 
#define RTC_IER_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
 
#define RTC_IER_TAIE_MASK   (0x4U)
 
#define RTC_IER_TAIE_SHIFT   (2U)
 
#define RTC_IER_TAIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
 
#define RTC_IER_MOIE_MASK   (0x8U)
 
#define RTC_IER_MOIE_SHIFT   (3U)
 
#define RTC_IER_MOIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
 
#define RTC_IER_TSIE_MASK   (0x10U)
 
#define RTC_IER_TSIE_SHIFT   (4U)
 
#define RTC_IER_TSIE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
 
#define RTC_IER_WPON_MASK   (0x80U)
 
#define RTC_IER_WPON_SHIFT   (7U)
 
#define RTC_IER_WPON(x)   (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
 

WAR - RTC Write Access Register

#define RTC_WAR_TSRW_MASK   (0x1U)
 
#define RTC_WAR_TSRW_SHIFT   (0U)
 
#define RTC_WAR_TSRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
 
#define RTC_WAR_TPRW_MASK   (0x2U)
 
#define RTC_WAR_TPRW_SHIFT   (1U)
 
#define RTC_WAR_TPRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
 
#define RTC_WAR_TARW_MASK   (0x4U)
 
#define RTC_WAR_TARW_SHIFT   (2U)
 
#define RTC_WAR_TARW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
 
#define RTC_WAR_TCRW_MASK   (0x8U)
 
#define RTC_WAR_TCRW_SHIFT   (3U)
 
#define RTC_WAR_TCRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
 
#define RTC_WAR_CRW_MASK   (0x10U)
 
#define RTC_WAR_CRW_SHIFT   (4U)
 
#define RTC_WAR_CRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
 
#define RTC_WAR_SRW_MASK   (0x20U)
 
#define RTC_WAR_SRW_SHIFT   (5U)
 
#define RTC_WAR_SRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
 
#define RTC_WAR_LRW_MASK   (0x40U)
 
#define RTC_WAR_LRW_SHIFT   (6U)
 
#define RTC_WAR_LRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
 
#define RTC_WAR_IERW_MASK   (0x80U)
 
#define RTC_WAR_IERW_SHIFT   (7U)
 
#define RTC_WAR_IERW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
 
#define RTC_WAR_TSRW_MASK   0x1u
 
#define RTC_WAR_TSRW_SHIFT   0
 
#define RTC_WAR_TPRW_MASK   0x2u
 
#define RTC_WAR_TPRW_SHIFT   1
 
#define RTC_WAR_TARW_MASK   0x4u
 
#define RTC_WAR_TARW_SHIFT   2
 
#define RTC_WAR_TCRW_MASK   0x8u
 
#define RTC_WAR_TCRW_SHIFT   3
 
#define RTC_WAR_CRW_MASK   0x10u
 
#define RTC_WAR_CRW_SHIFT   4
 
#define RTC_WAR_SRW_MASK   0x20u
 
#define RTC_WAR_SRW_SHIFT   5
 
#define RTC_WAR_LRW_MASK   0x40u
 
#define RTC_WAR_LRW_SHIFT   6
 
#define RTC_WAR_TSRW_MASK   (0x1U)
 
#define RTC_WAR_TSRW_SHIFT   (0U)
 
#define RTC_WAR_TSRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
 
#define RTC_WAR_TPRW_MASK   (0x2U)
 
#define RTC_WAR_TPRW_SHIFT   (1U)
 
#define RTC_WAR_TPRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
 
#define RTC_WAR_TARW_MASK   (0x4U)
 
#define RTC_WAR_TARW_SHIFT   (2U)
 
#define RTC_WAR_TARW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
 
#define RTC_WAR_TCRW_MASK   (0x8U)
 
#define RTC_WAR_TCRW_SHIFT   (3U)
 
#define RTC_WAR_TCRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
 
#define RTC_WAR_CRW_MASK   (0x10U)
 
#define RTC_WAR_CRW_SHIFT   (4U)
 
#define RTC_WAR_CRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
 
#define RTC_WAR_SRW_MASK   (0x20U)
 
#define RTC_WAR_SRW_SHIFT   (5U)
 
#define RTC_WAR_SRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
 
#define RTC_WAR_LRW_MASK   (0x40U)
 
#define RTC_WAR_LRW_SHIFT   (6U)
 
#define RTC_WAR_LRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
 
#define RTC_WAR_IERW_MASK   (0x80U)
 
#define RTC_WAR_IERW_SHIFT   (7U)
 
#define RTC_WAR_IERW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
 
#define RTC_WAR_TSRW_MASK   (0x1U)
 
#define RTC_WAR_TSRW_SHIFT   (0U)
 
#define RTC_WAR_TSRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
 
#define RTC_WAR_TPRW_MASK   (0x2U)
 
#define RTC_WAR_TPRW_SHIFT   (1U)
 
#define RTC_WAR_TPRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
 
#define RTC_WAR_TARW_MASK   (0x4U)
 
#define RTC_WAR_TARW_SHIFT   (2U)
 
#define RTC_WAR_TARW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
 
#define RTC_WAR_TCRW_MASK   (0x8U)
 
#define RTC_WAR_TCRW_SHIFT   (3U)
 
#define RTC_WAR_TCRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
 
#define RTC_WAR_CRW_MASK   (0x10U)
 
#define RTC_WAR_CRW_SHIFT   (4U)
 
#define RTC_WAR_CRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
 
#define RTC_WAR_SRW_MASK   (0x20U)
 
#define RTC_WAR_SRW_SHIFT   (5U)
 
#define RTC_WAR_SRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
 
#define RTC_WAR_LRW_MASK   (0x40U)
 
#define RTC_WAR_LRW_SHIFT   (6U)
 
#define RTC_WAR_LRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
 
#define RTC_WAR_IERW_MASK   (0x80U)
 
#define RTC_WAR_IERW_SHIFT   (7U)
 
#define RTC_WAR_IERW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
 
#define RTC_WAR_TTSW_MASK   (0x100U)
 
#define RTC_WAR_TTSW_SHIFT   (8U)
 
#define RTC_WAR_TTSW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
 
#define RTC_WAR_MERW_MASK   (0x200U)
 
#define RTC_WAR_MERW_SHIFT   (9U)
 
#define RTC_WAR_MERW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
 
#define RTC_WAR_MCLW_MASK   (0x400U)
 
#define RTC_WAR_MCLW_SHIFT   (10U)
 
#define RTC_WAR_MCLW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
 
#define RTC_WAR_MCHW_MASK   (0x800U)
 
#define RTC_WAR_MCHW_SHIFT   (11U)
 
#define RTC_WAR_MCHW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
 
#define RTC_WAR_TSRW_MASK   (0x1U)
 
#define RTC_WAR_TSRW_SHIFT   (0U)
 
#define RTC_WAR_TSRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
 
#define RTC_WAR_TPRW_MASK   (0x2U)
 
#define RTC_WAR_TPRW_SHIFT   (1U)
 
#define RTC_WAR_TPRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
 
#define RTC_WAR_TARW_MASK   (0x4U)
 
#define RTC_WAR_TARW_SHIFT   (2U)
 
#define RTC_WAR_TARW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
 
#define RTC_WAR_TCRW_MASK   (0x8U)
 
#define RTC_WAR_TCRW_SHIFT   (3U)
 
#define RTC_WAR_TCRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
 
#define RTC_WAR_CRW_MASK   (0x10U)
 
#define RTC_WAR_CRW_SHIFT   (4U)
 
#define RTC_WAR_CRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
 
#define RTC_WAR_SRW_MASK   (0x20U)
 
#define RTC_WAR_SRW_SHIFT   (5U)
 
#define RTC_WAR_SRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
 
#define RTC_WAR_LRW_MASK   (0x40U)
 
#define RTC_WAR_LRW_SHIFT   (6U)
 
#define RTC_WAR_LRW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
 
#define RTC_WAR_IERW_MASK   (0x80U)
 
#define RTC_WAR_IERW_SHIFT   (7U)
 
#define RTC_WAR_IERW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
 
#define RTC_WAR_TTSW_MASK   (0x100U)
 
#define RTC_WAR_TTSW_SHIFT   (8U)
 
#define RTC_WAR_TTSW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
 
#define RTC_WAR_MERW_MASK   (0x200U)
 
#define RTC_WAR_MERW_SHIFT   (9U)
 
#define RTC_WAR_MERW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
 
#define RTC_WAR_MCLW_MASK   (0x400U)
 
#define RTC_WAR_MCLW_SHIFT   (10U)
 
#define RTC_WAR_MCLW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
 
#define RTC_WAR_MCHW_MASK   (0x800U)
 
#define RTC_WAR_MCHW_SHIFT   (11U)
 
#define RTC_WAR_MCHW(x)   (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
 

RAR - RTC Read Access Register

#define RTC_RAR_TSRR_MASK   (0x1U)
 
#define RTC_RAR_TSRR_SHIFT   (0U)
 
#define RTC_RAR_TSRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
 
#define RTC_RAR_TPRR_MASK   (0x2U)
 
#define RTC_RAR_TPRR_SHIFT   (1U)
 
#define RTC_RAR_TPRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
 
#define RTC_RAR_TARR_MASK   (0x4U)
 
#define RTC_RAR_TARR_SHIFT   (2U)
 
#define RTC_RAR_TARR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
 
#define RTC_RAR_TCRR_MASK   (0x8U)
 
#define RTC_RAR_TCRR_SHIFT   (3U)
 
#define RTC_RAR_TCRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
 
#define RTC_RAR_CRR_MASK   (0x10U)
 
#define RTC_RAR_CRR_SHIFT   (4U)
 
#define RTC_RAR_CRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
 
#define RTC_RAR_SRR_MASK   (0x20U)
 
#define RTC_RAR_SRR_SHIFT   (5U)
 
#define RTC_RAR_SRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
 
#define RTC_RAR_LRR_MASK   (0x40U)
 
#define RTC_RAR_LRR_SHIFT   (6U)
 
#define RTC_RAR_LRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
 
#define RTC_RAR_IERR_MASK   (0x80U)
 
#define RTC_RAR_IERR_SHIFT   (7U)
 
#define RTC_RAR_IERR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
 
#define RTC_RAR_TSRR_MASK   0x1u
 
#define RTC_RAR_TSRR_SHIFT   0
 
#define RTC_RAR_TPRR_MASK   0x2u
 
#define RTC_RAR_TPRR_SHIFT   1
 
#define RTC_RAR_TARR_MASK   0x4u
 
#define RTC_RAR_TARR_SHIFT   2
 
#define RTC_RAR_TCRR_MASK   0x8u
 
#define RTC_RAR_TCRR_SHIFT   3
 
#define RTC_RAR_CRR_MASK   0x10u
 
#define RTC_RAR_CRR_SHIFT   4
 
#define RTC_RAR_SRR_MASK   0x20u
 
#define RTC_RAR_SRR_SHIFT   5
 
#define RTC_RAR_LRR_MASK   0x40u
 
#define RTC_RAR_LRR_SHIFT   6
 
#define RTC_RAR_TSRR_MASK   (0x1U)
 
#define RTC_RAR_TSRR_SHIFT   (0U)
 
#define RTC_RAR_TSRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
 
#define RTC_RAR_TPRR_MASK   (0x2U)
 
#define RTC_RAR_TPRR_SHIFT   (1U)
 
#define RTC_RAR_TPRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
 
#define RTC_RAR_TARR_MASK   (0x4U)
 
#define RTC_RAR_TARR_SHIFT   (2U)
 
#define RTC_RAR_TARR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
 
#define RTC_RAR_TCRR_MASK   (0x8U)
 
#define RTC_RAR_TCRR_SHIFT   (3U)
 
#define RTC_RAR_TCRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
 
#define RTC_RAR_CRR_MASK   (0x10U)
 
#define RTC_RAR_CRR_SHIFT   (4U)
 
#define RTC_RAR_CRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
 
#define RTC_RAR_SRR_MASK   (0x20U)
 
#define RTC_RAR_SRR_SHIFT   (5U)
 
#define RTC_RAR_SRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
 
#define RTC_RAR_LRR_MASK   (0x40U)
 
#define RTC_RAR_LRR_SHIFT   (6U)
 
#define RTC_RAR_LRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
 
#define RTC_RAR_IERR_MASK   (0x80U)
 
#define RTC_RAR_IERR_SHIFT   (7U)
 
#define RTC_RAR_IERR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
 
#define RTC_RAR_TSRR_MASK   (0x1U)
 
#define RTC_RAR_TSRR_SHIFT   (0U)
 
#define RTC_RAR_TSRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
 
#define RTC_RAR_TPRR_MASK   (0x2U)
 
#define RTC_RAR_TPRR_SHIFT   (1U)
 
#define RTC_RAR_TPRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
 
#define RTC_RAR_TARR_MASK   (0x4U)
 
#define RTC_RAR_TARR_SHIFT   (2U)
 
#define RTC_RAR_TARR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
 
#define RTC_RAR_TCRR_MASK   (0x8U)
 
#define RTC_RAR_TCRR_SHIFT   (3U)
 
#define RTC_RAR_TCRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
 
#define RTC_RAR_CRR_MASK   (0x10U)
 
#define RTC_RAR_CRR_SHIFT   (4U)
 
#define RTC_RAR_CRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
 
#define RTC_RAR_SRR_MASK   (0x20U)
 
#define RTC_RAR_SRR_SHIFT   (5U)
 
#define RTC_RAR_SRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
 
#define RTC_RAR_LRR_MASK   (0x40U)
 
#define RTC_RAR_LRR_SHIFT   (6U)
 
#define RTC_RAR_LRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
 
#define RTC_RAR_IERR_MASK   (0x80U)
 
#define RTC_RAR_IERR_SHIFT   (7U)
 
#define RTC_RAR_IERR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
 
#define RTC_RAR_TTSR_MASK   (0x100U)
 
#define RTC_RAR_TTSR_SHIFT   (8U)
 
#define RTC_RAR_TTSR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
 
#define RTC_RAR_MERR_MASK   (0x200U)
 
#define RTC_RAR_MERR_SHIFT   (9U)
 
#define RTC_RAR_MERR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
 
#define RTC_RAR_MCLR_MASK   (0x400U)
 
#define RTC_RAR_MCLR_SHIFT   (10U)
 
#define RTC_RAR_MCLR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
 
#define RTC_RAR_MCHR_MASK   (0x800U)
 
#define RTC_RAR_MCHR_SHIFT   (11U)
 
#define RTC_RAR_MCHR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
 
#define RTC_RAR_TSRR_MASK   (0x1U)
 
#define RTC_RAR_TSRR_SHIFT   (0U)
 
#define RTC_RAR_TSRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
 
#define RTC_RAR_TPRR_MASK   (0x2U)
 
#define RTC_RAR_TPRR_SHIFT   (1U)
 
#define RTC_RAR_TPRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
 
#define RTC_RAR_TARR_MASK   (0x4U)
 
#define RTC_RAR_TARR_SHIFT   (2U)
 
#define RTC_RAR_TARR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
 
#define RTC_RAR_TCRR_MASK   (0x8U)
 
#define RTC_RAR_TCRR_SHIFT   (3U)
 
#define RTC_RAR_TCRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
 
#define RTC_RAR_CRR_MASK   (0x10U)
 
#define RTC_RAR_CRR_SHIFT   (4U)
 
#define RTC_RAR_CRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
 
#define RTC_RAR_SRR_MASK   (0x20U)
 
#define RTC_RAR_SRR_SHIFT   (5U)
 
#define RTC_RAR_SRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
 
#define RTC_RAR_LRR_MASK   (0x40U)
 
#define RTC_RAR_LRR_SHIFT   (6U)
 
#define RTC_RAR_LRR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
 
#define RTC_RAR_IERR_MASK   (0x80U)
 
#define RTC_RAR_IERR_SHIFT   (7U)
 
#define RTC_RAR_IERR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
 
#define RTC_RAR_TTSR_MASK   (0x100U)
 
#define RTC_RAR_TTSR_SHIFT   (8U)
 
#define RTC_RAR_TTSR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
 
#define RTC_RAR_MERR_MASK   (0x200U)
 
#define RTC_RAR_MERR_SHIFT   (9U)
 
#define RTC_RAR_MERR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
 
#define RTC_RAR_MCLR_MASK   (0x400U)
 
#define RTC_RAR_MCLR_SHIFT   (10U)
 
#define RTC_RAR_MCLR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
 
#define RTC_RAR_MCHR_MASK   (0x800U)
 
#define RTC_RAR_MCHR_SHIFT   (11U)
 
#define RTC_RAR_MCHR(x)   (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
 

TTSR - RTC Tamper Time Seconds Register

#define RTC_TTSR_TTS_MASK   (0xFFFFFFFFU)
 
#define RTC_TTSR_TTS_SHIFT   (0U)
 
#define RTC_TTSR_TTS(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
 
#define RTC_TTSR_TTS_MASK   (0xFFFFFFFFU)
 
#define RTC_TTSR_TTS_SHIFT   (0U)
 
#define RTC_TTSR_TTS(x)   (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
 

MER - RTC Monotonic Enable Register

#define RTC_MER_MCE_MASK   (0x10U)
 
#define RTC_MER_MCE_SHIFT   (4U)
 
#define RTC_MER_MCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
 
#define RTC_MER_MCE_MASK   (0x10U)
 
#define RTC_MER_MCE_SHIFT   (4U)
 
#define RTC_MER_MCE(x)   (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
 

MCLR - RTC Monotonic Counter Low Register

#define RTC_MCLR_MCL_MASK   (0xFFFFFFFFU)
 
#define RTC_MCLR_MCL_SHIFT   (0U)
 
#define RTC_MCLR_MCL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
 
#define RTC_MCLR_MCL_MASK   (0xFFFFFFFFU)
 
#define RTC_MCLR_MCL_SHIFT   (0U)
 
#define RTC_MCLR_MCL(x)   (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
 

MCHR - RTC Monotonic Counter High Register

#define RTC_MCHR_MCH_MASK   (0xFFFFFFFFU)
 
#define RTC_MCHR_MCH_SHIFT   (0U)
 
#define RTC_MCHR_MCH(x)   (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
 
#define RTC_MCHR_MCH_MASK   (0xFFFFFFFFU)
 
#define RTC_MCHR_MCH_SHIFT   (0U)
 
#define RTC_MCHR_MCH(x)   (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
 

Macro Definition Documentation

◆ RTC

#define RTC   ((RTC_Type *)RTC_BASE)

Peripheral RTC base pointer

◆ RTC_BASE

#define RTC_BASE   (0x4003D000u)

Peripheral RTC base address

◆ RTC_BASE_ADDRS

#define RTC_BASE_ADDRS   { RTC_BASE }

Array initializer of RTC peripheral base addresses

◆ RTC_BASE_PTRS

#define RTC_BASE_PTRS   { RTC }

Array initializer of RTC peripheral base pointers

◆ RTC_CR_CLKO [1/4]

#define RTC_CR_CLKO ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)

CLKO - Clock Output 0b0..The 32 kHz clock is output to other peripherals. 0b1..The 32 kHz clock is not output to other peripherals.

◆ RTC_CR_CLKO [2/4]

#define RTC_CR_CLKO ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)

CLKO - Clock Output 0b0..The 32 kHz clock is output to other peripherals. 0b1..The 32 kHz clock is not output to other peripherals.

◆ RTC_CR_CLKO [3/4]

#define RTC_CR_CLKO ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)

CLKO - Clock Output 0b0..The 32 kHz clock is output to other peripherals. 0b1..The 32 kHz clock is not output to other peripherals.

◆ RTC_CR_CLKO [4/4]

#define RTC_CR_CLKO ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)

CLKO - Clock Output 0b0..The 32 kHz clock is output to other peripherals. 0b1..The 32 kHz clock is not output to other peripherals.

◆ RTC_CR_OSCE [1/4]

#define RTC_CR_OSCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)

OSCE - Oscillator Enable 0b0..32.768 kHz oscillator is disabled. 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.

◆ RTC_CR_OSCE [2/4]

#define RTC_CR_OSCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)

OSCE - Oscillator Enable 0b0..32.768 kHz oscillator is disabled. 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.

◆ RTC_CR_OSCE [3/4]

#define RTC_CR_OSCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)

OSCE - Oscillator Enable 0b0..32.768 kHz oscillator is disabled. 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.

◆ RTC_CR_OSCE [4/4]

#define RTC_CR_OSCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)

OSCE - Oscillator Enable 0b0..32.768 kHz oscillator is disabled. 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.

◆ RTC_CR_SC16P [1/4]

#define RTC_CR_SC16P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)

SC16P - Oscillator 16pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC16P [2/4]

#define RTC_CR_SC16P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)

SC16P - Oscillator 16pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC16P [3/4]

#define RTC_CR_SC16P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)

SC16P - Oscillator 16pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC16P [4/4]

#define RTC_CR_SC16P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)

SC16P - Oscillator 16pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC2P [1/4]

#define RTC_CR_SC2P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)

SC2P - Oscillator 2pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC2P [2/4]

#define RTC_CR_SC2P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)

SC2P - Oscillator 2pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC2P [3/4]

#define RTC_CR_SC2P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)

SC2P - Oscillator 2pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC2P [4/4]

#define RTC_CR_SC2P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)

SC2P - Oscillator 2pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC4P [1/4]

#define RTC_CR_SC4P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)

SC4P - Oscillator 4pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC4P [2/4]

#define RTC_CR_SC4P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)

SC4P - Oscillator 4pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC4P [3/4]

#define RTC_CR_SC4P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)

SC4P - Oscillator 4pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC4P [4/4]

#define RTC_CR_SC4P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)

SC4P - Oscillator 4pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC8P [1/4]

#define RTC_CR_SC8P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)

SC8P - Oscillator 8pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC8P [2/4]

#define RTC_CR_SC8P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)

SC8P - Oscillator 8pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC8P [3/4]

#define RTC_CR_SC8P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)

SC8P - Oscillator 8pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SC8P [4/4]

#define RTC_CR_SC8P ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)

SC8P - Oscillator 8pF Load Configure 0b0..Disable the load. 0b1..Enable the additional load.

◆ RTC_CR_SUP [1/4]

#define RTC_CR_SUP ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)

SUP - Supervisor Access 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. 0b1..Non-supervisor mode write accesses are supported.

◆ RTC_CR_SUP [2/4]

#define RTC_CR_SUP ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)

SUP - Supervisor Access 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. 0b1..Non-supervisor mode write accesses are supported.

◆ RTC_CR_SUP [3/4]

#define RTC_CR_SUP ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)

SUP - Supervisor Access 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. 0b1..Non-supervisor mode write accesses are supported.

◆ RTC_CR_SUP [4/4]

#define RTC_CR_SUP ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)

SUP - Supervisor Access 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. 0b1..Non-supervisor mode write accesses are supported.

◆ RTC_CR_SWR [1/4]

#define RTC_CR_SWR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)

SWR - Software Reset 0b0..No effect. 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.

◆ RTC_CR_SWR [2/4]

#define RTC_CR_SWR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)

SWR - Software Reset 0b0..No effect. 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.

◆ RTC_CR_SWR [3/4]

#define RTC_CR_SWR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)

SWR - Software Reset 0b0..No effect. 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.

◆ RTC_CR_SWR [4/4]

#define RTC_CR_SWR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)

SWR - Software Reset 0b0..No effect. 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.

◆ RTC_CR_UM [1/4]

#define RTC_CR_UM ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)

UM - Update Mode 0b0..Registers cannot be written when locked. 0b1..Registers can be written when locked under limited conditions.

◆ RTC_CR_UM [2/4]

#define RTC_CR_UM ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)

UM - Update Mode 0b0..Registers cannot be written when locked. 0b1..Registers can be written when locked under limited conditions.

◆ RTC_CR_UM [3/4]

#define RTC_CR_UM ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)

UM - Update Mode 0b0..Registers cannot be written when locked. 0b1..Registers can be written when locked under limited conditions.

◆ RTC_CR_UM [4/4]

#define RTC_CR_UM ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)

UM - Update Mode 0b0..Registers cannot be written when locked. 0b1..Registers can be written when locked under limited conditions.

◆ RTC_CR_WPE [1/4]

#define RTC_CR_WPE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)

WPE - Wakeup Pin Enable 0b0..Wakeup pin is disabled. 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.

◆ RTC_CR_WPE [2/4]

#define RTC_CR_WPE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)

WPE - Wakeup Pin Enable 0b0..Wakeup pin is disabled. 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.

◆ RTC_CR_WPE [3/4]

#define RTC_CR_WPE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)

WPE - Wakeup Pin Enable 0b0..Wakeup pin is disabled. 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.

◆ RTC_CR_WPE [4/4]

#define RTC_CR_WPE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)

WPE - Wakeup Pin Enable 0b0..Wakeup pin is disabled. 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.

◆ RTC_CR_WPS [1/3]

#define RTC_CR_WPS ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)

WPS - Wakeup Pin Select 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.

◆ RTC_CR_WPS [2/3]

#define RTC_CR_WPS ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)

WPS - Wakeup Pin Select 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.

◆ RTC_CR_WPS [3/3]

#define RTC_CR_WPS ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)

WPS - Wakeup Pin Select 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.

◆ RTC_IER_MOIE [1/2]

#define RTC_IER_MOIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)

MOIE - Monotonic Overflow Interrupt Enable 0b0..Monotonic overflow flag does not generate an interrupt. 0b1..Monotonic overflow flag does generate an interrupt.

◆ RTC_IER_MOIE [2/2]

#define RTC_IER_MOIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)

MOIE - Monotonic Overflow Interrupt Enable 0b0..Monotonic overflow flag does not generate an interrupt. 0b1..Monotonic overflow flag does generate an interrupt.

◆ RTC_IER_TAIE [1/4]

#define RTC_IER_TAIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)

TAIE - Time Alarm Interrupt Enable 0b0..Time alarm flag does not generate an interrupt. 0b1..Time alarm flag does generate an interrupt.

◆ RTC_IER_TAIE [2/4]

#define RTC_IER_TAIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)

TAIE - Time Alarm Interrupt Enable 0b0..Time alarm flag does not generate an interrupt. 0b1..Time alarm flag does generate an interrupt.

◆ RTC_IER_TAIE [3/4]

#define RTC_IER_TAIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)

TAIE - Time Alarm Interrupt Enable 0b0..Time alarm flag does not generate an interrupt. 0b1..Time alarm flag does generate an interrupt.

◆ RTC_IER_TAIE [4/4]

#define RTC_IER_TAIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)

TAIE - Time Alarm Interrupt Enable 0b0..Time alarm flag does not generate an interrupt. 0b1..Time alarm flag does generate an interrupt.

◆ RTC_IER_TIIE [1/4]

#define RTC_IER_TIIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)

TIIE - Time Invalid Interrupt Enable 0b0..Time invalid flag does not generate an interrupt. 0b1..Time invalid flag does generate an interrupt.

◆ RTC_IER_TIIE [2/4]

#define RTC_IER_TIIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)

TIIE - Time Invalid Interrupt Enable 0b0..Time invalid flag does not generate an interrupt. 0b1..Time invalid flag does generate an interrupt.

◆ RTC_IER_TIIE [3/4]

#define RTC_IER_TIIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)

TIIE - Time Invalid Interrupt Enable 0b0..Time invalid flag does not generate an interrupt. 0b1..Time invalid flag does generate an interrupt.

◆ RTC_IER_TIIE [4/4]

#define RTC_IER_TIIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)

TIIE - Time Invalid Interrupt Enable 0b0..Time invalid flag does not generate an interrupt. 0b1..Time invalid flag does generate an interrupt.

◆ RTC_IER_TOIE [1/4]

#define RTC_IER_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)

TOIE - Time Overflow Interrupt Enable 0b0..Time overflow flag does not generate an interrupt. 0b1..Time overflow flag does generate an interrupt.

◆ RTC_IER_TOIE [2/4]

#define RTC_IER_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)

TOIE - Time Overflow Interrupt Enable 0b0..Time overflow flag does not generate an interrupt. 0b1..Time overflow flag does generate an interrupt.

◆ RTC_IER_TOIE [3/4]

#define RTC_IER_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)

TOIE - Time Overflow Interrupt Enable 0b0..Time overflow flag does not generate an interrupt. 0b1..Time overflow flag does generate an interrupt.

◆ RTC_IER_TOIE [4/4]

#define RTC_IER_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)

TOIE - Time Overflow Interrupt Enable 0b0..Time overflow flag does not generate an interrupt. 0b1..Time overflow flag does generate an interrupt.

◆ RTC_IER_TSIE [1/4]

#define RTC_IER_TSIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)

TSIE - Time Seconds Interrupt Enable 0b0..Seconds interrupt is disabled. 0b1..Seconds interrupt is enabled.

◆ RTC_IER_TSIE [2/4]

#define RTC_IER_TSIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)

TSIE - Time Seconds Interrupt Enable 0b0..Seconds interrupt is disabled. 0b1..Seconds interrupt is enabled.

◆ RTC_IER_TSIE [3/4]

#define RTC_IER_TSIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)

TSIE - Time Seconds Interrupt Enable 0b0..Seconds interrupt is disabled. 0b1..Seconds interrupt is enabled.

◆ RTC_IER_TSIE [4/4]

#define RTC_IER_TSIE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)

TSIE - Time Seconds Interrupt Enable 0b0..Seconds interrupt is disabled. 0b1..Seconds interrupt is enabled.

◆ RTC_IER_WPON [1/4]

#define RTC_IER_WPON ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)

WPON - Wakeup Pin On 0b0..No effect. 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.

◆ RTC_IER_WPON [2/4]

#define RTC_IER_WPON ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)

WPON - Wakeup Pin On 0b0..No effect. 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.

◆ RTC_IER_WPON [3/4]

#define RTC_IER_WPON ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)

WPON - Wakeup Pin On 0b0..No effect. 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.

◆ RTC_IER_WPON [4/4]

#define RTC_IER_WPON ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)

WPON - Wakeup Pin On 0b0..No effect. 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.

◆ RTC_IRQS

#define RTC_IRQS   { RTC_IRQn }

Interrupt vectors for the RTC peripheral type

◆ RTC_LR_CRL [1/4]

#define RTC_LR_CRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)

CRL - Control Register Lock 0b0..Control Register is locked and writes are ignored. 0b1..Control Register is not locked and writes complete as normal.

◆ RTC_LR_CRL [2/4]

#define RTC_LR_CRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)

CRL - Control Register Lock 0b0..Control Register is locked and writes are ignored. 0b1..Control Register is not locked and writes complete as normal.

◆ RTC_LR_CRL [3/4]

#define RTC_LR_CRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)

CRL - Control Register Lock 0b0..Control Register is locked and writes are ignored. 0b1..Control Register is not locked and writes complete as normal.

◆ RTC_LR_CRL [4/4]

#define RTC_LR_CRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)

CRL - Control Register Lock 0b0..Control Register is locked and writes are ignored. 0b1..Control Register is not locked and writes complete as normal.

◆ RTC_LR_LRL [1/4]

#define RTC_LR_LRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)

LRL - Lock Register Lock 0b0..Lock Register is locked and writes are ignored. 0b1..Lock Register is not locked and writes complete as normal.

◆ RTC_LR_LRL [2/4]

#define RTC_LR_LRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)

LRL - Lock Register Lock 0b0..Lock Register is locked and writes are ignored. 0b1..Lock Register is not locked and writes complete as normal.

◆ RTC_LR_LRL [3/4]

#define RTC_LR_LRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)

LRL - Lock Register Lock 0b0..Lock Register is locked and writes are ignored. 0b1..Lock Register is not locked and writes complete as normal.

◆ RTC_LR_LRL [4/4]

#define RTC_LR_LRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)

LRL - Lock Register Lock 0b0..Lock Register is locked and writes are ignored. 0b1..Lock Register is not locked and writes complete as normal.

◆ RTC_LR_MCHL [1/2]

#define RTC_LR_MCHL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)

MCHL - Monotonic Counter High Lock 0b0..Monotonic Counter High Register is locked and writes are ignored. 0b1..Monotonic Counter High Register is not locked and writes complete as normal.

◆ RTC_LR_MCHL [2/2]

#define RTC_LR_MCHL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)

MCHL - Monotonic Counter High Lock 0b0..Monotonic Counter High Register is locked and writes are ignored. 0b1..Monotonic Counter High Register is not locked and writes complete as normal.

◆ RTC_LR_MCLL [1/2]

#define RTC_LR_MCLL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)

MCLL - Monotonic Counter Low Lock 0b0..Monotonic Counter Low Register is locked and writes are ignored. 0b1..Monotonic Counter Low Register is not locked and writes complete as normal.

◆ RTC_LR_MCLL [2/2]

#define RTC_LR_MCLL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)

MCLL - Monotonic Counter Low Lock 0b0..Monotonic Counter Low Register is locked and writes are ignored. 0b1..Monotonic Counter Low Register is not locked and writes complete as normal.

◆ RTC_LR_MEL [1/2]

#define RTC_LR_MEL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)

MEL - Monotonic Enable Lock 0b0..Monotonic Enable Register is locked and writes are ignored. 0b1..Monotonic Enable Register is not locked and writes complete as normal.

◆ RTC_LR_MEL [2/2]

#define RTC_LR_MEL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)

MEL - Monotonic Enable Lock 0b0..Monotonic Enable Register is locked and writes are ignored. 0b1..Monotonic Enable Register is not locked and writes complete as normal.

◆ RTC_LR_SRL [1/4]

#define RTC_LR_SRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)

SRL - Status Register Lock 0b0..Status Register is locked and writes are ignored. 0b1..Status Register is not locked and writes complete as normal.

◆ RTC_LR_SRL [2/4]

#define RTC_LR_SRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)

SRL - Status Register Lock 0b0..Status Register is locked and writes are ignored. 0b1..Status Register is not locked and writes complete as normal.

◆ RTC_LR_SRL [3/4]

#define RTC_LR_SRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)

SRL - Status Register Lock 0b0..Status Register is locked and writes are ignored. 0b1..Status Register is not locked and writes complete as normal.

◆ RTC_LR_SRL [4/4]

#define RTC_LR_SRL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)

SRL - Status Register Lock 0b0..Status Register is locked and writes are ignored. 0b1..Status Register is not locked and writes complete as normal.

◆ RTC_LR_TCL [1/4]

#define RTC_LR_TCL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)

TCL - Time Compensation Lock 0b0..Time Compensation Register is locked and writes are ignored. 0b1..Time Compensation Register is not locked and writes complete as normal.

◆ RTC_LR_TCL [2/4]

#define RTC_LR_TCL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)

TCL - Time Compensation Lock 0b0..Time Compensation Register is locked and writes are ignored. 0b1..Time Compensation Register is not locked and writes complete as normal.

◆ RTC_LR_TCL [3/4]

#define RTC_LR_TCL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)

TCL - Time Compensation Lock 0b0..Time Compensation Register is locked and writes are ignored. 0b1..Time Compensation Register is not locked and writes complete as normal.

◆ RTC_LR_TCL [4/4]

#define RTC_LR_TCL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)

TCL - Time Compensation Lock 0b0..Time Compensation Register is locked and writes are ignored. 0b1..Time Compensation Register is not locked and writes complete as normal.

◆ RTC_LR_TTSL [1/2]

#define RTC_LR_TTSL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)

TTSL - Tamper Time Seconds Lock 0b0..Tamper Time Seconds Register is locked and writes are ignored. 0b1..Tamper Time Seconds Register is not locked and writes complete as normal.

◆ RTC_LR_TTSL [2/2]

#define RTC_LR_TTSL ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)

TTSL - Tamper Time Seconds Lock 0b0..Tamper Time Seconds Register is locked and writes are ignored. 0b1..Tamper Time Seconds Register is not locked and writes complete as normal.

◆ RTC_MER_MCE [1/2]

#define RTC_MER_MCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)

MCE - Monotonic Counter Enable 0b0..Writes to the monotonic counter load the counter with the value written. 0b1..Writes to the monotonic counter increment the counter.

◆ RTC_MER_MCE [2/2]

#define RTC_MER_MCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)

MCE - Monotonic Counter Enable 0b0..Writes to the monotonic counter load the counter with the value written. 0b1..Writes to the monotonic counter increment the counter.

◆ RTC_RAR_CRR [1/4]

#define RTC_RAR_CRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)

CRR - Control Register Read 0b0..Reads to the Control Register are ignored. 0b1..Reads to the Control Register complete as normal.

◆ RTC_RAR_CRR [2/4]

#define RTC_RAR_CRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)

CRR - Control Register Read 0b0..Reads to the Control Register are ignored. 0b1..Reads to the Control Register complete as normal.

◆ RTC_RAR_CRR [3/4]

#define RTC_RAR_CRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)

CRR - Control Register Read 0b0..Reads to the Control Register are ignored. 0b1..Reads to the Control Register complete as normal.

◆ RTC_RAR_CRR [4/4]

#define RTC_RAR_CRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)

CRR - Control Register Read 0b0..Reads to the Control Register are ignored. 0b1..Reads to the Control Register complete as normal.

◆ RTC_RAR_IERR [1/4]

#define RTC_RAR_IERR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)

IERR - Interrupt Enable Register Read 0b0..Reads to the Interrupt Enable Register are ignored. 0b1..Reads to the Interrupt Enable Register complete as normal.

◆ RTC_RAR_IERR [2/4]

#define RTC_RAR_IERR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)

IERR - Interrupt Enable Register Read 0b0..Reads to the Interrupt Enable Register are ignored. 0b1..Reads to the Interrupt Enable Register complete as normal.

◆ RTC_RAR_IERR [3/4]

#define RTC_RAR_IERR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)

IERR - Interrupt Enable Register Read 0b0..Reads to the Interrupt Enable Register are ignored. 0b1..Reads to the Interrupt Enable Register complete as normal.

◆ RTC_RAR_IERR [4/4]

#define RTC_RAR_IERR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)

IERR - Interrupt Enable Register Read 0b0..Reads to the Interrupt Enable Register are ignored. 0b1..Reads to the Interrupt Enable Register complete as normal.

◆ RTC_RAR_LRR [1/4]

#define RTC_RAR_LRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)

LRR - Lock Register Read 0b0..Reads to the Lock Register are ignored. 0b1..Reads to the Lock Register complete as normal.

◆ RTC_RAR_LRR [2/4]

#define RTC_RAR_LRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)

LRR - Lock Register Read 0b0..Reads to the Lock Register are ignored. 0b1..Reads to the Lock Register complete as normal.

◆ RTC_RAR_LRR [3/4]

#define RTC_RAR_LRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)

LRR - Lock Register Read 0b0..Reads to the Lock Register are ignored. 0b1..Reads to the Lock Register complete as normal.

◆ RTC_RAR_LRR [4/4]

#define RTC_RAR_LRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)

LRR - Lock Register Read 0b0..Reads to the Lock Register are ignored. 0b1..Reads to the Lock Register complete as normal.

◆ RTC_RAR_MCHR [1/2]

#define RTC_RAR_MCHR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)

MCHR - Monotonic Counter High Read 0b0..Reads to the Monotonic Counter High Register are ignored. 0b1..Reads to the Monotonic Counter High Register complete as normal.

◆ RTC_RAR_MCHR [2/2]

#define RTC_RAR_MCHR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)

MCHR - Monotonic Counter High Read 0b0..Reads to the Monotonic Counter High Register are ignored. 0b1..Reads to the Monotonic Counter High Register complete as normal.

◆ RTC_RAR_MCLR [1/2]

#define RTC_RAR_MCLR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)

MCLR - Monotonic Counter Low Read 0b0..Reads to the Monotonic Counter Low Register are ignored. 0b1..Reads to the Monotonic Counter Low Register complete as normal.

◆ RTC_RAR_MCLR [2/2]

#define RTC_RAR_MCLR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)

MCLR - Monotonic Counter Low Read 0b0..Reads to the Monotonic Counter Low Register are ignored. 0b1..Reads to the Monotonic Counter Low Register complete as normal.

◆ RTC_RAR_MERR [1/2]

#define RTC_RAR_MERR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)

MERR - Monotonic Enable Register Read 0b0..Reads to the Monotonic Enable Register are ignored. 0b1..Reads to the Monotonic Enable Register complete as normal.

◆ RTC_RAR_MERR [2/2]

#define RTC_RAR_MERR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)

MERR - Monotonic Enable Register Read 0b0..Reads to the Monotonic Enable Register are ignored. 0b1..Reads to the Monotonic Enable Register complete as normal.

◆ RTC_RAR_SRR [1/4]

#define RTC_RAR_SRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)

SRR - Status Register Read 0b0..Reads to the Status Register are ignored. 0b1..Reads to the Status Register complete as normal.

◆ RTC_RAR_SRR [2/4]

#define RTC_RAR_SRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)

SRR - Status Register Read 0b0..Reads to the Status Register are ignored. 0b1..Reads to the Status Register complete as normal.

◆ RTC_RAR_SRR [3/4]

#define RTC_RAR_SRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)

SRR - Status Register Read 0b0..Reads to the Status Register are ignored. 0b1..Reads to the Status Register complete as normal.

◆ RTC_RAR_SRR [4/4]

#define RTC_RAR_SRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)

SRR - Status Register Read 0b0..Reads to the Status Register are ignored. 0b1..Reads to the Status Register complete as normal.

◆ RTC_RAR_TARR [1/4]

#define RTC_RAR_TARR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)

TARR - Time Alarm Register Read 0b0..Reads to the Time Alarm Register are ignored. 0b1..Reads to the Time Alarm Register complete as normal.

◆ RTC_RAR_TARR [2/4]

#define RTC_RAR_TARR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)

TARR - Time Alarm Register Read 0b0..Reads to the Time Alarm Register are ignored. 0b1..Reads to the Time Alarm Register complete as normal.

◆ RTC_RAR_TARR [3/4]

#define RTC_RAR_TARR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)

TARR - Time Alarm Register Read 0b0..Reads to the Time Alarm Register are ignored. 0b1..Reads to the Time Alarm Register complete as normal.

◆ RTC_RAR_TARR [4/4]

#define RTC_RAR_TARR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)

TARR - Time Alarm Register Read 0b0..Reads to the Time Alarm Register are ignored. 0b1..Reads to the Time Alarm Register complete as normal.

◆ RTC_RAR_TCRR [1/4]

#define RTC_RAR_TCRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)

TCRR - Time Compensation Register Read 0b0..Reads to the Time Compensation Register are ignored. 0b1..Reads to the Time Compensation Register complete as normal.

◆ RTC_RAR_TCRR [2/4]

#define RTC_RAR_TCRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)

TCRR - Time Compensation Register Read 0b0..Reads to the Time Compensation Register are ignored. 0b1..Reads to the Time Compensation Register complete as normal.

◆ RTC_RAR_TCRR [3/4]

#define RTC_RAR_TCRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)

TCRR - Time Compensation Register Read 0b0..Reads to the Time Compensation Register are ignored. 0b1..Reads to the Time Compensation Register complete as normal.

◆ RTC_RAR_TCRR [4/4]

#define RTC_RAR_TCRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)

TCRR - Time Compensation Register Read 0b0..Reads to the Time Compensation Register are ignored. 0b1..Reads to the Time Compensation Register complete as normal.

◆ RTC_RAR_TPRR [1/4]

#define RTC_RAR_TPRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)

TPRR - Time Prescaler Register Read 0b0..Reads to the Time Pprescaler Register are ignored. 0b1..Reads to the Time Prescaler Register complete as normal.

◆ RTC_RAR_TPRR [2/4]

#define RTC_RAR_TPRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)

TPRR - Time Prescaler Register Read 0b0..Reads to the Time Pprescaler Register are ignored. 0b1..Reads to the Time Prescaler Register complete as normal.

◆ RTC_RAR_TPRR [3/4]

#define RTC_RAR_TPRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)

TPRR - Time Prescaler Register Read 0b0..Reads to the Time Pprescaler Register are ignored. 0b1..Reads to the Time Prescaler Register complete as normal.

◆ RTC_RAR_TPRR [4/4]

#define RTC_RAR_TPRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)

TPRR - Time Prescaler Register Read 0b0..Reads to the Time Pprescaler Register are ignored. 0b1..Reads to the Time Prescaler Register complete as normal.

◆ RTC_RAR_TSRR [1/4]

#define RTC_RAR_TSRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)

TSRR - Time Seconds Register Read 0b0..Reads to the Time Seconds Register are ignored. 0b1..Reads to the Time Seconds Register complete as normal.

◆ RTC_RAR_TSRR [2/4]

#define RTC_RAR_TSRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)

TSRR - Time Seconds Register Read 0b0..Reads to the Time Seconds Register are ignored. 0b1..Reads to the Time Seconds Register complete as normal.

◆ RTC_RAR_TSRR [3/4]

#define RTC_RAR_TSRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)

TSRR - Time Seconds Register Read 0b0..Reads to the Time Seconds Register are ignored. 0b1..Reads to the Time Seconds Register complete as normal.

◆ RTC_RAR_TSRR [4/4]

#define RTC_RAR_TSRR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)

TSRR - Time Seconds Register Read 0b0..Reads to the Time Seconds Register are ignored. 0b1..Reads to the Time Seconds Register complete as normal.

◆ RTC_RAR_TTSR [1/2]

#define RTC_RAR_TTSR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)

TTSR - Tamper Time Seconds Read 0b0..Reads to the Tamper Time Seconds Register are ignored. 0b1..Reads to the Tamper Time Seconds Register complete as normal.

◆ RTC_RAR_TTSR [2/2]

#define RTC_RAR_TTSR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)

TTSR - Tamper Time Seconds Read 0b0..Reads to the Tamper Time Seconds Register are ignored. 0b1..Reads to the Tamper Time Seconds Register complete as normal.

◆ RTC_SR_MOF [1/2]

#define RTC_SR_MOF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)

MOF - Monotonic Overflow Flag 0b0..Monotonic counter overflow has not occurred. 0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.

◆ RTC_SR_MOF [2/2]

#define RTC_SR_MOF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)

MOF - Monotonic Overflow Flag 0b0..Monotonic counter overflow has not occurred. 0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.

◆ RTC_SR_TAF [1/4]

#define RTC_SR_TAF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)

TAF - Time Alarm Flag 0b0..Time alarm has not occurred. 0b1..Time alarm has occurred.

◆ RTC_SR_TAF [2/4]

#define RTC_SR_TAF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)

TAF - Time Alarm Flag 0b0..Time alarm has not occurred. 0b1..Time alarm has occurred.

◆ RTC_SR_TAF [3/4]

#define RTC_SR_TAF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)

TAF - Time Alarm Flag 0b0..Time alarm has not occurred. 0b1..Time alarm has occurred.

◆ RTC_SR_TAF [4/4]

#define RTC_SR_TAF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)

TAF - Time Alarm Flag 0b0..Time alarm has not occurred. 0b1..Time alarm has occurred.

◆ RTC_SR_TCE [1/4]

#define RTC_SR_TCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)

TCE - Time Counter Enable 0b0..Time counter is disabled. 0b1..Time counter is enabled.

◆ RTC_SR_TCE [2/4]

#define RTC_SR_TCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)

TCE - Time Counter Enable 0b0..Time counter is disabled. 0b1..Time counter is enabled.

◆ RTC_SR_TCE [3/4]

#define RTC_SR_TCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)

TCE - Time Counter Enable 0b0..Time counter is disabled. 0b1..Time counter is enabled.

◆ RTC_SR_TCE [4/4]

#define RTC_SR_TCE ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)

TCE - Time Counter Enable 0b0..Time counter is disabled. 0b1..Time counter is enabled.

◆ RTC_SR_TIF [1/4]

#define RTC_SR_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)

TIF - Time Invalid Flag 0b0..Time is valid. 0b1..Time is invalid and time counter is read as zero.

◆ RTC_SR_TIF [2/4]

#define RTC_SR_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)

TIF - Time Invalid Flag 0b0..Time is valid. 0b1..Time is invalid and time counter is read as zero.

◆ RTC_SR_TIF [3/4]

#define RTC_SR_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)

TIF - Time Invalid Flag 0b0..Time is valid. 0b1..Time is invalid and time counter is read as zero.

◆ RTC_SR_TIF [4/4]

#define RTC_SR_TIF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)

TIF - Time Invalid Flag 0b0..Time is valid. 0b1..Time is invalid and time counter is read as zero.

◆ RTC_SR_TOF [1/4]

#define RTC_SR_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)

TOF - Time Overflow Flag 0b0..Time overflow has not occurred. 0b1..Time overflow has occurred and time counter is read as zero.

◆ RTC_SR_TOF [2/4]

#define RTC_SR_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)

TOF - Time Overflow Flag 0b0..Time overflow has not occurred. 0b1..Time overflow has occurred and time counter is read as zero.

◆ RTC_SR_TOF [3/4]

#define RTC_SR_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)

TOF - Time Overflow Flag 0b0..Time overflow has not occurred. 0b1..Time overflow has occurred and time counter is read as zero.

◆ RTC_SR_TOF [4/4]

#define RTC_SR_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)

TOF - Time Overflow Flag 0b0..Time overflow has not occurred. 0b1..Time overflow has occurred and time counter is read as zero.

◆ RTC_TCR_TCR [1/5]

#define RTC_TCR_TCR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)

TCR - Time Compensation Register 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.

◆ RTC_TCR_TCR [2/5]

#define RTC_TCR_TCR ( x)    (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)

TCR - Time Compensation Register 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.

◆ RTC_TCR_TCR [3/5]

#define RTC_TCR_TCR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)

TCR - Time Compensation Register 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.

◆ RTC_TCR_TCR [4/5]

#define RTC_TCR_TCR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)

TCR - Time Compensation Register 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.

◆ RTC_TCR_TCR [5/5]

#define RTC_TCR_TCR ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)

TCR - Time Compensation Register 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.

◆ RTC_WAR_CRW [1/4]

#define RTC_WAR_CRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)

CRW - Control Register Write 0b0..Writes to the Control Register are ignored. 0b1..Writes to the Control Register complete as normal.

◆ RTC_WAR_CRW [2/4]

#define RTC_WAR_CRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)

CRW - Control Register Write 0b0..Writes to the Control Register are ignored. 0b1..Writes to the Control Register complete as normal.

◆ RTC_WAR_CRW [3/4]

#define RTC_WAR_CRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)

CRW - Control Register Write 0b0..Writes to the Control Register are ignored. 0b1..Writes to the Control Register complete as normal.

◆ RTC_WAR_CRW [4/4]

#define RTC_WAR_CRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)

CRW - Control Register Write 0b0..Writes to the Control Register are ignored. 0b1..Writes to the Control Register complete as normal.

◆ RTC_WAR_IERW [1/4]

#define RTC_WAR_IERW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)

IERW - Interrupt Enable Register Write 0b0..Writes to the Interupt Enable Register are ignored. 0b1..Writes to the Interrupt Enable Register complete as normal.

◆ RTC_WAR_IERW [2/4]

#define RTC_WAR_IERW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)

IERW - Interrupt Enable Register Write 0b0..Writes to the Interupt Enable Register are ignored. 0b1..Writes to the Interrupt Enable Register complete as normal.

◆ RTC_WAR_IERW [3/4]

#define RTC_WAR_IERW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)

IERW - Interrupt Enable Register Write 0b0..Writes to the Interupt Enable Register are ignored. 0b1..Writes to the Interrupt Enable Register complete as normal.

◆ RTC_WAR_IERW [4/4]

#define RTC_WAR_IERW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)

IERW - Interrupt Enable Register Write 0b0..Writes to the Interupt Enable Register are ignored. 0b1..Writes to the Interrupt Enable Register complete as normal.

◆ RTC_WAR_LRW [1/4]

#define RTC_WAR_LRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)

LRW - Lock Register Write 0b0..Writes to the Lock Register are ignored. 0b1..Writes to the Lock Register complete as normal.

◆ RTC_WAR_LRW [2/4]

#define RTC_WAR_LRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)

LRW - Lock Register Write 0b0..Writes to the Lock Register are ignored. 0b1..Writes to the Lock Register complete as normal.

◆ RTC_WAR_LRW [3/4]

#define RTC_WAR_LRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)

LRW - Lock Register Write 0b0..Writes to the Lock Register are ignored. 0b1..Writes to the Lock Register complete as normal.

◆ RTC_WAR_LRW [4/4]

#define RTC_WAR_LRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)

LRW - Lock Register Write 0b0..Writes to the Lock Register are ignored. 0b1..Writes to the Lock Register complete as normal.

◆ RTC_WAR_MCHW [1/2]

#define RTC_WAR_MCHW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)

MCHW - Monotonic Counter High Write 0b0..Writes to the Monotonic Counter High Register are ignored. 0b1..Writes to the Monotonic Counter High Register complete as normal.

◆ RTC_WAR_MCHW [2/2]

#define RTC_WAR_MCHW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)

MCHW - Monotonic Counter High Write 0b0..Writes to the Monotonic Counter High Register are ignored. 0b1..Writes to the Monotonic Counter High Register complete as normal.

◆ RTC_WAR_MCLW [1/2]

#define RTC_WAR_MCLW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)

MCLW - Monotonic Counter Low Write 0b0..Writes to the Monotonic Counter Low Register are ignored. 0b1..Writes to the Monotonic Counter Low Register complete as normal.

◆ RTC_WAR_MCLW [2/2]

#define RTC_WAR_MCLW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)

MCLW - Monotonic Counter Low Write 0b0..Writes to the Monotonic Counter Low Register are ignored. 0b1..Writes to the Monotonic Counter Low Register complete as normal.

◆ RTC_WAR_MERW [1/2]

#define RTC_WAR_MERW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)

MERW - Monotonic Enable Register Write 0b0..Writes to the Monotonic Enable Register are ignored. 0b1..Writes to the Monotonic Enable Register complete as normal.

◆ RTC_WAR_MERW [2/2]

#define RTC_WAR_MERW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)

MERW - Monotonic Enable Register Write 0b0..Writes to the Monotonic Enable Register are ignored. 0b1..Writes to the Monotonic Enable Register complete as normal.

◆ RTC_WAR_SRW [1/4]

#define RTC_WAR_SRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)

SRW - Status Register Write 0b0..Writes to the Status Register are ignored. 0b1..Writes to the Status Register complete as normal.

◆ RTC_WAR_SRW [2/4]

#define RTC_WAR_SRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)

SRW - Status Register Write 0b0..Writes to the Status Register are ignored. 0b1..Writes to the Status Register complete as normal.

◆ RTC_WAR_SRW [3/4]

#define RTC_WAR_SRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)

SRW - Status Register Write 0b0..Writes to the Status Register are ignored. 0b1..Writes to the Status Register complete as normal.

◆ RTC_WAR_SRW [4/4]

#define RTC_WAR_SRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)

SRW - Status Register Write 0b0..Writes to the Status Register are ignored. 0b1..Writes to the Status Register complete as normal.

◆ RTC_WAR_TARW [1/4]

#define RTC_WAR_TARW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)

TARW - Time Alarm Register Write 0b0..Writes to the Time Alarm Register are ignored. 0b1..Writes to the Time Alarm Register complete as normal.

◆ RTC_WAR_TARW [2/4]

#define RTC_WAR_TARW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)

TARW - Time Alarm Register Write 0b0..Writes to the Time Alarm Register are ignored. 0b1..Writes to the Time Alarm Register complete as normal.

◆ RTC_WAR_TARW [3/4]

#define RTC_WAR_TARW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)

TARW - Time Alarm Register Write 0b0..Writes to the Time Alarm Register are ignored. 0b1..Writes to the Time Alarm Register complete as normal.

◆ RTC_WAR_TARW [4/4]

#define RTC_WAR_TARW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)

TARW - Time Alarm Register Write 0b0..Writes to the Time Alarm Register are ignored. 0b1..Writes to the Time Alarm Register complete as normal.

◆ RTC_WAR_TCRW [1/4]

#define RTC_WAR_TCRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)

TCRW - Time Compensation Register Write 0b0..Writes to the Time Compensation Register are ignored. 0b1..Writes to the Time Compensation Register complete as normal.

◆ RTC_WAR_TCRW [2/4]

#define RTC_WAR_TCRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)

TCRW - Time Compensation Register Write 0b0..Writes to the Time Compensation Register are ignored. 0b1..Writes to the Time Compensation Register complete as normal.

◆ RTC_WAR_TCRW [3/4]

#define RTC_WAR_TCRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)

TCRW - Time Compensation Register Write 0b0..Writes to the Time Compensation Register are ignored. 0b1..Writes to the Time Compensation Register complete as normal.

◆ RTC_WAR_TCRW [4/4]

#define RTC_WAR_TCRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)

TCRW - Time Compensation Register Write 0b0..Writes to the Time Compensation Register are ignored. 0b1..Writes to the Time Compensation Register complete as normal.

◆ RTC_WAR_TPRW [1/4]

#define RTC_WAR_TPRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)

TPRW - Time Prescaler Register Write 0b0..Writes to the Time Prescaler Register are ignored. 0b1..Writes to the Time Prescaler Register complete as normal.

◆ RTC_WAR_TPRW [2/4]

#define RTC_WAR_TPRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)

TPRW - Time Prescaler Register Write 0b0..Writes to the Time Prescaler Register are ignored. 0b1..Writes to the Time Prescaler Register complete as normal.

◆ RTC_WAR_TPRW [3/4]

#define RTC_WAR_TPRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)

TPRW - Time Prescaler Register Write 0b0..Writes to the Time Prescaler Register are ignored. 0b1..Writes to the Time Prescaler Register complete as normal.

◆ RTC_WAR_TPRW [4/4]

#define RTC_WAR_TPRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)

TPRW - Time Prescaler Register Write 0b0..Writes to the Time Prescaler Register are ignored. 0b1..Writes to the Time Prescaler Register complete as normal.

◆ RTC_WAR_TSRW [1/4]

#define RTC_WAR_TSRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)

TSRW - Time Seconds Register Write 0b0..Writes to the Time Seconds Register are ignored. 0b1..Writes to the Time Seconds Register complete as normal.

◆ RTC_WAR_TSRW [2/4]

#define RTC_WAR_TSRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)

TSRW - Time Seconds Register Write 0b0..Writes to the Time Seconds Register are ignored. 0b1..Writes to the Time Seconds Register complete as normal.

◆ RTC_WAR_TSRW [3/4]

#define RTC_WAR_TSRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)

TSRW - Time Seconds Register Write 0b0..Writes to the Time Seconds Register are ignored. 0b1..Writes to the Time Seconds Register complete as normal.

◆ RTC_WAR_TSRW [4/4]

#define RTC_WAR_TSRW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)

TSRW - Time Seconds Register Write 0b0..Writes to the Time Seconds Register are ignored. 0b1..Writes to the Time Seconds Register complete as normal.

◆ RTC_WAR_TTSW [1/2]

#define RTC_WAR_TTSW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)

TTSW - Tamper Time Seconds Write 0b0..Writes to the Tamper Time Seconds Register are ignored. 0b1..Writes to the Tamper Time Seconds Register complete as normal.

◆ RTC_WAR_TTSW [2/2]

#define RTC_WAR_TTSW ( x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)

TTSW - Tamper Time Seconds Write 0b0..Writes to the Tamper Time Seconds Register are ignored. 0b1..Writes to the Tamper Time Seconds Register complete as normal.