mikroSDK Reference Manual
Macros
SDHC Register Masks
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Macros

#define SDHC_BASE   (0x400B1000u)
 
#define SDHC   ((SDHC_Type *)SDHC_BASE)
 
#define SDHC_BASE_ADDRS   { SDHC_BASE }
 
#define SDHC_BASE_PTRS   { SDHC }
 
#define SDHC_IRQS   { SDHC_IRQn }
 
#define SDHC_HTCAPBLT_VS30_MASK   0x2000000u
 
#define SDHC_HTCAPBLT_VS30_SHIFT   25
 
#define SDHC_HTCAPBLT_VS18_MASK   0x4000000u
 
#define SDHC_HTCAPBLT_VS18_SHIFT   26
 
#define SDHC_WML_WRBRSTLEN_MASK   0x1F000000u
 
#define SDHC_WML_WRBRSTLEN_SHIFT   24
 
#define SDHC_WML_WRBRSTLEN(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRBRSTLEN_SHIFT))&SDHC_WML_WRBRSTLEN_MASK)
 
#define SDHC_VENDOR_VOLTSEL_MASK   0x2u
 
#define SDHC_VENDOR_VOLTSEL_SHIFT   1
 
#define SDHC_CMDRSP_COUNT   (4U)
 
#define SDHC_CMDRSP_COUNT   (4U)
 
#define SDHC_CMDRSP_COUNT   (4U)
 

DSADDR - DMA System Address register

#define SDHC_DSADDR_DSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_DSADDR_DSADDR_SHIFT   (2U)
 
#define SDHC_DSADDR_DSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
 
#define SDHC_DSADDR_DSADDR_MASK   0xFFFFFFFCu
 
#define SDHC_DSADDR_DSADDR_SHIFT   2
 
#define SDHC_DSADDR_DSADDR(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
 
#define SDHC_DSADDR_DSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_DSADDR_DSADDR_SHIFT   (2U)
 
#define SDHC_DSADDR_DSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
 
#define SDHC_DSADDR_DSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_DSADDR_DSADDR_SHIFT   (2U)
 
#define SDHC_DSADDR_DSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
 
#define SDHC_DSADDR_DSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_DSADDR_DSADDR_SHIFT   (2U)
 
#define SDHC_DSADDR_DSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
 

BLKATTR - Block Attributes register

#define SDHC_BLKATTR_BLKSIZE_MASK   (0x1FFFU)
 
#define SDHC_BLKATTR_BLKSIZE_SHIFT   (0U)
 
#define SDHC_BLKATTR_BLKSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
 
#define SDHC_BLKATTR_BLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_BLKATTR_BLKCNT_SHIFT   (16U)
 
#define SDHC_BLKATTR_BLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
 
#define SDHC_BLKATTR_BLKSIZE_MASK   0x1FFFu
 
#define SDHC_BLKATTR_BLKSIZE_SHIFT   0
 
#define SDHC_BLKATTR_BLKSIZE(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
 
#define SDHC_BLKATTR_BLKCNT_MASK   0xFFFF0000u
 
#define SDHC_BLKATTR_BLKCNT_SHIFT   16
 
#define SDHC_BLKATTR_BLKCNT(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
 
#define SDHC_BLKATTR_BLKSIZE_MASK   (0x1FFFU)
 
#define SDHC_BLKATTR_BLKSIZE_SHIFT   (0U)
 
#define SDHC_BLKATTR_BLKSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
 
#define SDHC_BLKATTR_BLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_BLKATTR_BLKCNT_SHIFT   (16U)
 
#define SDHC_BLKATTR_BLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
 
#define SDHC_BLKATTR_BLKSIZE_MASK   (0x1FFFU)
 
#define SDHC_BLKATTR_BLKSIZE_SHIFT   (0U)
 
#define SDHC_BLKATTR_BLKSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
 
#define SDHC_BLKATTR_BLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_BLKATTR_BLKCNT_SHIFT   (16U)
 
#define SDHC_BLKATTR_BLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
 
#define SDHC_BLKATTR_BLKSIZE_MASK   (0x1FFFU)
 
#define SDHC_BLKATTR_BLKSIZE_SHIFT   (0U)
 
#define SDHC_BLKATTR_BLKSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
 
#define SDHC_BLKATTR_BLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_BLKATTR_BLKCNT_SHIFT   (16U)
 
#define SDHC_BLKATTR_BLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
 

CMDARG - Command Argument register

#define SDHC_CMDARG_CMDARG_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDARG_CMDARG_SHIFT   (0U)
 
#define SDHC_CMDARG_CMDARG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
 
#define SDHC_CMDARG_CMDARG_MASK   0xFFFFFFFFu
 
#define SDHC_CMDARG_CMDARG_SHIFT   0
 
#define SDHC_CMDARG_CMDARG(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
 
#define SDHC_CMDARG_CMDARG_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDARG_CMDARG_SHIFT   (0U)
 
#define SDHC_CMDARG_CMDARG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
 
#define SDHC_CMDARG_CMDARG_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDARG_CMDARG_SHIFT   (0U)
 
#define SDHC_CMDARG_CMDARG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
 
#define SDHC_CMDARG_CMDARG_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDARG_CMDARG_SHIFT   (0U)
 
#define SDHC_CMDARG_CMDARG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
 

XFERTYP - Transfer Type register

#define SDHC_XFERTYP_DMAEN_MASK   (0x1U)
 
#define SDHC_XFERTYP_DMAEN_SHIFT   (0U)
 
#define SDHC_XFERTYP_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
 
#define SDHC_XFERTYP_BCEN_MASK   (0x2U)
 
#define SDHC_XFERTYP_BCEN_SHIFT   (1U)
 
#define SDHC_XFERTYP_BCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
 
#define SDHC_XFERTYP_AC12EN_MASK   (0x4U)
 
#define SDHC_XFERTYP_AC12EN_SHIFT   (2U)
 
#define SDHC_XFERTYP_AC12EN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
 
#define SDHC_XFERTYP_DTDSEL_MASK   (0x10U)
 
#define SDHC_XFERTYP_DTDSEL_SHIFT   (4U)
 
#define SDHC_XFERTYP_DTDSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
 
#define SDHC_XFERTYP_MSBSEL_MASK   (0x20U)
 
#define SDHC_XFERTYP_MSBSEL_SHIFT   (5U)
 
#define SDHC_XFERTYP_MSBSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
 
#define SDHC_XFERTYP_RSPTYP_MASK   (0x30000U)
 
#define SDHC_XFERTYP_RSPTYP_SHIFT   (16U)
 
#define SDHC_XFERTYP_RSPTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
 
#define SDHC_XFERTYP_CCCEN_MASK   (0x80000U)
 
#define SDHC_XFERTYP_CCCEN_SHIFT   (19U)
 
#define SDHC_XFERTYP_CCCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
 
#define SDHC_XFERTYP_CICEN_MASK   (0x100000U)
 
#define SDHC_XFERTYP_CICEN_SHIFT   (20U)
 
#define SDHC_XFERTYP_CICEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
 
#define SDHC_XFERTYP_DPSEL_MASK   (0x200000U)
 
#define SDHC_XFERTYP_DPSEL_SHIFT   (21U)
 
#define SDHC_XFERTYP_DPSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
 
#define SDHC_XFERTYP_CMDTYP_MASK   (0xC00000U)
 
#define SDHC_XFERTYP_CMDTYP_SHIFT   (22U)
 
#define SDHC_XFERTYP_CMDTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
 
#define SDHC_XFERTYP_CMDINX_MASK   (0x3F000000U)
 
#define SDHC_XFERTYP_CMDINX_SHIFT   (24U)
 
#define SDHC_XFERTYP_CMDINX(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
 
#define SDHC_XFERTYP_DMAEN_MASK   0x1u
 
#define SDHC_XFERTYP_DMAEN_SHIFT   0
 
#define SDHC_XFERTYP_BCEN_MASK   0x2u
 
#define SDHC_XFERTYP_BCEN_SHIFT   1
 
#define SDHC_XFERTYP_AC12EN_MASK   0x4u
 
#define SDHC_XFERTYP_AC12EN_SHIFT   2
 
#define SDHC_XFERTYP_DTDSEL_MASK   0x10u
 
#define SDHC_XFERTYP_DTDSEL_SHIFT   4
 
#define SDHC_XFERTYP_MSBSEL_MASK   0x20u
 
#define SDHC_XFERTYP_MSBSEL_SHIFT   5
 
#define SDHC_XFERTYP_RSPTYP_MASK   0x30000u
 
#define SDHC_XFERTYP_RSPTYP_SHIFT   16
 
#define SDHC_XFERTYP_RSPTYP(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
 
#define SDHC_XFERTYP_CCCEN_MASK   0x80000u
 
#define SDHC_XFERTYP_CCCEN_SHIFT   19
 
#define SDHC_XFERTYP_CICEN_MASK   0x100000u
 
#define SDHC_XFERTYP_CICEN_SHIFT   20
 
#define SDHC_XFERTYP_DPSEL_MASK   0x200000u
 
#define SDHC_XFERTYP_DPSEL_SHIFT   21
 
#define SDHC_XFERTYP_CMDTYP_MASK   0xC00000u
 
#define SDHC_XFERTYP_CMDTYP_SHIFT   22
 
#define SDHC_XFERTYP_CMDTYP(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
 
#define SDHC_XFERTYP_CMDINX_MASK   0x3F000000u
 
#define SDHC_XFERTYP_CMDINX_SHIFT   24
 
#define SDHC_XFERTYP_CMDINX(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
 
#define SDHC_XFERTYP_DMAEN_MASK   (0x1U)
 
#define SDHC_XFERTYP_DMAEN_SHIFT   (0U)
 
#define SDHC_XFERTYP_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
 
#define SDHC_XFERTYP_BCEN_MASK   (0x2U)
 
#define SDHC_XFERTYP_BCEN_SHIFT   (1U)
 
#define SDHC_XFERTYP_BCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
 
#define SDHC_XFERTYP_AC12EN_MASK   (0x4U)
 
#define SDHC_XFERTYP_AC12EN_SHIFT   (2U)
 
#define SDHC_XFERTYP_AC12EN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
 
#define SDHC_XFERTYP_DTDSEL_MASK   (0x10U)
 
#define SDHC_XFERTYP_DTDSEL_SHIFT   (4U)
 
#define SDHC_XFERTYP_DTDSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
 
#define SDHC_XFERTYP_MSBSEL_MASK   (0x20U)
 
#define SDHC_XFERTYP_MSBSEL_SHIFT   (5U)
 
#define SDHC_XFERTYP_MSBSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
 
#define SDHC_XFERTYP_RSPTYP_MASK   (0x30000U)
 
#define SDHC_XFERTYP_RSPTYP_SHIFT   (16U)
 
#define SDHC_XFERTYP_RSPTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
 
#define SDHC_XFERTYP_CCCEN_MASK   (0x80000U)
 
#define SDHC_XFERTYP_CCCEN_SHIFT   (19U)
 
#define SDHC_XFERTYP_CCCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
 
#define SDHC_XFERTYP_CICEN_MASK   (0x100000U)
 
#define SDHC_XFERTYP_CICEN_SHIFT   (20U)
 
#define SDHC_XFERTYP_CICEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
 
#define SDHC_XFERTYP_DPSEL_MASK   (0x200000U)
 
#define SDHC_XFERTYP_DPSEL_SHIFT   (21U)
 
#define SDHC_XFERTYP_DPSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
 
#define SDHC_XFERTYP_CMDTYP_MASK   (0xC00000U)
 
#define SDHC_XFERTYP_CMDTYP_SHIFT   (22U)
 
#define SDHC_XFERTYP_CMDTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
 
#define SDHC_XFERTYP_CMDINX_MASK   (0x3F000000U)
 
#define SDHC_XFERTYP_CMDINX_SHIFT   (24U)
 
#define SDHC_XFERTYP_CMDINX(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
 
#define SDHC_XFERTYP_DMAEN_MASK   (0x1U)
 
#define SDHC_XFERTYP_DMAEN_SHIFT   (0U)
 
#define SDHC_XFERTYP_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
 
#define SDHC_XFERTYP_BCEN_MASK   (0x2U)
 
#define SDHC_XFERTYP_BCEN_SHIFT   (1U)
 
#define SDHC_XFERTYP_BCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
 
#define SDHC_XFERTYP_AC12EN_MASK   (0x4U)
 
#define SDHC_XFERTYP_AC12EN_SHIFT   (2U)
 
#define SDHC_XFERTYP_AC12EN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
 
#define SDHC_XFERTYP_DTDSEL_MASK   (0x10U)
 
#define SDHC_XFERTYP_DTDSEL_SHIFT   (4U)
 
#define SDHC_XFERTYP_DTDSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
 
#define SDHC_XFERTYP_MSBSEL_MASK   (0x20U)
 
#define SDHC_XFERTYP_MSBSEL_SHIFT   (5U)
 
#define SDHC_XFERTYP_MSBSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
 
#define SDHC_XFERTYP_RSPTYP_MASK   (0x30000U)
 
#define SDHC_XFERTYP_RSPTYP_SHIFT   (16U)
 
#define SDHC_XFERTYP_RSPTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
 
#define SDHC_XFERTYP_CCCEN_MASK   (0x80000U)
 
#define SDHC_XFERTYP_CCCEN_SHIFT   (19U)
 
#define SDHC_XFERTYP_CCCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
 
#define SDHC_XFERTYP_CICEN_MASK   (0x100000U)
 
#define SDHC_XFERTYP_CICEN_SHIFT   (20U)
 
#define SDHC_XFERTYP_CICEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
 
#define SDHC_XFERTYP_DPSEL_MASK   (0x200000U)
 
#define SDHC_XFERTYP_DPSEL_SHIFT   (21U)
 
#define SDHC_XFERTYP_DPSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
 
#define SDHC_XFERTYP_CMDTYP_MASK   (0xC00000U)
 
#define SDHC_XFERTYP_CMDTYP_SHIFT   (22U)
 
#define SDHC_XFERTYP_CMDTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
 
#define SDHC_XFERTYP_CMDINX_MASK   (0x3F000000U)
 
#define SDHC_XFERTYP_CMDINX_SHIFT   (24U)
 
#define SDHC_XFERTYP_CMDINX(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
 
#define SDHC_XFERTYP_DMAEN_MASK   (0x1U)
 
#define SDHC_XFERTYP_DMAEN_SHIFT   (0U)
 
#define SDHC_XFERTYP_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
 
#define SDHC_XFERTYP_BCEN_MASK   (0x2U)
 
#define SDHC_XFERTYP_BCEN_SHIFT   (1U)
 
#define SDHC_XFERTYP_BCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
 
#define SDHC_XFERTYP_AC12EN_MASK   (0x4U)
 
#define SDHC_XFERTYP_AC12EN_SHIFT   (2U)
 
#define SDHC_XFERTYP_AC12EN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
 
#define SDHC_XFERTYP_DTDSEL_MASK   (0x10U)
 
#define SDHC_XFERTYP_DTDSEL_SHIFT   (4U)
 
#define SDHC_XFERTYP_DTDSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
 
#define SDHC_XFERTYP_MSBSEL_MASK   (0x20U)
 
#define SDHC_XFERTYP_MSBSEL_SHIFT   (5U)
 
#define SDHC_XFERTYP_MSBSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
 
#define SDHC_XFERTYP_RSPTYP_MASK   (0x30000U)
 
#define SDHC_XFERTYP_RSPTYP_SHIFT   (16U)
 
#define SDHC_XFERTYP_RSPTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
 
#define SDHC_XFERTYP_CCCEN_MASK   (0x80000U)
 
#define SDHC_XFERTYP_CCCEN_SHIFT   (19U)
 
#define SDHC_XFERTYP_CCCEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
 
#define SDHC_XFERTYP_CICEN_MASK   (0x100000U)
 
#define SDHC_XFERTYP_CICEN_SHIFT   (20U)
 
#define SDHC_XFERTYP_CICEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
 
#define SDHC_XFERTYP_DPSEL_MASK   (0x200000U)
 
#define SDHC_XFERTYP_DPSEL_SHIFT   (21U)
 
#define SDHC_XFERTYP_DPSEL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
 
#define SDHC_XFERTYP_CMDTYP_MASK   (0xC00000U)
 
#define SDHC_XFERTYP_CMDTYP_SHIFT   (22U)
 
#define SDHC_XFERTYP_CMDTYP(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
 
#define SDHC_XFERTYP_CMDINX_MASK   (0x3F000000U)
 
#define SDHC_XFERTYP_CMDINX_SHIFT   (24U)
 
#define SDHC_XFERTYP_CMDINX(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
 

CMDRSP - Command Response 0..Command Response 3

#define SDHC_CMDRSP_CMDRSP0_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP0_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP0(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
 
#define SDHC_CMDRSP_CMDRSP1_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP1_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP1(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
 
#define SDHC_CMDRSP_CMDRSP2_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP2_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP2(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
 
#define SDHC_CMDRSP_CMDRSP3_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP3_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP3(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
 
#define SDHC_CMDRSP_CMDRSP0_MASK   0xFFFFFFFFu
 
#define SDHC_CMDRSP_CMDRSP0_SHIFT   0
 
#define SDHC_CMDRSP_CMDRSP0(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
 
#define SDHC_CMDRSP_CMDRSP1_MASK   0xFFFFFFFFu
 
#define SDHC_CMDRSP_CMDRSP1_SHIFT   0
 
#define SDHC_CMDRSP_CMDRSP1(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
 
#define SDHC_CMDRSP_CMDRSP2_MASK   0xFFFFFFFFu
 
#define SDHC_CMDRSP_CMDRSP2_SHIFT   0
 
#define SDHC_CMDRSP_CMDRSP2(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
 
#define SDHC_CMDRSP_CMDRSP3_MASK   0xFFFFFFFFu
 
#define SDHC_CMDRSP_CMDRSP3_SHIFT   0
 
#define SDHC_CMDRSP_CMDRSP3(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
 
#define SDHC_CMDRSP_CMDRSP0_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP0_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP0(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
 
#define SDHC_CMDRSP_CMDRSP1_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP1_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP1(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
 
#define SDHC_CMDRSP_CMDRSP2_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP2_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP2(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
 
#define SDHC_CMDRSP_CMDRSP3_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP3_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP3(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
 
#define SDHC_CMDRSP_CMDRSP0_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP0_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP0(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
 
#define SDHC_CMDRSP_CMDRSP1_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP1_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP1(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
 
#define SDHC_CMDRSP_CMDRSP2_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP2_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP2(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
 
#define SDHC_CMDRSP_CMDRSP3_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP3_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP3(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
 
#define SDHC_CMDRSP_CMDRSP0_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP0_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP0(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
 
#define SDHC_CMDRSP_CMDRSP1_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP1_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP1(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
 
#define SDHC_CMDRSP_CMDRSP2_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP2_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP2(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
 
#define SDHC_CMDRSP_CMDRSP3_MASK   (0xFFFFFFFFU)
 
#define SDHC_CMDRSP_CMDRSP3_SHIFT   (0U)
 
#define SDHC_CMDRSP_CMDRSP3(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
 

CMDRSP - Command Response 0..Command Response 3

#define SDHC_CMDRSP_COUNT   (4U)
 

DATPORT - Buffer Data Port register

#define SDHC_DATPORT_DATCONT_MASK   (0xFFFFFFFFU)
 
#define SDHC_DATPORT_DATCONT_SHIFT   (0U)
 
#define SDHC_DATPORT_DATCONT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
 
#define SDHC_DATPORT_DATCONT_MASK   0xFFFFFFFFu
 
#define SDHC_DATPORT_DATCONT_SHIFT   0
 
#define SDHC_DATPORT_DATCONT(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
 
#define SDHC_DATPORT_DATCONT_MASK   (0xFFFFFFFFU)
 
#define SDHC_DATPORT_DATCONT_SHIFT   (0U)
 
#define SDHC_DATPORT_DATCONT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
 
#define SDHC_DATPORT_DATCONT_MASK   (0xFFFFFFFFU)
 
#define SDHC_DATPORT_DATCONT_SHIFT   (0U)
 
#define SDHC_DATPORT_DATCONT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
 
#define SDHC_DATPORT_DATCONT_MASK   (0xFFFFFFFFU)
 
#define SDHC_DATPORT_DATCONT_SHIFT   (0U)
 
#define SDHC_DATPORT_DATCONT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
 

PRSSTAT - Present State register

#define SDHC_PRSSTAT_CIHB_MASK   (0x1U)
 
#define SDHC_PRSSTAT_CIHB_SHIFT   (0U)
 
#define SDHC_PRSSTAT_CIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
 
#define SDHC_PRSSTAT_CDIHB_MASK   (0x2U)
 
#define SDHC_PRSSTAT_CDIHB_SHIFT   (1U)
 
#define SDHC_PRSSTAT_CDIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
 
#define SDHC_PRSSTAT_DLA_MASK   (0x4U)
 
#define SDHC_PRSSTAT_DLA_SHIFT   (2U)
 
#define SDHC_PRSSTAT_DLA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
 
#define SDHC_PRSSTAT_SDSTB_MASK   (0x8U)
 
#define SDHC_PRSSTAT_SDSTB_SHIFT   (3U)
 
#define SDHC_PRSSTAT_SDSTB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
 
#define SDHC_PRSSTAT_IPGOFF_MASK   (0x10U)
 
#define SDHC_PRSSTAT_IPGOFF_SHIFT   (4U)
 
#define SDHC_PRSSTAT_IPGOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
 
#define SDHC_PRSSTAT_HCKOFF_MASK   (0x20U)
 
#define SDHC_PRSSTAT_HCKOFF_SHIFT   (5U)
 
#define SDHC_PRSSTAT_HCKOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
 
#define SDHC_PRSSTAT_PEROFF_MASK   (0x40U)
 
#define SDHC_PRSSTAT_PEROFF_SHIFT   (6U)
 
#define SDHC_PRSSTAT_PEROFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
 
#define SDHC_PRSSTAT_SDOFF_MASK   (0x80U)
 
#define SDHC_PRSSTAT_SDOFF_SHIFT   (7U)
 
#define SDHC_PRSSTAT_SDOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
 
#define SDHC_PRSSTAT_WTA_MASK   (0x100U)
 
#define SDHC_PRSSTAT_WTA_SHIFT   (8U)
 
#define SDHC_PRSSTAT_WTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
 
#define SDHC_PRSSTAT_RTA_MASK   (0x200U)
 
#define SDHC_PRSSTAT_RTA_SHIFT   (9U)
 
#define SDHC_PRSSTAT_RTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
 
#define SDHC_PRSSTAT_BWEN_MASK   (0x400U)
 
#define SDHC_PRSSTAT_BWEN_SHIFT   (10U)
 
#define SDHC_PRSSTAT_BWEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
 
#define SDHC_PRSSTAT_BREN_MASK   (0x800U)
 
#define SDHC_PRSSTAT_BREN_SHIFT   (11U)
 
#define SDHC_PRSSTAT_BREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
 
#define SDHC_PRSSTAT_CINS_MASK   (0x10000U)
 
#define SDHC_PRSSTAT_CINS_SHIFT   (16U)
 
#define SDHC_PRSSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
 
#define SDHC_PRSSTAT_CLSL_MASK   (0x800000U)
 
#define SDHC_PRSSTAT_CLSL_SHIFT   (23U)
 
#define SDHC_PRSSTAT_CLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
 
#define SDHC_PRSSTAT_DLSL_MASK   (0xFF000000U)
 
#define SDHC_PRSSTAT_DLSL_SHIFT   (24U)
 
#define SDHC_PRSSTAT_DLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
 
#define SDHC_PRSSTAT_CIHB_MASK   0x1u
 
#define SDHC_PRSSTAT_CIHB_SHIFT   0
 
#define SDHC_PRSSTAT_CDIHB_MASK   0x2u
 
#define SDHC_PRSSTAT_CDIHB_SHIFT   1
 
#define SDHC_PRSSTAT_DLA_MASK   0x4u
 
#define SDHC_PRSSTAT_DLA_SHIFT   2
 
#define SDHC_PRSSTAT_SDSTB_MASK   0x8u
 
#define SDHC_PRSSTAT_SDSTB_SHIFT   3
 
#define SDHC_PRSSTAT_IPGOFF_MASK   0x10u
 
#define SDHC_PRSSTAT_IPGOFF_SHIFT   4
 
#define SDHC_PRSSTAT_HCKOFF_MASK   0x20u
 
#define SDHC_PRSSTAT_HCKOFF_SHIFT   5
 
#define SDHC_PRSSTAT_PEROFF_MASK   0x40u
 
#define SDHC_PRSSTAT_PEROFF_SHIFT   6
 
#define SDHC_PRSSTAT_SDOFF_MASK   0x80u
 
#define SDHC_PRSSTAT_SDOFF_SHIFT   7
 
#define SDHC_PRSSTAT_WTA_MASK   0x100u
 
#define SDHC_PRSSTAT_WTA_SHIFT   8
 
#define SDHC_PRSSTAT_RTA_MASK   0x200u
 
#define SDHC_PRSSTAT_RTA_SHIFT   9
 
#define SDHC_PRSSTAT_BWEN_MASK   0x400u
 
#define SDHC_PRSSTAT_BWEN_SHIFT   10
 
#define SDHC_PRSSTAT_BREN_MASK   0x800u
 
#define SDHC_PRSSTAT_BREN_SHIFT   11
 
#define SDHC_PRSSTAT_CINS_MASK   0x10000u
 
#define SDHC_PRSSTAT_CINS_SHIFT   16
 
#define SDHC_PRSSTAT_CLSL_MASK   0x800000u
 
#define SDHC_PRSSTAT_CLSL_SHIFT   23
 
#define SDHC_PRSSTAT_DLSL_MASK   0xFF000000u
 
#define SDHC_PRSSTAT_DLSL_SHIFT   24
 
#define SDHC_PRSSTAT_DLSL(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
 
#define SDHC_PRSSTAT_CIHB_MASK   (0x1U)
 
#define SDHC_PRSSTAT_CIHB_SHIFT   (0U)
 
#define SDHC_PRSSTAT_CIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
 
#define SDHC_PRSSTAT_CDIHB_MASK   (0x2U)
 
#define SDHC_PRSSTAT_CDIHB_SHIFT   (1U)
 
#define SDHC_PRSSTAT_CDIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
 
#define SDHC_PRSSTAT_DLA_MASK   (0x4U)
 
#define SDHC_PRSSTAT_DLA_SHIFT   (2U)
 
#define SDHC_PRSSTAT_DLA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
 
#define SDHC_PRSSTAT_SDSTB_MASK   (0x8U)
 
#define SDHC_PRSSTAT_SDSTB_SHIFT   (3U)
 
#define SDHC_PRSSTAT_SDSTB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
 
#define SDHC_PRSSTAT_IPGOFF_MASK   (0x10U)
 
#define SDHC_PRSSTAT_IPGOFF_SHIFT   (4U)
 
#define SDHC_PRSSTAT_IPGOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
 
#define SDHC_PRSSTAT_HCKOFF_MASK   (0x20U)
 
#define SDHC_PRSSTAT_HCKOFF_SHIFT   (5U)
 
#define SDHC_PRSSTAT_HCKOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
 
#define SDHC_PRSSTAT_PEROFF_MASK   (0x40U)
 
#define SDHC_PRSSTAT_PEROFF_SHIFT   (6U)
 
#define SDHC_PRSSTAT_PEROFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
 
#define SDHC_PRSSTAT_SDOFF_MASK   (0x80U)
 
#define SDHC_PRSSTAT_SDOFF_SHIFT   (7U)
 
#define SDHC_PRSSTAT_SDOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
 
#define SDHC_PRSSTAT_WTA_MASK   (0x100U)
 
#define SDHC_PRSSTAT_WTA_SHIFT   (8U)
 
#define SDHC_PRSSTAT_WTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
 
#define SDHC_PRSSTAT_RTA_MASK   (0x200U)
 
#define SDHC_PRSSTAT_RTA_SHIFT   (9U)
 
#define SDHC_PRSSTAT_RTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
 
#define SDHC_PRSSTAT_BWEN_MASK   (0x400U)
 
#define SDHC_PRSSTAT_BWEN_SHIFT   (10U)
 
#define SDHC_PRSSTAT_BWEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
 
#define SDHC_PRSSTAT_BREN_MASK   (0x800U)
 
#define SDHC_PRSSTAT_BREN_SHIFT   (11U)
 
#define SDHC_PRSSTAT_BREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
 
#define SDHC_PRSSTAT_CINS_MASK   (0x10000U)
 
#define SDHC_PRSSTAT_CINS_SHIFT   (16U)
 
#define SDHC_PRSSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
 
#define SDHC_PRSSTAT_CLSL_MASK   (0x800000U)
 
#define SDHC_PRSSTAT_CLSL_SHIFT   (23U)
 
#define SDHC_PRSSTAT_CLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
 
#define SDHC_PRSSTAT_DLSL_MASK   (0xFF000000U)
 
#define SDHC_PRSSTAT_DLSL_SHIFT   (24U)
 
#define SDHC_PRSSTAT_DLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
 
#define SDHC_PRSSTAT_CIHB_MASK   (0x1U)
 
#define SDHC_PRSSTAT_CIHB_SHIFT   (0U)
 
#define SDHC_PRSSTAT_CIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
 
#define SDHC_PRSSTAT_CDIHB_MASK   (0x2U)
 
#define SDHC_PRSSTAT_CDIHB_SHIFT   (1U)
 
#define SDHC_PRSSTAT_CDIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
 
#define SDHC_PRSSTAT_DLA_MASK   (0x4U)
 
#define SDHC_PRSSTAT_DLA_SHIFT   (2U)
 
#define SDHC_PRSSTAT_DLA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
 
#define SDHC_PRSSTAT_SDSTB_MASK   (0x8U)
 
#define SDHC_PRSSTAT_SDSTB_SHIFT   (3U)
 
#define SDHC_PRSSTAT_SDSTB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
 
#define SDHC_PRSSTAT_IPGOFF_MASK   (0x10U)
 
#define SDHC_PRSSTAT_IPGOFF_SHIFT   (4U)
 
#define SDHC_PRSSTAT_IPGOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
 
#define SDHC_PRSSTAT_HCKOFF_MASK   (0x20U)
 
#define SDHC_PRSSTAT_HCKOFF_SHIFT   (5U)
 
#define SDHC_PRSSTAT_HCKOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
 
#define SDHC_PRSSTAT_PEROFF_MASK   (0x40U)
 
#define SDHC_PRSSTAT_PEROFF_SHIFT   (6U)
 
#define SDHC_PRSSTAT_PEROFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
 
#define SDHC_PRSSTAT_SDOFF_MASK   (0x80U)
 
#define SDHC_PRSSTAT_SDOFF_SHIFT   (7U)
 
#define SDHC_PRSSTAT_SDOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
 
#define SDHC_PRSSTAT_WTA_MASK   (0x100U)
 
#define SDHC_PRSSTAT_WTA_SHIFT   (8U)
 
#define SDHC_PRSSTAT_WTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
 
#define SDHC_PRSSTAT_RTA_MASK   (0x200U)
 
#define SDHC_PRSSTAT_RTA_SHIFT   (9U)
 
#define SDHC_PRSSTAT_RTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
 
#define SDHC_PRSSTAT_BWEN_MASK   (0x400U)
 
#define SDHC_PRSSTAT_BWEN_SHIFT   (10U)
 
#define SDHC_PRSSTAT_BWEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
 
#define SDHC_PRSSTAT_BREN_MASK   (0x800U)
 
#define SDHC_PRSSTAT_BREN_SHIFT   (11U)
 
#define SDHC_PRSSTAT_BREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
 
#define SDHC_PRSSTAT_CINS_MASK   (0x10000U)
 
#define SDHC_PRSSTAT_CINS_SHIFT   (16U)
 
#define SDHC_PRSSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
 
#define SDHC_PRSSTAT_CLSL_MASK   (0x800000U)
 
#define SDHC_PRSSTAT_CLSL_SHIFT   (23U)
 
#define SDHC_PRSSTAT_CLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
 
#define SDHC_PRSSTAT_DLSL_MASK   (0xFF000000U)
 
#define SDHC_PRSSTAT_DLSL_SHIFT   (24U)
 
#define SDHC_PRSSTAT_DLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
 
#define SDHC_PRSSTAT_CIHB_MASK   (0x1U)
 
#define SDHC_PRSSTAT_CIHB_SHIFT   (0U)
 
#define SDHC_PRSSTAT_CIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
 
#define SDHC_PRSSTAT_CDIHB_MASK   (0x2U)
 
#define SDHC_PRSSTAT_CDIHB_SHIFT   (1U)
 
#define SDHC_PRSSTAT_CDIHB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
 
#define SDHC_PRSSTAT_DLA_MASK   (0x4U)
 
#define SDHC_PRSSTAT_DLA_SHIFT   (2U)
 
#define SDHC_PRSSTAT_DLA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
 
#define SDHC_PRSSTAT_SDSTB_MASK   (0x8U)
 
#define SDHC_PRSSTAT_SDSTB_SHIFT   (3U)
 
#define SDHC_PRSSTAT_SDSTB(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
 
#define SDHC_PRSSTAT_IPGOFF_MASK   (0x10U)
 
#define SDHC_PRSSTAT_IPGOFF_SHIFT   (4U)
 
#define SDHC_PRSSTAT_IPGOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
 
#define SDHC_PRSSTAT_HCKOFF_MASK   (0x20U)
 
#define SDHC_PRSSTAT_HCKOFF_SHIFT   (5U)
 
#define SDHC_PRSSTAT_HCKOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
 
#define SDHC_PRSSTAT_PEROFF_MASK   (0x40U)
 
#define SDHC_PRSSTAT_PEROFF_SHIFT   (6U)
 
#define SDHC_PRSSTAT_PEROFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
 
#define SDHC_PRSSTAT_SDOFF_MASK   (0x80U)
 
#define SDHC_PRSSTAT_SDOFF_SHIFT   (7U)
 
#define SDHC_PRSSTAT_SDOFF(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
 
#define SDHC_PRSSTAT_WTA_MASK   (0x100U)
 
#define SDHC_PRSSTAT_WTA_SHIFT   (8U)
 
#define SDHC_PRSSTAT_WTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
 
#define SDHC_PRSSTAT_RTA_MASK   (0x200U)
 
#define SDHC_PRSSTAT_RTA_SHIFT   (9U)
 
#define SDHC_PRSSTAT_RTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
 
#define SDHC_PRSSTAT_BWEN_MASK   (0x400U)
 
#define SDHC_PRSSTAT_BWEN_SHIFT   (10U)
 
#define SDHC_PRSSTAT_BWEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
 
#define SDHC_PRSSTAT_BREN_MASK   (0x800U)
 
#define SDHC_PRSSTAT_BREN_SHIFT   (11U)
 
#define SDHC_PRSSTAT_BREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
 
#define SDHC_PRSSTAT_CINS_MASK   (0x10000U)
 
#define SDHC_PRSSTAT_CINS_SHIFT   (16U)
 
#define SDHC_PRSSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
 
#define SDHC_PRSSTAT_CLSL_MASK   (0x800000U)
 
#define SDHC_PRSSTAT_CLSL_SHIFT   (23U)
 
#define SDHC_PRSSTAT_CLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
 
#define SDHC_PRSSTAT_DLSL_MASK   (0xFF000000U)
 
#define SDHC_PRSSTAT_DLSL_SHIFT   (24U)
 
#define SDHC_PRSSTAT_DLSL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
 

PROCTL - Protocol Control register

#define SDHC_PROCTL_LCTL_MASK   (0x1U)
 
#define SDHC_PROCTL_LCTL_SHIFT   (0U)
 
#define SDHC_PROCTL_LCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
 
#define SDHC_PROCTL_DTW_MASK   (0x6U)
 
#define SDHC_PROCTL_DTW_SHIFT   (1U)
 
#define SDHC_PROCTL_DTW(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
 
#define SDHC_PROCTL_D3CD_MASK   (0x8U)
 
#define SDHC_PROCTL_D3CD_SHIFT   (3U)
 
#define SDHC_PROCTL_D3CD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
 
#define SDHC_PROCTL_EMODE_MASK   (0x30U)
 
#define SDHC_PROCTL_EMODE_SHIFT   (4U)
 
#define SDHC_PROCTL_EMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
 
#define SDHC_PROCTL_CDTL_MASK   (0x40U)
 
#define SDHC_PROCTL_CDTL_SHIFT   (6U)
 
#define SDHC_PROCTL_CDTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
 
#define SDHC_PROCTL_CDSS_MASK   (0x80U)
 
#define SDHC_PROCTL_CDSS_SHIFT   (7U)
 
#define SDHC_PROCTL_CDSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
 
#define SDHC_PROCTL_DMAS_MASK   (0x300U)
 
#define SDHC_PROCTL_DMAS_SHIFT   (8U)
 
#define SDHC_PROCTL_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
 
#define SDHC_PROCTL_SABGREQ_MASK   (0x10000U)
 
#define SDHC_PROCTL_SABGREQ_SHIFT   (16U)
 
#define SDHC_PROCTL_SABGREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
 
#define SDHC_PROCTL_CREQ_MASK   (0x20000U)
 
#define SDHC_PROCTL_CREQ_SHIFT   (17U)
 
#define SDHC_PROCTL_CREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
 
#define SDHC_PROCTL_RWCTL_MASK   (0x40000U)
 
#define SDHC_PROCTL_RWCTL_SHIFT   (18U)
 
#define SDHC_PROCTL_RWCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
 
#define SDHC_PROCTL_IABG_MASK   (0x80000U)
 
#define SDHC_PROCTL_IABG_SHIFT   (19U)
 
#define SDHC_PROCTL_IABG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
 
#define SDHC_PROCTL_WECINT_MASK   (0x1000000U)
 
#define SDHC_PROCTL_WECINT_SHIFT   (24U)
 
#define SDHC_PROCTL_WECINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
 
#define SDHC_PROCTL_WECINS_MASK   (0x2000000U)
 
#define SDHC_PROCTL_WECINS_SHIFT   (25U)
 
#define SDHC_PROCTL_WECINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
 
#define SDHC_PROCTL_WECRM_MASK   (0x4000000U)
 
#define SDHC_PROCTL_WECRM_SHIFT   (26U)
 
#define SDHC_PROCTL_WECRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
 
#define SDHC_PROCTL_LCTL_MASK   0x1u
 
#define SDHC_PROCTL_LCTL_SHIFT   0
 
#define SDHC_PROCTL_DTW_MASK   0x6u
 
#define SDHC_PROCTL_DTW_SHIFT   1
 
#define SDHC_PROCTL_DTW(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
 
#define SDHC_PROCTL_D3CD_MASK   0x8u
 
#define SDHC_PROCTL_D3CD_SHIFT   3
 
#define SDHC_PROCTL_EMODE_MASK   0x30u
 
#define SDHC_PROCTL_EMODE_SHIFT   4
 
#define SDHC_PROCTL_EMODE(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
 
#define SDHC_PROCTL_CDTL_MASK   0x40u
 
#define SDHC_PROCTL_CDTL_SHIFT   6
 
#define SDHC_PROCTL_CDSS_MASK   0x80u
 
#define SDHC_PROCTL_CDSS_SHIFT   7
 
#define SDHC_PROCTL_DMAS_MASK   0x300u
 
#define SDHC_PROCTL_DMAS_SHIFT   8
 
#define SDHC_PROCTL_DMAS(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
 
#define SDHC_PROCTL_SABGREQ_MASK   0x10000u
 
#define SDHC_PROCTL_SABGREQ_SHIFT   16
 
#define SDHC_PROCTL_CREQ_MASK   0x20000u
 
#define SDHC_PROCTL_CREQ_SHIFT   17
 
#define SDHC_PROCTL_RWCTL_MASK   0x40000u
 
#define SDHC_PROCTL_RWCTL_SHIFT   18
 
#define SDHC_PROCTL_IABG_MASK   0x80000u
 
#define SDHC_PROCTL_IABG_SHIFT   19
 
#define SDHC_PROCTL_WECINT_MASK   0x1000000u
 
#define SDHC_PROCTL_WECINT_SHIFT   24
 
#define SDHC_PROCTL_WECINS_MASK   0x2000000u
 
#define SDHC_PROCTL_WECINS_SHIFT   25
 
#define SDHC_PROCTL_WECRM_MASK   0x4000000u
 
#define SDHC_PROCTL_WECRM_SHIFT   26
 
#define SDHC_PROCTL_LCTL_MASK   (0x1U)
 
#define SDHC_PROCTL_LCTL_SHIFT   (0U)
 
#define SDHC_PROCTL_LCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
 
#define SDHC_PROCTL_DTW_MASK   (0x6U)
 
#define SDHC_PROCTL_DTW_SHIFT   (1U)
 
#define SDHC_PROCTL_DTW(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
 
#define SDHC_PROCTL_D3CD_MASK   (0x8U)
 
#define SDHC_PROCTL_D3CD_SHIFT   (3U)
 
#define SDHC_PROCTL_D3CD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
 
#define SDHC_PROCTL_EMODE_MASK   (0x30U)
 
#define SDHC_PROCTL_EMODE_SHIFT   (4U)
 
#define SDHC_PROCTL_EMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
 
#define SDHC_PROCTL_CDTL_MASK   (0x40U)
 
#define SDHC_PROCTL_CDTL_SHIFT   (6U)
 
#define SDHC_PROCTL_CDTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
 
#define SDHC_PROCTL_CDSS_MASK   (0x80U)
 
#define SDHC_PROCTL_CDSS_SHIFT   (7U)
 
#define SDHC_PROCTL_CDSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
 
#define SDHC_PROCTL_DMAS_MASK   (0x300U)
 
#define SDHC_PROCTL_DMAS_SHIFT   (8U)
 
#define SDHC_PROCTL_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
 
#define SDHC_PROCTL_SABGREQ_MASK   (0x10000U)
 
#define SDHC_PROCTL_SABGREQ_SHIFT   (16U)
 
#define SDHC_PROCTL_SABGREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
 
#define SDHC_PROCTL_CREQ_MASK   (0x20000U)
 
#define SDHC_PROCTL_CREQ_SHIFT   (17U)
 
#define SDHC_PROCTL_CREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
 
#define SDHC_PROCTL_RWCTL_MASK   (0x40000U)
 
#define SDHC_PROCTL_RWCTL_SHIFT   (18U)
 
#define SDHC_PROCTL_RWCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
 
#define SDHC_PROCTL_IABG_MASK   (0x80000U)
 
#define SDHC_PROCTL_IABG_SHIFT   (19U)
 
#define SDHC_PROCTL_IABG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
 
#define SDHC_PROCTL_WECINT_MASK   (0x1000000U)
 
#define SDHC_PROCTL_WECINT_SHIFT   (24U)
 
#define SDHC_PROCTL_WECINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
 
#define SDHC_PROCTL_WECINS_MASK   (0x2000000U)
 
#define SDHC_PROCTL_WECINS_SHIFT   (25U)
 
#define SDHC_PROCTL_WECINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
 
#define SDHC_PROCTL_WECRM_MASK   (0x4000000U)
 
#define SDHC_PROCTL_WECRM_SHIFT   (26U)
 
#define SDHC_PROCTL_WECRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
 
#define SDHC_PROCTL_LCTL_MASK   (0x1U)
 
#define SDHC_PROCTL_LCTL_SHIFT   (0U)
 
#define SDHC_PROCTL_LCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
 
#define SDHC_PROCTL_DTW_MASK   (0x6U)
 
#define SDHC_PROCTL_DTW_SHIFT   (1U)
 
#define SDHC_PROCTL_DTW(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
 
#define SDHC_PROCTL_D3CD_MASK   (0x8U)
 
#define SDHC_PROCTL_D3CD_SHIFT   (3U)
 
#define SDHC_PROCTL_D3CD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
 
#define SDHC_PROCTL_EMODE_MASK   (0x30U)
 
#define SDHC_PROCTL_EMODE_SHIFT   (4U)
 
#define SDHC_PROCTL_EMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
 
#define SDHC_PROCTL_CDTL_MASK   (0x40U)
 
#define SDHC_PROCTL_CDTL_SHIFT   (6U)
 
#define SDHC_PROCTL_CDTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
 
#define SDHC_PROCTL_CDSS_MASK   (0x80U)
 
#define SDHC_PROCTL_CDSS_SHIFT   (7U)
 
#define SDHC_PROCTL_CDSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
 
#define SDHC_PROCTL_DMAS_MASK   (0x300U)
 
#define SDHC_PROCTL_DMAS_SHIFT   (8U)
 
#define SDHC_PROCTL_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
 
#define SDHC_PROCTL_SABGREQ_MASK   (0x10000U)
 
#define SDHC_PROCTL_SABGREQ_SHIFT   (16U)
 
#define SDHC_PROCTL_SABGREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
 
#define SDHC_PROCTL_CREQ_MASK   (0x20000U)
 
#define SDHC_PROCTL_CREQ_SHIFT   (17U)
 
#define SDHC_PROCTL_CREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
 
#define SDHC_PROCTL_RWCTL_MASK   (0x40000U)
 
#define SDHC_PROCTL_RWCTL_SHIFT   (18U)
 
#define SDHC_PROCTL_RWCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
 
#define SDHC_PROCTL_IABG_MASK   (0x80000U)
 
#define SDHC_PROCTL_IABG_SHIFT   (19U)
 
#define SDHC_PROCTL_IABG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
 
#define SDHC_PROCTL_WECINT_MASK   (0x1000000U)
 
#define SDHC_PROCTL_WECINT_SHIFT   (24U)
 
#define SDHC_PROCTL_WECINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
 
#define SDHC_PROCTL_WECINS_MASK   (0x2000000U)
 
#define SDHC_PROCTL_WECINS_SHIFT   (25U)
 
#define SDHC_PROCTL_WECINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
 
#define SDHC_PROCTL_WECRM_MASK   (0x4000000U)
 
#define SDHC_PROCTL_WECRM_SHIFT   (26U)
 
#define SDHC_PROCTL_WECRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
 
#define SDHC_PROCTL_LCTL_MASK   (0x1U)
 
#define SDHC_PROCTL_LCTL_SHIFT   (0U)
 
#define SDHC_PROCTL_LCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
 
#define SDHC_PROCTL_DTW_MASK   (0x6U)
 
#define SDHC_PROCTL_DTW_SHIFT   (1U)
 
#define SDHC_PROCTL_DTW(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
 
#define SDHC_PROCTL_D3CD_MASK   (0x8U)
 
#define SDHC_PROCTL_D3CD_SHIFT   (3U)
 
#define SDHC_PROCTL_D3CD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
 
#define SDHC_PROCTL_EMODE_MASK   (0x30U)
 
#define SDHC_PROCTL_EMODE_SHIFT   (4U)
 
#define SDHC_PROCTL_EMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
 
#define SDHC_PROCTL_CDTL_MASK   (0x40U)
 
#define SDHC_PROCTL_CDTL_SHIFT   (6U)
 
#define SDHC_PROCTL_CDTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
 
#define SDHC_PROCTL_CDSS_MASK   (0x80U)
 
#define SDHC_PROCTL_CDSS_SHIFT   (7U)
 
#define SDHC_PROCTL_CDSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
 
#define SDHC_PROCTL_DMAS_MASK   (0x300U)
 
#define SDHC_PROCTL_DMAS_SHIFT   (8U)
 
#define SDHC_PROCTL_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
 
#define SDHC_PROCTL_SABGREQ_MASK   (0x10000U)
 
#define SDHC_PROCTL_SABGREQ_SHIFT   (16U)
 
#define SDHC_PROCTL_SABGREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
 
#define SDHC_PROCTL_CREQ_MASK   (0x20000U)
 
#define SDHC_PROCTL_CREQ_SHIFT   (17U)
 
#define SDHC_PROCTL_CREQ(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
 
#define SDHC_PROCTL_RWCTL_MASK   (0x40000U)
 
#define SDHC_PROCTL_RWCTL_SHIFT   (18U)
 
#define SDHC_PROCTL_RWCTL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
 
#define SDHC_PROCTL_IABG_MASK   (0x80000U)
 
#define SDHC_PROCTL_IABG_SHIFT   (19U)
 
#define SDHC_PROCTL_IABG(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
 
#define SDHC_PROCTL_WECINT_MASK   (0x1000000U)
 
#define SDHC_PROCTL_WECINT_SHIFT   (24U)
 
#define SDHC_PROCTL_WECINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
 
#define SDHC_PROCTL_WECINS_MASK   (0x2000000U)
 
#define SDHC_PROCTL_WECINS_SHIFT   (25U)
 
#define SDHC_PROCTL_WECINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
 
#define SDHC_PROCTL_WECRM_MASK   (0x4000000U)
 
#define SDHC_PROCTL_WECRM_SHIFT   (26U)
 
#define SDHC_PROCTL_WECRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
 

SYSCTL - System Control register

#define SDHC_SYSCTL_IPGEN_MASK   (0x1U)
 
#define SDHC_SYSCTL_IPGEN_SHIFT   (0U)
 
#define SDHC_SYSCTL_IPGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
 
#define SDHC_SYSCTL_HCKEN_MASK   (0x2U)
 
#define SDHC_SYSCTL_HCKEN_SHIFT   (1U)
 
#define SDHC_SYSCTL_HCKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
 
#define SDHC_SYSCTL_PEREN_MASK   (0x4U)
 
#define SDHC_SYSCTL_PEREN_SHIFT   (2U)
 
#define SDHC_SYSCTL_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
 
#define SDHC_SYSCTL_SDCLKEN_MASK   (0x8U)
 
#define SDHC_SYSCTL_SDCLKEN_SHIFT   (3U)
 
#define SDHC_SYSCTL_SDCLKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
 
#define SDHC_SYSCTL_DVS_MASK   (0xF0U)
 
#define SDHC_SYSCTL_DVS_SHIFT   (4U)
 
#define SDHC_SYSCTL_DVS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
 
#define SDHC_SYSCTL_SDCLKFS_MASK   (0xFF00U)
 
#define SDHC_SYSCTL_SDCLKFS_SHIFT   (8U)
 
#define SDHC_SYSCTL_SDCLKFS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
 
#define SDHC_SYSCTL_DTOCV_MASK   (0xF0000U)
 
#define SDHC_SYSCTL_DTOCV_SHIFT   (16U)
 
#define SDHC_SYSCTL_DTOCV(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
 
#define SDHC_SYSCTL_RSTA_MASK   (0x1000000U)
 
#define SDHC_SYSCTL_RSTA_SHIFT   (24U)
 
#define SDHC_SYSCTL_RSTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
 
#define SDHC_SYSCTL_RSTC_MASK   (0x2000000U)
 
#define SDHC_SYSCTL_RSTC_SHIFT   (25U)
 
#define SDHC_SYSCTL_RSTC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
 
#define SDHC_SYSCTL_RSTD_MASK   (0x4000000U)
 
#define SDHC_SYSCTL_RSTD_SHIFT   (26U)
 
#define SDHC_SYSCTL_RSTD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
 
#define SDHC_SYSCTL_INITA_MASK   (0x8000000U)
 
#define SDHC_SYSCTL_INITA_SHIFT   (27U)
 
#define SDHC_SYSCTL_INITA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
 
#define SDHC_SYSCTL_IPGEN_MASK   0x1u
 
#define SDHC_SYSCTL_IPGEN_SHIFT   0
 
#define SDHC_SYSCTL_HCKEN_MASK   0x2u
 
#define SDHC_SYSCTL_HCKEN_SHIFT   1
 
#define SDHC_SYSCTL_PEREN_MASK   0x4u
 
#define SDHC_SYSCTL_PEREN_SHIFT   2
 
#define SDHC_SYSCTL_SDCLKEN_MASK   0x8u
 
#define SDHC_SYSCTL_SDCLKEN_SHIFT   3
 
#define SDHC_SYSCTL_DVS_MASK   0xF0u
 
#define SDHC_SYSCTL_DVS_SHIFT   4
 
#define SDHC_SYSCTL_DVS(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
 
#define SDHC_SYSCTL_SDCLKFS_MASK   0xFF00u
 
#define SDHC_SYSCTL_SDCLKFS_SHIFT   8
 
#define SDHC_SYSCTL_SDCLKFS(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
 
#define SDHC_SYSCTL_DTOCV_MASK   0xF0000u
 
#define SDHC_SYSCTL_DTOCV_SHIFT   16
 
#define SDHC_SYSCTL_DTOCV(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
 
#define SDHC_SYSCTL_RSTA_MASK   0x1000000u
 
#define SDHC_SYSCTL_RSTA_SHIFT   24
 
#define SDHC_SYSCTL_RSTC_MASK   0x2000000u
 
#define SDHC_SYSCTL_RSTC_SHIFT   25
 
#define SDHC_SYSCTL_RSTD_MASK   0x4000000u
 
#define SDHC_SYSCTL_RSTD_SHIFT   26
 
#define SDHC_SYSCTL_INITA_MASK   0x8000000u
 
#define SDHC_SYSCTL_INITA_SHIFT   27
 
#define SDHC_SYSCTL_IPGEN_MASK   (0x1U)
 
#define SDHC_SYSCTL_IPGEN_SHIFT   (0U)
 
#define SDHC_SYSCTL_IPGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
 
#define SDHC_SYSCTL_HCKEN_MASK   (0x2U)
 
#define SDHC_SYSCTL_HCKEN_SHIFT   (1U)
 
#define SDHC_SYSCTL_HCKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
 
#define SDHC_SYSCTL_PEREN_MASK   (0x4U)
 
#define SDHC_SYSCTL_PEREN_SHIFT   (2U)
 
#define SDHC_SYSCTL_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
 
#define SDHC_SYSCTL_SDCLKEN_MASK   (0x8U)
 
#define SDHC_SYSCTL_SDCLKEN_SHIFT   (3U)
 
#define SDHC_SYSCTL_SDCLKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
 
#define SDHC_SYSCTL_DVS_MASK   (0xF0U)
 
#define SDHC_SYSCTL_DVS_SHIFT   (4U)
 
#define SDHC_SYSCTL_DVS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
 
#define SDHC_SYSCTL_SDCLKFS_MASK   (0xFF00U)
 
#define SDHC_SYSCTL_SDCLKFS_SHIFT   (8U)
 
#define SDHC_SYSCTL_SDCLKFS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
 
#define SDHC_SYSCTL_DTOCV_MASK   (0xF0000U)
 
#define SDHC_SYSCTL_DTOCV_SHIFT   (16U)
 
#define SDHC_SYSCTL_DTOCV(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
 
#define SDHC_SYSCTL_RSTA_MASK   (0x1000000U)
 
#define SDHC_SYSCTL_RSTA_SHIFT   (24U)
 
#define SDHC_SYSCTL_RSTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
 
#define SDHC_SYSCTL_RSTC_MASK   (0x2000000U)
 
#define SDHC_SYSCTL_RSTC_SHIFT   (25U)
 
#define SDHC_SYSCTL_RSTC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
 
#define SDHC_SYSCTL_RSTD_MASK   (0x4000000U)
 
#define SDHC_SYSCTL_RSTD_SHIFT   (26U)
 
#define SDHC_SYSCTL_RSTD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
 
#define SDHC_SYSCTL_INITA_MASK   (0x8000000U)
 
#define SDHC_SYSCTL_INITA_SHIFT   (27U)
 
#define SDHC_SYSCTL_INITA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
 
#define SDHC_SYSCTL_IPGEN_MASK   (0x1U)
 
#define SDHC_SYSCTL_IPGEN_SHIFT   (0U)
 
#define SDHC_SYSCTL_IPGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
 
#define SDHC_SYSCTL_HCKEN_MASK   (0x2U)
 
#define SDHC_SYSCTL_HCKEN_SHIFT   (1U)
 
#define SDHC_SYSCTL_HCKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
 
#define SDHC_SYSCTL_PEREN_MASK   (0x4U)
 
#define SDHC_SYSCTL_PEREN_SHIFT   (2U)
 
#define SDHC_SYSCTL_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
 
#define SDHC_SYSCTL_SDCLKEN_MASK   (0x8U)
 
#define SDHC_SYSCTL_SDCLKEN_SHIFT   (3U)
 
#define SDHC_SYSCTL_SDCLKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
 
#define SDHC_SYSCTL_DVS_MASK   (0xF0U)
 
#define SDHC_SYSCTL_DVS_SHIFT   (4U)
 
#define SDHC_SYSCTL_DVS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
 
#define SDHC_SYSCTL_SDCLKFS_MASK   (0xFF00U)
 
#define SDHC_SYSCTL_SDCLKFS_SHIFT   (8U)
 
#define SDHC_SYSCTL_SDCLKFS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
 
#define SDHC_SYSCTL_DTOCV_MASK   (0xF0000U)
 
#define SDHC_SYSCTL_DTOCV_SHIFT   (16U)
 
#define SDHC_SYSCTL_DTOCV(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
 
#define SDHC_SYSCTL_RSTA_MASK   (0x1000000U)
 
#define SDHC_SYSCTL_RSTA_SHIFT   (24U)
 
#define SDHC_SYSCTL_RSTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
 
#define SDHC_SYSCTL_RSTC_MASK   (0x2000000U)
 
#define SDHC_SYSCTL_RSTC_SHIFT   (25U)
 
#define SDHC_SYSCTL_RSTC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
 
#define SDHC_SYSCTL_RSTD_MASK   (0x4000000U)
 
#define SDHC_SYSCTL_RSTD_SHIFT   (26U)
 
#define SDHC_SYSCTL_RSTD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
 
#define SDHC_SYSCTL_INITA_MASK   (0x8000000U)
 
#define SDHC_SYSCTL_INITA_SHIFT   (27U)
 
#define SDHC_SYSCTL_INITA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
 
#define SDHC_SYSCTL_IPGEN_MASK   (0x1U)
 
#define SDHC_SYSCTL_IPGEN_SHIFT   (0U)
 
#define SDHC_SYSCTL_IPGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
 
#define SDHC_SYSCTL_HCKEN_MASK   (0x2U)
 
#define SDHC_SYSCTL_HCKEN_SHIFT   (1U)
 
#define SDHC_SYSCTL_HCKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
 
#define SDHC_SYSCTL_PEREN_MASK   (0x4U)
 
#define SDHC_SYSCTL_PEREN_SHIFT   (2U)
 
#define SDHC_SYSCTL_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
 
#define SDHC_SYSCTL_SDCLKEN_MASK   (0x8U)
 
#define SDHC_SYSCTL_SDCLKEN_SHIFT   (3U)
 
#define SDHC_SYSCTL_SDCLKEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
 
#define SDHC_SYSCTL_DVS_MASK   (0xF0U)
 
#define SDHC_SYSCTL_DVS_SHIFT   (4U)
 
#define SDHC_SYSCTL_DVS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
 
#define SDHC_SYSCTL_SDCLKFS_MASK   (0xFF00U)
 
#define SDHC_SYSCTL_SDCLKFS_SHIFT   (8U)
 
#define SDHC_SYSCTL_SDCLKFS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
 
#define SDHC_SYSCTL_DTOCV_MASK   (0xF0000U)
 
#define SDHC_SYSCTL_DTOCV_SHIFT   (16U)
 
#define SDHC_SYSCTL_DTOCV(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
 
#define SDHC_SYSCTL_RSTA_MASK   (0x1000000U)
 
#define SDHC_SYSCTL_RSTA_SHIFT   (24U)
 
#define SDHC_SYSCTL_RSTA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
 
#define SDHC_SYSCTL_RSTC_MASK   (0x2000000U)
 
#define SDHC_SYSCTL_RSTC_SHIFT   (25U)
 
#define SDHC_SYSCTL_RSTC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
 
#define SDHC_SYSCTL_RSTD_MASK   (0x4000000U)
 
#define SDHC_SYSCTL_RSTD_SHIFT   (26U)
 
#define SDHC_SYSCTL_RSTD(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
 
#define SDHC_SYSCTL_INITA_MASK   (0x8000000U)
 
#define SDHC_SYSCTL_INITA_SHIFT   (27U)
 
#define SDHC_SYSCTL_INITA(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
 

IRQSTAT - Interrupt Status register

#define SDHC_IRQSTAT_CC_MASK   (0x1U)
 
#define SDHC_IRQSTAT_CC_SHIFT   (0U)
 
#define SDHC_IRQSTAT_CC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
 
#define SDHC_IRQSTAT_TC_MASK   (0x2U)
 
#define SDHC_IRQSTAT_TC_SHIFT   (1U)
 
#define SDHC_IRQSTAT_TC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
 
#define SDHC_IRQSTAT_BGE_MASK   (0x4U)
 
#define SDHC_IRQSTAT_BGE_SHIFT   (2U)
 
#define SDHC_IRQSTAT_BGE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
 
#define SDHC_IRQSTAT_DINT_MASK   (0x8U)
 
#define SDHC_IRQSTAT_DINT_SHIFT   (3U)
 
#define SDHC_IRQSTAT_DINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
 
#define SDHC_IRQSTAT_BWR_MASK   (0x10U)
 
#define SDHC_IRQSTAT_BWR_SHIFT   (4U)
 
#define SDHC_IRQSTAT_BWR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
 
#define SDHC_IRQSTAT_BRR_MASK   (0x20U)
 
#define SDHC_IRQSTAT_BRR_SHIFT   (5U)
 
#define SDHC_IRQSTAT_BRR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
 
#define SDHC_IRQSTAT_CINS_MASK   (0x40U)
 
#define SDHC_IRQSTAT_CINS_SHIFT   (6U)
 
#define SDHC_IRQSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
 
#define SDHC_IRQSTAT_CRM_MASK   (0x80U)
 
#define SDHC_IRQSTAT_CRM_SHIFT   (7U)
 
#define SDHC_IRQSTAT_CRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
 
#define SDHC_IRQSTAT_CINT_MASK   (0x100U)
 
#define SDHC_IRQSTAT_CINT_SHIFT   (8U)
 
#define SDHC_IRQSTAT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
 
#define SDHC_IRQSTAT_CTOE_MASK   (0x10000U)
 
#define SDHC_IRQSTAT_CTOE_SHIFT   (16U)
 
#define SDHC_IRQSTAT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
 
#define SDHC_IRQSTAT_CCE_MASK   (0x20000U)
 
#define SDHC_IRQSTAT_CCE_SHIFT   (17U)
 
#define SDHC_IRQSTAT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
 
#define SDHC_IRQSTAT_CEBE_MASK   (0x40000U)
 
#define SDHC_IRQSTAT_CEBE_SHIFT   (18U)
 
#define SDHC_IRQSTAT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
 
#define SDHC_IRQSTAT_CIE_MASK   (0x80000U)
 
#define SDHC_IRQSTAT_CIE_SHIFT   (19U)
 
#define SDHC_IRQSTAT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
 
#define SDHC_IRQSTAT_DTOE_MASK   (0x100000U)
 
#define SDHC_IRQSTAT_DTOE_SHIFT   (20U)
 
#define SDHC_IRQSTAT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
 
#define SDHC_IRQSTAT_DCE_MASK   (0x200000U)
 
#define SDHC_IRQSTAT_DCE_SHIFT   (21U)
 
#define SDHC_IRQSTAT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
 
#define SDHC_IRQSTAT_DEBE_MASK   (0x400000U)
 
#define SDHC_IRQSTAT_DEBE_SHIFT   (22U)
 
#define SDHC_IRQSTAT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
 
#define SDHC_IRQSTAT_AC12E_MASK   (0x1000000U)
 
#define SDHC_IRQSTAT_AC12E_SHIFT   (24U)
 
#define SDHC_IRQSTAT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
 
#define SDHC_IRQSTAT_DMAE_MASK   (0x10000000U)
 
#define SDHC_IRQSTAT_DMAE_SHIFT   (28U)
 
#define SDHC_IRQSTAT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
 
#define SDHC_IRQSTAT_CC_MASK   0x1u
 
#define SDHC_IRQSTAT_CC_SHIFT   0
 
#define SDHC_IRQSTAT_TC_MASK   0x2u
 
#define SDHC_IRQSTAT_TC_SHIFT   1
 
#define SDHC_IRQSTAT_BGE_MASK   0x4u
 
#define SDHC_IRQSTAT_BGE_SHIFT   2
 
#define SDHC_IRQSTAT_DINT_MASK   0x8u
 
#define SDHC_IRQSTAT_DINT_SHIFT   3
 
#define SDHC_IRQSTAT_BWR_MASK   0x10u
 
#define SDHC_IRQSTAT_BWR_SHIFT   4
 
#define SDHC_IRQSTAT_BRR_MASK   0x20u
 
#define SDHC_IRQSTAT_BRR_SHIFT   5
 
#define SDHC_IRQSTAT_CINS_MASK   0x40u
 
#define SDHC_IRQSTAT_CINS_SHIFT   6
 
#define SDHC_IRQSTAT_CRM_MASK   0x80u
 
#define SDHC_IRQSTAT_CRM_SHIFT   7
 
#define SDHC_IRQSTAT_CINT_MASK   0x100u
 
#define SDHC_IRQSTAT_CINT_SHIFT   8
 
#define SDHC_IRQSTAT_CTOE_MASK   0x10000u
 
#define SDHC_IRQSTAT_CTOE_SHIFT   16
 
#define SDHC_IRQSTAT_CCE_MASK   0x20000u
 
#define SDHC_IRQSTAT_CCE_SHIFT   17
 
#define SDHC_IRQSTAT_CEBE_MASK   0x40000u
 
#define SDHC_IRQSTAT_CEBE_SHIFT   18
 
#define SDHC_IRQSTAT_CIE_MASK   0x80000u
 
#define SDHC_IRQSTAT_CIE_SHIFT   19
 
#define SDHC_IRQSTAT_DTOE_MASK   0x100000u
 
#define SDHC_IRQSTAT_DTOE_SHIFT   20
 
#define SDHC_IRQSTAT_DCE_MASK   0x200000u
 
#define SDHC_IRQSTAT_DCE_SHIFT   21
 
#define SDHC_IRQSTAT_DEBE_MASK   0x400000u
 
#define SDHC_IRQSTAT_DEBE_SHIFT   22
 
#define SDHC_IRQSTAT_AC12E_MASK   0x1000000u
 
#define SDHC_IRQSTAT_AC12E_SHIFT   24
 
#define SDHC_IRQSTAT_DMAE_MASK   0x10000000u
 
#define SDHC_IRQSTAT_DMAE_SHIFT   28
 
#define SDHC_IRQSTAT_CC_MASK   (0x1U)
 
#define SDHC_IRQSTAT_CC_SHIFT   (0U)
 
#define SDHC_IRQSTAT_CC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
 
#define SDHC_IRQSTAT_TC_MASK   (0x2U)
 
#define SDHC_IRQSTAT_TC_SHIFT   (1U)
 
#define SDHC_IRQSTAT_TC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
 
#define SDHC_IRQSTAT_BGE_MASK   (0x4U)
 
#define SDHC_IRQSTAT_BGE_SHIFT   (2U)
 
#define SDHC_IRQSTAT_BGE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
 
#define SDHC_IRQSTAT_DINT_MASK   (0x8U)
 
#define SDHC_IRQSTAT_DINT_SHIFT   (3U)
 
#define SDHC_IRQSTAT_DINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
 
#define SDHC_IRQSTAT_BWR_MASK   (0x10U)
 
#define SDHC_IRQSTAT_BWR_SHIFT   (4U)
 
#define SDHC_IRQSTAT_BWR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
 
#define SDHC_IRQSTAT_BRR_MASK   (0x20U)
 
#define SDHC_IRQSTAT_BRR_SHIFT   (5U)
 
#define SDHC_IRQSTAT_BRR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
 
#define SDHC_IRQSTAT_CINS_MASK   (0x40U)
 
#define SDHC_IRQSTAT_CINS_SHIFT   (6U)
 
#define SDHC_IRQSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
 
#define SDHC_IRQSTAT_CRM_MASK   (0x80U)
 
#define SDHC_IRQSTAT_CRM_SHIFT   (7U)
 
#define SDHC_IRQSTAT_CRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
 
#define SDHC_IRQSTAT_CINT_MASK   (0x100U)
 
#define SDHC_IRQSTAT_CINT_SHIFT   (8U)
 
#define SDHC_IRQSTAT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
 
#define SDHC_IRQSTAT_CTOE_MASK   (0x10000U)
 
#define SDHC_IRQSTAT_CTOE_SHIFT   (16U)
 
#define SDHC_IRQSTAT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
 
#define SDHC_IRQSTAT_CCE_MASK   (0x20000U)
 
#define SDHC_IRQSTAT_CCE_SHIFT   (17U)
 
#define SDHC_IRQSTAT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
 
#define SDHC_IRQSTAT_CEBE_MASK   (0x40000U)
 
#define SDHC_IRQSTAT_CEBE_SHIFT   (18U)
 
#define SDHC_IRQSTAT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
 
#define SDHC_IRQSTAT_CIE_MASK   (0x80000U)
 
#define SDHC_IRQSTAT_CIE_SHIFT   (19U)
 
#define SDHC_IRQSTAT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
 
#define SDHC_IRQSTAT_DTOE_MASK   (0x100000U)
 
#define SDHC_IRQSTAT_DTOE_SHIFT   (20U)
 
#define SDHC_IRQSTAT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
 
#define SDHC_IRQSTAT_DCE_MASK   (0x200000U)
 
#define SDHC_IRQSTAT_DCE_SHIFT   (21U)
 
#define SDHC_IRQSTAT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
 
#define SDHC_IRQSTAT_DEBE_MASK   (0x400000U)
 
#define SDHC_IRQSTAT_DEBE_SHIFT   (22U)
 
#define SDHC_IRQSTAT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
 
#define SDHC_IRQSTAT_AC12E_MASK   (0x1000000U)
 
#define SDHC_IRQSTAT_AC12E_SHIFT   (24U)
 
#define SDHC_IRQSTAT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
 
#define SDHC_IRQSTAT_DMAE_MASK   (0x10000000U)
 
#define SDHC_IRQSTAT_DMAE_SHIFT   (28U)
 
#define SDHC_IRQSTAT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
 
#define SDHC_IRQSTAT_CC_MASK   (0x1U)
 
#define SDHC_IRQSTAT_CC_SHIFT   (0U)
 
#define SDHC_IRQSTAT_CC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
 
#define SDHC_IRQSTAT_TC_MASK   (0x2U)
 
#define SDHC_IRQSTAT_TC_SHIFT   (1U)
 
#define SDHC_IRQSTAT_TC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
 
#define SDHC_IRQSTAT_BGE_MASK   (0x4U)
 
#define SDHC_IRQSTAT_BGE_SHIFT   (2U)
 
#define SDHC_IRQSTAT_BGE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
 
#define SDHC_IRQSTAT_DINT_MASK   (0x8U)
 
#define SDHC_IRQSTAT_DINT_SHIFT   (3U)
 
#define SDHC_IRQSTAT_DINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
 
#define SDHC_IRQSTAT_BWR_MASK   (0x10U)
 
#define SDHC_IRQSTAT_BWR_SHIFT   (4U)
 
#define SDHC_IRQSTAT_BWR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
 
#define SDHC_IRQSTAT_BRR_MASK   (0x20U)
 
#define SDHC_IRQSTAT_BRR_SHIFT   (5U)
 
#define SDHC_IRQSTAT_BRR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
 
#define SDHC_IRQSTAT_CINS_MASK   (0x40U)
 
#define SDHC_IRQSTAT_CINS_SHIFT   (6U)
 
#define SDHC_IRQSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
 
#define SDHC_IRQSTAT_CRM_MASK   (0x80U)
 
#define SDHC_IRQSTAT_CRM_SHIFT   (7U)
 
#define SDHC_IRQSTAT_CRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
 
#define SDHC_IRQSTAT_CINT_MASK   (0x100U)
 
#define SDHC_IRQSTAT_CINT_SHIFT   (8U)
 
#define SDHC_IRQSTAT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
 
#define SDHC_IRQSTAT_CTOE_MASK   (0x10000U)
 
#define SDHC_IRQSTAT_CTOE_SHIFT   (16U)
 
#define SDHC_IRQSTAT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
 
#define SDHC_IRQSTAT_CCE_MASK   (0x20000U)
 
#define SDHC_IRQSTAT_CCE_SHIFT   (17U)
 
#define SDHC_IRQSTAT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
 
#define SDHC_IRQSTAT_CEBE_MASK   (0x40000U)
 
#define SDHC_IRQSTAT_CEBE_SHIFT   (18U)
 
#define SDHC_IRQSTAT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
 
#define SDHC_IRQSTAT_CIE_MASK   (0x80000U)
 
#define SDHC_IRQSTAT_CIE_SHIFT   (19U)
 
#define SDHC_IRQSTAT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
 
#define SDHC_IRQSTAT_DTOE_MASK   (0x100000U)
 
#define SDHC_IRQSTAT_DTOE_SHIFT   (20U)
 
#define SDHC_IRQSTAT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
 
#define SDHC_IRQSTAT_DCE_MASK   (0x200000U)
 
#define SDHC_IRQSTAT_DCE_SHIFT   (21U)
 
#define SDHC_IRQSTAT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
 
#define SDHC_IRQSTAT_DEBE_MASK   (0x400000U)
 
#define SDHC_IRQSTAT_DEBE_SHIFT   (22U)
 
#define SDHC_IRQSTAT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
 
#define SDHC_IRQSTAT_AC12E_MASK   (0x1000000U)
 
#define SDHC_IRQSTAT_AC12E_SHIFT   (24U)
 
#define SDHC_IRQSTAT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
 
#define SDHC_IRQSTAT_DMAE_MASK   (0x10000000U)
 
#define SDHC_IRQSTAT_DMAE_SHIFT   (28U)
 
#define SDHC_IRQSTAT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
 
#define SDHC_IRQSTAT_CC_MASK   (0x1U)
 
#define SDHC_IRQSTAT_CC_SHIFT   (0U)
 
#define SDHC_IRQSTAT_CC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
 
#define SDHC_IRQSTAT_TC_MASK   (0x2U)
 
#define SDHC_IRQSTAT_TC_SHIFT   (1U)
 
#define SDHC_IRQSTAT_TC(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
 
#define SDHC_IRQSTAT_BGE_MASK   (0x4U)
 
#define SDHC_IRQSTAT_BGE_SHIFT   (2U)
 
#define SDHC_IRQSTAT_BGE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
 
#define SDHC_IRQSTAT_DINT_MASK   (0x8U)
 
#define SDHC_IRQSTAT_DINT_SHIFT   (3U)
 
#define SDHC_IRQSTAT_DINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
 
#define SDHC_IRQSTAT_BWR_MASK   (0x10U)
 
#define SDHC_IRQSTAT_BWR_SHIFT   (4U)
 
#define SDHC_IRQSTAT_BWR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
 
#define SDHC_IRQSTAT_BRR_MASK   (0x20U)
 
#define SDHC_IRQSTAT_BRR_SHIFT   (5U)
 
#define SDHC_IRQSTAT_BRR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
 
#define SDHC_IRQSTAT_CINS_MASK   (0x40U)
 
#define SDHC_IRQSTAT_CINS_SHIFT   (6U)
 
#define SDHC_IRQSTAT_CINS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
 
#define SDHC_IRQSTAT_CRM_MASK   (0x80U)
 
#define SDHC_IRQSTAT_CRM_SHIFT   (7U)
 
#define SDHC_IRQSTAT_CRM(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
 
#define SDHC_IRQSTAT_CINT_MASK   (0x100U)
 
#define SDHC_IRQSTAT_CINT_SHIFT   (8U)
 
#define SDHC_IRQSTAT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
 
#define SDHC_IRQSTAT_CTOE_MASK   (0x10000U)
 
#define SDHC_IRQSTAT_CTOE_SHIFT   (16U)
 
#define SDHC_IRQSTAT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
 
#define SDHC_IRQSTAT_CCE_MASK   (0x20000U)
 
#define SDHC_IRQSTAT_CCE_SHIFT   (17U)
 
#define SDHC_IRQSTAT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
 
#define SDHC_IRQSTAT_CEBE_MASK   (0x40000U)
 
#define SDHC_IRQSTAT_CEBE_SHIFT   (18U)
 
#define SDHC_IRQSTAT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
 
#define SDHC_IRQSTAT_CIE_MASK   (0x80000U)
 
#define SDHC_IRQSTAT_CIE_SHIFT   (19U)
 
#define SDHC_IRQSTAT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
 
#define SDHC_IRQSTAT_DTOE_MASK   (0x100000U)
 
#define SDHC_IRQSTAT_DTOE_SHIFT   (20U)
 
#define SDHC_IRQSTAT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
 
#define SDHC_IRQSTAT_DCE_MASK   (0x200000U)
 
#define SDHC_IRQSTAT_DCE_SHIFT   (21U)
 
#define SDHC_IRQSTAT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
 
#define SDHC_IRQSTAT_DEBE_MASK   (0x400000U)
 
#define SDHC_IRQSTAT_DEBE_SHIFT   (22U)
 
#define SDHC_IRQSTAT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
 
#define SDHC_IRQSTAT_AC12E_MASK   (0x1000000U)
 
#define SDHC_IRQSTAT_AC12E_SHIFT   (24U)
 
#define SDHC_IRQSTAT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
 
#define SDHC_IRQSTAT_DMAE_MASK   (0x10000000U)
 
#define SDHC_IRQSTAT_DMAE_SHIFT   (28U)
 
#define SDHC_IRQSTAT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
 

IRQSTATEN - Interrupt Status Enable register

#define SDHC_IRQSTATEN_CCSEN_MASK   (0x1U)
 
#define SDHC_IRQSTATEN_CCSEN_SHIFT   (0U)
 
#define SDHC_IRQSTATEN_CCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
 
#define SDHC_IRQSTATEN_TCSEN_MASK   (0x2U)
 
#define SDHC_IRQSTATEN_TCSEN_SHIFT   (1U)
 
#define SDHC_IRQSTATEN_TCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
 
#define SDHC_IRQSTATEN_BGESEN_MASK   (0x4U)
 
#define SDHC_IRQSTATEN_BGESEN_SHIFT   (2U)
 
#define SDHC_IRQSTATEN_BGESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
 
#define SDHC_IRQSTATEN_DINTSEN_MASK   (0x8U)
 
#define SDHC_IRQSTATEN_DINTSEN_SHIFT   (3U)
 
#define SDHC_IRQSTATEN_DINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
 
#define SDHC_IRQSTATEN_BWRSEN_MASK   (0x10U)
 
#define SDHC_IRQSTATEN_BWRSEN_SHIFT   (4U)
 
#define SDHC_IRQSTATEN_BWRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
 
#define SDHC_IRQSTATEN_BRRSEN_MASK   (0x20U)
 
#define SDHC_IRQSTATEN_BRRSEN_SHIFT   (5U)
 
#define SDHC_IRQSTATEN_BRRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
 
#define SDHC_IRQSTATEN_CINSEN_MASK   (0x40U)
 
#define SDHC_IRQSTATEN_CINSEN_SHIFT   (6U)
 
#define SDHC_IRQSTATEN_CINSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
 
#define SDHC_IRQSTATEN_CRMSEN_MASK   (0x80U)
 
#define SDHC_IRQSTATEN_CRMSEN_SHIFT   (7U)
 
#define SDHC_IRQSTATEN_CRMSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
 
#define SDHC_IRQSTATEN_CINTSEN_MASK   (0x100U)
 
#define SDHC_IRQSTATEN_CINTSEN_SHIFT   (8U)
 
#define SDHC_IRQSTATEN_CINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
 
#define SDHC_IRQSTATEN_CTOESEN_MASK   (0x10000U)
 
#define SDHC_IRQSTATEN_CTOESEN_SHIFT   (16U)
 
#define SDHC_IRQSTATEN_CTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
 
#define SDHC_IRQSTATEN_CCESEN_MASK   (0x20000U)
 
#define SDHC_IRQSTATEN_CCESEN_SHIFT   (17U)
 
#define SDHC_IRQSTATEN_CCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
 
#define SDHC_IRQSTATEN_CEBESEN_MASK   (0x40000U)
 
#define SDHC_IRQSTATEN_CEBESEN_SHIFT   (18U)
 
#define SDHC_IRQSTATEN_CEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
 
#define SDHC_IRQSTATEN_CIESEN_MASK   (0x80000U)
 
#define SDHC_IRQSTATEN_CIESEN_SHIFT   (19U)
 
#define SDHC_IRQSTATEN_CIESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
 
#define SDHC_IRQSTATEN_DTOESEN_MASK   (0x100000U)
 
#define SDHC_IRQSTATEN_DTOESEN_SHIFT   (20U)
 
#define SDHC_IRQSTATEN_DTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
 
#define SDHC_IRQSTATEN_DCESEN_MASK   (0x200000U)
 
#define SDHC_IRQSTATEN_DCESEN_SHIFT   (21U)
 
#define SDHC_IRQSTATEN_DCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
 
#define SDHC_IRQSTATEN_DEBESEN_MASK   (0x400000U)
 
#define SDHC_IRQSTATEN_DEBESEN_SHIFT   (22U)
 
#define SDHC_IRQSTATEN_DEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
 
#define SDHC_IRQSTATEN_AC12ESEN_MASK   (0x1000000U)
 
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT   (24U)
 
#define SDHC_IRQSTATEN_AC12ESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
 
#define SDHC_IRQSTATEN_DMAESEN_MASK   (0x10000000U)
 
#define SDHC_IRQSTATEN_DMAESEN_SHIFT   (28U)
 
#define SDHC_IRQSTATEN_DMAESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
 
#define SDHC_IRQSTATEN_CCSEN_MASK   0x1u
 
#define SDHC_IRQSTATEN_CCSEN_SHIFT   0
 
#define SDHC_IRQSTATEN_TCSEN_MASK   0x2u
 
#define SDHC_IRQSTATEN_TCSEN_SHIFT   1
 
#define SDHC_IRQSTATEN_BGESEN_MASK   0x4u
 
#define SDHC_IRQSTATEN_BGESEN_SHIFT   2
 
#define SDHC_IRQSTATEN_DINTSEN_MASK   0x8u
 
#define SDHC_IRQSTATEN_DINTSEN_SHIFT   3
 
#define SDHC_IRQSTATEN_BWRSEN_MASK   0x10u
 
#define SDHC_IRQSTATEN_BWRSEN_SHIFT   4
 
#define SDHC_IRQSTATEN_BRRSEN_MASK   0x20u
 
#define SDHC_IRQSTATEN_BRRSEN_SHIFT   5
 
#define SDHC_IRQSTATEN_CINSEN_MASK   0x40u
 
#define SDHC_IRQSTATEN_CINSEN_SHIFT   6
 
#define SDHC_IRQSTATEN_CRMSEN_MASK   0x80u
 
#define SDHC_IRQSTATEN_CRMSEN_SHIFT   7
 
#define SDHC_IRQSTATEN_CINTSEN_MASK   0x100u
 
#define SDHC_IRQSTATEN_CINTSEN_SHIFT   8
 
#define SDHC_IRQSTATEN_CTOESEN_MASK   0x10000u
 
#define SDHC_IRQSTATEN_CTOESEN_SHIFT   16
 
#define SDHC_IRQSTATEN_CCESEN_MASK   0x20000u
 
#define SDHC_IRQSTATEN_CCESEN_SHIFT   17
 
#define SDHC_IRQSTATEN_CEBESEN_MASK   0x40000u
 
#define SDHC_IRQSTATEN_CEBESEN_SHIFT   18
 
#define SDHC_IRQSTATEN_CIESEN_MASK   0x80000u
 
#define SDHC_IRQSTATEN_CIESEN_SHIFT   19
 
#define SDHC_IRQSTATEN_DTOESEN_MASK   0x100000u
 
#define SDHC_IRQSTATEN_DTOESEN_SHIFT   20
 
#define SDHC_IRQSTATEN_DCESEN_MASK   0x200000u
 
#define SDHC_IRQSTATEN_DCESEN_SHIFT   21
 
#define SDHC_IRQSTATEN_DEBESEN_MASK   0x400000u
 
#define SDHC_IRQSTATEN_DEBESEN_SHIFT   22
 
#define SDHC_IRQSTATEN_AC12ESEN_MASK   0x1000000u
 
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT   24
 
#define SDHC_IRQSTATEN_DMAESEN_MASK   0x10000000u
 
#define SDHC_IRQSTATEN_DMAESEN_SHIFT   28
 
#define SDHC_IRQSTATEN_CCSEN_MASK   (0x1U)
 
#define SDHC_IRQSTATEN_CCSEN_SHIFT   (0U)
 
#define SDHC_IRQSTATEN_CCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
 
#define SDHC_IRQSTATEN_TCSEN_MASK   (0x2U)
 
#define SDHC_IRQSTATEN_TCSEN_SHIFT   (1U)
 
#define SDHC_IRQSTATEN_TCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
 
#define SDHC_IRQSTATEN_BGESEN_MASK   (0x4U)
 
#define SDHC_IRQSTATEN_BGESEN_SHIFT   (2U)
 
#define SDHC_IRQSTATEN_BGESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
 
#define SDHC_IRQSTATEN_DINTSEN_MASK   (0x8U)
 
#define SDHC_IRQSTATEN_DINTSEN_SHIFT   (3U)
 
#define SDHC_IRQSTATEN_DINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
 
#define SDHC_IRQSTATEN_BWRSEN_MASK   (0x10U)
 
#define SDHC_IRQSTATEN_BWRSEN_SHIFT   (4U)
 
#define SDHC_IRQSTATEN_BWRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
 
#define SDHC_IRQSTATEN_BRRSEN_MASK   (0x20U)
 
#define SDHC_IRQSTATEN_BRRSEN_SHIFT   (5U)
 
#define SDHC_IRQSTATEN_BRRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
 
#define SDHC_IRQSTATEN_CINSEN_MASK   (0x40U)
 
#define SDHC_IRQSTATEN_CINSEN_SHIFT   (6U)
 
#define SDHC_IRQSTATEN_CINSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
 
#define SDHC_IRQSTATEN_CRMSEN_MASK   (0x80U)
 
#define SDHC_IRQSTATEN_CRMSEN_SHIFT   (7U)
 
#define SDHC_IRQSTATEN_CRMSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
 
#define SDHC_IRQSTATEN_CINTSEN_MASK   (0x100U)
 
#define SDHC_IRQSTATEN_CINTSEN_SHIFT   (8U)
 
#define SDHC_IRQSTATEN_CINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
 
#define SDHC_IRQSTATEN_CTOESEN_MASK   (0x10000U)
 
#define SDHC_IRQSTATEN_CTOESEN_SHIFT   (16U)
 
#define SDHC_IRQSTATEN_CTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
 
#define SDHC_IRQSTATEN_CCESEN_MASK   (0x20000U)
 
#define SDHC_IRQSTATEN_CCESEN_SHIFT   (17U)
 
#define SDHC_IRQSTATEN_CCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
 
#define SDHC_IRQSTATEN_CEBESEN_MASK   (0x40000U)
 
#define SDHC_IRQSTATEN_CEBESEN_SHIFT   (18U)
 
#define SDHC_IRQSTATEN_CEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
 
#define SDHC_IRQSTATEN_CIESEN_MASK   (0x80000U)
 
#define SDHC_IRQSTATEN_CIESEN_SHIFT   (19U)
 
#define SDHC_IRQSTATEN_CIESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
 
#define SDHC_IRQSTATEN_DTOESEN_MASK   (0x100000U)
 
#define SDHC_IRQSTATEN_DTOESEN_SHIFT   (20U)
 
#define SDHC_IRQSTATEN_DTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
 
#define SDHC_IRQSTATEN_DCESEN_MASK   (0x200000U)
 
#define SDHC_IRQSTATEN_DCESEN_SHIFT   (21U)
 
#define SDHC_IRQSTATEN_DCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
 
#define SDHC_IRQSTATEN_DEBESEN_MASK   (0x400000U)
 
#define SDHC_IRQSTATEN_DEBESEN_SHIFT   (22U)
 
#define SDHC_IRQSTATEN_DEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
 
#define SDHC_IRQSTATEN_AC12ESEN_MASK   (0x1000000U)
 
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT   (24U)
 
#define SDHC_IRQSTATEN_AC12ESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
 
#define SDHC_IRQSTATEN_DMAESEN_MASK   (0x10000000U)
 
#define SDHC_IRQSTATEN_DMAESEN_SHIFT   (28U)
 
#define SDHC_IRQSTATEN_DMAESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
 
#define SDHC_IRQSTATEN_CCSEN_MASK   (0x1U)
 
#define SDHC_IRQSTATEN_CCSEN_SHIFT   (0U)
 
#define SDHC_IRQSTATEN_CCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
 
#define SDHC_IRQSTATEN_TCSEN_MASK   (0x2U)
 
#define SDHC_IRQSTATEN_TCSEN_SHIFT   (1U)
 
#define SDHC_IRQSTATEN_TCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
 
#define SDHC_IRQSTATEN_BGESEN_MASK   (0x4U)
 
#define SDHC_IRQSTATEN_BGESEN_SHIFT   (2U)
 
#define SDHC_IRQSTATEN_BGESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
 
#define SDHC_IRQSTATEN_DINTSEN_MASK   (0x8U)
 
#define SDHC_IRQSTATEN_DINTSEN_SHIFT   (3U)
 
#define SDHC_IRQSTATEN_DINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
 
#define SDHC_IRQSTATEN_BWRSEN_MASK   (0x10U)
 
#define SDHC_IRQSTATEN_BWRSEN_SHIFT   (4U)
 
#define SDHC_IRQSTATEN_BWRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
 
#define SDHC_IRQSTATEN_BRRSEN_MASK   (0x20U)
 
#define SDHC_IRQSTATEN_BRRSEN_SHIFT   (5U)
 
#define SDHC_IRQSTATEN_BRRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
 
#define SDHC_IRQSTATEN_CINSEN_MASK   (0x40U)
 
#define SDHC_IRQSTATEN_CINSEN_SHIFT   (6U)
 
#define SDHC_IRQSTATEN_CINSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
 
#define SDHC_IRQSTATEN_CRMSEN_MASK   (0x80U)
 
#define SDHC_IRQSTATEN_CRMSEN_SHIFT   (7U)
 
#define SDHC_IRQSTATEN_CRMSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
 
#define SDHC_IRQSTATEN_CINTSEN_MASK   (0x100U)
 
#define SDHC_IRQSTATEN_CINTSEN_SHIFT   (8U)
 
#define SDHC_IRQSTATEN_CINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
 
#define SDHC_IRQSTATEN_CTOESEN_MASK   (0x10000U)
 
#define SDHC_IRQSTATEN_CTOESEN_SHIFT   (16U)
 
#define SDHC_IRQSTATEN_CTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
 
#define SDHC_IRQSTATEN_CCESEN_MASK   (0x20000U)
 
#define SDHC_IRQSTATEN_CCESEN_SHIFT   (17U)
 
#define SDHC_IRQSTATEN_CCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
 
#define SDHC_IRQSTATEN_CEBESEN_MASK   (0x40000U)
 
#define SDHC_IRQSTATEN_CEBESEN_SHIFT   (18U)
 
#define SDHC_IRQSTATEN_CEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
 
#define SDHC_IRQSTATEN_CIESEN_MASK   (0x80000U)
 
#define SDHC_IRQSTATEN_CIESEN_SHIFT   (19U)
 
#define SDHC_IRQSTATEN_CIESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
 
#define SDHC_IRQSTATEN_DTOESEN_MASK   (0x100000U)
 
#define SDHC_IRQSTATEN_DTOESEN_SHIFT   (20U)
 
#define SDHC_IRQSTATEN_DTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
 
#define SDHC_IRQSTATEN_DCESEN_MASK   (0x200000U)
 
#define SDHC_IRQSTATEN_DCESEN_SHIFT   (21U)
 
#define SDHC_IRQSTATEN_DCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
 
#define SDHC_IRQSTATEN_DEBESEN_MASK   (0x400000U)
 
#define SDHC_IRQSTATEN_DEBESEN_SHIFT   (22U)
 
#define SDHC_IRQSTATEN_DEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
 
#define SDHC_IRQSTATEN_AC12ESEN_MASK   (0x1000000U)
 
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT   (24U)
 
#define SDHC_IRQSTATEN_AC12ESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
 
#define SDHC_IRQSTATEN_DMAESEN_MASK   (0x10000000U)
 
#define SDHC_IRQSTATEN_DMAESEN_SHIFT   (28U)
 
#define SDHC_IRQSTATEN_DMAESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
 
#define SDHC_IRQSTATEN_CCSEN_MASK   (0x1U)
 
#define SDHC_IRQSTATEN_CCSEN_SHIFT   (0U)
 
#define SDHC_IRQSTATEN_CCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
 
#define SDHC_IRQSTATEN_TCSEN_MASK   (0x2U)
 
#define SDHC_IRQSTATEN_TCSEN_SHIFT   (1U)
 
#define SDHC_IRQSTATEN_TCSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
 
#define SDHC_IRQSTATEN_BGESEN_MASK   (0x4U)
 
#define SDHC_IRQSTATEN_BGESEN_SHIFT   (2U)
 
#define SDHC_IRQSTATEN_BGESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
 
#define SDHC_IRQSTATEN_DINTSEN_MASK   (0x8U)
 
#define SDHC_IRQSTATEN_DINTSEN_SHIFT   (3U)
 
#define SDHC_IRQSTATEN_DINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
 
#define SDHC_IRQSTATEN_BWRSEN_MASK   (0x10U)
 
#define SDHC_IRQSTATEN_BWRSEN_SHIFT   (4U)
 
#define SDHC_IRQSTATEN_BWRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
 
#define SDHC_IRQSTATEN_BRRSEN_MASK   (0x20U)
 
#define SDHC_IRQSTATEN_BRRSEN_SHIFT   (5U)
 
#define SDHC_IRQSTATEN_BRRSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
 
#define SDHC_IRQSTATEN_CINSEN_MASK   (0x40U)
 
#define SDHC_IRQSTATEN_CINSEN_SHIFT   (6U)
 
#define SDHC_IRQSTATEN_CINSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
 
#define SDHC_IRQSTATEN_CRMSEN_MASK   (0x80U)
 
#define SDHC_IRQSTATEN_CRMSEN_SHIFT   (7U)
 
#define SDHC_IRQSTATEN_CRMSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
 
#define SDHC_IRQSTATEN_CINTSEN_MASK   (0x100U)
 
#define SDHC_IRQSTATEN_CINTSEN_SHIFT   (8U)
 
#define SDHC_IRQSTATEN_CINTSEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
 
#define SDHC_IRQSTATEN_CTOESEN_MASK   (0x10000U)
 
#define SDHC_IRQSTATEN_CTOESEN_SHIFT   (16U)
 
#define SDHC_IRQSTATEN_CTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
 
#define SDHC_IRQSTATEN_CCESEN_MASK   (0x20000U)
 
#define SDHC_IRQSTATEN_CCESEN_SHIFT   (17U)
 
#define SDHC_IRQSTATEN_CCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
 
#define SDHC_IRQSTATEN_CEBESEN_MASK   (0x40000U)
 
#define SDHC_IRQSTATEN_CEBESEN_SHIFT   (18U)
 
#define SDHC_IRQSTATEN_CEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
 
#define SDHC_IRQSTATEN_CIESEN_MASK   (0x80000U)
 
#define SDHC_IRQSTATEN_CIESEN_SHIFT   (19U)
 
#define SDHC_IRQSTATEN_CIESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
 
#define SDHC_IRQSTATEN_DTOESEN_MASK   (0x100000U)
 
#define SDHC_IRQSTATEN_DTOESEN_SHIFT   (20U)
 
#define SDHC_IRQSTATEN_DTOESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
 
#define SDHC_IRQSTATEN_DCESEN_MASK   (0x200000U)
 
#define SDHC_IRQSTATEN_DCESEN_SHIFT   (21U)
 
#define SDHC_IRQSTATEN_DCESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
 
#define SDHC_IRQSTATEN_DEBESEN_MASK   (0x400000U)
 
#define SDHC_IRQSTATEN_DEBESEN_SHIFT   (22U)
 
#define SDHC_IRQSTATEN_DEBESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
 
#define SDHC_IRQSTATEN_AC12ESEN_MASK   (0x1000000U)
 
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT   (24U)
 
#define SDHC_IRQSTATEN_AC12ESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
 
#define SDHC_IRQSTATEN_DMAESEN_MASK   (0x10000000U)
 
#define SDHC_IRQSTATEN_DMAESEN_SHIFT   (28U)
 
#define SDHC_IRQSTATEN_DMAESEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
 

IRQSIGEN - Interrupt Signal Enable register

#define SDHC_IRQSIGEN_CCIEN_MASK   (0x1U)
 
#define SDHC_IRQSIGEN_CCIEN_SHIFT   (0U)
 
#define SDHC_IRQSIGEN_CCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
 
#define SDHC_IRQSIGEN_TCIEN_MASK   (0x2U)
 
#define SDHC_IRQSIGEN_TCIEN_SHIFT   (1U)
 
#define SDHC_IRQSIGEN_TCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
 
#define SDHC_IRQSIGEN_BGEIEN_MASK   (0x4U)
 
#define SDHC_IRQSIGEN_BGEIEN_SHIFT   (2U)
 
#define SDHC_IRQSIGEN_BGEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
 
#define SDHC_IRQSIGEN_DINTIEN_MASK   (0x8U)
 
#define SDHC_IRQSIGEN_DINTIEN_SHIFT   (3U)
 
#define SDHC_IRQSIGEN_DINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
 
#define SDHC_IRQSIGEN_BWRIEN_MASK   (0x10U)
 
#define SDHC_IRQSIGEN_BWRIEN_SHIFT   (4U)
 
#define SDHC_IRQSIGEN_BWRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
 
#define SDHC_IRQSIGEN_BRRIEN_MASK   (0x20U)
 
#define SDHC_IRQSIGEN_BRRIEN_SHIFT   (5U)
 
#define SDHC_IRQSIGEN_BRRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
 
#define SDHC_IRQSIGEN_CINSIEN_MASK   (0x40U)
 
#define SDHC_IRQSIGEN_CINSIEN_SHIFT   (6U)
 
#define SDHC_IRQSIGEN_CINSIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
 
#define SDHC_IRQSIGEN_CRMIEN_MASK   (0x80U)
 
#define SDHC_IRQSIGEN_CRMIEN_SHIFT   (7U)
 
#define SDHC_IRQSIGEN_CRMIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
 
#define SDHC_IRQSIGEN_CINTIEN_MASK   (0x100U)
 
#define SDHC_IRQSIGEN_CINTIEN_SHIFT   (8U)
 
#define SDHC_IRQSIGEN_CINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
 
#define SDHC_IRQSIGEN_CTOEIEN_MASK   (0x10000U)
 
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT   (16U)
 
#define SDHC_IRQSIGEN_CTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCEIEN_MASK   (0x20000U)
 
#define SDHC_IRQSIGEN_CCEIEN_SHIFT   (17U)
 
#define SDHC_IRQSIGEN_CCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
 
#define SDHC_IRQSIGEN_CEBEIEN_MASK   (0x40000U)
 
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT   (18U)
 
#define SDHC_IRQSIGEN_CEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_CIEIEN_MASK   (0x80000U)
 
#define SDHC_IRQSIGEN_CIEIEN_SHIFT   (19U)
 
#define SDHC_IRQSIGEN_CIEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
 
#define SDHC_IRQSIGEN_DTOEIEN_MASK   (0x100000U)
 
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT   (20U)
 
#define SDHC_IRQSIGEN_DTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_DCEIEN_MASK   (0x200000U)
 
#define SDHC_IRQSIGEN_DCEIEN_SHIFT   (21U)
 
#define SDHC_IRQSIGEN_DCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
 
#define SDHC_IRQSIGEN_DEBEIEN_MASK   (0x400000U)
 
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT   (22U)
 
#define SDHC_IRQSIGEN_DEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_AC12EIEN_MASK   (0x1000000U)
 
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT   (24U)
 
#define SDHC_IRQSIGEN_AC12EIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
 
#define SDHC_IRQSIGEN_DMAEIEN_MASK   (0x10000000U)
 
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT   (28U)
 
#define SDHC_IRQSIGEN_DMAEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCIEN_MASK   0x1u
 
#define SDHC_IRQSIGEN_CCIEN_SHIFT   0
 
#define SDHC_IRQSIGEN_TCIEN_MASK   0x2u
 
#define SDHC_IRQSIGEN_TCIEN_SHIFT   1
 
#define SDHC_IRQSIGEN_BGEIEN_MASK   0x4u
 
#define SDHC_IRQSIGEN_BGEIEN_SHIFT   2
 
#define SDHC_IRQSIGEN_DINTIEN_MASK   0x8u
 
#define SDHC_IRQSIGEN_DINTIEN_SHIFT   3
 
#define SDHC_IRQSIGEN_BWRIEN_MASK   0x10u
 
#define SDHC_IRQSIGEN_BWRIEN_SHIFT   4
 
#define SDHC_IRQSIGEN_BRRIEN_MASK   0x20u
 
#define SDHC_IRQSIGEN_BRRIEN_SHIFT   5
 
#define SDHC_IRQSIGEN_CINSIEN_MASK   0x40u
 
#define SDHC_IRQSIGEN_CINSIEN_SHIFT   6
 
#define SDHC_IRQSIGEN_CRMIEN_MASK   0x80u
 
#define SDHC_IRQSIGEN_CRMIEN_SHIFT   7
 
#define SDHC_IRQSIGEN_CINTIEN_MASK   0x100u
 
#define SDHC_IRQSIGEN_CINTIEN_SHIFT   8
 
#define SDHC_IRQSIGEN_CTOEIEN_MASK   0x10000u
 
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT   16
 
#define SDHC_IRQSIGEN_CCEIEN_MASK   0x20000u
 
#define SDHC_IRQSIGEN_CCEIEN_SHIFT   17
 
#define SDHC_IRQSIGEN_CEBEIEN_MASK   0x40000u
 
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT   18
 
#define SDHC_IRQSIGEN_CIEIEN_MASK   0x80000u
 
#define SDHC_IRQSIGEN_CIEIEN_SHIFT   19
 
#define SDHC_IRQSIGEN_DTOEIEN_MASK   0x100000u
 
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT   20
 
#define SDHC_IRQSIGEN_DCEIEN_MASK   0x200000u
 
#define SDHC_IRQSIGEN_DCEIEN_SHIFT   21
 
#define SDHC_IRQSIGEN_DEBEIEN_MASK   0x400000u
 
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT   22
 
#define SDHC_IRQSIGEN_AC12EIEN_MASK   0x1000000u
 
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT   24
 
#define SDHC_IRQSIGEN_DMAEIEN_MASK   0x10000000u
 
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT   28
 
#define SDHC_IRQSIGEN_CCIEN_MASK   (0x1U)
 
#define SDHC_IRQSIGEN_CCIEN_SHIFT   (0U)
 
#define SDHC_IRQSIGEN_CCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
 
#define SDHC_IRQSIGEN_TCIEN_MASK   (0x2U)
 
#define SDHC_IRQSIGEN_TCIEN_SHIFT   (1U)
 
#define SDHC_IRQSIGEN_TCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
 
#define SDHC_IRQSIGEN_BGEIEN_MASK   (0x4U)
 
#define SDHC_IRQSIGEN_BGEIEN_SHIFT   (2U)
 
#define SDHC_IRQSIGEN_BGEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
 
#define SDHC_IRQSIGEN_DINTIEN_MASK   (0x8U)
 
#define SDHC_IRQSIGEN_DINTIEN_SHIFT   (3U)
 
#define SDHC_IRQSIGEN_DINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
 
#define SDHC_IRQSIGEN_BWRIEN_MASK   (0x10U)
 
#define SDHC_IRQSIGEN_BWRIEN_SHIFT   (4U)
 
#define SDHC_IRQSIGEN_BWRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
 
#define SDHC_IRQSIGEN_BRRIEN_MASK   (0x20U)
 
#define SDHC_IRQSIGEN_BRRIEN_SHIFT   (5U)
 
#define SDHC_IRQSIGEN_BRRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
 
#define SDHC_IRQSIGEN_CINSIEN_MASK   (0x40U)
 
#define SDHC_IRQSIGEN_CINSIEN_SHIFT   (6U)
 
#define SDHC_IRQSIGEN_CINSIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
 
#define SDHC_IRQSIGEN_CRMIEN_MASK   (0x80U)
 
#define SDHC_IRQSIGEN_CRMIEN_SHIFT   (7U)
 
#define SDHC_IRQSIGEN_CRMIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
 
#define SDHC_IRQSIGEN_CINTIEN_MASK   (0x100U)
 
#define SDHC_IRQSIGEN_CINTIEN_SHIFT   (8U)
 
#define SDHC_IRQSIGEN_CINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
 
#define SDHC_IRQSIGEN_CTOEIEN_MASK   (0x10000U)
 
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT   (16U)
 
#define SDHC_IRQSIGEN_CTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCEIEN_MASK   (0x20000U)
 
#define SDHC_IRQSIGEN_CCEIEN_SHIFT   (17U)
 
#define SDHC_IRQSIGEN_CCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
 
#define SDHC_IRQSIGEN_CEBEIEN_MASK   (0x40000U)
 
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT   (18U)
 
#define SDHC_IRQSIGEN_CEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_CIEIEN_MASK   (0x80000U)
 
#define SDHC_IRQSIGEN_CIEIEN_SHIFT   (19U)
 
#define SDHC_IRQSIGEN_CIEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
 
#define SDHC_IRQSIGEN_DTOEIEN_MASK   (0x100000U)
 
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT   (20U)
 
#define SDHC_IRQSIGEN_DTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_DCEIEN_MASK   (0x200000U)
 
#define SDHC_IRQSIGEN_DCEIEN_SHIFT   (21U)
 
#define SDHC_IRQSIGEN_DCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
 
#define SDHC_IRQSIGEN_DEBEIEN_MASK   (0x400000U)
 
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT   (22U)
 
#define SDHC_IRQSIGEN_DEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_AC12EIEN_MASK   (0x1000000U)
 
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT   (24U)
 
#define SDHC_IRQSIGEN_AC12EIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
 
#define SDHC_IRQSIGEN_DMAEIEN_MASK   (0x10000000U)
 
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT   (28U)
 
#define SDHC_IRQSIGEN_DMAEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCIEN_MASK   (0x1U)
 
#define SDHC_IRQSIGEN_CCIEN_SHIFT   (0U)
 
#define SDHC_IRQSIGEN_CCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
 
#define SDHC_IRQSIGEN_TCIEN_MASK   (0x2U)
 
#define SDHC_IRQSIGEN_TCIEN_SHIFT   (1U)
 
#define SDHC_IRQSIGEN_TCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
 
#define SDHC_IRQSIGEN_BGEIEN_MASK   (0x4U)
 
#define SDHC_IRQSIGEN_BGEIEN_SHIFT   (2U)
 
#define SDHC_IRQSIGEN_BGEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
 
#define SDHC_IRQSIGEN_DINTIEN_MASK   (0x8U)
 
#define SDHC_IRQSIGEN_DINTIEN_SHIFT   (3U)
 
#define SDHC_IRQSIGEN_DINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
 
#define SDHC_IRQSIGEN_BWRIEN_MASK   (0x10U)
 
#define SDHC_IRQSIGEN_BWRIEN_SHIFT   (4U)
 
#define SDHC_IRQSIGEN_BWRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
 
#define SDHC_IRQSIGEN_BRRIEN_MASK   (0x20U)
 
#define SDHC_IRQSIGEN_BRRIEN_SHIFT   (5U)
 
#define SDHC_IRQSIGEN_BRRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
 
#define SDHC_IRQSIGEN_CINSIEN_MASK   (0x40U)
 
#define SDHC_IRQSIGEN_CINSIEN_SHIFT   (6U)
 
#define SDHC_IRQSIGEN_CINSIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
 
#define SDHC_IRQSIGEN_CRMIEN_MASK   (0x80U)
 
#define SDHC_IRQSIGEN_CRMIEN_SHIFT   (7U)
 
#define SDHC_IRQSIGEN_CRMIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
 
#define SDHC_IRQSIGEN_CINTIEN_MASK   (0x100U)
 
#define SDHC_IRQSIGEN_CINTIEN_SHIFT   (8U)
 
#define SDHC_IRQSIGEN_CINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
 
#define SDHC_IRQSIGEN_CTOEIEN_MASK   (0x10000U)
 
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT   (16U)
 
#define SDHC_IRQSIGEN_CTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCEIEN_MASK   (0x20000U)
 
#define SDHC_IRQSIGEN_CCEIEN_SHIFT   (17U)
 
#define SDHC_IRQSIGEN_CCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
 
#define SDHC_IRQSIGEN_CEBEIEN_MASK   (0x40000U)
 
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT   (18U)
 
#define SDHC_IRQSIGEN_CEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_CIEIEN_MASK   (0x80000U)
 
#define SDHC_IRQSIGEN_CIEIEN_SHIFT   (19U)
 
#define SDHC_IRQSIGEN_CIEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
 
#define SDHC_IRQSIGEN_DTOEIEN_MASK   (0x100000U)
 
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT   (20U)
 
#define SDHC_IRQSIGEN_DTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_DCEIEN_MASK   (0x200000U)
 
#define SDHC_IRQSIGEN_DCEIEN_SHIFT   (21U)
 
#define SDHC_IRQSIGEN_DCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
 
#define SDHC_IRQSIGEN_DEBEIEN_MASK   (0x400000U)
 
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT   (22U)
 
#define SDHC_IRQSIGEN_DEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_AC12EIEN_MASK   (0x1000000U)
 
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT   (24U)
 
#define SDHC_IRQSIGEN_AC12EIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
 
#define SDHC_IRQSIGEN_DMAEIEN_MASK   (0x10000000U)
 
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT   (28U)
 
#define SDHC_IRQSIGEN_DMAEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCIEN_MASK   (0x1U)
 
#define SDHC_IRQSIGEN_CCIEN_SHIFT   (0U)
 
#define SDHC_IRQSIGEN_CCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
 
#define SDHC_IRQSIGEN_TCIEN_MASK   (0x2U)
 
#define SDHC_IRQSIGEN_TCIEN_SHIFT   (1U)
 
#define SDHC_IRQSIGEN_TCIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
 
#define SDHC_IRQSIGEN_BGEIEN_MASK   (0x4U)
 
#define SDHC_IRQSIGEN_BGEIEN_SHIFT   (2U)
 
#define SDHC_IRQSIGEN_BGEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
 
#define SDHC_IRQSIGEN_DINTIEN_MASK   (0x8U)
 
#define SDHC_IRQSIGEN_DINTIEN_SHIFT   (3U)
 
#define SDHC_IRQSIGEN_DINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
 
#define SDHC_IRQSIGEN_BWRIEN_MASK   (0x10U)
 
#define SDHC_IRQSIGEN_BWRIEN_SHIFT   (4U)
 
#define SDHC_IRQSIGEN_BWRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
 
#define SDHC_IRQSIGEN_BRRIEN_MASK   (0x20U)
 
#define SDHC_IRQSIGEN_BRRIEN_SHIFT   (5U)
 
#define SDHC_IRQSIGEN_BRRIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
 
#define SDHC_IRQSIGEN_CINSIEN_MASK   (0x40U)
 
#define SDHC_IRQSIGEN_CINSIEN_SHIFT   (6U)
 
#define SDHC_IRQSIGEN_CINSIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
 
#define SDHC_IRQSIGEN_CRMIEN_MASK   (0x80U)
 
#define SDHC_IRQSIGEN_CRMIEN_SHIFT   (7U)
 
#define SDHC_IRQSIGEN_CRMIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
 
#define SDHC_IRQSIGEN_CINTIEN_MASK   (0x100U)
 
#define SDHC_IRQSIGEN_CINTIEN_SHIFT   (8U)
 
#define SDHC_IRQSIGEN_CINTIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
 
#define SDHC_IRQSIGEN_CTOEIEN_MASK   (0x10000U)
 
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT   (16U)
 
#define SDHC_IRQSIGEN_CTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_CCEIEN_MASK   (0x20000U)
 
#define SDHC_IRQSIGEN_CCEIEN_SHIFT   (17U)
 
#define SDHC_IRQSIGEN_CCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
 
#define SDHC_IRQSIGEN_CEBEIEN_MASK   (0x40000U)
 
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT   (18U)
 
#define SDHC_IRQSIGEN_CEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_CIEIEN_MASK   (0x80000U)
 
#define SDHC_IRQSIGEN_CIEIEN_SHIFT   (19U)
 
#define SDHC_IRQSIGEN_CIEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
 
#define SDHC_IRQSIGEN_DTOEIEN_MASK   (0x100000U)
 
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT   (20U)
 
#define SDHC_IRQSIGEN_DTOEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
 
#define SDHC_IRQSIGEN_DCEIEN_MASK   (0x200000U)
 
#define SDHC_IRQSIGEN_DCEIEN_SHIFT   (21U)
 
#define SDHC_IRQSIGEN_DCEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
 
#define SDHC_IRQSIGEN_DEBEIEN_MASK   (0x400000U)
 
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT   (22U)
 
#define SDHC_IRQSIGEN_DEBEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
 
#define SDHC_IRQSIGEN_AC12EIEN_MASK   (0x1000000U)
 
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT   (24U)
 
#define SDHC_IRQSIGEN_AC12EIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
 
#define SDHC_IRQSIGEN_DMAEIEN_MASK   (0x10000000U)
 
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT   (28U)
 
#define SDHC_IRQSIGEN_DMAEIEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
 

AC12ERR - Auto CMD12 Error Status Register

#define SDHC_AC12ERR_AC12NE_MASK   (0x1U)
 
#define SDHC_AC12ERR_AC12NE_SHIFT   (0U)
 
#define SDHC_AC12ERR_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
 
#define SDHC_AC12ERR_AC12TOE_MASK   (0x2U)
 
#define SDHC_AC12ERR_AC12TOE_SHIFT   (1U)
 
#define SDHC_AC12ERR_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
 
#define SDHC_AC12ERR_AC12EBE_MASK   (0x4U)
 
#define SDHC_AC12ERR_AC12EBE_SHIFT   (2U)
 
#define SDHC_AC12ERR_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
 
#define SDHC_AC12ERR_AC12CE_MASK   (0x8U)
 
#define SDHC_AC12ERR_AC12CE_SHIFT   (3U)
 
#define SDHC_AC12ERR_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
 
#define SDHC_AC12ERR_AC12IE_MASK   (0x10U)
 
#define SDHC_AC12ERR_AC12IE_SHIFT   (4U)
 
#define SDHC_AC12ERR_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
 
#define SDHC_AC12ERR_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_AC12ERR_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_AC12ERR_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
 
#define SDHC_AC12ERR_AC12NE_MASK   0x1u
 
#define SDHC_AC12ERR_AC12NE_SHIFT   0
 
#define SDHC_AC12ERR_AC12TOE_MASK   0x2u
 
#define SDHC_AC12ERR_AC12TOE_SHIFT   1
 
#define SDHC_AC12ERR_AC12EBE_MASK   0x4u
 
#define SDHC_AC12ERR_AC12EBE_SHIFT   2
 
#define SDHC_AC12ERR_AC12CE_MASK   0x8u
 
#define SDHC_AC12ERR_AC12CE_SHIFT   3
 
#define SDHC_AC12ERR_AC12IE_MASK   0x10u
 
#define SDHC_AC12ERR_AC12IE_SHIFT   4
 
#define SDHC_AC12ERR_CNIBAC12E_MASK   0x80u
 
#define SDHC_AC12ERR_CNIBAC12E_SHIFT   7
 
#define SDHC_AC12ERR_AC12NE_MASK   (0x1U)
 
#define SDHC_AC12ERR_AC12NE_SHIFT   (0U)
 
#define SDHC_AC12ERR_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
 
#define SDHC_AC12ERR_AC12TOE_MASK   (0x2U)
 
#define SDHC_AC12ERR_AC12TOE_SHIFT   (1U)
 
#define SDHC_AC12ERR_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
 
#define SDHC_AC12ERR_AC12EBE_MASK   (0x4U)
 
#define SDHC_AC12ERR_AC12EBE_SHIFT   (2U)
 
#define SDHC_AC12ERR_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
 
#define SDHC_AC12ERR_AC12CE_MASK   (0x8U)
 
#define SDHC_AC12ERR_AC12CE_SHIFT   (3U)
 
#define SDHC_AC12ERR_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
 
#define SDHC_AC12ERR_AC12IE_MASK   (0x10U)
 
#define SDHC_AC12ERR_AC12IE_SHIFT   (4U)
 
#define SDHC_AC12ERR_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
 
#define SDHC_AC12ERR_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_AC12ERR_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_AC12ERR_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
 
#define SDHC_AC12ERR_AC12NE_MASK   (0x1U)
 
#define SDHC_AC12ERR_AC12NE_SHIFT   (0U)
 
#define SDHC_AC12ERR_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
 
#define SDHC_AC12ERR_AC12TOE_MASK   (0x2U)
 
#define SDHC_AC12ERR_AC12TOE_SHIFT   (1U)
 
#define SDHC_AC12ERR_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
 
#define SDHC_AC12ERR_AC12EBE_MASK   (0x4U)
 
#define SDHC_AC12ERR_AC12EBE_SHIFT   (2U)
 
#define SDHC_AC12ERR_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
 
#define SDHC_AC12ERR_AC12CE_MASK   (0x8U)
 
#define SDHC_AC12ERR_AC12CE_SHIFT   (3U)
 
#define SDHC_AC12ERR_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
 
#define SDHC_AC12ERR_AC12IE_MASK   (0x10U)
 
#define SDHC_AC12ERR_AC12IE_SHIFT   (4U)
 
#define SDHC_AC12ERR_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
 
#define SDHC_AC12ERR_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_AC12ERR_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_AC12ERR_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
 
#define SDHC_AC12ERR_AC12NE_MASK   (0x1U)
 
#define SDHC_AC12ERR_AC12NE_SHIFT   (0U)
 
#define SDHC_AC12ERR_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
 
#define SDHC_AC12ERR_AC12TOE_MASK   (0x2U)
 
#define SDHC_AC12ERR_AC12TOE_SHIFT   (1U)
 
#define SDHC_AC12ERR_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
 
#define SDHC_AC12ERR_AC12EBE_MASK   (0x4U)
 
#define SDHC_AC12ERR_AC12EBE_SHIFT   (2U)
 
#define SDHC_AC12ERR_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
 
#define SDHC_AC12ERR_AC12CE_MASK   (0x8U)
 
#define SDHC_AC12ERR_AC12CE_SHIFT   (3U)
 
#define SDHC_AC12ERR_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
 
#define SDHC_AC12ERR_AC12IE_MASK   (0x10U)
 
#define SDHC_AC12ERR_AC12IE_SHIFT   (4U)
 
#define SDHC_AC12ERR_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
 
#define SDHC_AC12ERR_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_AC12ERR_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_AC12ERR_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
 

HTCAPBLT - Host Controller Capabilities

#define SDHC_HTCAPBLT_MBL_MASK   (0x70000U)
 
#define SDHC_HTCAPBLT_MBL_SHIFT   (16U)
 
#define SDHC_HTCAPBLT_MBL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
 
#define SDHC_HTCAPBLT_ADMAS_MASK   (0x100000U)
 
#define SDHC_HTCAPBLT_ADMAS_SHIFT   (20U)
 
#define SDHC_HTCAPBLT_ADMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
 
#define SDHC_HTCAPBLT_HSS_MASK   (0x200000U)
 
#define SDHC_HTCAPBLT_HSS_SHIFT   (21U)
 
#define SDHC_HTCAPBLT_HSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
 
#define SDHC_HTCAPBLT_DMAS_MASK   (0x400000U)
 
#define SDHC_HTCAPBLT_DMAS_SHIFT   (22U)
 
#define SDHC_HTCAPBLT_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
 
#define SDHC_HTCAPBLT_SRS_MASK   (0x800000U)
 
#define SDHC_HTCAPBLT_SRS_SHIFT   (23U)
 
#define SDHC_HTCAPBLT_SRS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
 
#define SDHC_HTCAPBLT_VS33_MASK   (0x1000000U)
 
#define SDHC_HTCAPBLT_VS33_SHIFT   (24U)
 
#define SDHC_HTCAPBLT_VS33(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
 
#define SDHC_HTCAPBLT_MBL_MASK   0x70000u
 
#define SDHC_HTCAPBLT_MBL_SHIFT   16
 
#define SDHC_HTCAPBLT_MBL(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
 
#define SDHC_HTCAPBLT_ADMAS_MASK   0x100000u
 
#define SDHC_HTCAPBLT_ADMAS_SHIFT   20
 
#define SDHC_HTCAPBLT_HSS_MASK   0x200000u
 
#define SDHC_HTCAPBLT_HSS_SHIFT   21
 
#define SDHC_HTCAPBLT_DMAS_MASK   0x400000u
 
#define SDHC_HTCAPBLT_DMAS_SHIFT   22
 
#define SDHC_HTCAPBLT_SRS_MASK   0x800000u
 
#define SDHC_HTCAPBLT_SRS_SHIFT   23
 
#define SDHC_HTCAPBLT_VS33_MASK   0x1000000u
 
#define SDHC_HTCAPBLT_VS33_SHIFT   24
 
#define SDHC_HTCAPBLT_MBL_MASK   (0x70000U)
 
#define SDHC_HTCAPBLT_MBL_SHIFT   (16U)
 
#define SDHC_HTCAPBLT_MBL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
 
#define SDHC_HTCAPBLT_ADMAS_MASK   (0x100000U)
 
#define SDHC_HTCAPBLT_ADMAS_SHIFT   (20U)
 
#define SDHC_HTCAPBLT_ADMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
 
#define SDHC_HTCAPBLT_HSS_MASK   (0x200000U)
 
#define SDHC_HTCAPBLT_HSS_SHIFT   (21U)
 
#define SDHC_HTCAPBLT_HSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
 
#define SDHC_HTCAPBLT_DMAS_MASK   (0x400000U)
 
#define SDHC_HTCAPBLT_DMAS_SHIFT   (22U)
 
#define SDHC_HTCAPBLT_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
 
#define SDHC_HTCAPBLT_SRS_MASK   (0x800000U)
 
#define SDHC_HTCAPBLT_SRS_SHIFT   (23U)
 
#define SDHC_HTCAPBLT_SRS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
 
#define SDHC_HTCAPBLT_VS33_MASK   (0x1000000U)
 
#define SDHC_HTCAPBLT_VS33_SHIFT   (24U)
 
#define SDHC_HTCAPBLT_VS33(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
 
#define SDHC_HTCAPBLT_MBL_MASK   (0x70000U)
 
#define SDHC_HTCAPBLT_MBL_SHIFT   (16U)
 
#define SDHC_HTCAPBLT_MBL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
 
#define SDHC_HTCAPBLT_ADMAS_MASK   (0x100000U)
 
#define SDHC_HTCAPBLT_ADMAS_SHIFT   (20U)
 
#define SDHC_HTCAPBLT_ADMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
 
#define SDHC_HTCAPBLT_HSS_MASK   (0x200000U)
 
#define SDHC_HTCAPBLT_HSS_SHIFT   (21U)
 
#define SDHC_HTCAPBLT_HSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
 
#define SDHC_HTCAPBLT_DMAS_MASK   (0x400000U)
 
#define SDHC_HTCAPBLT_DMAS_SHIFT   (22U)
 
#define SDHC_HTCAPBLT_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
 
#define SDHC_HTCAPBLT_SRS_MASK   (0x800000U)
 
#define SDHC_HTCAPBLT_SRS_SHIFT   (23U)
 
#define SDHC_HTCAPBLT_SRS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
 
#define SDHC_HTCAPBLT_VS33_MASK   (0x1000000U)
 
#define SDHC_HTCAPBLT_VS33_SHIFT   (24U)
 
#define SDHC_HTCAPBLT_VS33(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
 
#define SDHC_HTCAPBLT_MBL_MASK   (0x70000U)
 
#define SDHC_HTCAPBLT_MBL_SHIFT   (16U)
 
#define SDHC_HTCAPBLT_MBL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
 
#define SDHC_HTCAPBLT_ADMAS_MASK   (0x100000U)
 
#define SDHC_HTCAPBLT_ADMAS_SHIFT   (20U)
 
#define SDHC_HTCAPBLT_ADMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
 
#define SDHC_HTCAPBLT_HSS_MASK   (0x200000U)
 
#define SDHC_HTCAPBLT_HSS_SHIFT   (21U)
 
#define SDHC_HTCAPBLT_HSS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
 
#define SDHC_HTCAPBLT_DMAS_MASK   (0x400000U)
 
#define SDHC_HTCAPBLT_DMAS_SHIFT   (22U)
 
#define SDHC_HTCAPBLT_DMAS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
 
#define SDHC_HTCAPBLT_SRS_MASK   (0x800000U)
 
#define SDHC_HTCAPBLT_SRS_SHIFT   (23U)
 
#define SDHC_HTCAPBLT_SRS(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
 
#define SDHC_HTCAPBLT_VS33_MASK   (0x1000000U)
 
#define SDHC_HTCAPBLT_VS33_SHIFT   (24U)
 
#define SDHC_HTCAPBLT_VS33(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
 

HTCAPBLT - Host Controller Capabilities

#define SDHC_HTCAPBLT_VS30_MASK   (0x2000000U)
 
#define SDHC_HTCAPBLT_VS30_SHIFT   (25U)
 
#define SDHC_HTCAPBLT_VS30(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS30_SHIFT)) & SDHC_HTCAPBLT_VS30_MASK)
 
#define SDHC_HTCAPBLT_VS18_MASK   (0x4000000U)
 
#define SDHC_HTCAPBLT_VS18_SHIFT   (26U)
 
#define SDHC_HTCAPBLT_VS18(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS18_SHIFT)) & SDHC_HTCAPBLT_VS18_MASK)
 

WML - Watermark Level Register

#define SDHC_WML_RDWML_MASK   (0xFFU)
 
#define SDHC_WML_RDWML_SHIFT   (0U)
 
#define SDHC_WML_RDWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
 
#define SDHC_WML_WRWML_MASK   (0xFF0000U)
 
#define SDHC_WML_WRWML_SHIFT   (16U)
 
#define SDHC_WML_WRWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
 
#define SDHC_WML_RDWML_MASK   0xFFu
 
#define SDHC_WML_RDWML_SHIFT   0
 
#define SDHC_WML_RDWML(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
 
#define SDHC_WML_WRWML_MASK   0xFF0000u
 
#define SDHC_WML_WRWML_SHIFT   16
 
#define SDHC_WML_WRWML(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
 
#define SDHC_WML_RDWML_MASK   (0xFFU)
 
#define SDHC_WML_RDWML_SHIFT   (0U)
 
#define SDHC_WML_RDWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
 
#define SDHC_WML_WRWML_MASK   (0xFF0000U)
 
#define SDHC_WML_WRWML_SHIFT   (16U)
 
#define SDHC_WML_WRWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
 
#define SDHC_WML_RDWML_MASK   (0xFFU)
 
#define SDHC_WML_RDWML_SHIFT   (0U)
 
#define SDHC_WML_RDWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
 
#define SDHC_WML_WRWML_MASK   (0xFF0000U)
 
#define SDHC_WML_WRWML_SHIFT   (16U)
 
#define SDHC_WML_WRWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
 
#define SDHC_WML_RDWML_MASK   (0xFFU)
 
#define SDHC_WML_RDWML_SHIFT   (0U)
 
#define SDHC_WML_RDWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
 
#define SDHC_WML_WRWML_MASK   (0xFF0000U)
 
#define SDHC_WML_WRWML_SHIFT   (16U)
 
#define SDHC_WML_WRWML(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
 

FEVT - Force Event register

#define SDHC_FEVT_AC12NE_MASK   (0x1U)
 
#define SDHC_FEVT_AC12NE_SHIFT   (0U)
 
#define SDHC_FEVT_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
 
#define SDHC_FEVT_AC12TOE_MASK   (0x2U)
 
#define SDHC_FEVT_AC12TOE_SHIFT   (1U)
 
#define SDHC_FEVT_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
 
#define SDHC_FEVT_AC12CE_MASK   (0x4U)
 
#define SDHC_FEVT_AC12CE_SHIFT   (2U)
 
#define SDHC_FEVT_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
 
#define SDHC_FEVT_AC12EBE_MASK   (0x8U)
 
#define SDHC_FEVT_AC12EBE_SHIFT   (3U)
 
#define SDHC_FEVT_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
 
#define SDHC_FEVT_AC12IE_MASK   (0x10U)
 
#define SDHC_FEVT_AC12IE_SHIFT   (4U)
 
#define SDHC_FEVT_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
 
#define SDHC_FEVT_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_FEVT_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_FEVT_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
 
#define SDHC_FEVT_CTOE_MASK   (0x10000U)
 
#define SDHC_FEVT_CTOE_SHIFT   (16U)
 
#define SDHC_FEVT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
 
#define SDHC_FEVT_CCE_MASK   (0x20000U)
 
#define SDHC_FEVT_CCE_SHIFT   (17U)
 
#define SDHC_FEVT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
 
#define SDHC_FEVT_CEBE_MASK   (0x40000U)
 
#define SDHC_FEVT_CEBE_SHIFT   (18U)
 
#define SDHC_FEVT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
 
#define SDHC_FEVT_CIE_MASK   (0x80000U)
 
#define SDHC_FEVT_CIE_SHIFT   (19U)
 
#define SDHC_FEVT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
 
#define SDHC_FEVT_DTOE_MASK   (0x100000U)
 
#define SDHC_FEVT_DTOE_SHIFT   (20U)
 
#define SDHC_FEVT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
 
#define SDHC_FEVT_DCE_MASK   (0x200000U)
 
#define SDHC_FEVT_DCE_SHIFT   (21U)
 
#define SDHC_FEVT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
 
#define SDHC_FEVT_DEBE_MASK   (0x400000U)
 
#define SDHC_FEVT_DEBE_SHIFT   (22U)
 
#define SDHC_FEVT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
 
#define SDHC_FEVT_AC12E_MASK   (0x1000000U)
 
#define SDHC_FEVT_AC12E_SHIFT   (24U)
 
#define SDHC_FEVT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
 
#define SDHC_FEVT_DMAE_MASK   (0x10000000U)
 
#define SDHC_FEVT_DMAE_SHIFT   (28U)
 
#define SDHC_FEVT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
 
#define SDHC_FEVT_CINT_MASK   (0x80000000U)
 
#define SDHC_FEVT_CINT_SHIFT   (31U)
 
#define SDHC_FEVT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
 
#define SDHC_FEVT_AC12NE_MASK   0x1u
 
#define SDHC_FEVT_AC12NE_SHIFT   0
 
#define SDHC_FEVT_AC12TOE_MASK   0x2u
 
#define SDHC_FEVT_AC12TOE_SHIFT   1
 
#define SDHC_FEVT_AC12CE_MASK   0x4u
 
#define SDHC_FEVT_AC12CE_SHIFT   2
 
#define SDHC_FEVT_AC12EBE_MASK   0x8u
 
#define SDHC_FEVT_AC12EBE_SHIFT   3
 
#define SDHC_FEVT_AC12IE_MASK   0x10u
 
#define SDHC_FEVT_AC12IE_SHIFT   4
 
#define SDHC_FEVT_CNIBAC12E_MASK   0x80u
 
#define SDHC_FEVT_CNIBAC12E_SHIFT   7
 
#define SDHC_FEVT_CTOE_MASK   0x10000u
 
#define SDHC_FEVT_CTOE_SHIFT   16
 
#define SDHC_FEVT_CCE_MASK   0x20000u
 
#define SDHC_FEVT_CCE_SHIFT   17
 
#define SDHC_FEVT_CEBE_MASK   0x40000u
 
#define SDHC_FEVT_CEBE_SHIFT   18
 
#define SDHC_FEVT_CIE_MASK   0x80000u
 
#define SDHC_FEVT_CIE_SHIFT   19
 
#define SDHC_FEVT_DTOE_MASK   0x100000u
 
#define SDHC_FEVT_DTOE_SHIFT   20
 
#define SDHC_FEVT_DCE_MASK   0x200000u
 
#define SDHC_FEVT_DCE_SHIFT   21
 
#define SDHC_FEVT_DEBE_MASK   0x400000u
 
#define SDHC_FEVT_DEBE_SHIFT   22
 
#define SDHC_FEVT_AC12E_MASK   0x1000000u
 
#define SDHC_FEVT_AC12E_SHIFT   24
 
#define SDHC_FEVT_DMAE_MASK   0x10000000u
 
#define SDHC_FEVT_DMAE_SHIFT   28
 
#define SDHC_FEVT_CINT_MASK   0x80000000u
 
#define SDHC_FEVT_CINT_SHIFT   31
 
#define SDHC_FEVT_AC12NE_MASK   (0x1U)
 
#define SDHC_FEVT_AC12NE_SHIFT   (0U)
 
#define SDHC_FEVT_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
 
#define SDHC_FEVT_AC12TOE_MASK   (0x2U)
 
#define SDHC_FEVT_AC12TOE_SHIFT   (1U)
 
#define SDHC_FEVT_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
 
#define SDHC_FEVT_AC12CE_MASK   (0x4U)
 
#define SDHC_FEVT_AC12CE_SHIFT   (2U)
 
#define SDHC_FEVT_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
 
#define SDHC_FEVT_AC12EBE_MASK   (0x8U)
 
#define SDHC_FEVT_AC12EBE_SHIFT   (3U)
 
#define SDHC_FEVT_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
 
#define SDHC_FEVT_AC12IE_MASK   (0x10U)
 
#define SDHC_FEVT_AC12IE_SHIFT   (4U)
 
#define SDHC_FEVT_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
 
#define SDHC_FEVT_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_FEVT_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_FEVT_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
 
#define SDHC_FEVT_CTOE_MASK   (0x10000U)
 
#define SDHC_FEVT_CTOE_SHIFT   (16U)
 
#define SDHC_FEVT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
 
#define SDHC_FEVT_CCE_MASK   (0x20000U)
 
#define SDHC_FEVT_CCE_SHIFT   (17U)
 
#define SDHC_FEVT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
 
#define SDHC_FEVT_CEBE_MASK   (0x40000U)
 
#define SDHC_FEVT_CEBE_SHIFT   (18U)
 
#define SDHC_FEVT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
 
#define SDHC_FEVT_CIE_MASK   (0x80000U)
 
#define SDHC_FEVT_CIE_SHIFT   (19U)
 
#define SDHC_FEVT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
 
#define SDHC_FEVT_DTOE_MASK   (0x100000U)
 
#define SDHC_FEVT_DTOE_SHIFT   (20U)
 
#define SDHC_FEVT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
 
#define SDHC_FEVT_DCE_MASK   (0x200000U)
 
#define SDHC_FEVT_DCE_SHIFT   (21U)
 
#define SDHC_FEVT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
 
#define SDHC_FEVT_DEBE_MASK   (0x400000U)
 
#define SDHC_FEVT_DEBE_SHIFT   (22U)
 
#define SDHC_FEVT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
 
#define SDHC_FEVT_AC12E_MASK   (0x1000000U)
 
#define SDHC_FEVT_AC12E_SHIFT   (24U)
 
#define SDHC_FEVT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
 
#define SDHC_FEVT_DMAE_MASK   (0x10000000U)
 
#define SDHC_FEVT_DMAE_SHIFT   (28U)
 
#define SDHC_FEVT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
 
#define SDHC_FEVT_CINT_MASK   (0x80000000U)
 
#define SDHC_FEVT_CINT_SHIFT   (31U)
 
#define SDHC_FEVT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
 
#define SDHC_FEVT_AC12NE_MASK   (0x1U)
 
#define SDHC_FEVT_AC12NE_SHIFT   (0U)
 
#define SDHC_FEVT_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
 
#define SDHC_FEVT_AC12TOE_MASK   (0x2U)
 
#define SDHC_FEVT_AC12TOE_SHIFT   (1U)
 
#define SDHC_FEVT_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
 
#define SDHC_FEVT_AC12CE_MASK   (0x4U)
 
#define SDHC_FEVT_AC12CE_SHIFT   (2U)
 
#define SDHC_FEVT_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
 
#define SDHC_FEVT_AC12EBE_MASK   (0x8U)
 
#define SDHC_FEVT_AC12EBE_SHIFT   (3U)
 
#define SDHC_FEVT_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
 
#define SDHC_FEVT_AC12IE_MASK   (0x10U)
 
#define SDHC_FEVT_AC12IE_SHIFT   (4U)
 
#define SDHC_FEVT_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
 
#define SDHC_FEVT_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_FEVT_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_FEVT_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
 
#define SDHC_FEVT_CTOE_MASK   (0x10000U)
 
#define SDHC_FEVT_CTOE_SHIFT   (16U)
 
#define SDHC_FEVT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
 
#define SDHC_FEVT_CCE_MASK   (0x20000U)
 
#define SDHC_FEVT_CCE_SHIFT   (17U)
 
#define SDHC_FEVT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
 
#define SDHC_FEVT_CEBE_MASK   (0x40000U)
 
#define SDHC_FEVT_CEBE_SHIFT   (18U)
 
#define SDHC_FEVT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
 
#define SDHC_FEVT_CIE_MASK   (0x80000U)
 
#define SDHC_FEVT_CIE_SHIFT   (19U)
 
#define SDHC_FEVT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
 
#define SDHC_FEVT_DTOE_MASK   (0x100000U)
 
#define SDHC_FEVT_DTOE_SHIFT   (20U)
 
#define SDHC_FEVT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
 
#define SDHC_FEVT_DCE_MASK   (0x200000U)
 
#define SDHC_FEVT_DCE_SHIFT   (21U)
 
#define SDHC_FEVT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
 
#define SDHC_FEVT_DEBE_MASK   (0x400000U)
 
#define SDHC_FEVT_DEBE_SHIFT   (22U)
 
#define SDHC_FEVT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
 
#define SDHC_FEVT_AC12E_MASK   (0x1000000U)
 
#define SDHC_FEVT_AC12E_SHIFT   (24U)
 
#define SDHC_FEVT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
 
#define SDHC_FEVT_DMAE_MASK   (0x10000000U)
 
#define SDHC_FEVT_DMAE_SHIFT   (28U)
 
#define SDHC_FEVT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
 
#define SDHC_FEVT_CINT_MASK   (0x80000000U)
 
#define SDHC_FEVT_CINT_SHIFT   (31U)
 
#define SDHC_FEVT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
 
#define SDHC_FEVT_AC12NE_MASK   (0x1U)
 
#define SDHC_FEVT_AC12NE_SHIFT   (0U)
 
#define SDHC_FEVT_AC12NE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
 
#define SDHC_FEVT_AC12TOE_MASK   (0x2U)
 
#define SDHC_FEVT_AC12TOE_SHIFT   (1U)
 
#define SDHC_FEVT_AC12TOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
 
#define SDHC_FEVT_AC12CE_MASK   (0x4U)
 
#define SDHC_FEVT_AC12CE_SHIFT   (2U)
 
#define SDHC_FEVT_AC12CE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
 
#define SDHC_FEVT_AC12EBE_MASK   (0x8U)
 
#define SDHC_FEVT_AC12EBE_SHIFT   (3U)
 
#define SDHC_FEVT_AC12EBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
 
#define SDHC_FEVT_AC12IE_MASK   (0x10U)
 
#define SDHC_FEVT_AC12IE_SHIFT   (4U)
 
#define SDHC_FEVT_AC12IE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
 
#define SDHC_FEVT_CNIBAC12E_MASK   (0x80U)
 
#define SDHC_FEVT_CNIBAC12E_SHIFT   (7U)
 
#define SDHC_FEVT_CNIBAC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
 
#define SDHC_FEVT_CTOE_MASK   (0x10000U)
 
#define SDHC_FEVT_CTOE_SHIFT   (16U)
 
#define SDHC_FEVT_CTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
 
#define SDHC_FEVT_CCE_MASK   (0x20000U)
 
#define SDHC_FEVT_CCE_SHIFT   (17U)
 
#define SDHC_FEVT_CCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
 
#define SDHC_FEVT_CEBE_MASK   (0x40000U)
 
#define SDHC_FEVT_CEBE_SHIFT   (18U)
 
#define SDHC_FEVT_CEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
 
#define SDHC_FEVT_CIE_MASK   (0x80000U)
 
#define SDHC_FEVT_CIE_SHIFT   (19U)
 
#define SDHC_FEVT_CIE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
 
#define SDHC_FEVT_DTOE_MASK   (0x100000U)
 
#define SDHC_FEVT_DTOE_SHIFT   (20U)
 
#define SDHC_FEVT_DTOE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
 
#define SDHC_FEVT_DCE_MASK   (0x200000U)
 
#define SDHC_FEVT_DCE_SHIFT   (21U)
 
#define SDHC_FEVT_DCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
 
#define SDHC_FEVT_DEBE_MASK   (0x400000U)
 
#define SDHC_FEVT_DEBE_SHIFT   (22U)
 
#define SDHC_FEVT_DEBE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
 
#define SDHC_FEVT_AC12E_MASK   (0x1000000U)
 
#define SDHC_FEVT_AC12E_SHIFT   (24U)
 
#define SDHC_FEVT_AC12E(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
 
#define SDHC_FEVT_DMAE_MASK   (0x10000000U)
 
#define SDHC_FEVT_DMAE_SHIFT   (28U)
 
#define SDHC_FEVT_DMAE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
 
#define SDHC_FEVT_CINT_MASK   (0x80000000U)
 
#define SDHC_FEVT_CINT_SHIFT   (31U)
 
#define SDHC_FEVT_CINT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
 

ADMAES - ADMA Error Status register

#define SDHC_ADMAES_ADMAES_MASK   (0x3U)
 
#define SDHC_ADMAES_ADMAES_SHIFT   (0U)
 
#define SDHC_ADMAES_ADMAES(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
 
#define SDHC_ADMAES_ADMALME_MASK   (0x4U)
 
#define SDHC_ADMAES_ADMALME_SHIFT   (2U)
 
#define SDHC_ADMAES_ADMALME(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
 
#define SDHC_ADMAES_ADMADCE_MASK   (0x8U)
 
#define SDHC_ADMAES_ADMADCE_SHIFT   (3U)
 
#define SDHC_ADMAES_ADMADCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
 
#define SDHC_ADMAES_ADMAES_MASK   0x3u
 
#define SDHC_ADMAES_ADMAES_SHIFT   0
 
#define SDHC_ADMAES_ADMAES(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
 
#define SDHC_ADMAES_ADMALME_MASK   0x4u
 
#define SDHC_ADMAES_ADMALME_SHIFT   2
 
#define SDHC_ADMAES_ADMADCE_MASK   0x8u
 
#define SDHC_ADMAES_ADMADCE_SHIFT   3
 
#define SDHC_ADMAES_ADMAES_MASK   (0x3U)
 
#define SDHC_ADMAES_ADMAES_SHIFT   (0U)
 
#define SDHC_ADMAES_ADMAES(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
 
#define SDHC_ADMAES_ADMALME_MASK   (0x4U)
 
#define SDHC_ADMAES_ADMALME_SHIFT   (2U)
 
#define SDHC_ADMAES_ADMALME(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
 
#define SDHC_ADMAES_ADMADCE_MASK   (0x8U)
 
#define SDHC_ADMAES_ADMADCE_SHIFT   (3U)
 
#define SDHC_ADMAES_ADMADCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
 
#define SDHC_ADMAES_ADMAES_MASK   (0x3U)
 
#define SDHC_ADMAES_ADMAES_SHIFT   (0U)
 
#define SDHC_ADMAES_ADMAES(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
 
#define SDHC_ADMAES_ADMALME_MASK   (0x4U)
 
#define SDHC_ADMAES_ADMALME_SHIFT   (2U)
 
#define SDHC_ADMAES_ADMALME(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
 
#define SDHC_ADMAES_ADMADCE_MASK   (0x8U)
 
#define SDHC_ADMAES_ADMADCE_SHIFT   (3U)
 
#define SDHC_ADMAES_ADMADCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
 
#define SDHC_ADMAES_ADMAES_MASK   (0x3U)
 
#define SDHC_ADMAES_ADMAES_SHIFT   (0U)
 
#define SDHC_ADMAES_ADMAES(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
 
#define SDHC_ADMAES_ADMALME_MASK   (0x4U)
 
#define SDHC_ADMAES_ADMALME_SHIFT   (2U)
 
#define SDHC_ADMAES_ADMALME(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
 
#define SDHC_ADMAES_ADMADCE_MASK   (0x8U)
 
#define SDHC_ADMAES_ADMADCE_SHIFT   (3U)
 
#define SDHC_ADMAES_ADMADCE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
 

ADSADDR - ADMA System Addressregister

#define SDHC_ADSADDR_ADSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_ADSADDR_ADSADDR_SHIFT   (2U)
 
#define SDHC_ADSADDR_ADSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
 
#define SDHC_ADSADDR_ADSADDR_MASK   0xFFFFFFFCu
 
#define SDHC_ADSADDR_ADSADDR_SHIFT   2
 
#define SDHC_ADSADDR_ADSADDR(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
 
#define SDHC_ADSADDR_ADSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_ADSADDR_ADSADDR_SHIFT   (2U)
 
#define SDHC_ADSADDR_ADSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
 
#define SDHC_ADSADDR_ADSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_ADSADDR_ADSADDR_SHIFT   (2U)
 
#define SDHC_ADSADDR_ADSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
 
#define SDHC_ADSADDR_ADSADDR_MASK   (0xFFFFFFFCU)
 
#define SDHC_ADSADDR_ADSADDR_SHIFT   (2U)
 
#define SDHC_ADSADDR_ADSADDR(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
 

VENDOR - Vendor Specific register

#define SDHC_VENDOR_EXTDMAEN_MASK   (0x1U)
 
#define SDHC_VENDOR_EXTDMAEN_SHIFT   (0U)
 
#define SDHC_VENDOR_EXTDMAEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
 
#define SDHC_VENDOR_EXTDMAEN_MASK   0x1u
 
#define SDHC_VENDOR_EXTDMAEN_SHIFT   0
 
#define SDHC_VENDOR_EXTDMAEN_MASK   (0x1U)
 
#define SDHC_VENDOR_EXTDMAEN_SHIFT   (0U)
 
#define SDHC_VENDOR_EXTDMAEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
 

VENDOR - Vendor Specific register

#define SDHC_VENDOR_EXBLKNU_MASK   (0x2U)
 
#define SDHC_VENDOR_EXBLKNU_SHIFT   (1U)
 
#define SDHC_VENDOR_EXBLKNU(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
 
#define SDHC_VENDOR_INTSTVAL_MASK   (0xFF0000U)
 
#define SDHC_VENDOR_INTSTVAL_SHIFT   (16U)
 
#define SDHC_VENDOR_INTSTVAL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
 
#define SDHC_VENDOR_INTSTVAL_MASK   0xFF0000u
 
#define SDHC_VENDOR_INTSTVAL_SHIFT   16
 
#define SDHC_VENDOR_INTSTVAL(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
 
#define SDHC_VENDOR_EXBLKNU_MASK   (0x2U)
 
#define SDHC_VENDOR_EXBLKNU_SHIFT   (1U)
 
#define SDHC_VENDOR_EXBLKNU(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
 
#define SDHC_VENDOR_INTSTVAL_MASK   (0xFF0000U)
 
#define SDHC_VENDOR_INTSTVAL_SHIFT   (16U)
 
#define SDHC_VENDOR_INTSTVAL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
 
#define SDHC_VENDOR_EXBLKNU_MASK   (0x2U)
 
#define SDHC_VENDOR_EXBLKNU_SHIFT   (1U)
 
#define SDHC_VENDOR_EXBLKNU(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
 
#define SDHC_VENDOR_INTSTVAL_MASK   (0xFF0000U)
 
#define SDHC_VENDOR_INTSTVAL_SHIFT   (16U)
 
#define SDHC_VENDOR_INTSTVAL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
 
#define SDHC_VENDOR_EXBLKNU_MASK   (0x2U)
 
#define SDHC_VENDOR_EXBLKNU_SHIFT   (1U)
 
#define SDHC_VENDOR_EXBLKNU(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
 
#define SDHC_VENDOR_INTSTVAL_MASK   (0xFF0000U)
 
#define SDHC_VENDOR_INTSTVAL_SHIFT   (16U)
 
#define SDHC_VENDOR_INTSTVAL(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
 

MMCBOOT - MMC Boot register

#define SDHC_MMCBOOT_DTOCVACK_MASK   (0xFU)
 
#define SDHC_MMCBOOT_DTOCVACK_SHIFT   (0U)
 
#define SDHC_MMCBOOT_DTOCVACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
 
#define SDHC_MMCBOOT_BOOTACK_MASK   (0x10U)
 
#define SDHC_MMCBOOT_BOOTACK_SHIFT   (4U)
 
#define SDHC_MMCBOOT_BOOTACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
 
#define SDHC_MMCBOOT_BOOTMODE_MASK   (0x20U)
 
#define SDHC_MMCBOOT_BOOTMODE_SHIFT   (5U)
 
#define SDHC_MMCBOOT_BOOTMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
 
#define SDHC_MMCBOOT_BOOTEN_MASK   (0x40U)
 
#define SDHC_MMCBOOT_BOOTEN_SHIFT   (6U)
 
#define SDHC_MMCBOOT_BOOTEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
 
#define SDHC_MMCBOOT_AUTOSABGEN_MASK   (0x80U)
 
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT   (7U)
 
#define SDHC_MMCBOOT_AUTOSABGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT   (16U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
 
#define SDHC_MMCBOOT_DTOCVACK_MASK   0xFu
 
#define SDHC_MMCBOOT_DTOCVACK_SHIFT   0
 
#define SDHC_MMCBOOT_DTOCVACK(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
 
#define SDHC_MMCBOOT_BOOTACK_MASK   0x10u
 
#define SDHC_MMCBOOT_BOOTACK_SHIFT   4
 
#define SDHC_MMCBOOT_BOOTMODE_MASK   0x20u
 
#define SDHC_MMCBOOT_BOOTMODE_SHIFT   5
 
#define SDHC_MMCBOOT_BOOTEN_MASK   0x40u
 
#define SDHC_MMCBOOT_BOOTEN_SHIFT   6
 
#define SDHC_MMCBOOT_AUTOSABGEN_MASK   0x80u
 
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT   7
 
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK   0xFFFF0000u
 
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT   16
 
#define SDHC_MMCBOOT_BOOTBLKCNT(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
 
#define SDHC_MMCBOOT_DTOCVACK_MASK   (0xFU)
 
#define SDHC_MMCBOOT_DTOCVACK_SHIFT   (0U)
 
#define SDHC_MMCBOOT_DTOCVACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
 
#define SDHC_MMCBOOT_BOOTACK_MASK   (0x10U)
 
#define SDHC_MMCBOOT_BOOTACK_SHIFT   (4U)
 
#define SDHC_MMCBOOT_BOOTACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
 
#define SDHC_MMCBOOT_BOOTMODE_MASK   (0x20U)
 
#define SDHC_MMCBOOT_BOOTMODE_SHIFT   (5U)
 
#define SDHC_MMCBOOT_BOOTMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
 
#define SDHC_MMCBOOT_BOOTEN_MASK   (0x40U)
 
#define SDHC_MMCBOOT_BOOTEN_SHIFT   (6U)
 
#define SDHC_MMCBOOT_BOOTEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
 
#define SDHC_MMCBOOT_AUTOSABGEN_MASK   (0x80U)
 
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT   (7U)
 
#define SDHC_MMCBOOT_AUTOSABGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT   (16U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
 
#define SDHC_MMCBOOT_DTOCVACK_MASK   (0xFU)
 
#define SDHC_MMCBOOT_DTOCVACK_SHIFT   (0U)
 
#define SDHC_MMCBOOT_DTOCVACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
 
#define SDHC_MMCBOOT_BOOTACK_MASK   (0x10U)
 
#define SDHC_MMCBOOT_BOOTACK_SHIFT   (4U)
 
#define SDHC_MMCBOOT_BOOTACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
 
#define SDHC_MMCBOOT_BOOTMODE_MASK   (0x20U)
 
#define SDHC_MMCBOOT_BOOTMODE_SHIFT   (5U)
 
#define SDHC_MMCBOOT_BOOTMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
 
#define SDHC_MMCBOOT_BOOTEN_MASK   (0x40U)
 
#define SDHC_MMCBOOT_BOOTEN_SHIFT   (6U)
 
#define SDHC_MMCBOOT_BOOTEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
 
#define SDHC_MMCBOOT_AUTOSABGEN_MASK   (0x80U)
 
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT   (7U)
 
#define SDHC_MMCBOOT_AUTOSABGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT   (16U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
 
#define SDHC_MMCBOOT_DTOCVACK_MASK   (0xFU)
 
#define SDHC_MMCBOOT_DTOCVACK_SHIFT   (0U)
 
#define SDHC_MMCBOOT_DTOCVACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
 
#define SDHC_MMCBOOT_BOOTACK_MASK   (0x10U)
 
#define SDHC_MMCBOOT_BOOTACK_SHIFT   (4U)
 
#define SDHC_MMCBOOT_BOOTACK(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
 
#define SDHC_MMCBOOT_BOOTMODE_MASK   (0x20U)
 
#define SDHC_MMCBOOT_BOOTMODE_SHIFT   (5U)
 
#define SDHC_MMCBOOT_BOOTMODE(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
 
#define SDHC_MMCBOOT_BOOTEN_MASK   (0x40U)
 
#define SDHC_MMCBOOT_BOOTEN_SHIFT   (6U)
 
#define SDHC_MMCBOOT_BOOTEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
 
#define SDHC_MMCBOOT_AUTOSABGEN_MASK   (0x80U)
 
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT   (7U)
 
#define SDHC_MMCBOOT_AUTOSABGEN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK   (0xFFFF0000U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT   (16U)
 
#define SDHC_MMCBOOT_BOOTBLKCNT(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
 

HOSTVER - Host Controller Version

#define SDHC_HOSTVER_SVN_MASK   (0xFFU)
 
#define SDHC_HOSTVER_SVN_SHIFT   (0U)
 
#define SDHC_HOSTVER_SVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
 
#define SDHC_HOSTVER_VVN_MASK   (0xFF00U)
 
#define SDHC_HOSTVER_VVN_SHIFT   (8U)
 
#define SDHC_HOSTVER_VVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
 
#define SDHC_HOSTVER_SVN_MASK   0xFFu
 
#define SDHC_HOSTVER_SVN_SHIFT   0
 
#define SDHC_HOSTVER_SVN(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
 
#define SDHC_HOSTVER_VVN_MASK   0xFF00u
 
#define SDHC_HOSTVER_VVN_SHIFT   8
 
#define SDHC_HOSTVER_VVN(x)   (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
 
#define SDHC_HOSTVER_SVN_MASK   (0xFFU)
 
#define SDHC_HOSTVER_SVN_SHIFT   (0U)
 
#define SDHC_HOSTVER_SVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
 
#define SDHC_HOSTVER_VVN_MASK   (0xFF00U)
 
#define SDHC_HOSTVER_VVN_SHIFT   (8U)
 
#define SDHC_HOSTVER_VVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
 
#define SDHC_HOSTVER_SVN_MASK   (0xFFU)
 
#define SDHC_HOSTVER_SVN_SHIFT   (0U)
 
#define SDHC_HOSTVER_SVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
 
#define SDHC_HOSTVER_VVN_MASK   (0xFF00U)
 
#define SDHC_HOSTVER_VVN_SHIFT   (8U)
 
#define SDHC_HOSTVER_VVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
 
#define SDHC_HOSTVER_SVN_MASK   (0xFFU)
 
#define SDHC_HOSTVER_SVN_SHIFT   (0U)
 
#define SDHC_HOSTVER_SVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
 
#define SDHC_HOSTVER_VVN_MASK   (0xFF00U)
 
#define SDHC_HOSTVER_VVN_SHIFT   (8U)
 
#define SDHC_HOSTVER_VVN(x)   (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
 

Macro Definition Documentation

◆ SDHC

#define SDHC   ((SDHC_Type *)SDHC_BASE)

Peripheral SDHC base pointer

◆ SDHC_AC12ERR_AC12CE [1/4]

#define SDHC_AC12ERR_AC12CE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)

AC12CE - Auto CMD12 CRC Error 0b0..No CRC error. 0b1..CRC error met in Auto CMD12 response.

◆ SDHC_AC12ERR_AC12CE [2/4]

#define SDHC_AC12ERR_AC12CE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)

AC12CE - Auto CMD12 CRC Error 0b0..No CRC error. 0b1..CRC error met in Auto CMD12 response.

◆ SDHC_AC12ERR_AC12CE [3/4]

#define SDHC_AC12ERR_AC12CE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)

AC12CE - Auto CMD12 CRC Error 0b0..No CRC error. 0b1..CRC error met in Auto CMD12 response.

◆ SDHC_AC12ERR_AC12CE [4/4]

#define SDHC_AC12ERR_AC12CE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)

AC12CE - Auto CMD12 CRC Error 0b0..No CRC error. 0b1..CRC error met in Auto CMD12 response.

◆ SDHC_AC12ERR_AC12EBE [1/4]

#define SDHC_AC12ERR_AC12EBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)

AC12EBE - Auto CMD12 End Bit Error 0b0..No error. 0b1..End bit error generated.

◆ SDHC_AC12ERR_AC12EBE [2/4]

#define SDHC_AC12ERR_AC12EBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)

AC12EBE - Auto CMD12 End Bit Error 0b0..No error. 0b1..End bit error generated.

◆ SDHC_AC12ERR_AC12EBE [3/4]

#define SDHC_AC12ERR_AC12EBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)

AC12EBE - Auto CMD12 End Bit Error 0b0..No error. 0b1..End bit error generated.

◆ SDHC_AC12ERR_AC12EBE [4/4]

#define SDHC_AC12ERR_AC12EBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)

AC12EBE - Auto CMD12 End Bit Error 0b0..No error. 0b1..End bit error generated.

◆ SDHC_AC12ERR_AC12IE [1/4]

#define SDHC_AC12ERR_AC12IE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)

AC12IE - Auto CMD12 Index Error 0b0..No error. 0b1..Error, the CMD index in response is not CMD12.

◆ SDHC_AC12ERR_AC12IE [2/4]

#define SDHC_AC12ERR_AC12IE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)

AC12IE - Auto CMD12 Index Error 0b0..No error. 0b1..Error, the CMD index in response is not CMD12.

◆ SDHC_AC12ERR_AC12IE [3/4]

#define SDHC_AC12ERR_AC12IE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)

AC12IE - Auto CMD12 Index Error 0b0..No error. 0b1..Error, the CMD index in response is not CMD12.

◆ SDHC_AC12ERR_AC12IE [4/4]

#define SDHC_AC12ERR_AC12IE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)

AC12IE - Auto CMD12 Index Error 0b0..No error. 0b1..Error, the CMD index in response is not CMD12.

◆ SDHC_AC12ERR_AC12NE [1/4]

#define SDHC_AC12ERR_AC12NE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)

AC12NE - Auto CMD12 Not Executed 0b0..Executed. 0b1..Not executed.

◆ SDHC_AC12ERR_AC12NE [2/4]

#define SDHC_AC12ERR_AC12NE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)

AC12NE - Auto CMD12 Not Executed 0b0..Executed. 0b1..Not executed.

◆ SDHC_AC12ERR_AC12NE [3/4]

#define SDHC_AC12ERR_AC12NE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)

AC12NE - Auto CMD12 Not Executed 0b0..Executed. 0b1..Not executed.

◆ SDHC_AC12ERR_AC12NE [4/4]

#define SDHC_AC12ERR_AC12NE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)

AC12NE - Auto CMD12 Not Executed 0b0..Executed. 0b1..Not executed.

◆ SDHC_AC12ERR_AC12TOE [1/4]

#define SDHC_AC12ERR_AC12TOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)

AC12TOE - Auto CMD12 Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_AC12ERR_AC12TOE [2/4]

#define SDHC_AC12ERR_AC12TOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)

AC12TOE - Auto CMD12 Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_AC12ERR_AC12TOE [3/4]

#define SDHC_AC12ERR_AC12TOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)

AC12TOE - Auto CMD12 Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_AC12ERR_AC12TOE [4/4]

#define SDHC_AC12ERR_AC12TOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)

AC12TOE - Auto CMD12 Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_AC12ERR_CNIBAC12E [1/4]

#define SDHC_AC12ERR_CNIBAC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)

CNIBAC12E - Command Not Issued By Auto CMD12 Error 0b0..No error. 0b1..Not issued.

◆ SDHC_AC12ERR_CNIBAC12E [2/4]

#define SDHC_AC12ERR_CNIBAC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)

CNIBAC12E - Command Not Issued By Auto CMD12 Error 0b0..No error. 0b1..Not issued.

◆ SDHC_AC12ERR_CNIBAC12E [3/4]

#define SDHC_AC12ERR_CNIBAC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)

CNIBAC12E - Command Not Issued By Auto CMD12 Error 0b0..No error. 0b1..Not issued.

◆ SDHC_AC12ERR_CNIBAC12E [4/4]

#define SDHC_AC12ERR_CNIBAC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)

CNIBAC12E - Command Not Issued By Auto CMD12 Error 0b0..No error. 0b1..Not issued.

◆ SDHC_ADMAES_ADMADCE [1/4]

#define SDHC_ADMAES_ADMADCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)

ADMADCE - ADMA Descriptor Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMADCE [2/4]

#define SDHC_ADMAES_ADMADCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)

ADMADCE - ADMA Descriptor Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMADCE [3/4]

#define SDHC_ADMAES_ADMADCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)

ADMADCE - ADMA Descriptor Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMADCE [4/4]

#define SDHC_ADMAES_ADMADCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)

ADMADCE - ADMA Descriptor Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMALME [1/4]

#define SDHC_ADMAES_ADMALME ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)

ADMALME - ADMA Length Mismatch Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMALME [2/4]

#define SDHC_ADMAES_ADMALME ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)

ADMALME - ADMA Length Mismatch Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMALME [3/4]

#define SDHC_ADMAES_ADMALME ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)

ADMALME - ADMA Length Mismatch Error 0b0..No error. 0b1..Error.

◆ SDHC_ADMAES_ADMALME [4/4]

#define SDHC_ADMAES_ADMALME ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)

ADMALME - ADMA Length Mismatch Error 0b0..No error. 0b1..Error.

◆ SDHC_BASE

#define SDHC_BASE   (0x400B1000u)

Peripheral SDHC base address

◆ SDHC_BASE_ADDRS

#define SDHC_BASE_ADDRS   { SDHC_BASE }

Array initializer of SDHC peripheral base addresses

◆ SDHC_BASE_PTRS

#define SDHC_BASE_PTRS   { SDHC }

Array initializer of SDHC peripheral base pointers

◆ SDHC_BLKATTR_BLKCNT [1/5]

#define SDHC_BLKATTR_BLKCNT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)

BLKCNT - Blocks Count For Current Transfer 0b0000000000000000..Stop count. 0b0000000000000001..1 block 0b0000000000000010..2 blocks 0b1111111111111111..65535 blocks

◆ SDHC_BLKATTR_BLKCNT [2/5]

#define SDHC_BLKATTR_BLKCNT ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)

BLKCNT - Blocks Count For Current Transfer 0b0000000000000000..Stop count. 0b0000000000000001..1 block 0b0000000000000010..2 blocks 0b1111111111111111..65535 blocks

◆ SDHC_BLKATTR_BLKCNT [3/5]

#define SDHC_BLKATTR_BLKCNT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)

BLKCNT - Blocks Count For Current Transfer 0b0000000000000000..Stop count. 0b0000000000000001..1 block 0b0000000000000010..2 blocks 0b1111111111111111..65535 blocks

◆ SDHC_BLKATTR_BLKCNT [4/5]

#define SDHC_BLKATTR_BLKCNT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)

BLKCNT - Blocks Count For Current Transfer 0b0000000000000000..Stop count. 0b0000000000000001..1 block 0b0000000000000010..2 blocks 0b1111111111111111..65535 blocks

◆ SDHC_BLKATTR_BLKCNT [5/5]

#define SDHC_BLKATTR_BLKCNT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)

BLKCNT - Blocks Count For Current Transfer 0b0000000000000000..Stop count. 0b0000000000000001..1 block 0b0000000000000010..2 blocks 0b1111111111111111..65535 blocks

◆ SDHC_BLKATTR_BLKSIZE [1/5]

#define SDHC_BLKATTR_BLKSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)

BLKSIZE - Transfer Block Size 0b0000000000000..No data transfer. 0b0000000000001..1 Byte 0b0000000000010..2 Bytes 0b0000000000011..3 Bytes 0b0000000000100..4 Bytes 0b0000111111111..511 Bytes 0b0001000000000..512 Bytes 0b0100000000000..2048 Bytes 0b1000000000000..4096 Bytes

◆ SDHC_BLKATTR_BLKSIZE [2/5]

#define SDHC_BLKATTR_BLKSIZE ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)

BLKSIZE - Transfer Block Size 0b0000000000000..No data transfer. 0b0000000000001..1 Byte 0b0000000000010..2 Bytes 0b0000000000011..3 Bytes 0b0000000000100..4 Bytes 0b0000111111111..511 Bytes 0b0001000000000..512 Bytes 0b0100000000000..2048 Bytes 0b1000000000000..4096 Bytes

◆ SDHC_BLKATTR_BLKSIZE [3/5]

#define SDHC_BLKATTR_BLKSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)

BLKSIZE - Transfer Block Size 0b0000000000000..No data transfer. 0b0000000000001..1 Byte 0b0000000000010..2 Bytes 0b0000000000011..3 Bytes 0b0000000000100..4 Bytes 0b0000111111111..511 Bytes 0b0001000000000..512 Bytes 0b0100000000000..2048 Bytes 0b1000000000000..4096 Bytes

◆ SDHC_BLKATTR_BLKSIZE [4/5]

#define SDHC_BLKATTR_BLKSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)

BLKSIZE - Transfer Block Size 0b0000000000000..No data transfer. 0b0000000000001..1 Byte 0b0000000000010..2 Bytes 0b0000000000011..3 Bytes 0b0000000000100..4 Bytes 0b0000111111111..511 Bytes 0b0001000000000..512 Bytes 0b0100000000000..2048 Bytes 0b1000000000000..4096 Bytes

◆ SDHC_BLKATTR_BLKSIZE [5/5]

#define SDHC_BLKATTR_BLKSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)

BLKSIZE - Transfer Block Size 0b0000000000000..No data transfer. 0b0000000000001..1 Byte 0b0000000000010..2 Bytes 0b0000000000011..3 Bytes 0b0000000000100..4 Bytes 0b0000111111111..511 Bytes 0b0001000000000..512 Bytes 0b0100000000000..2048 Bytes 0b1000000000000..4096 Bytes

◆ SDHC_HOSTVER_SVN [1/5]

#define SDHC_HOSTVER_SVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)

SVN - Specification Version Number 0b00000001..SD host specification version 2.0, supports test event register and ADMA.

◆ SDHC_HOSTVER_SVN [2/5]

#define SDHC_HOSTVER_SVN ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)

SVN - Specification Version Number 0b00000001..SD host specification version 2.0, supports test event register and ADMA.

◆ SDHC_HOSTVER_SVN [3/5]

#define SDHC_HOSTVER_SVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)

SVN - Specification Version Number 0b00000001..SD host specification version 2.0, supports test event register and ADMA.

◆ SDHC_HOSTVER_SVN [4/5]

#define SDHC_HOSTVER_SVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)

SVN - Specification Version Number 0b00000001..SD host specification version 2.0, supports test event register and ADMA.

◆ SDHC_HOSTVER_SVN [5/5]

#define SDHC_HOSTVER_SVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)

SVN - Specification Version Number 0b00000001..SD host specification version 2.0, supports test event register and ADMA.

◆ SDHC_HOSTVER_VVN [1/5]

#define SDHC_HOSTVER_VVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)

VVN - Vendor Version Number 0b00000000..Freescale SDHC version 1.0 0b00010000..Freescale SDHC version 2.0 0b00010001..Freescale SDHC version 2.1 0b00010010..Freescale SDHC version 2.2

◆ SDHC_HOSTVER_VVN [2/5]

#define SDHC_HOSTVER_VVN ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)

VVN - Vendor Version Number 0b00000000..Freescale SDHC version 1.0 0b00010000..Freescale SDHC version 2.0 0b00010001..Freescale SDHC version 2.1 0b00010010..Freescale SDHC version 2.2

◆ SDHC_HOSTVER_VVN [3/5]

#define SDHC_HOSTVER_VVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)

VVN - Vendor Version Number 0b00000000..Freescale SDHC version 1.0 0b00010000..Freescale SDHC version 2.0 0b00010001..Freescale SDHC version 2.1 0b00010010..Freescale SDHC version 2.2

◆ SDHC_HOSTVER_VVN [4/5]

#define SDHC_HOSTVER_VVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)

VVN - Vendor Version Number 0b00000000..Freescale SDHC version 1.0 0b00010000..Freescale SDHC version 2.0 0b00010001..Freescale SDHC version 2.1 0b00010010..Freescale SDHC version 2.2

◆ SDHC_HOSTVER_VVN [5/5]

#define SDHC_HOSTVER_VVN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)

VVN - Vendor Version Number 0b00000000..Freescale SDHC version 1.0 0b00010000..Freescale SDHC version 2.0 0b00010001..Freescale SDHC version 2.1 0b00010010..Freescale SDHC version 2.2

◆ SDHC_HTCAPBLT_ADMAS [1/4]

#define SDHC_HTCAPBLT_ADMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)

ADMAS - ADMA Support 0b0..Advanced DMA not supported. 0b1..Advanced DMA supported.

◆ SDHC_HTCAPBLT_ADMAS [2/4]

#define SDHC_HTCAPBLT_ADMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)

ADMAS - ADMA Support 0b0..Advanced DMA not supported. 0b1..Advanced DMA supported.

◆ SDHC_HTCAPBLT_ADMAS [3/4]

#define SDHC_HTCAPBLT_ADMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)

ADMAS - ADMA Support 0b0..Advanced DMA not supported. 0b1..Advanced DMA supported.

◆ SDHC_HTCAPBLT_ADMAS [4/4]

#define SDHC_HTCAPBLT_ADMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)

ADMAS - ADMA Support 0b0..Advanced DMA not supported. 0b1..Advanced DMA supported.

◆ SDHC_HTCAPBLT_DMAS [1/4]

#define SDHC_HTCAPBLT_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)

DMAS - DMA Support 0b0..DMA not supported. 0b1..DMA supported.

◆ SDHC_HTCAPBLT_DMAS [2/4]

#define SDHC_HTCAPBLT_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)

DMAS - DMA Support 0b0..DMA not supported. 0b1..DMA supported.

◆ SDHC_HTCAPBLT_DMAS [3/4]

#define SDHC_HTCAPBLT_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)

DMAS - DMA Support 0b0..DMA not supported. 0b1..DMA supported.

◆ SDHC_HTCAPBLT_DMAS [4/4]

#define SDHC_HTCAPBLT_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)

DMAS - DMA Support 0b0..DMA not supported. 0b1..DMA supported.

◆ SDHC_HTCAPBLT_HSS [1/4]

#define SDHC_HTCAPBLT_HSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)

HSS - High Speed Support 0b0..High speed not supported. 0b1..High speed supported.

◆ SDHC_HTCAPBLT_HSS [2/4]

#define SDHC_HTCAPBLT_HSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)

HSS - High Speed Support 0b0..High speed not supported. 0b1..High speed supported.

◆ SDHC_HTCAPBLT_HSS [3/4]

#define SDHC_HTCAPBLT_HSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)

HSS - High Speed Support 0b0..High speed not supported. 0b1..High speed supported.

◆ SDHC_HTCAPBLT_HSS [4/4]

#define SDHC_HTCAPBLT_HSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)

HSS - High Speed Support 0b0..High speed not supported. 0b1..High speed supported.

◆ SDHC_HTCAPBLT_MBL [1/5]

#define SDHC_HTCAPBLT_MBL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)

MBL - Max Block Length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ SDHC_HTCAPBLT_MBL [2/5]

#define SDHC_HTCAPBLT_MBL ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)

MBL - Max Block Length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ SDHC_HTCAPBLT_MBL [3/5]

#define SDHC_HTCAPBLT_MBL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)

MBL - Max Block Length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ SDHC_HTCAPBLT_MBL [4/5]

#define SDHC_HTCAPBLT_MBL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)

MBL - Max Block Length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ SDHC_HTCAPBLT_MBL [5/5]

#define SDHC_HTCAPBLT_MBL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)

MBL - Max Block Length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ SDHC_HTCAPBLT_SRS [1/4]

#define SDHC_HTCAPBLT_SRS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)

SRS - Suspend/Resume Support 0b0..Not supported. 0b1..Supported.

◆ SDHC_HTCAPBLT_SRS [2/4]

#define SDHC_HTCAPBLT_SRS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)

SRS - Suspend/Resume Support 0b0..Not supported. 0b1..Supported.

◆ SDHC_HTCAPBLT_SRS [3/4]

#define SDHC_HTCAPBLT_SRS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)

SRS - Suspend/Resume Support 0b0..Not supported. 0b1..Supported.

◆ SDHC_HTCAPBLT_SRS [4/4]

#define SDHC_HTCAPBLT_SRS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)

SRS - Suspend/Resume Support 0b0..Not supported. 0b1..Supported.

◆ SDHC_HTCAPBLT_VS33 [1/4]

#define SDHC_HTCAPBLT_VS33 ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)

VS33 - Voltage Support 3.3 V 0b0..3.3 V not supported. 0b1..3.3 V supported.

◆ SDHC_HTCAPBLT_VS33 [2/4]

#define SDHC_HTCAPBLT_VS33 ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)

VS33 - Voltage Support 3.3 V 0b0..3.3 V not supported. 0b1..3.3 V supported.

◆ SDHC_HTCAPBLT_VS33 [3/4]

#define SDHC_HTCAPBLT_VS33 ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)

VS33 - Voltage Support 3.3 V 0b0..3.3 V not supported. 0b1..3.3 V supported.

◆ SDHC_HTCAPBLT_VS33 [4/4]

#define SDHC_HTCAPBLT_VS33 ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)

VS33 - Voltage Support 3.3 V 0b0..3.3 V not supported. 0b1..3.3 V supported.

◆ SDHC_IRQS

#define SDHC_IRQS   { SDHC_IRQn }

Interrupt vectors for the SDHC peripheral type

◆ SDHC_IRQSIGEN_AC12EIEN [1/4]

#define SDHC_IRQSIGEN_AC12EIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_AC12EIEN [2/4]

#define SDHC_IRQSIGEN_AC12EIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_AC12EIEN [3/4]

#define SDHC_IRQSIGEN_AC12EIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_AC12EIEN [4/4]

#define SDHC_IRQSIGEN_AC12EIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BGEIEN [1/4]

#define SDHC_IRQSIGEN_BGEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)

BGEIEN - Block Gap Event Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BGEIEN [2/4]

#define SDHC_IRQSIGEN_BGEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)

BGEIEN - Block Gap Event Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BGEIEN [3/4]

#define SDHC_IRQSIGEN_BGEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)

BGEIEN - Block Gap Event Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BGEIEN [4/4]

#define SDHC_IRQSIGEN_BGEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)

BGEIEN - Block Gap Event Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BRRIEN [1/4]

#define SDHC_IRQSIGEN_BRRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)

BRRIEN - Buffer Read Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BRRIEN [2/4]

#define SDHC_IRQSIGEN_BRRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)

BRRIEN - Buffer Read Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BRRIEN [3/4]

#define SDHC_IRQSIGEN_BRRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)

BRRIEN - Buffer Read Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BRRIEN [4/4]

#define SDHC_IRQSIGEN_BRRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)

BRRIEN - Buffer Read Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BWRIEN [1/4]

#define SDHC_IRQSIGEN_BWRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)

BWRIEN - Buffer Write Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BWRIEN [2/4]

#define SDHC_IRQSIGEN_BWRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)

BWRIEN - Buffer Write Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BWRIEN [3/4]

#define SDHC_IRQSIGEN_BWRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)

BWRIEN - Buffer Write Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_BWRIEN [4/4]

#define SDHC_IRQSIGEN_BWRIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)

BWRIEN - Buffer Write Ready Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCEIEN [1/4]

#define SDHC_IRQSIGEN_CCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)

CCEIEN - Command CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCEIEN [2/4]

#define SDHC_IRQSIGEN_CCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)

CCEIEN - Command CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCEIEN [3/4]

#define SDHC_IRQSIGEN_CCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)

CCEIEN - Command CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCEIEN [4/4]

#define SDHC_IRQSIGEN_CCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)

CCEIEN - Command CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCIEN [1/4]

#define SDHC_IRQSIGEN_CCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)

CCIEN - Command Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCIEN [2/4]

#define SDHC_IRQSIGEN_CCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)

CCIEN - Command Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCIEN [3/4]

#define SDHC_IRQSIGEN_CCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)

CCIEN - Command Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CCIEN [4/4]

#define SDHC_IRQSIGEN_CCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)

CCIEN - Command Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CEBEIEN [1/4]

#define SDHC_IRQSIGEN_CEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)

CEBEIEN - Command End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CEBEIEN [2/4]

#define SDHC_IRQSIGEN_CEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)

CEBEIEN - Command End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CEBEIEN [3/4]

#define SDHC_IRQSIGEN_CEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)

CEBEIEN - Command End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CEBEIEN [4/4]

#define SDHC_IRQSIGEN_CEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)

CEBEIEN - Command End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CIEIEN [1/4]

#define SDHC_IRQSIGEN_CIEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)

CIEIEN - Command Index Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CIEIEN [2/4]

#define SDHC_IRQSIGEN_CIEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)

CIEIEN - Command Index Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CIEIEN [3/4]

#define SDHC_IRQSIGEN_CIEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)

CIEIEN - Command Index Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CIEIEN [4/4]

#define SDHC_IRQSIGEN_CIEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)

CIEIEN - Command Index Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINSIEN [1/4]

#define SDHC_IRQSIGEN_CINSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)

CINSIEN - Card Insertion Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINSIEN [2/4]

#define SDHC_IRQSIGEN_CINSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)

CINSIEN - Card Insertion Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINSIEN [3/4]

#define SDHC_IRQSIGEN_CINSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)

CINSIEN - Card Insertion Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINSIEN [4/4]

#define SDHC_IRQSIGEN_CINSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)

CINSIEN - Card Insertion Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINTIEN [1/4]

#define SDHC_IRQSIGEN_CINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)

CINTIEN - Card Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINTIEN [2/4]

#define SDHC_IRQSIGEN_CINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)

CINTIEN - Card Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINTIEN [3/4]

#define SDHC_IRQSIGEN_CINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)

CINTIEN - Card Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CINTIEN [4/4]

#define SDHC_IRQSIGEN_CINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)

CINTIEN - Card Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CRMIEN [1/4]

#define SDHC_IRQSIGEN_CRMIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)

CRMIEN - Card Removal Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CRMIEN [2/4]

#define SDHC_IRQSIGEN_CRMIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)

CRMIEN - Card Removal Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CRMIEN [3/4]

#define SDHC_IRQSIGEN_CRMIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)

CRMIEN - Card Removal Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CRMIEN [4/4]

#define SDHC_IRQSIGEN_CRMIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)

CRMIEN - Card Removal Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CTOEIEN [1/4]

#define SDHC_IRQSIGEN_CTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)

CTOEIEN - Command Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CTOEIEN [2/4]

#define SDHC_IRQSIGEN_CTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)

CTOEIEN - Command Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CTOEIEN [3/4]

#define SDHC_IRQSIGEN_CTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)

CTOEIEN - Command Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_CTOEIEN [4/4]

#define SDHC_IRQSIGEN_CTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)

CTOEIEN - Command Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DCEIEN [1/4]

#define SDHC_IRQSIGEN_DCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)

DCEIEN - Data CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DCEIEN [2/4]

#define SDHC_IRQSIGEN_DCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)

DCEIEN - Data CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DCEIEN [3/4]

#define SDHC_IRQSIGEN_DCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)

DCEIEN - Data CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DCEIEN [4/4]

#define SDHC_IRQSIGEN_DCEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)

DCEIEN - Data CRC Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DEBEIEN [1/4]

#define SDHC_IRQSIGEN_DEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)

DEBEIEN - Data End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DEBEIEN [2/4]

#define SDHC_IRQSIGEN_DEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)

DEBEIEN - Data End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DEBEIEN [3/4]

#define SDHC_IRQSIGEN_DEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)

DEBEIEN - Data End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DEBEIEN [4/4]

#define SDHC_IRQSIGEN_DEBEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)

DEBEIEN - Data End Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DINTIEN [1/4]

#define SDHC_IRQSIGEN_DINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)

DINTIEN - DMA Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DINTIEN [2/4]

#define SDHC_IRQSIGEN_DINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)

DINTIEN - DMA Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DINTIEN [3/4]

#define SDHC_IRQSIGEN_DINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)

DINTIEN - DMA Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DINTIEN [4/4]

#define SDHC_IRQSIGEN_DINTIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)

DINTIEN - DMA Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DMAEIEN [1/4]

#define SDHC_IRQSIGEN_DMAEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)

DMAEIEN - DMA Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DMAEIEN [2/4]

#define SDHC_IRQSIGEN_DMAEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)

DMAEIEN - DMA Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DMAEIEN [3/4]

#define SDHC_IRQSIGEN_DMAEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)

DMAEIEN - DMA Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DMAEIEN [4/4]

#define SDHC_IRQSIGEN_DMAEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)

DMAEIEN - DMA Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DTOEIEN [1/4]

#define SDHC_IRQSIGEN_DTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)

DTOEIEN - Data Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DTOEIEN [2/4]

#define SDHC_IRQSIGEN_DTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)

DTOEIEN - Data Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DTOEIEN [3/4]

#define SDHC_IRQSIGEN_DTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)

DTOEIEN - Data Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_DTOEIEN [4/4]

#define SDHC_IRQSIGEN_DTOEIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)

DTOEIEN - Data Timeout Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_TCIEN [1/4]

#define SDHC_IRQSIGEN_TCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)

TCIEN - Transfer Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_TCIEN [2/4]

#define SDHC_IRQSIGEN_TCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)

TCIEN - Transfer Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_TCIEN [3/4]

#define SDHC_IRQSIGEN_TCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)

TCIEN - Transfer Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSIGEN_TCIEN [4/4]

#define SDHC_IRQSIGEN_TCIEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)

TCIEN - Transfer Complete Interrupt Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTAT_AC12E [1/4]

#define SDHC_IRQSTAT_AC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)

AC12E - Auto CMD12 Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_AC12E [2/4]

#define SDHC_IRQSTAT_AC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)

AC12E - Auto CMD12 Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_AC12E [3/4]

#define SDHC_IRQSTAT_AC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)

AC12E - Auto CMD12 Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_AC12E [4/4]

#define SDHC_IRQSTAT_AC12E ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)

AC12E - Auto CMD12 Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_BGE [1/4]

#define SDHC_IRQSTAT_BGE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)

BGE - Block Gap Event 0b0..No block gap event. 0b1..Transaction stopped at block gap.

◆ SDHC_IRQSTAT_BGE [2/4]

#define SDHC_IRQSTAT_BGE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)

BGE - Block Gap Event 0b0..No block gap event. 0b1..Transaction stopped at block gap.

◆ SDHC_IRQSTAT_BGE [3/4]

#define SDHC_IRQSTAT_BGE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)

BGE - Block Gap Event 0b0..No block gap event. 0b1..Transaction stopped at block gap.

◆ SDHC_IRQSTAT_BGE [4/4]

#define SDHC_IRQSTAT_BGE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)

BGE - Block Gap Event 0b0..No block gap event. 0b1..Transaction stopped at block gap.

◆ SDHC_IRQSTAT_BRR [1/4]

#define SDHC_IRQSTAT_BRR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)

BRR - Buffer Read Ready 0b0..Not ready to read buffer. 0b1..Ready to read buffer.

◆ SDHC_IRQSTAT_BRR [2/4]

#define SDHC_IRQSTAT_BRR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)

BRR - Buffer Read Ready 0b0..Not ready to read buffer. 0b1..Ready to read buffer.

◆ SDHC_IRQSTAT_BRR [3/4]

#define SDHC_IRQSTAT_BRR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)

BRR - Buffer Read Ready 0b0..Not ready to read buffer. 0b1..Ready to read buffer.

◆ SDHC_IRQSTAT_BRR [4/4]

#define SDHC_IRQSTAT_BRR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)

BRR - Buffer Read Ready 0b0..Not ready to read buffer. 0b1..Ready to read buffer.

◆ SDHC_IRQSTAT_BWR [1/4]

#define SDHC_IRQSTAT_BWR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)

BWR - Buffer Write Ready 0b0..Not ready to write buffer. 0b1..Ready to write buffer.

◆ SDHC_IRQSTAT_BWR [2/4]

#define SDHC_IRQSTAT_BWR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)

BWR - Buffer Write Ready 0b0..Not ready to write buffer. 0b1..Ready to write buffer.

◆ SDHC_IRQSTAT_BWR [3/4]

#define SDHC_IRQSTAT_BWR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)

BWR - Buffer Write Ready 0b0..Not ready to write buffer. 0b1..Ready to write buffer.

◆ SDHC_IRQSTAT_BWR [4/4]

#define SDHC_IRQSTAT_BWR ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)

BWR - Buffer Write Ready 0b0..Not ready to write buffer. 0b1..Ready to write buffer.

◆ SDHC_IRQSTAT_CC [1/4]

#define SDHC_IRQSTAT_CC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)

CC - Command Complete 0b0..Command not complete. 0b1..Command complete.

◆ SDHC_IRQSTAT_CC [2/4]

#define SDHC_IRQSTAT_CC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)

CC - Command Complete 0b0..Command not complete. 0b1..Command complete.

◆ SDHC_IRQSTAT_CC [3/4]

#define SDHC_IRQSTAT_CC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)

CC - Command Complete 0b0..Command not complete. 0b1..Command complete.

◆ SDHC_IRQSTAT_CC [4/4]

#define SDHC_IRQSTAT_CC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)

CC - Command Complete 0b0..Command not complete. 0b1..Command complete.

◆ SDHC_IRQSTAT_CCE [1/4]

#define SDHC_IRQSTAT_CCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)

CCE - Command CRC Error 0b0..No error. 0b1..CRC Error generated.

◆ SDHC_IRQSTAT_CCE [2/4]

#define SDHC_IRQSTAT_CCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)

CCE - Command CRC Error 0b0..No error. 0b1..CRC Error generated.

◆ SDHC_IRQSTAT_CCE [3/4]

#define SDHC_IRQSTAT_CCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)

CCE - Command CRC Error 0b0..No error. 0b1..CRC Error generated.

◆ SDHC_IRQSTAT_CCE [4/4]

#define SDHC_IRQSTAT_CCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)

CCE - Command CRC Error 0b0..No error. 0b1..CRC Error generated.

◆ SDHC_IRQSTAT_CEBE [1/4]

#define SDHC_IRQSTAT_CEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)

CEBE - Command End Bit Error 0b0..No error. 0b1..End Bit Error generated.

◆ SDHC_IRQSTAT_CEBE [2/4]

#define SDHC_IRQSTAT_CEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)

CEBE - Command End Bit Error 0b0..No error. 0b1..End Bit Error generated.

◆ SDHC_IRQSTAT_CEBE [3/4]

#define SDHC_IRQSTAT_CEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)

CEBE - Command End Bit Error 0b0..No error. 0b1..End Bit Error generated.

◆ SDHC_IRQSTAT_CEBE [4/4]

#define SDHC_IRQSTAT_CEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)

CEBE - Command End Bit Error 0b0..No error. 0b1..End Bit Error generated.

◆ SDHC_IRQSTAT_CIE [1/4]

#define SDHC_IRQSTAT_CIE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)

CIE - Command Index Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_CIE [2/4]

#define SDHC_IRQSTAT_CIE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)

CIE - Command Index Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_CIE [3/4]

#define SDHC_IRQSTAT_CIE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)

CIE - Command Index Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_CIE [4/4]

#define SDHC_IRQSTAT_CIE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)

CIE - Command Index Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_CINS [1/4]

#define SDHC_IRQSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)

CINS - Card Insertion 0b0..Card state unstable or removed. 0b1..Card inserted.

◆ SDHC_IRQSTAT_CINS [2/4]

#define SDHC_IRQSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)

CINS - Card Insertion 0b0..Card state unstable or removed. 0b1..Card inserted.

◆ SDHC_IRQSTAT_CINS [3/4]

#define SDHC_IRQSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)

CINS - Card Insertion 0b0..Card state unstable or removed. 0b1..Card inserted.

◆ SDHC_IRQSTAT_CINS [4/4]

#define SDHC_IRQSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)

CINS - Card Insertion 0b0..Card state unstable or removed. 0b1..Card inserted.

◆ SDHC_IRQSTAT_CINT [1/4]

#define SDHC_IRQSTAT_CINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)

CINT - Card Interrupt 0b0..No Card Interrupt. 0b1..Generate Card Interrupt.

◆ SDHC_IRQSTAT_CINT [2/4]

#define SDHC_IRQSTAT_CINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)

CINT - Card Interrupt 0b0..No Card Interrupt. 0b1..Generate Card Interrupt.

◆ SDHC_IRQSTAT_CINT [3/4]

#define SDHC_IRQSTAT_CINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)

CINT - Card Interrupt 0b0..No Card Interrupt. 0b1..Generate Card Interrupt.

◆ SDHC_IRQSTAT_CINT [4/4]

#define SDHC_IRQSTAT_CINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)

CINT - Card Interrupt 0b0..No Card Interrupt. 0b1..Generate Card Interrupt.

◆ SDHC_IRQSTAT_CRM [1/4]

#define SDHC_IRQSTAT_CRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)

CRM - Card Removal 0b0..Card state unstable or inserted. 0b1..Card removed.

◆ SDHC_IRQSTAT_CRM [2/4]

#define SDHC_IRQSTAT_CRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)

CRM - Card Removal 0b0..Card state unstable or inserted. 0b1..Card removed.

◆ SDHC_IRQSTAT_CRM [3/4]

#define SDHC_IRQSTAT_CRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)

CRM - Card Removal 0b0..Card state unstable or inserted. 0b1..Card removed.

◆ SDHC_IRQSTAT_CRM [4/4]

#define SDHC_IRQSTAT_CRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)

CRM - Card Removal 0b0..Card state unstable or inserted. 0b1..Card removed.

◆ SDHC_IRQSTAT_CTOE [1/4]

#define SDHC_IRQSTAT_CTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)

CTOE - Command Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_CTOE [2/4]

#define SDHC_IRQSTAT_CTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)

CTOE - Command Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_CTOE [3/4]

#define SDHC_IRQSTAT_CTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)

CTOE - Command Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_CTOE [4/4]

#define SDHC_IRQSTAT_CTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)

CTOE - Command Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_DCE [1/4]

#define SDHC_IRQSTAT_DCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)

DCE - Data CRC Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DCE [2/4]

#define SDHC_IRQSTAT_DCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)

DCE - Data CRC Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DCE [3/4]

#define SDHC_IRQSTAT_DCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)

DCE - Data CRC Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DCE [4/4]

#define SDHC_IRQSTAT_DCE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)

DCE - Data CRC Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DEBE [1/4]

#define SDHC_IRQSTAT_DEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)

DEBE - Data End Bit Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DEBE [2/4]

#define SDHC_IRQSTAT_DEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)

DEBE - Data End Bit Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DEBE [3/4]

#define SDHC_IRQSTAT_DEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)

DEBE - Data End Bit Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DEBE [4/4]

#define SDHC_IRQSTAT_DEBE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)

DEBE - Data End Bit Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DINT [1/4]

#define SDHC_IRQSTAT_DINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)

DINT - DMA Interrupt 0b0..No DMA Interrupt. 0b1..DMA Interrupt is generated.

◆ SDHC_IRQSTAT_DINT [2/4]

#define SDHC_IRQSTAT_DINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)

DINT - DMA Interrupt 0b0..No DMA Interrupt. 0b1..DMA Interrupt is generated.

◆ SDHC_IRQSTAT_DINT [3/4]

#define SDHC_IRQSTAT_DINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)

DINT - DMA Interrupt 0b0..No DMA Interrupt. 0b1..DMA Interrupt is generated.

◆ SDHC_IRQSTAT_DINT [4/4]

#define SDHC_IRQSTAT_DINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)

DINT - DMA Interrupt 0b0..No DMA Interrupt. 0b1..DMA Interrupt is generated.

◆ SDHC_IRQSTAT_DMAE [1/4]

#define SDHC_IRQSTAT_DMAE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)

DMAE - DMA Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DMAE [2/4]

#define SDHC_IRQSTAT_DMAE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)

DMAE - DMA Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DMAE [3/4]

#define SDHC_IRQSTAT_DMAE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)

DMAE - DMA Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DMAE [4/4]

#define SDHC_IRQSTAT_DMAE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)

DMAE - DMA Error 0b0..No error. 0b1..Error.

◆ SDHC_IRQSTAT_DTOE [1/4]

#define SDHC_IRQSTAT_DTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)

DTOE - Data Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_DTOE [2/4]

#define SDHC_IRQSTAT_DTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)

DTOE - Data Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_DTOE [3/4]

#define SDHC_IRQSTAT_DTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)

DTOE - Data Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_DTOE [4/4]

#define SDHC_IRQSTAT_DTOE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)

DTOE - Data Timeout Error 0b0..No error. 0b1..Time out.

◆ SDHC_IRQSTAT_TC [1/4]

#define SDHC_IRQSTAT_TC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)

TC - Transfer Complete 0b0..Transfer not complete. 0b1..Transfer complete.

◆ SDHC_IRQSTAT_TC [2/4]

#define SDHC_IRQSTAT_TC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)

TC - Transfer Complete 0b0..Transfer not complete. 0b1..Transfer complete.

◆ SDHC_IRQSTAT_TC [3/4]

#define SDHC_IRQSTAT_TC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)

TC - Transfer Complete 0b0..Transfer not complete. 0b1..Transfer complete.

◆ SDHC_IRQSTAT_TC [4/4]

#define SDHC_IRQSTAT_TC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)

TC - Transfer Complete 0b0..Transfer not complete. 0b1..Transfer complete.

◆ SDHC_IRQSTATEN_AC12ESEN [1/4]

#define SDHC_IRQSTATEN_AC12ESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_AC12ESEN [2/4]

#define SDHC_IRQSTATEN_AC12ESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_AC12ESEN [3/4]

#define SDHC_IRQSTATEN_AC12ESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_AC12ESEN [4/4]

#define SDHC_IRQSTATEN_AC12ESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BGESEN [1/4]

#define SDHC_IRQSTATEN_BGESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)

BGESEN - Block Gap Event Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BGESEN [2/4]

#define SDHC_IRQSTATEN_BGESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)

BGESEN - Block Gap Event Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BGESEN [3/4]

#define SDHC_IRQSTATEN_BGESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)

BGESEN - Block Gap Event Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BGESEN [4/4]

#define SDHC_IRQSTATEN_BGESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)

BGESEN - Block Gap Event Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BRRSEN [1/4]

#define SDHC_IRQSTATEN_BRRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)

BRRSEN - Buffer Read Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BRRSEN [2/4]

#define SDHC_IRQSTATEN_BRRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)

BRRSEN - Buffer Read Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BRRSEN [3/4]

#define SDHC_IRQSTATEN_BRRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)

BRRSEN - Buffer Read Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BRRSEN [4/4]

#define SDHC_IRQSTATEN_BRRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)

BRRSEN - Buffer Read Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BWRSEN [1/4]

#define SDHC_IRQSTATEN_BWRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)

BWRSEN - Buffer Write Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BWRSEN [2/4]

#define SDHC_IRQSTATEN_BWRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)

BWRSEN - Buffer Write Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BWRSEN [3/4]

#define SDHC_IRQSTATEN_BWRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)

BWRSEN - Buffer Write Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_BWRSEN [4/4]

#define SDHC_IRQSTATEN_BWRSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)

BWRSEN - Buffer Write Ready Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCESEN [1/4]

#define SDHC_IRQSTATEN_CCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)

CCESEN - Command CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCESEN [2/4]

#define SDHC_IRQSTATEN_CCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)

CCESEN - Command CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCESEN [3/4]

#define SDHC_IRQSTATEN_CCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)

CCESEN - Command CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCESEN [4/4]

#define SDHC_IRQSTATEN_CCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)

CCESEN - Command CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCSEN [1/4]

#define SDHC_IRQSTATEN_CCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)

CCSEN - Command Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCSEN [2/4]

#define SDHC_IRQSTATEN_CCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)

CCSEN - Command Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCSEN [3/4]

#define SDHC_IRQSTATEN_CCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)

CCSEN - Command Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CCSEN [4/4]

#define SDHC_IRQSTATEN_CCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)

CCSEN - Command Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CEBESEN [1/4]

#define SDHC_IRQSTATEN_CEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)

CEBESEN - Command End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CEBESEN [2/4]

#define SDHC_IRQSTATEN_CEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)

CEBESEN - Command End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CEBESEN [3/4]

#define SDHC_IRQSTATEN_CEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)

CEBESEN - Command End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CEBESEN [4/4]

#define SDHC_IRQSTATEN_CEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)

CEBESEN - Command End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CIESEN [1/4]

#define SDHC_IRQSTATEN_CIESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)

CIESEN - Command Index Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CIESEN [2/4]

#define SDHC_IRQSTATEN_CIESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)

CIESEN - Command Index Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CIESEN [3/4]

#define SDHC_IRQSTATEN_CIESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)

CIESEN - Command Index Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CIESEN [4/4]

#define SDHC_IRQSTATEN_CIESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)

CIESEN - Command Index Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINSEN [1/4]

#define SDHC_IRQSTATEN_CINSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)

CINSEN - Card Insertion Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINSEN [2/4]

#define SDHC_IRQSTATEN_CINSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)

CINSEN - Card Insertion Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINSEN [3/4]

#define SDHC_IRQSTATEN_CINSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)

CINSEN - Card Insertion Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINSEN [4/4]

#define SDHC_IRQSTATEN_CINSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)

CINSEN - Card Insertion Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINTSEN [1/4]

#define SDHC_IRQSTATEN_CINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)

CINTSEN - Card Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINTSEN [2/4]

#define SDHC_IRQSTATEN_CINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)

CINTSEN - Card Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINTSEN [3/4]

#define SDHC_IRQSTATEN_CINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)

CINTSEN - Card Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CINTSEN [4/4]

#define SDHC_IRQSTATEN_CINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)

CINTSEN - Card Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CRMSEN [1/4]

#define SDHC_IRQSTATEN_CRMSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)

CRMSEN - Card Removal Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CRMSEN [2/4]

#define SDHC_IRQSTATEN_CRMSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)

CRMSEN - Card Removal Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CRMSEN [3/4]

#define SDHC_IRQSTATEN_CRMSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)

CRMSEN - Card Removal Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CRMSEN [4/4]

#define SDHC_IRQSTATEN_CRMSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)

CRMSEN - Card Removal Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CTOESEN [1/4]

#define SDHC_IRQSTATEN_CTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)

CTOESEN - Command Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CTOESEN [2/4]

#define SDHC_IRQSTATEN_CTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)

CTOESEN - Command Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CTOESEN [3/4]

#define SDHC_IRQSTATEN_CTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)

CTOESEN - Command Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_CTOESEN [4/4]

#define SDHC_IRQSTATEN_CTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)

CTOESEN - Command Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DCESEN [1/4]

#define SDHC_IRQSTATEN_DCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)

DCESEN - Data CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DCESEN [2/4]

#define SDHC_IRQSTATEN_DCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)

DCESEN - Data CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DCESEN [3/4]

#define SDHC_IRQSTATEN_DCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)

DCESEN - Data CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DCESEN [4/4]

#define SDHC_IRQSTATEN_DCESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)

DCESEN - Data CRC Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DEBESEN [1/4]

#define SDHC_IRQSTATEN_DEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)

DEBESEN - Data End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DEBESEN [2/4]

#define SDHC_IRQSTATEN_DEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)

DEBESEN - Data End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DEBESEN [3/4]

#define SDHC_IRQSTATEN_DEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)

DEBESEN - Data End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DEBESEN [4/4]

#define SDHC_IRQSTATEN_DEBESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)

DEBESEN - Data End Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DINTSEN [1/4]

#define SDHC_IRQSTATEN_DINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)

DINTSEN - DMA Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DINTSEN [2/4]

#define SDHC_IRQSTATEN_DINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)

DINTSEN - DMA Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DINTSEN [3/4]

#define SDHC_IRQSTATEN_DINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)

DINTSEN - DMA Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DINTSEN [4/4]

#define SDHC_IRQSTATEN_DINTSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)

DINTSEN - DMA Interrupt Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DMAESEN [1/4]

#define SDHC_IRQSTATEN_DMAESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)

DMAESEN - DMA Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DMAESEN [2/4]

#define SDHC_IRQSTATEN_DMAESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)

DMAESEN - DMA Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DMAESEN [3/4]

#define SDHC_IRQSTATEN_DMAESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)

DMAESEN - DMA Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DMAESEN [4/4]

#define SDHC_IRQSTATEN_DMAESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)

DMAESEN - DMA Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DTOESEN [1/4]

#define SDHC_IRQSTATEN_DTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)

DTOESEN - Data Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DTOESEN [2/4]

#define SDHC_IRQSTATEN_DTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)

DTOESEN - Data Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DTOESEN [3/4]

#define SDHC_IRQSTATEN_DTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)

DTOESEN - Data Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_DTOESEN [4/4]

#define SDHC_IRQSTATEN_DTOESEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)

DTOESEN - Data Timeout Error Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_TCSEN [1/4]

#define SDHC_IRQSTATEN_TCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)

TCSEN - Transfer Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_TCSEN [2/4]

#define SDHC_IRQSTATEN_TCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)

TCSEN - Transfer Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_TCSEN [3/4]

#define SDHC_IRQSTATEN_TCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)

TCSEN - Transfer Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_IRQSTATEN_TCSEN [4/4]

#define SDHC_IRQSTATEN_TCSEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)

TCSEN - Transfer Complete Status Enable 0b0..Masked 0b1..Enabled

◆ SDHC_MMCBOOT_BOOTACK [1/4]

#define SDHC_MMCBOOT_BOOTACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)

BOOTACK - Boot Ack Mode Select 0b0..No ack. 0b1..Ack.

◆ SDHC_MMCBOOT_BOOTACK [2/4]

#define SDHC_MMCBOOT_BOOTACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)

BOOTACK - Boot Ack Mode Select 0b0..No ack. 0b1..Ack.

◆ SDHC_MMCBOOT_BOOTACK [3/4]

#define SDHC_MMCBOOT_BOOTACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)

BOOTACK - Boot Ack Mode Select 0b0..No ack. 0b1..Ack.

◆ SDHC_MMCBOOT_BOOTACK [4/4]

#define SDHC_MMCBOOT_BOOTACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)

BOOTACK - Boot Ack Mode Select 0b0..No ack. 0b1..Ack.

◆ SDHC_MMCBOOT_BOOTEN [1/4]

#define SDHC_MMCBOOT_BOOTEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)

BOOTEN - Boot Mode Enable 0b0..Fast boot disable. 0b1..Fast boot enable.

◆ SDHC_MMCBOOT_BOOTEN [2/4]

#define SDHC_MMCBOOT_BOOTEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)

BOOTEN - Boot Mode Enable 0b0..Fast boot disable. 0b1..Fast boot enable.

◆ SDHC_MMCBOOT_BOOTEN [3/4]

#define SDHC_MMCBOOT_BOOTEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)

BOOTEN - Boot Mode Enable 0b0..Fast boot disable. 0b1..Fast boot enable.

◆ SDHC_MMCBOOT_BOOTEN [4/4]

#define SDHC_MMCBOOT_BOOTEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)

BOOTEN - Boot Mode Enable 0b0..Fast boot disable. 0b1..Fast boot enable.

◆ SDHC_MMCBOOT_BOOTMODE [1/4]

#define SDHC_MMCBOOT_BOOTMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)

BOOTMODE - Boot Mode Select 0b0..Normal boot. 0b1..Alternative boot.

◆ SDHC_MMCBOOT_BOOTMODE [2/4]

#define SDHC_MMCBOOT_BOOTMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)

BOOTMODE - Boot Mode Select 0b0..Normal boot. 0b1..Alternative boot.

◆ SDHC_MMCBOOT_BOOTMODE [3/4]

#define SDHC_MMCBOOT_BOOTMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)

BOOTMODE - Boot Mode Select 0b0..Normal boot. 0b1..Alternative boot.

◆ SDHC_MMCBOOT_BOOTMODE [4/4]

#define SDHC_MMCBOOT_BOOTMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)

BOOTMODE - Boot Mode Select 0b0..Normal boot. 0b1..Alternative boot.

◆ SDHC_MMCBOOT_DTOCVACK [1/5]

#define SDHC_MMCBOOT_DTOCVACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)

DTOCVACK - Boot ACK Time Out Counter Value 0b0000..SDCLK x 2^8 0b0001..SDCLK x 2^9 0b0010..SDCLK x 2^10 0b0011..SDCLK x 2^11 0b0100..SDCLK x 2^12 0b0101..SDCLK x 2^13 0b0110..SDCLK x 2^14 0b0111..SDCLK x 2^15 0b1110..SDCLK x 2^22 0b1111..Reserved

◆ SDHC_MMCBOOT_DTOCVACK [2/5]

#define SDHC_MMCBOOT_DTOCVACK ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)

DTOCVACK - Boot ACK Time Out Counter Value 0b0000..SDCLK x 2^8 0b0001..SDCLK x 2^9 0b0010..SDCLK x 2^10 0b0011..SDCLK x 2^11 0b0100..SDCLK x 2^12 0b0101..SDCLK x 2^13 0b0110..SDCLK x 2^14 0b0111..SDCLK x 2^15 0b1110..SDCLK x 2^22 0b1111..Reserved

◆ SDHC_MMCBOOT_DTOCVACK [3/5]

#define SDHC_MMCBOOT_DTOCVACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)

DTOCVACK - Boot ACK Time Out Counter Value 0b0000..SDCLK x 2^8 0b0001..SDCLK x 2^9 0b0010..SDCLK x 2^10 0b0011..SDCLK x 2^11 0b0100..SDCLK x 2^12 0b0101..SDCLK x 2^13 0b0110..SDCLK x 2^14 0b0111..SDCLK x 2^15 0b1110..SDCLK x 2^22 0b1111..Reserved

◆ SDHC_MMCBOOT_DTOCVACK [4/5]

#define SDHC_MMCBOOT_DTOCVACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)

DTOCVACK - Boot ACK Time Out Counter Value 0b0000..SDCLK x 2^8 0b0001..SDCLK x 2^9 0b0010..SDCLK x 2^10 0b0011..SDCLK x 2^11 0b0100..SDCLK x 2^12 0b0101..SDCLK x 2^13 0b0110..SDCLK x 2^14 0b0111..SDCLK x 2^15 0b1110..SDCLK x 2^22 0b1111..Reserved

◆ SDHC_MMCBOOT_DTOCVACK [5/5]

#define SDHC_MMCBOOT_DTOCVACK ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)

DTOCVACK - Boot ACK Time Out Counter Value 0b0000..SDCLK x 2^8 0b0001..SDCLK x 2^9 0b0010..SDCLK x 2^10 0b0011..SDCLK x 2^11 0b0100..SDCLK x 2^12 0b0101..SDCLK x 2^13 0b0110..SDCLK x 2^14 0b0111..SDCLK x 2^15 0b1110..SDCLK x 2^22 0b1111..Reserved

◆ SDHC_PROCTL_CDSS [1/4]

#define SDHC_PROCTL_CDSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)

CDSS - Card Detect Signal Selection 0b0..Card detection level is selected for normal purpose. 0b1..Card detection test level is selected for test purpose.

◆ SDHC_PROCTL_CDSS [2/4]

#define SDHC_PROCTL_CDSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)

CDSS - Card Detect Signal Selection 0b0..Card detection level is selected for normal purpose. 0b1..Card detection test level is selected for test purpose.

◆ SDHC_PROCTL_CDSS [3/4]

#define SDHC_PROCTL_CDSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)

CDSS - Card Detect Signal Selection 0b0..Card detection level is selected for normal purpose. 0b1..Card detection test level is selected for test purpose.

◆ SDHC_PROCTL_CDSS [4/4]

#define SDHC_PROCTL_CDSS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)

CDSS - Card Detect Signal Selection 0b0..Card detection level is selected for normal purpose. 0b1..Card detection test level is selected for test purpose.

◆ SDHC_PROCTL_CDTL [1/4]

#define SDHC_PROCTL_CDTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)

CDTL - Card Detect Test Level 0b0..Card detect test level is 0, no card inserted. 0b1..Card detect test level is 1, card inserted.

◆ SDHC_PROCTL_CDTL [2/4]

#define SDHC_PROCTL_CDTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)

CDTL - Card Detect Test Level 0b0..Card detect test level is 0, no card inserted. 0b1..Card detect test level is 1, card inserted.

◆ SDHC_PROCTL_CDTL [3/4]

#define SDHC_PROCTL_CDTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)

CDTL - Card Detect Test Level 0b0..Card detect test level is 0, no card inserted. 0b1..Card detect test level is 1, card inserted.

◆ SDHC_PROCTL_CDTL [4/4]

#define SDHC_PROCTL_CDTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)

CDTL - Card Detect Test Level 0b0..Card detect test level is 0, no card inserted. 0b1..Card detect test level is 1, card inserted.

◆ SDHC_PROCTL_CREQ [1/4]

#define SDHC_PROCTL_CREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)

CREQ - Continue Request 0b0..No effect. 0b1..Restart

◆ SDHC_PROCTL_CREQ [2/4]

#define SDHC_PROCTL_CREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)

CREQ - Continue Request 0b0..No effect. 0b1..Restart

◆ SDHC_PROCTL_CREQ [3/4]

#define SDHC_PROCTL_CREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)

CREQ - Continue Request 0b0..No effect. 0b1..Restart

◆ SDHC_PROCTL_CREQ [4/4]

#define SDHC_PROCTL_CREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)

CREQ - Continue Request 0b0..No effect. 0b1..Restart

◆ SDHC_PROCTL_D3CD [1/4]

#define SDHC_PROCTL_D3CD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)

D3CD - DAT3 As Card Detection Pin 0b0..DAT3 does not monitor card Insertion. 0b1..DAT3 as card detection pin.

◆ SDHC_PROCTL_D3CD [2/4]

#define SDHC_PROCTL_D3CD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)

D3CD - DAT3 As Card Detection Pin 0b0..DAT3 does not monitor card Insertion. 0b1..DAT3 as card detection pin.

◆ SDHC_PROCTL_D3CD [3/4]

#define SDHC_PROCTL_D3CD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)

D3CD - DAT3 As Card Detection Pin 0b0..DAT3 does not monitor card Insertion. 0b1..DAT3 as card detection pin.

◆ SDHC_PROCTL_D3CD [4/4]

#define SDHC_PROCTL_D3CD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)

D3CD - DAT3 As Card Detection Pin 0b0..DAT3 does not monitor card Insertion. 0b1..DAT3 as card detection pin.

◆ SDHC_PROCTL_DMAS [1/5]

#define SDHC_PROCTL_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)

DMAS - DMA Select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ SDHC_PROCTL_DMAS [2/5]

#define SDHC_PROCTL_DMAS ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)

DMAS - DMA Select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ SDHC_PROCTL_DMAS [3/5]

#define SDHC_PROCTL_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)

DMAS - DMA Select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ SDHC_PROCTL_DMAS [4/5]

#define SDHC_PROCTL_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)

DMAS - DMA Select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ SDHC_PROCTL_DMAS [5/5]

#define SDHC_PROCTL_DMAS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)

DMAS - DMA Select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ SDHC_PROCTL_DTW [1/5]

#define SDHC_PROCTL_DTW ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)

DTW - Data Transfer Width 0b00..1-bit mode 0b01..4-bit mode 0b10..8-bit mode 0b11..Reserved

◆ SDHC_PROCTL_DTW [2/5]

#define SDHC_PROCTL_DTW ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)

DTW - Data Transfer Width 0b00..1-bit mode 0b01..4-bit mode 0b10..8-bit mode 0b11..Reserved

◆ SDHC_PROCTL_DTW [3/5]

#define SDHC_PROCTL_DTW ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)

DTW - Data Transfer Width 0b00..1-bit mode 0b01..4-bit mode 0b10..8-bit mode 0b11..Reserved

◆ SDHC_PROCTL_DTW [4/5]

#define SDHC_PROCTL_DTW ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)

DTW - Data Transfer Width 0b00..1-bit mode 0b01..4-bit mode 0b10..8-bit mode 0b11..Reserved

◆ SDHC_PROCTL_DTW [5/5]

#define SDHC_PROCTL_DTW ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)

DTW - Data Transfer Width 0b00..1-bit mode 0b01..4-bit mode 0b10..8-bit mode 0b11..Reserved

◆ SDHC_PROCTL_EMODE [1/5]

#define SDHC_PROCTL_EMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)

EMODE - Endian Mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ SDHC_PROCTL_EMODE [2/5]

#define SDHC_PROCTL_EMODE ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)

EMODE - Endian Mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ SDHC_PROCTL_EMODE [3/5]

#define SDHC_PROCTL_EMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)

EMODE - Endian Mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ SDHC_PROCTL_EMODE [4/5]

#define SDHC_PROCTL_EMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)

EMODE - Endian Mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ SDHC_PROCTL_EMODE [5/5]

#define SDHC_PROCTL_EMODE ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)

EMODE - Endian Mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ SDHC_PROCTL_IABG [1/4]

#define SDHC_PROCTL_IABG ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)

IABG - Interrupt At Block Gap 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_IABG [2/4]

#define SDHC_PROCTL_IABG ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)

IABG - Interrupt At Block Gap 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_IABG [3/4]

#define SDHC_PROCTL_IABG ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)

IABG - Interrupt At Block Gap 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_IABG [4/4]

#define SDHC_PROCTL_IABG ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)

IABG - Interrupt At Block Gap 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_LCTL [1/4]

#define SDHC_PROCTL_LCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)

LCTL - LED Control 0b0..LED off. 0b1..LED on.

◆ SDHC_PROCTL_LCTL [2/4]

#define SDHC_PROCTL_LCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)

LCTL - LED Control 0b0..LED off. 0b1..LED on.

◆ SDHC_PROCTL_LCTL [3/4]

#define SDHC_PROCTL_LCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)

LCTL - LED Control 0b0..LED off. 0b1..LED on.

◆ SDHC_PROCTL_LCTL [4/4]

#define SDHC_PROCTL_LCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)

LCTL - LED Control 0b0..LED off. 0b1..LED on.

◆ SDHC_PROCTL_RWCTL [1/4]

#define SDHC_PROCTL_RWCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)

RWCTL - Read Wait Control 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set. 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.

◆ SDHC_PROCTL_RWCTL [2/4]

#define SDHC_PROCTL_RWCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)

RWCTL - Read Wait Control 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set. 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.

◆ SDHC_PROCTL_RWCTL [3/4]

#define SDHC_PROCTL_RWCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)

RWCTL - Read Wait Control 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set. 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.

◆ SDHC_PROCTL_RWCTL [4/4]

#define SDHC_PROCTL_RWCTL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)

RWCTL - Read Wait Control 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set. 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.

◆ SDHC_PROCTL_SABGREQ [1/4]

#define SDHC_PROCTL_SABGREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)

SABGREQ - Stop At Block Gap Request 0b0..Transfer 0b1..Stop

◆ SDHC_PROCTL_SABGREQ [2/4]

#define SDHC_PROCTL_SABGREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)

SABGREQ - Stop At Block Gap Request 0b0..Transfer 0b1..Stop

◆ SDHC_PROCTL_SABGREQ [3/4]

#define SDHC_PROCTL_SABGREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)

SABGREQ - Stop At Block Gap Request 0b0..Transfer 0b1..Stop

◆ SDHC_PROCTL_SABGREQ [4/4]

#define SDHC_PROCTL_SABGREQ ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)

SABGREQ - Stop At Block Gap Request 0b0..Transfer 0b1..Stop

◆ SDHC_PROCTL_WECINS [1/4]

#define SDHC_PROCTL_WECINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)

WECINS - Wakeup Event Enable On SD Card Insertion 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINS [2/4]

#define SDHC_PROCTL_WECINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)

WECINS - Wakeup Event Enable On SD Card Insertion 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINS [3/4]

#define SDHC_PROCTL_WECINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)

WECINS - Wakeup Event Enable On SD Card Insertion 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINS [4/4]

#define SDHC_PROCTL_WECINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)

WECINS - Wakeup Event Enable On SD Card Insertion 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINT [1/4]

#define SDHC_PROCTL_WECINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)

WECINT - Wakeup Event Enable On Card Interrupt 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINT [2/4]

#define SDHC_PROCTL_WECINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)

WECINT - Wakeup Event Enable On Card Interrupt 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINT [3/4]

#define SDHC_PROCTL_WECINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)

WECINT - Wakeup Event Enable On Card Interrupt 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECINT [4/4]

#define SDHC_PROCTL_WECINT ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)

WECINT - Wakeup Event Enable On Card Interrupt 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECRM [1/4]

#define SDHC_PROCTL_WECRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)

WECRM - Wakeup Event Enable On SD Card Removal 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECRM [2/4]

#define SDHC_PROCTL_WECRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)

WECRM - Wakeup Event Enable On SD Card Removal 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECRM [3/4]

#define SDHC_PROCTL_WECRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)

WECRM - Wakeup Event Enable On SD Card Removal 0b0..Disabled 0b1..Enabled

◆ SDHC_PROCTL_WECRM [4/4]

#define SDHC_PROCTL_WECRM ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)

WECRM - Wakeup Event Enable On SD Card Removal 0b0..Disabled 0b1..Enabled

◆ SDHC_PRSSTAT_BREN [1/4]

#define SDHC_PRSSTAT_BREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)

BREN - Buffer Read Enable 0b0..Read disable, valid data less than the watermark level exist in the buffer. 0b1..Read enable, valid data greater than the watermark level exist in the buffer.

◆ SDHC_PRSSTAT_BREN [2/4]

#define SDHC_PRSSTAT_BREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)

BREN - Buffer Read Enable 0b0..Read disable, valid data less than the watermark level exist in the buffer. 0b1..Read enable, valid data greater than the watermark level exist in the buffer.

◆ SDHC_PRSSTAT_BREN [3/4]

#define SDHC_PRSSTAT_BREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)

BREN - Buffer Read Enable 0b0..Read disable, valid data less than the watermark level exist in the buffer. 0b1..Read enable, valid data greater than the watermark level exist in the buffer.

◆ SDHC_PRSSTAT_BREN [4/4]

#define SDHC_PRSSTAT_BREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)

BREN - Buffer Read Enable 0b0..Read disable, valid data less than the watermark level exist in the buffer. 0b1..Read enable, valid data greater than the watermark level exist in the buffer.

◆ SDHC_PRSSTAT_BWEN [1/4]

#define SDHC_PRSSTAT_BWEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)

BWEN - Buffer Write Enable 0b0..Write disable, the buffer can hold valid data less than the write watermark level. 0b1..Write enable, the buffer can hold valid data greater than the write watermark level.

◆ SDHC_PRSSTAT_BWEN [2/4]

#define SDHC_PRSSTAT_BWEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)

BWEN - Buffer Write Enable 0b0..Write disable, the buffer can hold valid data less than the write watermark level. 0b1..Write enable, the buffer can hold valid data greater than the write watermark level.

◆ SDHC_PRSSTAT_BWEN [3/4]

#define SDHC_PRSSTAT_BWEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)

BWEN - Buffer Write Enable 0b0..Write disable, the buffer can hold valid data less than the write watermark level. 0b1..Write enable, the buffer can hold valid data greater than the write watermark level.

◆ SDHC_PRSSTAT_BWEN [4/4]

#define SDHC_PRSSTAT_BWEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)

BWEN - Buffer Write Enable 0b0..Write disable, the buffer can hold valid data less than the write watermark level. 0b1..Write enable, the buffer can hold valid data greater than the write watermark level.

◆ SDHC_PRSSTAT_CDIHB [1/4]

#define SDHC_PRSSTAT_CDIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)

CDIHB - Command Inhibit (DAT) 0b0..Can issue command which uses the DAT line. 0b1..Cannot issue command which uses the DAT line.

◆ SDHC_PRSSTAT_CDIHB [2/4]

#define SDHC_PRSSTAT_CDIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)

CDIHB - Command Inhibit (DAT) 0b0..Can issue command which uses the DAT line. 0b1..Cannot issue command which uses the DAT line.

◆ SDHC_PRSSTAT_CDIHB [3/4]

#define SDHC_PRSSTAT_CDIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)

CDIHB - Command Inhibit (DAT) 0b0..Can issue command which uses the DAT line. 0b1..Cannot issue command which uses the DAT line.

◆ SDHC_PRSSTAT_CDIHB [4/4]

#define SDHC_PRSSTAT_CDIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)

CDIHB - Command Inhibit (DAT) 0b0..Can issue command which uses the DAT line. 0b1..Cannot issue command which uses the DAT line.

◆ SDHC_PRSSTAT_CIHB [1/4]

#define SDHC_PRSSTAT_CIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)

CIHB - Command Inhibit (CMD) 0b0..Can issue command using only CMD line. 0b1..Cannot issue command.

◆ SDHC_PRSSTAT_CIHB [2/4]

#define SDHC_PRSSTAT_CIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)

CIHB - Command Inhibit (CMD) 0b0..Can issue command using only CMD line. 0b1..Cannot issue command.

◆ SDHC_PRSSTAT_CIHB [3/4]

#define SDHC_PRSSTAT_CIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)

CIHB - Command Inhibit (CMD) 0b0..Can issue command using only CMD line. 0b1..Cannot issue command.

◆ SDHC_PRSSTAT_CIHB [4/4]

#define SDHC_PRSSTAT_CIHB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)

CIHB - Command Inhibit (CMD) 0b0..Can issue command using only CMD line. 0b1..Cannot issue command.

◆ SDHC_PRSSTAT_CINS [1/4]

#define SDHC_PRSSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)

CINS - Card Inserted 0b0..Power on reset or no card. 0b1..Card inserted.

◆ SDHC_PRSSTAT_CINS [2/4]

#define SDHC_PRSSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)

CINS - Card Inserted 0b0..Power on reset or no card. 0b1..Card inserted.

◆ SDHC_PRSSTAT_CINS [3/4]

#define SDHC_PRSSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)

CINS - Card Inserted 0b0..Power on reset or no card. 0b1..Card inserted.

◆ SDHC_PRSSTAT_CINS [4/4]

#define SDHC_PRSSTAT_CINS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)

CINS - Card Inserted 0b0..Power on reset or no card. 0b1..Card inserted.

◆ SDHC_PRSSTAT_DLA [1/4]

#define SDHC_PRSSTAT_DLA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)

DLA - Data Line Active 0b0..DAT line inactive. 0b1..DAT line active.

◆ SDHC_PRSSTAT_DLA [2/4]

#define SDHC_PRSSTAT_DLA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)

DLA - Data Line Active 0b0..DAT line inactive. 0b1..DAT line active.

◆ SDHC_PRSSTAT_DLA [3/4]

#define SDHC_PRSSTAT_DLA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)

DLA - Data Line Active 0b0..DAT line inactive. 0b1..DAT line active.

◆ SDHC_PRSSTAT_DLA [4/4]

#define SDHC_PRSSTAT_DLA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)

DLA - Data Line Active 0b0..DAT line inactive. 0b1..DAT line active.

◆ SDHC_PRSSTAT_HCKOFF [1/4]

#define SDHC_PRSSTAT_HCKOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)

HCKOFF - System Clock Gated Off Internally 0b0..System clock is active. 0b1..System clock is gated off.

◆ SDHC_PRSSTAT_HCKOFF [2/4]

#define SDHC_PRSSTAT_HCKOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)

HCKOFF - System Clock Gated Off Internally 0b0..System clock is active. 0b1..System clock is gated off.

◆ SDHC_PRSSTAT_HCKOFF [3/4]

#define SDHC_PRSSTAT_HCKOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)

HCKOFF - System Clock Gated Off Internally 0b0..System clock is active. 0b1..System clock is gated off.

◆ SDHC_PRSSTAT_HCKOFF [4/4]

#define SDHC_PRSSTAT_HCKOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)

HCKOFF - System Clock Gated Off Internally 0b0..System clock is active. 0b1..System clock is gated off.

◆ SDHC_PRSSTAT_IPGOFF [1/4]

#define SDHC_PRSSTAT_IPGOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)

IPGOFF - Bus Clock Gated Off Internally 0b0..Bus clock is active. 0b1..Bus clock is gated off.

◆ SDHC_PRSSTAT_IPGOFF [2/4]

#define SDHC_PRSSTAT_IPGOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)

IPGOFF - Bus Clock Gated Off Internally 0b0..Bus clock is active. 0b1..Bus clock is gated off.

◆ SDHC_PRSSTAT_IPGOFF [3/4]

#define SDHC_PRSSTAT_IPGOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)

IPGOFF - Bus Clock Gated Off Internally 0b0..Bus clock is active. 0b1..Bus clock is gated off.

◆ SDHC_PRSSTAT_IPGOFF [4/4]

#define SDHC_PRSSTAT_IPGOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)

IPGOFF - Bus Clock Gated Off Internally 0b0..Bus clock is active. 0b1..Bus clock is gated off.

◆ SDHC_PRSSTAT_PEROFF [1/4]

#define SDHC_PRSSTAT_PEROFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)

PEROFF - SDHC clock Gated Off Internally 0b0..SDHC clock is active. 0b1..SDHC clock is gated off.

◆ SDHC_PRSSTAT_PEROFF [2/4]

#define SDHC_PRSSTAT_PEROFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)

PEROFF - SDHC clock Gated Off Internally 0b0..SDHC clock is active. 0b1..SDHC clock is gated off.

◆ SDHC_PRSSTAT_PEROFF [3/4]

#define SDHC_PRSSTAT_PEROFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)

PEROFF - SDHC clock Gated Off Internally 0b0..SDHC clock is active. 0b1..SDHC clock is gated off.

◆ SDHC_PRSSTAT_PEROFF [4/4]

#define SDHC_PRSSTAT_PEROFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)

PEROFF - SDHC clock Gated Off Internally 0b0..SDHC clock is active. 0b1..SDHC clock is gated off.

◆ SDHC_PRSSTAT_RTA [1/4]

#define SDHC_PRSSTAT_RTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)

RTA - Read Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_RTA [2/4]

#define SDHC_PRSSTAT_RTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)

RTA - Read Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_RTA [3/4]

#define SDHC_PRSSTAT_RTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)

RTA - Read Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_RTA [4/4]

#define SDHC_PRSSTAT_RTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)

RTA - Read Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_SDOFF [1/4]

#define SDHC_PRSSTAT_SDOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)

SDOFF - SD Clock Gated Off Internally 0b0..SD clock is active. 0b1..SD clock is gated off.

◆ SDHC_PRSSTAT_SDOFF [2/4]

#define SDHC_PRSSTAT_SDOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)

SDOFF - SD Clock Gated Off Internally 0b0..SD clock is active. 0b1..SD clock is gated off.

◆ SDHC_PRSSTAT_SDOFF [3/4]

#define SDHC_PRSSTAT_SDOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)

SDOFF - SD Clock Gated Off Internally 0b0..SD clock is active. 0b1..SD clock is gated off.

◆ SDHC_PRSSTAT_SDOFF [4/4]

#define SDHC_PRSSTAT_SDOFF ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)

SDOFF - SD Clock Gated Off Internally 0b0..SD clock is active. 0b1..SD clock is gated off.

◆ SDHC_PRSSTAT_SDSTB [1/4]

#define SDHC_PRSSTAT_SDSTB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)

SDSTB - SD Clock Stable 0b0..Clock is changing frequency and not stable. 0b1..Clock is stable.

◆ SDHC_PRSSTAT_SDSTB [2/4]

#define SDHC_PRSSTAT_SDSTB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)

SDSTB - SD Clock Stable 0b0..Clock is changing frequency and not stable. 0b1..Clock is stable.

◆ SDHC_PRSSTAT_SDSTB [3/4]

#define SDHC_PRSSTAT_SDSTB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)

SDSTB - SD Clock Stable 0b0..Clock is changing frequency and not stable. 0b1..Clock is stable.

◆ SDHC_PRSSTAT_SDSTB [4/4]

#define SDHC_PRSSTAT_SDSTB ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)

SDSTB - SD Clock Stable 0b0..Clock is changing frequency and not stable. 0b1..Clock is stable.

◆ SDHC_PRSSTAT_WTA [1/4]

#define SDHC_PRSSTAT_WTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)

WTA - Write Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_WTA [2/4]

#define SDHC_PRSSTAT_WTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)

WTA - Write Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_WTA [3/4]

#define SDHC_PRSSTAT_WTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)

WTA - Write Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_PRSSTAT_WTA [4/4]

#define SDHC_PRSSTAT_WTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)

WTA - Write Transfer Active 0b0..No valid data. 0b1..Transferring data.

◆ SDHC_SYSCTL_DTOCV [1/5]

#define SDHC_SYSCTL_DTOCV ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)

DTOCV - Data Timeout Counter Value 0b0000..SDCLK x 2 13 0b0001..SDCLK x 2 14 0b1110..SDCLK x 2 27 0b1111..Reserved

◆ SDHC_SYSCTL_DTOCV [2/5]

#define SDHC_SYSCTL_DTOCV ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)

DTOCV - Data Timeout Counter Value 0b0000..SDCLK x 2 13 0b0001..SDCLK x 2 14 0b1110..SDCLK x 2 27 0b1111..Reserved

◆ SDHC_SYSCTL_DTOCV [3/5]

#define SDHC_SYSCTL_DTOCV ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)

DTOCV - Data Timeout Counter Value 0b0000..SDCLK x 2 13 0b0001..SDCLK x 2 14 0b1110..SDCLK x 2 27 0b1111..Reserved

◆ SDHC_SYSCTL_DTOCV [4/5]

#define SDHC_SYSCTL_DTOCV ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)

DTOCV - Data Timeout Counter Value 0b0000..SDCLK x 2 13 0b0001..SDCLK x 2 14 0b1110..SDCLK x 2 27 0b1111..Reserved

◆ SDHC_SYSCTL_DTOCV [5/5]

#define SDHC_SYSCTL_DTOCV ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)

DTOCV - Data Timeout Counter Value 0b0000..SDCLK x 2 13 0b0001..SDCLK x 2 14 0b1110..SDCLK x 2 27 0b1111..Reserved

◆ SDHC_SYSCTL_DVS [1/5]

#define SDHC_SYSCTL_DVS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)

DVS - Divisor 0b0000..Divisor by 1. 0b0001..Divisor by 2. 0b1110..Divisor by 15. 0b1111..Divisor by 16.

◆ SDHC_SYSCTL_DVS [2/5]

#define SDHC_SYSCTL_DVS ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)

DVS - Divisor 0b0000..Divisor by 1. 0b0001..Divisor by 2. 0b1110..Divisor by 15. 0b1111..Divisor by 16.

◆ SDHC_SYSCTL_DVS [3/5]

#define SDHC_SYSCTL_DVS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)

DVS - Divisor 0b0000..Divisor by 1. 0b0001..Divisor by 2. 0b1110..Divisor by 15. 0b1111..Divisor by 16.

◆ SDHC_SYSCTL_DVS [4/5]

#define SDHC_SYSCTL_DVS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)

DVS - Divisor 0b0000..Divisor by 1. 0b0001..Divisor by 2. 0b1110..Divisor by 15. 0b1111..Divisor by 16.

◆ SDHC_SYSCTL_DVS [5/5]

#define SDHC_SYSCTL_DVS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)

DVS - Divisor 0b0000..Divisor by 1. 0b0001..Divisor by 2. 0b1110..Divisor by 15. 0b1111..Divisor by 16.

◆ SDHC_SYSCTL_HCKEN [1/4]

#define SDHC_SYSCTL_HCKEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)

HCKEN - System Clock Enable 0b0..System clock will be internally gated off. 0b1..System clock will not be automatically gated off.

◆ SDHC_SYSCTL_HCKEN [2/4]

#define SDHC_SYSCTL_HCKEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)

HCKEN - System Clock Enable 0b0..System clock will be internally gated off. 0b1..System clock will not be automatically gated off.

◆ SDHC_SYSCTL_HCKEN [3/4]

#define SDHC_SYSCTL_HCKEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)

HCKEN - System Clock Enable 0b0..System clock will be internally gated off. 0b1..System clock will not be automatically gated off.

◆ SDHC_SYSCTL_HCKEN [4/4]

#define SDHC_SYSCTL_HCKEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)

HCKEN - System Clock Enable 0b0..System clock will be internally gated off. 0b1..System clock will not be automatically gated off.

◆ SDHC_SYSCTL_IPGEN [1/4]

#define SDHC_SYSCTL_IPGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)

IPGEN - IPG Clock Enable 0b0..Bus clock will be internally gated off. 0b1..Bus clock will not be automatically gated off.

◆ SDHC_SYSCTL_IPGEN [2/4]

#define SDHC_SYSCTL_IPGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)

IPGEN - IPG Clock Enable 0b0..Bus clock will be internally gated off. 0b1..Bus clock will not be automatically gated off.

◆ SDHC_SYSCTL_IPGEN [3/4]

#define SDHC_SYSCTL_IPGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)

IPGEN - IPG Clock Enable 0b0..Bus clock will be internally gated off. 0b1..Bus clock will not be automatically gated off.

◆ SDHC_SYSCTL_IPGEN [4/4]

#define SDHC_SYSCTL_IPGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)

IPGEN - IPG Clock Enable 0b0..Bus clock will be internally gated off. 0b1..Bus clock will not be automatically gated off.

◆ SDHC_SYSCTL_PEREN [1/4]

#define SDHC_SYSCTL_PEREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)

PEREN - Peripheral Clock Enable 0b0..SDHC clock will be internally gated off. 0b1..SDHC clock will not be automatically gated off.

◆ SDHC_SYSCTL_PEREN [2/4]

#define SDHC_SYSCTL_PEREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)

PEREN - Peripheral Clock Enable 0b0..SDHC clock will be internally gated off. 0b1..SDHC clock will not be automatically gated off.

◆ SDHC_SYSCTL_PEREN [3/4]

#define SDHC_SYSCTL_PEREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)

PEREN - Peripheral Clock Enable 0b0..SDHC clock will be internally gated off. 0b1..SDHC clock will not be automatically gated off.

◆ SDHC_SYSCTL_PEREN [4/4]

#define SDHC_SYSCTL_PEREN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)

PEREN - Peripheral Clock Enable 0b0..SDHC clock will be internally gated off. 0b1..SDHC clock will not be automatically gated off.

◆ SDHC_SYSCTL_RSTA [1/4]

#define SDHC_SYSCTL_RSTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)

RSTA - Software Reset For ALL 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTA [2/4]

#define SDHC_SYSCTL_RSTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)

RSTA - Software Reset For ALL 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTA [3/4]

#define SDHC_SYSCTL_RSTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)

RSTA - Software Reset For ALL 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTA [4/4]

#define SDHC_SYSCTL_RSTA ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)

RSTA - Software Reset For ALL 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTC [1/4]

#define SDHC_SYSCTL_RSTC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)

RSTC - Software Reset For CMD Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTC [2/4]

#define SDHC_SYSCTL_RSTC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)

RSTC - Software Reset For CMD Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTC [3/4]

#define SDHC_SYSCTL_RSTC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)

RSTC - Software Reset For CMD Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTC [4/4]

#define SDHC_SYSCTL_RSTC ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)

RSTC - Software Reset For CMD Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTD [1/4]

#define SDHC_SYSCTL_RSTD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)

RSTD - Software Reset For DAT Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTD [2/4]

#define SDHC_SYSCTL_RSTD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)

RSTD - Software Reset For DAT Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTD [3/4]

#define SDHC_SYSCTL_RSTD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)

RSTD - Software Reset For DAT Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_RSTD [4/4]

#define SDHC_SYSCTL_RSTD ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)

RSTD - Software Reset For DAT Line 0b0..No reset. 0b1..Reset.

◆ SDHC_SYSCTL_SDCLKFS [1/5]

#define SDHC_SYSCTL_SDCLKFS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)

SDCLKFS - SDCLK Frequency Select 0b00000001..Base clock divided by 2. 0b00000010..Base clock divided by 4. 0b00000100..Base clock divided by 8. 0b00001000..Base clock divided by 16. 0b00010000..Base clock divided by 32. 0b00100000..Base clock divided by 64. 0b01000000..Base clock divided by 128. 0b10000000..Base clock divided by 256.

◆ SDHC_SYSCTL_SDCLKFS [2/5]

#define SDHC_SYSCTL_SDCLKFS ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)

SDCLKFS - SDCLK Frequency Select 0b00000001..Base clock divided by 2. 0b00000010..Base clock divided by 4. 0b00000100..Base clock divided by 8. 0b00001000..Base clock divided by 16. 0b00010000..Base clock divided by 32. 0b00100000..Base clock divided by 64. 0b01000000..Base clock divided by 128. 0b10000000..Base clock divided by 256.

◆ SDHC_SYSCTL_SDCLKFS [3/5]

#define SDHC_SYSCTL_SDCLKFS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)

SDCLKFS - SDCLK Frequency Select 0b00000001..Base clock divided by 2. 0b00000010..Base clock divided by 4. 0b00000100..Base clock divided by 8. 0b00001000..Base clock divided by 16. 0b00010000..Base clock divided by 32. 0b00100000..Base clock divided by 64. 0b01000000..Base clock divided by 128. 0b10000000..Base clock divided by 256.

◆ SDHC_SYSCTL_SDCLKFS [4/5]

#define SDHC_SYSCTL_SDCLKFS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)

SDCLKFS - SDCLK Frequency Select 0b00000001..Base clock divided by 2. 0b00000010..Base clock divided by 4. 0b00000100..Base clock divided by 8. 0b00001000..Base clock divided by 16. 0b00010000..Base clock divided by 32. 0b00100000..Base clock divided by 64. 0b01000000..Base clock divided by 128. 0b10000000..Base clock divided by 256.

◆ SDHC_SYSCTL_SDCLKFS [5/5]

#define SDHC_SYSCTL_SDCLKFS ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)

SDCLKFS - SDCLK Frequency Select 0b00000001..Base clock divided by 2. 0b00000010..Base clock divided by 4. 0b00000100..Base clock divided by 8. 0b00001000..Base clock divided by 16. 0b00010000..Base clock divided by 32. 0b00100000..Base clock divided by 64. 0b01000000..Base clock divided by 128. 0b10000000..Base clock divided by 256.

◆ SDHC_VENDOR_EXBLKNU [1/4]

#define SDHC_VENDOR_EXBLKNU ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)

EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53 0b0..None exact block read. 0b1..Exact block read for SDIO CMD53.

◆ SDHC_VENDOR_EXBLKNU [2/4]

#define SDHC_VENDOR_EXBLKNU ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)

EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53 0b0..None exact block read. 0b1..Exact block read for SDIO CMD53.

◆ SDHC_VENDOR_EXBLKNU [3/4]

#define SDHC_VENDOR_EXBLKNU ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)

EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53 0b0..None exact block read. 0b1..Exact block read for SDIO CMD53.

◆ SDHC_VENDOR_EXBLKNU [4/4]

#define SDHC_VENDOR_EXBLKNU ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)

EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53 0b0..None exact block read. 0b1..Exact block read for SDIO CMD53.

◆ SDHC_VENDOR_EXTDMAEN [1/2]

#define SDHC_VENDOR_EXTDMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)

EXTDMAEN - External DMA Request Enable 0b0..In any scenario, SDHC does not send out the external DMA request. 0b1..When internal DMA is not active, the external DMA request will be sent out.

◆ SDHC_VENDOR_EXTDMAEN [2/2]

#define SDHC_VENDOR_EXTDMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)

EXTDMAEN - External DMA Request Enable 0b0..In any scenario, SDHC does not send out the external DMA request. 0b1..When internal DMA is not active, the external DMA request will be sent out.

◆ SDHC_XFERTYP_AC12EN [1/4]

#define SDHC_XFERTYP_AC12EN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)

AC12EN - Auto CMD12 Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_AC12EN [2/4]

#define SDHC_XFERTYP_AC12EN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)

AC12EN - Auto CMD12 Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_AC12EN [3/4]

#define SDHC_XFERTYP_AC12EN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)

AC12EN - Auto CMD12 Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_AC12EN [4/4]

#define SDHC_XFERTYP_AC12EN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)

AC12EN - Auto CMD12 Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_BCEN [1/4]

#define SDHC_XFERTYP_BCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)

BCEN - Block Count Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_BCEN [2/4]

#define SDHC_XFERTYP_BCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)

BCEN - Block Count Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_BCEN [3/4]

#define SDHC_XFERTYP_BCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)

BCEN - Block Count Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_BCEN [4/4]

#define SDHC_XFERTYP_BCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)

BCEN - Block Count Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CCCEN [1/4]

#define SDHC_XFERTYP_CCCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)

CCCEN - Command CRC Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CCCEN [2/4]

#define SDHC_XFERTYP_CCCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)

CCCEN - Command CRC Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CCCEN [3/4]

#define SDHC_XFERTYP_CCCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)

CCCEN - Command CRC Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CCCEN [4/4]

#define SDHC_XFERTYP_CCCEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)

CCCEN - Command CRC Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CICEN [1/4]

#define SDHC_XFERTYP_CICEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)

CICEN - Command Index Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CICEN [2/4]

#define SDHC_XFERTYP_CICEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)

CICEN - Command Index Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CICEN [3/4]

#define SDHC_XFERTYP_CICEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)

CICEN - Command Index Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CICEN [4/4]

#define SDHC_XFERTYP_CICEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)

CICEN - Command Index Check Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_CMDTYP [1/5]

#define SDHC_XFERTYP_CMDTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)

CMDTYP - Command Type 0b00..Normal other commands. 0b01..Suspend CMD52 for writing bus suspend in CCCR. 0b10..Resume CMD52 for writing function select in CCCR. 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.

◆ SDHC_XFERTYP_CMDTYP [2/5]

#define SDHC_XFERTYP_CMDTYP ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)

CMDTYP - Command Type 0b00..Normal other commands. 0b01..Suspend CMD52 for writing bus suspend in CCCR. 0b10..Resume CMD52 for writing function select in CCCR. 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.

◆ SDHC_XFERTYP_CMDTYP [3/5]

#define SDHC_XFERTYP_CMDTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)

CMDTYP - Command Type 0b00..Normal other commands. 0b01..Suspend CMD52 for writing bus suspend in CCCR. 0b10..Resume CMD52 for writing function select in CCCR. 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.

◆ SDHC_XFERTYP_CMDTYP [4/5]

#define SDHC_XFERTYP_CMDTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)

CMDTYP - Command Type 0b00..Normal other commands. 0b01..Suspend CMD52 for writing bus suspend in CCCR. 0b10..Resume CMD52 for writing function select in CCCR. 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.

◆ SDHC_XFERTYP_CMDTYP [5/5]

#define SDHC_XFERTYP_CMDTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)

CMDTYP - Command Type 0b00..Normal other commands. 0b01..Suspend CMD52 for writing bus suspend in CCCR. 0b10..Resume CMD52 for writing function select in CCCR. 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.

◆ SDHC_XFERTYP_DMAEN [1/4]

#define SDHC_XFERTYP_DMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)

DMAEN - DMA Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_DMAEN [2/4]

#define SDHC_XFERTYP_DMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)

DMAEN - DMA Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_DMAEN [3/4]

#define SDHC_XFERTYP_DMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)

DMAEN - DMA Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_DMAEN [4/4]

#define SDHC_XFERTYP_DMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)

DMAEN - DMA Enable 0b0..Disable 0b1..Enable

◆ SDHC_XFERTYP_DPSEL [1/4]

#define SDHC_XFERTYP_DPSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)

DPSEL - Data Present Select 0b0..No data present. 0b1..Data present.

◆ SDHC_XFERTYP_DPSEL [2/4]

#define SDHC_XFERTYP_DPSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)

DPSEL - Data Present Select 0b0..No data present. 0b1..Data present.

◆ SDHC_XFERTYP_DPSEL [3/4]

#define SDHC_XFERTYP_DPSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)

DPSEL - Data Present Select 0b0..No data present. 0b1..Data present.

◆ SDHC_XFERTYP_DPSEL [4/4]

#define SDHC_XFERTYP_DPSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)

DPSEL - Data Present Select 0b0..No data present. 0b1..Data present.

◆ SDHC_XFERTYP_DTDSEL [1/4]

#define SDHC_XFERTYP_DTDSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)

DTDSEL - Data Transfer Direction Select 0b0..Write host to card. 0b1..Read card to host.

◆ SDHC_XFERTYP_DTDSEL [2/4]

#define SDHC_XFERTYP_DTDSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)

DTDSEL - Data Transfer Direction Select 0b0..Write host to card. 0b1..Read card to host.

◆ SDHC_XFERTYP_DTDSEL [3/4]

#define SDHC_XFERTYP_DTDSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)

DTDSEL - Data Transfer Direction Select 0b0..Write host to card. 0b1..Read card to host.

◆ SDHC_XFERTYP_DTDSEL [4/4]

#define SDHC_XFERTYP_DTDSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)

DTDSEL - Data Transfer Direction Select 0b0..Write host to card. 0b1..Read card to host.

◆ SDHC_XFERTYP_MSBSEL [1/4]

#define SDHC_XFERTYP_MSBSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)

MSBSEL - Multi/Single Block Select 0b0..Single block. 0b1..Multiple blocks.

◆ SDHC_XFERTYP_MSBSEL [2/4]

#define SDHC_XFERTYP_MSBSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)

MSBSEL - Multi/Single Block Select 0b0..Single block. 0b1..Multiple blocks.

◆ SDHC_XFERTYP_MSBSEL [3/4]

#define SDHC_XFERTYP_MSBSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)

MSBSEL - Multi/Single Block Select 0b0..Single block. 0b1..Multiple blocks.

◆ SDHC_XFERTYP_MSBSEL [4/4]

#define SDHC_XFERTYP_MSBSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)

MSBSEL - Multi/Single Block Select 0b0..Single block. 0b1..Multiple blocks.

◆ SDHC_XFERTYP_RSPTYP [1/5]

#define SDHC_XFERTYP_RSPTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)

RSPTYP - Response Type Select 0b00..No response. 0b01..Response length 136. 0b10..Response length 48. 0b11..Response length 48, check busy after response.

◆ SDHC_XFERTYP_RSPTYP [2/5]

#define SDHC_XFERTYP_RSPTYP ( x)    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)

RSPTYP - Response Type Select 0b00..No response. 0b01..Response length 136. 0b10..Response length 48. 0b11..Response length 48, check busy after response.

◆ SDHC_XFERTYP_RSPTYP [3/5]

#define SDHC_XFERTYP_RSPTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)

RSPTYP - Response Type Select 0b00..No response. 0b01..Response length 136. 0b10..Response length 48. 0b11..Response length 48, check busy after response.

◆ SDHC_XFERTYP_RSPTYP [4/5]

#define SDHC_XFERTYP_RSPTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)

RSPTYP - Response Type Select 0b00..No response. 0b01..Response length 136. 0b10..Response length 48. 0b11..Response length 48, check busy after response.

◆ SDHC_XFERTYP_RSPTYP [5/5]

#define SDHC_XFERTYP_RSPTYP ( x)    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)

RSPTYP - Response Type Select 0b00..No response. 0b01..Response length 136. 0b10..Response length 48. 0b11..Response length 48, check busy after response.