SPI Peripheral Access Layer

Topics
	SPI Register Masks
	SYSMPU Peripheral Access Layer

Data Structures
struct	SPI_Type

Macros
#define	SPI0_BASE   (0x4002C000u)
#define	SPI0   ((SPI_Type *)SPI0_BASE)
#define	SPI1_BASE   (0x4002D000u)
#define	SPI1   ((SPI_Type *)SPI1_BASE)
#define	SPI2_BASE   (0x400AC000u)
#define	SPI2   ((SPI_Type *)SPI2_BASE)
#define	SPI0_BASE   (0x4002C000u)
#define	SPI0   ((SPI_Type *)SPI0_BASE)
#define	SPI1_BASE   (0x4002D000u)
#define	SPI1   ((SPI_Type *)SPI1_BASE)
#define	SPI2_BASE   (0x400AC000u)
#define	SPI2   ((SPI_Type *)SPI2_BASE)
#define	SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }
#define	SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }
#define	SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
#define	SPI0_BASE   (0x4002C000u)
#define	SPI0   ((SPI_Type *)SPI0_BASE)
#define	SPI1_BASE   (0x4002D000u)
#define	SPI1   ((SPI_Type *)SPI1_BASE)
#define	SPI2_BASE   (0x400AC000u)
#define	SPI2   ((SPI_Type *)SPI2_BASE)
#define	SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }
#define	SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }
#define	SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
#define	SPI0_BASE   (0x4002C000u)
#define	SPI0   ((SPI_Type *)SPI0_BASE)
#define	SPI1_BASE   (0x4002D000u)
#define	SPI1   ((SPI_Type *)SPI1_BASE)
#define	SPI2_BASE   (0x400AC000u)
#define	SPI2   ((SPI_Type *)SPI2_BASE)
#define	SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }
#define	SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }
#define	SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
#define	SPI0_BASE   (0x4002C000u)
#define	SPI0   ((SPI_Type *)SPI0_BASE)
#define	SPI1_BASE   (0x4002D000u)
#define	SPI1   ((SPI_Type *)SPI1_BASE)
#define	SPI2_BASE   (0x400AC000u)
#define	SPI2   ((SPI_Type *)SPI2_BASE)
#define	SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }
#define	SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }
#define	SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }

Macro Definition Documentation

SPI0 [1/5]

#define SPI0   ((SPI_Type *)SPI0_BASE)

Peripheral SPI0 base pointer

SPI0 [2/5]

#define SPI0   ((SPI_Type *)SPI0_BASE)

Peripheral SPI0 base pointer

SPI0 [3/5]

#define SPI0   ((SPI_Type *)SPI0_BASE)

Peripheral SPI0 base pointer

SPI0 [4/5]

#define SPI0   ((SPI_Type *)SPI0_BASE)

Peripheral SPI0 base pointer

SPI0 [5/5]

#define SPI0   ((SPI_Type *)SPI0_BASE)

Peripheral SPI0 base pointer

SPI0_BASE [1/5]

#define SPI0_BASE   (0x4002C000u)

Peripheral SPI0 base address

SPI0_BASE [2/5]

#define SPI0_BASE   (0x4002C000u)

Peripheral SPI0 base address

SPI0_BASE [3/5]

#define SPI0_BASE   (0x4002C000u)

Peripheral SPI0 base address

SPI0_BASE [4/5]

#define SPI0_BASE   (0x4002C000u)

Peripheral SPI0 base address

SPI0_BASE [5/5]

#define SPI0_BASE   (0x4002C000u)

Peripheral SPI0 base address

SPI1 [1/5]

#define SPI1   ((SPI_Type *)SPI1_BASE)

Peripheral SPI1 base pointer

SPI1 [2/5]

#define SPI1   ((SPI_Type *)SPI1_BASE)

Peripheral SPI1 base pointer

SPI1 [3/5]

#define SPI1   ((SPI_Type *)SPI1_BASE)

Peripheral SPI1 base pointer

SPI1 [4/5]

#define SPI1   ((SPI_Type *)SPI1_BASE)

Peripheral SPI1 base pointer

SPI1 [5/5]

#define SPI1   ((SPI_Type *)SPI1_BASE)

Peripheral SPI1 base pointer

SPI1_BASE [1/5]

#define SPI1_BASE   (0x4002D000u)

Peripheral SPI1 base address

SPI1_BASE [2/5]

#define SPI1_BASE   (0x4002D000u)

Peripheral SPI1 base address

SPI1_BASE [3/5]

#define SPI1_BASE   (0x4002D000u)

Peripheral SPI1 base address

SPI1_BASE [4/5]

#define SPI1_BASE   (0x4002D000u)

Peripheral SPI1 base address

SPI1_BASE [5/5]

#define SPI1_BASE   (0x4002D000u)

Peripheral SPI1 base address

SPI2 [1/5]

#define SPI2   ((SPI_Type *)SPI2_BASE)

Peripheral SPI2 base pointer

SPI2 [2/5]

#define SPI2   ((SPI_Type *)SPI2_BASE)

Peripheral SPI2 base pointer

SPI2 [3/5]

#define SPI2   ((SPI_Type *)SPI2_BASE)

Peripheral SPI2 base pointer

SPI2 [4/5]

#define SPI2   ((SPI_Type *)SPI2_BASE)

Peripheral SPI2 base pointer

SPI2 [5/5]

#define SPI2   ((SPI_Type *)SPI2_BASE)

Peripheral SPI2 base pointer

SPI2_BASE [1/5]

#define SPI2_BASE   (0x400AC000u)

Peripheral SPI2 base address

SPI2_BASE [2/5]

#define SPI2_BASE   (0x400AC000u)

Peripheral SPI2 base address

SPI2_BASE [3/5]

#define SPI2_BASE   (0x400AC000u)

Peripheral SPI2 base address

SPI2_BASE [4/5]

#define SPI2_BASE   (0x400AC000u)

Peripheral SPI2 base address

SPI2_BASE [5/5]

#define SPI2_BASE   (0x400AC000u)

Peripheral SPI2 base address

SPI_BASE_ADDRS [1/4]

#define SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }

Array initializer of SPI peripheral base addresses

SPI_BASE_ADDRS [2/4]

#define SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }

Array initializer of SPI peripheral base addresses

SPI_BASE_ADDRS [3/4]

#define SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }

Array initializer of SPI peripheral base addresses

SPI_BASE_ADDRS [4/4]

#define SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }

Array initializer of SPI peripheral base addresses

SPI_BASE_PTRS [1/4]

#define SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }

Array initializer of SPI peripheral base pointers

SPI_BASE_PTRS [2/4]

#define SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }

Array initializer of SPI peripheral base pointers

SPI_BASE_PTRS [3/4]

#define SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }

Array initializer of SPI peripheral base pointers

SPI_BASE_PTRS [4/4]

#define SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }

Array initializer of SPI peripheral base pointers

SPI_IRQS [1/4]

#define SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }

Interrupt vectors for the SPI peripheral type

SPI_IRQS [2/4]

#define SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }

Interrupt vectors for the SPI peripheral type

SPI_IRQS [3/4]

#define SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }

Interrupt vectors for the SPI peripheral type

SPI_IRQS [4/4]

#define SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }

Interrupt vectors for the SPI peripheral type