SPI Register Masks

Macros
#define	SPI0_BASE   (0x4002C000u)
#define	SPI0   ((SPI_Type *)SPI0_BASE)
#define	SPI1_BASE   (0x4002D000u)
#define	SPI1   ((SPI_Type *)SPI1_BASE)
#define	SPI2_BASE   (0x400AC000u)
#define	SPI2   ((SPI_Type *)SPI2_BASE)
#define	SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }
#define	SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }
#define	SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
#define	SPI_CTAR_COUNT   (2U)
#define	SPI_CTAR_SLAVE_COUNT   (1U)
#define	SPI_CTAR_COUNT   (2U)
#define	SPI_CTAR_SLAVE_COUNT   (1U)
#define	SPI_CTAR_COUNT   (2U)
#define	SPI_CTAR_SLAVE_COUNT   (1U)
#define	SPI_CTAR_COUNT   (2U)
#define	SPI_CTAR_SLAVE_COUNT   (1U)

MCR - Module Configuration Register
#define	SPI_MCR_HALT_MASK   (0x1U)
#define	SPI_MCR_HALT_SHIFT   (0U)
#define	SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
#define	SPI_MCR_SMPL_PT_MASK   (0x300U)
#define	SPI_MCR_SMPL_PT_SHIFT   (8U)
#define	SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
#define	SPI_MCR_CLR_RXF_MASK   (0x400U)
#define	SPI_MCR_CLR_RXF_SHIFT   (10U)
#define	SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
#define	SPI_MCR_CLR_TXF_MASK   (0x800U)
#define	SPI_MCR_CLR_TXF_SHIFT   (11U)
#define	SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
#define	SPI_MCR_DIS_RXF_MASK   (0x1000U)
#define	SPI_MCR_DIS_RXF_SHIFT   (12U)
#define	SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
#define	SPI_MCR_DIS_TXF_MASK   (0x2000U)
#define	SPI_MCR_DIS_TXF_SHIFT   (13U)
#define	SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
#define	SPI_MCR_MDIS_MASK   (0x4000U)
#define	SPI_MCR_MDIS_SHIFT   (14U)
#define	SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
#define	SPI_MCR_DOZE_MASK   (0x8000U)
#define	SPI_MCR_DOZE_SHIFT   (15U)
#define	SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
#define	SPI_MCR_PCSIS_MASK   (0x3F0000U)
#define	SPI_MCR_PCSIS_SHIFT   (16U)
#define	SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
#define	SPI_MCR_ROOE_MASK   (0x1000000U)
#define	SPI_MCR_ROOE_SHIFT   (24U)
#define	SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
#define	SPI_MCR_PCSSE_MASK   (0x2000000U)
#define	SPI_MCR_PCSSE_SHIFT   (25U)
#define	SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
#define	SPI_MCR_MTFE_MASK   (0x4000000U)
#define	SPI_MCR_MTFE_SHIFT   (26U)
#define	SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
#define	SPI_MCR_FRZ_MASK   (0x8000000U)
#define	SPI_MCR_FRZ_SHIFT   (27U)
#define	SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
#define	SPI_MCR_DCONF_MASK   (0x30000000U)
#define	SPI_MCR_DCONF_SHIFT   (28U)
#define	SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
#define	SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
#define	SPI_MCR_CONT_SCKE_SHIFT   (30U)
#define	SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
#define	SPI_MCR_MSTR_MASK   (0x80000000U)
#define	SPI_MCR_MSTR_SHIFT   (31U)
#define	SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
#define	SPI_MCR_HALT_MASK   0x1u
#define	SPI_MCR_HALT_SHIFT   0
#define	SPI_MCR_SMPL_PT_MASK   0x300u
#define	SPI_MCR_SMPL_PT_SHIFT   8
#define	SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
#define	SPI_MCR_CLR_RXF_MASK   0x400u
#define	SPI_MCR_CLR_RXF_SHIFT   10
#define	SPI_MCR_CLR_TXF_MASK   0x800u
#define	SPI_MCR_CLR_TXF_SHIFT   11
#define	SPI_MCR_DIS_RXF_MASK   0x1000u
#define	SPI_MCR_DIS_RXF_SHIFT   12
#define	SPI_MCR_DIS_TXF_MASK   0x2000u
#define	SPI_MCR_DIS_TXF_SHIFT   13
#define	SPI_MCR_MDIS_MASK   0x4000u
#define	SPI_MCR_MDIS_SHIFT   14
#define	SPI_MCR_DOZE_MASK   0x8000u
#define	SPI_MCR_DOZE_SHIFT   15
#define	SPI_MCR_PCSIS_MASK   0x3F0000u
#define	SPI_MCR_PCSIS_SHIFT   16
#define	SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
#define	SPI_MCR_ROOE_MASK   0x1000000u
#define	SPI_MCR_ROOE_SHIFT   24
#define	SPI_MCR_PCSSE_MASK   0x2000000u
#define	SPI_MCR_PCSSE_SHIFT   25
#define	SPI_MCR_MTFE_MASK   0x4000000u
#define	SPI_MCR_MTFE_SHIFT   26
#define	SPI_MCR_FRZ_MASK   0x8000000u
#define	SPI_MCR_FRZ_SHIFT   27
#define	SPI_MCR_DCONF_MASK   0x30000000u
#define	SPI_MCR_DCONF_SHIFT   28
#define	SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
#define	SPI_MCR_CONT_SCKE_MASK   0x40000000u
#define	SPI_MCR_CONT_SCKE_SHIFT   30
#define	SPI_MCR_MSTR_MASK   0x80000000u
#define	SPI_MCR_MSTR_SHIFT   31
#define	SPI_MCR_HALT_MASK   (0x1U)
#define	SPI_MCR_HALT_SHIFT   (0U)
#define	SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
#define	SPI_MCR_SMPL_PT_MASK   (0x300U)
#define	SPI_MCR_SMPL_PT_SHIFT   (8U)
#define	SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
#define	SPI_MCR_CLR_RXF_MASK   (0x400U)
#define	SPI_MCR_CLR_RXF_SHIFT   (10U)
#define	SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
#define	SPI_MCR_CLR_TXF_MASK   (0x800U)
#define	SPI_MCR_CLR_TXF_SHIFT   (11U)
#define	SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
#define	SPI_MCR_DIS_RXF_MASK   (0x1000U)
#define	SPI_MCR_DIS_RXF_SHIFT   (12U)
#define	SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
#define	SPI_MCR_DIS_TXF_MASK   (0x2000U)
#define	SPI_MCR_DIS_TXF_SHIFT   (13U)
#define	SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
#define	SPI_MCR_MDIS_MASK   (0x4000U)
#define	SPI_MCR_MDIS_SHIFT   (14U)
#define	SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
#define	SPI_MCR_DOZE_MASK   (0x8000U)
#define	SPI_MCR_DOZE_SHIFT   (15U)
#define	SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
#define	SPI_MCR_PCSIS_MASK   (0x3F0000U)
#define	SPI_MCR_PCSIS_SHIFT   (16U)
#define	SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
#define	SPI_MCR_ROOE_MASK   (0x1000000U)
#define	SPI_MCR_ROOE_SHIFT   (24U)
#define	SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
#define	SPI_MCR_PCSSE_MASK   (0x2000000U)
#define	SPI_MCR_PCSSE_SHIFT   (25U)
#define	SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
#define	SPI_MCR_MTFE_MASK   (0x4000000U)
#define	SPI_MCR_MTFE_SHIFT   (26U)
#define	SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
#define	SPI_MCR_FRZ_MASK   (0x8000000U)
#define	SPI_MCR_FRZ_SHIFT   (27U)
#define	SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
#define	SPI_MCR_DCONF_MASK   (0x30000000U)
#define	SPI_MCR_DCONF_SHIFT   (28U)
#define	SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
#define	SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
#define	SPI_MCR_CONT_SCKE_SHIFT   (30U)
#define	SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
#define	SPI_MCR_MSTR_MASK   (0x80000000U)
#define	SPI_MCR_MSTR_SHIFT   (31U)
#define	SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
#define	SPI_MCR_HALT_MASK   (0x1U)
#define	SPI_MCR_HALT_SHIFT   (0U)
#define	SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
#define	SPI_MCR_SMPL_PT_MASK   (0x300U)
#define	SPI_MCR_SMPL_PT_SHIFT   (8U)
#define	SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
#define	SPI_MCR_CLR_RXF_MASK   (0x400U)
#define	SPI_MCR_CLR_RXF_SHIFT   (10U)
#define	SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
#define	SPI_MCR_CLR_TXF_MASK   (0x800U)
#define	SPI_MCR_CLR_TXF_SHIFT   (11U)
#define	SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
#define	SPI_MCR_DIS_RXF_MASK   (0x1000U)
#define	SPI_MCR_DIS_RXF_SHIFT   (12U)
#define	SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
#define	SPI_MCR_DIS_TXF_MASK   (0x2000U)
#define	SPI_MCR_DIS_TXF_SHIFT   (13U)
#define	SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
#define	SPI_MCR_MDIS_MASK   (0x4000U)
#define	SPI_MCR_MDIS_SHIFT   (14U)
#define	SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
#define	SPI_MCR_DOZE_MASK   (0x8000U)
#define	SPI_MCR_DOZE_SHIFT   (15U)
#define	SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
#define	SPI_MCR_PCSIS_MASK   (0x3F0000U)
#define	SPI_MCR_PCSIS_SHIFT   (16U)
#define	SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
#define	SPI_MCR_ROOE_MASK   (0x1000000U)
#define	SPI_MCR_ROOE_SHIFT   (24U)
#define	SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
#define	SPI_MCR_PCSSE_MASK   (0x2000000U)
#define	SPI_MCR_PCSSE_SHIFT   (25U)
#define	SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
#define	SPI_MCR_MTFE_MASK   (0x4000000U)
#define	SPI_MCR_MTFE_SHIFT   (26U)
#define	SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
#define	SPI_MCR_FRZ_MASK   (0x8000000U)
#define	SPI_MCR_FRZ_SHIFT   (27U)
#define	SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
#define	SPI_MCR_DCONF_MASK   (0x30000000U)
#define	SPI_MCR_DCONF_SHIFT   (28U)
#define	SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
#define	SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
#define	SPI_MCR_CONT_SCKE_SHIFT   (30U)
#define	SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
#define	SPI_MCR_MSTR_MASK   (0x80000000U)
#define	SPI_MCR_MSTR_SHIFT   (31U)
#define	SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
#define	SPI_MCR_HALT_MASK   (0x1U)
#define	SPI_MCR_HALT_SHIFT   (0U)
#define	SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
#define	SPI_MCR_SMPL_PT_MASK   (0x300U)
#define	SPI_MCR_SMPL_PT_SHIFT   (8U)
#define	SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
#define	SPI_MCR_CLR_RXF_MASK   (0x400U)
#define	SPI_MCR_CLR_RXF_SHIFT   (10U)
#define	SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
#define	SPI_MCR_CLR_TXF_MASK   (0x800U)
#define	SPI_MCR_CLR_TXF_SHIFT   (11U)
#define	SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
#define	SPI_MCR_DIS_RXF_MASK   (0x1000U)
#define	SPI_MCR_DIS_RXF_SHIFT   (12U)
#define	SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
#define	SPI_MCR_DIS_TXF_MASK   (0x2000U)
#define	SPI_MCR_DIS_TXF_SHIFT   (13U)
#define	SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
#define	SPI_MCR_MDIS_MASK   (0x4000U)
#define	SPI_MCR_MDIS_SHIFT   (14U)
#define	SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
#define	SPI_MCR_DOZE_MASK   (0x8000U)
#define	SPI_MCR_DOZE_SHIFT   (15U)
#define	SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
#define	SPI_MCR_PCSIS_MASK   (0x3F0000U)
#define	SPI_MCR_PCSIS_SHIFT   (16U)
#define	SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
#define	SPI_MCR_ROOE_MASK   (0x1000000U)
#define	SPI_MCR_ROOE_SHIFT   (24U)
#define	SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
#define	SPI_MCR_PCSSE_MASK   (0x2000000U)
#define	SPI_MCR_PCSSE_SHIFT   (25U)
#define	SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
#define	SPI_MCR_MTFE_MASK   (0x4000000U)
#define	SPI_MCR_MTFE_SHIFT   (26U)
#define	SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
#define	SPI_MCR_FRZ_MASK   (0x8000000U)
#define	SPI_MCR_FRZ_SHIFT   (27U)
#define	SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
#define	SPI_MCR_DCONF_MASK   (0x30000000U)
#define	SPI_MCR_DCONF_SHIFT   (28U)
#define	SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
#define	SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
#define	SPI_MCR_CONT_SCKE_SHIFT   (30U)
#define	SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
#define	SPI_MCR_MSTR_MASK   (0x80000000U)
#define	SPI_MCR_MSTR_SHIFT   (31U)
#define	SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
#define	SPI_MCR_HALT_MASK   (0x1U)
#define	SPI_MCR_HALT_SHIFT   (0U)
#define	SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
#define	SPI_MCR_SMPL_PT_MASK   (0x300U)
#define	SPI_MCR_SMPL_PT_SHIFT   (8U)
#define	SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
#define	SPI_MCR_CLR_RXF_MASK   (0x400U)
#define	SPI_MCR_CLR_RXF_SHIFT   (10U)
#define	SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
#define	SPI_MCR_CLR_TXF_MASK   (0x800U)
#define	SPI_MCR_CLR_TXF_SHIFT   (11U)
#define	SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
#define	SPI_MCR_DIS_RXF_MASK   (0x1000U)
#define	SPI_MCR_DIS_RXF_SHIFT   (12U)
#define	SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
#define	SPI_MCR_DIS_TXF_MASK   (0x2000U)
#define	SPI_MCR_DIS_TXF_SHIFT   (13U)
#define	SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
#define	SPI_MCR_MDIS_MASK   (0x4000U)
#define	SPI_MCR_MDIS_SHIFT   (14U)
#define	SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
#define	SPI_MCR_DOZE_MASK   (0x8000U)
#define	SPI_MCR_DOZE_SHIFT   (15U)
#define	SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
#define	SPI_MCR_PCSIS_MASK   (0x3F0000U)
#define	SPI_MCR_PCSIS_SHIFT   (16U)
#define	SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
#define	SPI_MCR_ROOE_MASK   (0x1000000U)
#define	SPI_MCR_ROOE_SHIFT   (24U)
#define	SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
#define	SPI_MCR_PCSSE_MASK   (0x2000000U)
#define	SPI_MCR_PCSSE_SHIFT   (25U)
#define	SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
#define	SPI_MCR_MTFE_MASK   (0x4000000U)
#define	SPI_MCR_MTFE_SHIFT   (26U)
#define	SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
#define	SPI_MCR_FRZ_MASK   (0x8000000U)
#define	SPI_MCR_FRZ_SHIFT   (27U)
#define	SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
#define	SPI_MCR_DCONF_MASK   (0x30000000U)
#define	SPI_MCR_DCONF_SHIFT   (28U)
#define	SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
#define	SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
#define	SPI_MCR_CONT_SCKE_SHIFT   (30U)
#define	SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
#define	SPI_MCR_MSTR_MASK   (0x80000000U)
#define	SPI_MCR_MSTR_SHIFT   (31U)
#define	SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

TCR - Transfer Count Register
#define	SPI_TCR_SPI_TCNT_MASK   (0xFFFF0000U)
#define	SPI_TCR_SPI_TCNT_SHIFT   (16U)
#define	SPI_TCR_SPI_TCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
#define	SPI_TCR_SPI_TCNT_MASK   0xFFFF0000u
#define	SPI_TCR_SPI_TCNT_SHIFT   16
#define	SPI_TCR_SPI_TCNT(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
#define	SPI_TCR_SPI_TCNT_MASK   (0xFFFF0000U)
#define	SPI_TCR_SPI_TCNT_SHIFT   (16U)
#define	SPI_TCR_SPI_TCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
#define	SPI_TCR_SPI_TCNT_MASK   (0xFFFF0000U)
#define	SPI_TCR_SPI_TCNT_SHIFT   (16U)
#define	SPI_TCR_SPI_TCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
#define	SPI_TCR_SPI_TCNT_MASK   (0xFFFF0000U)
#define	SPI_TCR_SPI_TCNT_SHIFT   (16U)
#define	SPI_TCR_SPI_TCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
#define	SPI_TCR_SPI_TCNT_MASK   (0xFFFF0000U)
#define	SPI_TCR_SPI_TCNT_SHIFT   (16U)
#define	SPI_TCR_SPI_TCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)

CTAR - Clock and Transfer Attributes Register (In Master Mode)
#define	SPI_CTAR_BR_MASK   (0xFU)
#define	SPI_CTAR_BR_SHIFT   (0U)
#define	SPI_CTAR_BR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
#define	SPI_CTAR_DT_MASK   (0xF0U)
#define	SPI_CTAR_DT_SHIFT   (4U)
#define	SPI_CTAR_DT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
#define	SPI_CTAR_ASC_MASK   (0xF00U)
#define	SPI_CTAR_ASC_SHIFT   (8U)
#define	SPI_CTAR_ASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
#define	SPI_CTAR_CSSCK_MASK   (0xF000U)
#define	SPI_CTAR_CSSCK_SHIFT   (12U)
#define	SPI_CTAR_CSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
#define	SPI_CTAR_PBR_MASK   (0x30000U)
#define	SPI_CTAR_PBR_SHIFT   (16U)
#define	SPI_CTAR_PBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
#define	SPI_CTAR_PDT_MASK   (0xC0000U)
#define	SPI_CTAR_PDT_SHIFT   (18U)
#define	SPI_CTAR_PDT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
#define	SPI_CTAR_PASC_MASK   (0x300000U)
#define	SPI_CTAR_PASC_SHIFT   (20U)
#define	SPI_CTAR_PASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
#define	SPI_CTAR_PCSSCK_MASK   (0xC00000U)
#define	SPI_CTAR_PCSSCK_SHIFT   (22U)
#define	SPI_CTAR_PCSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
#define	SPI_CTAR_LSBFE_MASK   (0x1000000U)
#define	SPI_CTAR_LSBFE_SHIFT   (24U)
#define	SPI_CTAR_LSBFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
#define	SPI_CTAR_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_CPHA_SHIFT   (25U)
#define	SPI_CTAR_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
#define	SPI_CTAR_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_CPOL_SHIFT   (26U)
#define	SPI_CTAR_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
#define	SPI_CTAR_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
#define	SPI_CTAR_DBR_MASK   (0x80000000U)
#define	SPI_CTAR_DBR_SHIFT   (31U)
#define	SPI_CTAR_DBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
#define	SPI_CTAR_BR_MASK   0xFu
#define	SPI_CTAR_BR_SHIFT   0
#define	SPI_CTAR_BR(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
#define	SPI_CTAR_DT_MASK   0xF0u
#define	SPI_CTAR_DT_SHIFT   4
#define	SPI_CTAR_DT(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
#define	SPI_CTAR_ASC_MASK   0xF00u
#define	SPI_CTAR_ASC_SHIFT   8
#define	SPI_CTAR_ASC(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
#define	SPI_CTAR_CSSCK_MASK   0xF000u
#define	SPI_CTAR_CSSCK_SHIFT   12
#define	SPI_CTAR_CSSCK(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
#define	SPI_CTAR_PBR_MASK   0x30000u
#define	SPI_CTAR_PBR_SHIFT   16
#define	SPI_CTAR_PBR(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
#define	SPI_CTAR_PDT_MASK   0xC0000u
#define	SPI_CTAR_PDT_SHIFT   18
#define	SPI_CTAR_PDT(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
#define	SPI_CTAR_PASC_MASK   0x300000u
#define	SPI_CTAR_PASC_SHIFT   20
#define	SPI_CTAR_PASC(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
#define	SPI_CTAR_PCSSCK_MASK   0xC00000u
#define	SPI_CTAR_PCSSCK_SHIFT   22
#define	SPI_CTAR_PCSSCK(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
#define	SPI_CTAR_LSBFE_MASK   0x1000000u
#define	SPI_CTAR_LSBFE_SHIFT   24
#define	SPI_CTAR_CPHA_MASK   0x2000000u
#define	SPI_CTAR_CPHA_SHIFT   25
#define	SPI_CTAR_CPOL_MASK   0x4000000u
#define	SPI_CTAR_CPOL_SHIFT   26
#define	SPI_CTAR_FMSZ_MASK   0x78000000u
#define	SPI_CTAR_FMSZ_SHIFT   27
#define	SPI_CTAR_FMSZ(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
#define	SPI_CTAR_DBR_MASK   0x80000000u
#define	SPI_CTAR_DBR_SHIFT   31
#define	SPI_CTAR_BR_MASK   (0xFU)
#define	SPI_CTAR_BR_SHIFT   (0U)
#define	SPI_CTAR_BR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
#define	SPI_CTAR_DT_MASK   (0xF0U)
#define	SPI_CTAR_DT_SHIFT   (4U)
#define	SPI_CTAR_DT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
#define	SPI_CTAR_ASC_MASK   (0xF00U)
#define	SPI_CTAR_ASC_SHIFT   (8U)
#define	SPI_CTAR_ASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
#define	SPI_CTAR_CSSCK_MASK   (0xF000U)
#define	SPI_CTAR_CSSCK_SHIFT   (12U)
#define	SPI_CTAR_CSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
#define	SPI_CTAR_PBR_MASK   (0x30000U)
#define	SPI_CTAR_PBR_SHIFT   (16U)
#define	SPI_CTAR_PBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
#define	SPI_CTAR_PDT_MASK   (0xC0000U)
#define	SPI_CTAR_PDT_SHIFT   (18U)
#define	SPI_CTAR_PDT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
#define	SPI_CTAR_PASC_MASK   (0x300000U)
#define	SPI_CTAR_PASC_SHIFT   (20U)
#define	SPI_CTAR_PASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
#define	SPI_CTAR_PCSSCK_MASK   (0xC00000U)
#define	SPI_CTAR_PCSSCK_SHIFT   (22U)
#define	SPI_CTAR_PCSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
#define	SPI_CTAR_LSBFE_MASK   (0x1000000U)
#define	SPI_CTAR_LSBFE_SHIFT   (24U)
#define	SPI_CTAR_LSBFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
#define	SPI_CTAR_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_CPHA_SHIFT   (25U)
#define	SPI_CTAR_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
#define	SPI_CTAR_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_CPOL_SHIFT   (26U)
#define	SPI_CTAR_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
#define	SPI_CTAR_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
#define	SPI_CTAR_DBR_MASK   (0x80000000U)
#define	SPI_CTAR_DBR_SHIFT   (31U)
#define	SPI_CTAR_DBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
#define	SPI_CTAR_BR_MASK   (0xFU)
#define	SPI_CTAR_BR_SHIFT   (0U)
#define	SPI_CTAR_BR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
#define	SPI_CTAR_DT_MASK   (0xF0U)
#define	SPI_CTAR_DT_SHIFT   (4U)
#define	SPI_CTAR_DT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
#define	SPI_CTAR_ASC_MASK   (0xF00U)
#define	SPI_CTAR_ASC_SHIFT   (8U)
#define	SPI_CTAR_ASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
#define	SPI_CTAR_CSSCK_MASK   (0xF000U)
#define	SPI_CTAR_CSSCK_SHIFT   (12U)
#define	SPI_CTAR_CSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
#define	SPI_CTAR_PBR_MASK   (0x30000U)
#define	SPI_CTAR_PBR_SHIFT   (16U)
#define	SPI_CTAR_PBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
#define	SPI_CTAR_PDT_MASK   (0xC0000U)
#define	SPI_CTAR_PDT_SHIFT   (18U)
#define	SPI_CTAR_PDT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
#define	SPI_CTAR_PASC_MASK   (0x300000U)
#define	SPI_CTAR_PASC_SHIFT   (20U)
#define	SPI_CTAR_PASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
#define	SPI_CTAR_PCSSCK_MASK   (0xC00000U)
#define	SPI_CTAR_PCSSCK_SHIFT   (22U)
#define	SPI_CTAR_PCSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
#define	SPI_CTAR_LSBFE_MASK   (0x1000000U)
#define	SPI_CTAR_LSBFE_SHIFT   (24U)
#define	SPI_CTAR_LSBFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
#define	SPI_CTAR_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_CPHA_SHIFT   (25U)
#define	SPI_CTAR_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
#define	SPI_CTAR_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_CPOL_SHIFT   (26U)
#define	SPI_CTAR_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
#define	SPI_CTAR_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
#define	SPI_CTAR_DBR_MASK   (0x80000000U)
#define	SPI_CTAR_DBR_SHIFT   (31U)
#define	SPI_CTAR_DBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
#define	SPI_CTAR_BR_MASK   (0xFU)
#define	SPI_CTAR_BR_SHIFT   (0U)
#define	SPI_CTAR_BR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
#define	SPI_CTAR_DT_MASK   (0xF0U)
#define	SPI_CTAR_DT_SHIFT   (4U)
#define	SPI_CTAR_DT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
#define	SPI_CTAR_ASC_MASK   (0xF00U)
#define	SPI_CTAR_ASC_SHIFT   (8U)
#define	SPI_CTAR_ASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
#define	SPI_CTAR_CSSCK_MASK   (0xF000U)
#define	SPI_CTAR_CSSCK_SHIFT   (12U)
#define	SPI_CTAR_CSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
#define	SPI_CTAR_PBR_MASK   (0x30000U)
#define	SPI_CTAR_PBR_SHIFT   (16U)
#define	SPI_CTAR_PBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
#define	SPI_CTAR_PDT_MASK   (0xC0000U)
#define	SPI_CTAR_PDT_SHIFT   (18U)
#define	SPI_CTAR_PDT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
#define	SPI_CTAR_PASC_MASK   (0x300000U)
#define	SPI_CTAR_PASC_SHIFT   (20U)
#define	SPI_CTAR_PASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
#define	SPI_CTAR_PCSSCK_MASK   (0xC00000U)
#define	SPI_CTAR_PCSSCK_SHIFT   (22U)
#define	SPI_CTAR_PCSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
#define	SPI_CTAR_LSBFE_MASK   (0x1000000U)
#define	SPI_CTAR_LSBFE_SHIFT   (24U)
#define	SPI_CTAR_LSBFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
#define	SPI_CTAR_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_CPHA_SHIFT   (25U)
#define	SPI_CTAR_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
#define	SPI_CTAR_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_CPOL_SHIFT   (26U)
#define	SPI_CTAR_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
#define	SPI_CTAR_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
#define	SPI_CTAR_DBR_MASK   (0x80000000U)
#define	SPI_CTAR_DBR_SHIFT   (31U)
#define	SPI_CTAR_DBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
#define	SPI_CTAR_BR_MASK   (0xFU)
#define	SPI_CTAR_BR_SHIFT   (0U)
#define	SPI_CTAR_BR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
#define	SPI_CTAR_DT_MASK   (0xF0U)
#define	SPI_CTAR_DT_SHIFT   (4U)
#define	SPI_CTAR_DT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
#define	SPI_CTAR_ASC_MASK   (0xF00U)
#define	SPI_CTAR_ASC_SHIFT   (8U)
#define	SPI_CTAR_ASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
#define	SPI_CTAR_CSSCK_MASK   (0xF000U)
#define	SPI_CTAR_CSSCK_SHIFT   (12U)
#define	SPI_CTAR_CSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
#define	SPI_CTAR_PBR_MASK   (0x30000U)
#define	SPI_CTAR_PBR_SHIFT   (16U)
#define	SPI_CTAR_PBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
#define	SPI_CTAR_PDT_MASK   (0xC0000U)
#define	SPI_CTAR_PDT_SHIFT   (18U)
#define	SPI_CTAR_PDT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
#define	SPI_CTAR_PASC_MASK   (0x300000U)
#define	SPI_CTAR_PASC_SHIFT   (20U)
#define	SPI_CTAR_PASC(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
#define	SPI_CTAR_PCSSCK_MASK   (0xC00000U)
#define	SPI_CTAR_PCSSCK_SHIFT   (22U)
#define	SPI_CTAR_PCSSCK(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
#define	SPI_CTAR_LSBFE_MASK   (0x1000000U)
#define	SPI_CTAR_LSBFE_SHIFT   (24U)
#define	SPI_CTAR_LSBFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
#define	SPI_CTAR_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_CPHA_SHIFT   (25U)
#define	SPI_CTAR_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
#define	SPI_CTAR_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_CPOL_SHIFT   (26U)
#define	SPI_CTAR_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
#define	SPI_CTAR_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
#define	SPI_CTAR_DBR_MASK   (0x80000000U)
#define	SPI_CTAR_DBR_SHIFT   (31U)
#define	SPI_CTAR_DBR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)

CTAR - DSPI Clock and Transfer Attributes Register (In Master Mode)
#define	SPI_CTAR_COUNT   (2U)

CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
#define	SPI_CTAR_SLAVE_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_SLAVE_CPHA_SHIFT   (25U)
#define	SPI_CTAR_SLAVE_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
#define	SPI_CTAR_SLAVE_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_SLAVE_CPOL_SHIFT   (26U)
#define	SPI_CTAR_SLAVE_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
#define	SPI_CTAR_SLAVE_FMSZ_MASK   (0xF8000000U)
#define	SPI_CTAR_SLAVE_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_SLAVE_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
#define	SPI_CTAR_SLAVE_CPHA_MASK   0x2000000u
#define	SPI_CTAR_SLAVE_CPHA_SHIFT   25
#define	SPI_CTAR_SLAVE_CPOL_MASK   0x4000000u
#define	SPI_CTAR_SLAVE_CPOL_SHIFT   26
#define	SPI_CTAR_SLAVE_FMSZ_MASK   0xF8000000u
#define	SPI_CTAR_SLAVE_FMSZ_SHIFT   27
#define	SPI_CTAR_SLAVE_FMSZ(x)   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
#define	SPI_CTAR_SLAVE_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_SLAVE_CPHA_SHIFT   (25U)
#define	SPI_CTAR_SLAVE_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
#define	SPI_CTAR_SLAVE_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_SLAVE_CPOL_SHIFT   (26U)
#define	SPI_CTAR_SLAVE_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
#define	SPI_CTAR_SLAVE_FMSZ_MASK   (0xF8000000U)
#define	SPI_CTAR_SLAVE_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_SLAVE_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
#define	SPI_CTAR_SLAVE_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_SLAVE_CPHA_SHIFT   (25U)
#define	SPI_CTAR_SLAVE_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
#define	SPI_CTAR_SLAVE_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_SLAVE_CPOL_SHIFT   (26U)
#define	SPI_CTAR_SLAVE_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
#define	SPI_CTAR_SLAVE_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_SLAVE_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_SLAVE_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
#define	SPI_CTAR_SLAVE_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_SLAVE_CPHA_SHIFT   (25U)
#define	SPI_CTAR_SLAVE_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
#define	SPI_CTAR_SLAVE_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_SLAVE_CPOL_SHIFT   (26U)
#define	SPI_CTAR_SLAVE_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
#define	SPI_CTAR_SLAVE_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_SLAVE_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_SLAVE_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
#define	SPI_CTAR_SLAVE_CPHA_MASK   (0x2000000U)
#define	SPI_CTAR_SLAVE_CPHA_SHIFT   (25U)
#define	SPI_CTAR_SLAVE_CPHA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
#define	SPI_CTAR_SLAVE_CPOL_MASK   (0x4000000U)
#define	SPI_CTAR_SLAVE_CPOL_SHIFT   (26U)
#define	SPI_CTAR_SLAVE_CPOL(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
#define	SPI_CTAR_SLAVE_FMSZ_MASK   (0x78000000U)
#define	SPI_CTAR_SLAVE_FMSZ_SHIFT   (27U)
#define	SPI_CTAR_SLAVE_FMSZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)

CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
#define	SPI_CTAR_SLAVE_COUNT   (1U)

SR - Status Register
#define	SPI_SR_POPNXTPTR_MASK   (0xFU)
#define	SPI_SR_POPNXTPTR_SHIFT   (0U)
#define	SPI_SR_POPNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
#define	SPI_SR_RXCTR_MASK   (0xF0U)
#define	SPI_SR_RXCTR_SHIFT   (4U)
#define	SPI_SR_RXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
#define	SPI_SR_TXNXTPTR_MASK   (0xF00U)
#define	SPI_SR_TXNXTPTR_SHIFT   (8U)
#define	SPI_SR_TXNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
#define	SPI_SR_TXCTR_MASK   (0xF000U)
#define	SPI_SR_TXCTR_SHIFT   (12U)
#define	SPI_SR_TXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
#define	SPI_SR_RFDF_MASK   (0x20000U)
#define	SPI_SR_RFDF_SHIFT   (17U)
#define	SPI_SR_RFDF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
#define	SPI_SR_RFOF_MASK   (0x80000U)
#define	SPI_SR_RFOF_SHIFT   (19U)
#define	SPI_SR_RFOF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
#define	SPI_SR_TFFF_MASK   (0x2000000U)
#define	SPI_SR_TFFF_SHIFT   (25U)
#define	SPI_SR_TFFF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
#define	SPI_SR_TFUF_MASK   (0x8000000U)
#define	SPI_SR_TFUF_SHIFT   (27U)
#define	SPI_SR_TFUF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
#define	SPI_SR_EOQF_MASK   (0x10000000U)
#define	SPI_SR_EOQF_SHIFT   (28U)
#define	SPI_SR_EOQF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
#define	SPI_SR_TXRXS_MASK   (0x40000000U)
#define	SPI_SR_TXRXS_SHIFT   (30U)
#define	SPI_SR_TXRXS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
#define	SPI_SR_TCF_MASK   (0x80000000U)
#define	SPI_SR_TCF_SHIFT   (31U)
#define	SPI_SR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
#define	SPI_SR_POPNXTPTR_MASK   0xFu
#define	SPI_SR_POPNXTPTR_SHIFT   0
#define	SPI_SR_POPNXTPTR(x)   (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
#define	SPI_SR_RXCTR_MASK   0xF0u
#define	SPI_SR_RXCTR_SHIFT   4
#define	SPI_SR_RXCTR(x)   (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
#define	SPI_SR_TXNXTPTR_MASK   0xF00u
#define	SPI_SR_TXNXTPTR_SHIFT   8
#define	SPI_SR_TXNXTPTR(x)   (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
#define	SPI_SR_TXCTR_MASK   0xF000u
#define	SPI_SR_TXCTR_SHIFT   12
#define	SPI_SR_TXCTR(x)   (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
#define	SPI_SR_RFDF_MASK   0x20000u
#define	SPI_SR_RFDF_SHIFT   17
#define	SPI_SR_RFOF_MASK   0x80000u
#define	SPI_SR_RFOF_SHIFT   19
#define	SPI_SR_TFFF_MASK   0x2000000u
#define	SPI_SR_TFFF_SHIFT   25
#define	SPI_SR_TFUF_MASK   0x8000000u
#define	SPI_SR_TFUF_SHIFT   27
#define	SPI_SR_EOQF_MASK   0x10000000u
#define	SPI_SR_EOQF_SHIFT   28
#define	SPI_SR_TXRXS_MASK   0x40000000u
#define	SPI_SR_TXRXS_SHIFT   30
#define	SPI_SR_TCF_MASK   0x80000000u
#define	SPI_SR_TCF_SHIFT   31
#define	SPI_SR_POPNXTPTR_MASK   (0xFU)
#define	SPI_SR_POPNXTPTR_SHIFT   (0U)
#define	SPI_SR_POPNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
#define	SPI_SR_RXCTR_MASK   (0xF0U)
#define	SPI_SR_RXCTR_SHIFT   (4U)
#define	SPI_SR_RXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
#define	SPI_SR_TXNXTPTR_MASK   (0xF00U)
#define	SPI_SR_TXNXTPTR_SHIFT   (8U)
#define	SPI_SR_TXNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
#define	SPI_SR_TXCTR_MASK   (0xF000U)
#define	SPI_SR_TXCTR_SHIFT   (12U)
#define	SPI_SR_TXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
#define	SPI_SR_RFDF_MASK   (0x20000U)
#define	SPI_SR_RFDF_SHIFT   (17U)
#define	SPI_SR_RFDF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
#define	SPI_SR_RFOF_MASK   (0x80000U)
#define	SPI_SR_RFOF_SHIFT   (19U)
#define	SPI_SR_RFOF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
#define	SPI_SR_TFFF_MASK   (0x2000000U)
#define	SPI_SR_TFFF_SHIFT   (25U)
#define	SPI_SR_TFFF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
#define	SPI_SR_TFUF_MASK   (0x8000000U)
#define	SPI_SR_TFUF_SHIFT   (27U)
#define	SPI_SR_TFUF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
#define	SPI_SR_EOQF_MASK   (0x10000000U)
#define	SPI_SR_EOQF_SHIFT   (28U)
#define	SPI_SR_EOQF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
#define	SPI_SR_TXRXS_MASK   (0x40000000U)
#define	SPI_SR_TXRXS_SHIFT   (30U)
#define	SPI_SR_TXRXS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
#define	SPI_SR_TCF_MASK   (0x80000000U)
#define	SPI_SR_TCF_SHIFT   (31U)
#define	SPI_SR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
#define	SPI_SR_POPNXTPTR_MASK   (0xFU)
#define	SPI_SR_POPNXTPTR_SHIFT   (0U)
#define	SPI_SR_POPNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
#define	SPI_SR_RXCTR_MASK   (0xF0U)
#define	SPI_SR_RXCTR_SHIFT   (4U)
#define	SPI_SR_RXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
#define	SPI_SR_TXNXTPTR_MASK   (0xF00U)
#define	SPI_SR_TXNXTPTR_SHIFT   (8U)
#define	SPI_SR_TXNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
#define	SPI_SR_TXCTR_MASK   (0xF000U)
#define	SPI_SR_TXCTR_SHIFT   (12U)
#define	SPI_SR_TXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
#define	SPI_SR_RFDF_MASK   (0x20000U)
#define	SPI_SR_RFDF_SHIFT   (17U)
#define	SPI_SR_RFDF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
#define	SPI_SR_RFOF_MASK   (0x80000U)
#define	SPI_SR_RFOF_SHIFT   (19U)
#define	SPI_SR_RFOF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
#define	SPI_SR_TFFF_MASK   (0x2000000U)
#define	SPI_SR_TFFF_SHIFT   (25U)
#define	SPI_SR_TFFF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
#define	SPI_SR_TFUF_MASK   (0x8000000U)
#define	SPI_SR_TFUF_SHIFT   (27U)
#define	SPI_SR_TFUF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
#define	SPI_SR_EOQF_MASK   (0x10000000U)
#define	SPI_SR_EOQF_SHIFT   (28U)
#define	SPI_SR_EOQF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
#define	SPI_SR_TXRXS_MASK   (0x40000000U)
#define	SPI_SR_TXRXS_SHIFT   (30U)
#define	SPI_SR_TXRXS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
#define	SPI_SR_TCF_MASK   (0x80000000U)
#define	SPI_SR_TCF_SHIFT   (31U)
#define	SPI_SR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
#define	SPI_SR_POPNXTPTR_MASK   (0xFU)
#define	SPI_SR_POPNXTPTR_SHIFT   (0U)
#define	SPI_SR_POPNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
#define	SPI_SR_RXCTR_MASK   (0xF0U)
#define	SPI_SR_RXCTR_SHIFT   (4U)
#define	SPI_SR_RXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
#define	SPI_SR_TXNXTPTR_MASK   (0xF00U)
#define	SPI_SR_TXNXTPTR_SHIFT   (8U)
#define	SPI_SR_TXNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
#define	SPI_SR_TXCTR_MASK   (0xF000U)
#define	SPI_SR_TXCTR_SHIFT   (12U)
#define	SPI_SR_TXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
#define	SPI_SR_RFDF_MASK   (0x20000U)
#define	SPI_SR_RFDF_SHIFT   (17U)
#define	SPI_SR_RFDF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
#define	SPI_SR_RFOF_MASK   (0x80000U)
#define	SPI_SR_RFOF_SHIFT   (19U)
#define	SPI_SR_RFOF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
#define	SPI_SR_TFFF_MASK   (0x2000000U)
#define	SPI_SR_TFFF_SHIFT   (25U)
#define	SPI_SR_TFFF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
#define	SPI_SR_TFUF_MASK   (0x8000000U)
#define	SPI_SR_TFUF_SHIFT   (27U)
#define	SPI_SR_TFUF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
#define	SPI_SR_EOQF_MASK   (0x10000000U)
#define	SPI_SR_EOQF_SHIFT   (28U)
#define	SPI_SR_EOQF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
#define	SPI_SR_TXRXS_MASK   (0x40000000U)
#define	SPI_SR_TXRXS_SHIFT   (30U)
#define	SPI_SR_TXRXS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
#define	SPI_SR_TCF_MASK   (0x80000000U)
#define	SPI_SR_TCF_SHIFT   (31U)
#define	SPI_SR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
#define	SPI_SR_POPNXTPTR_MASK   (0xFU)
#define	SPI_SR_POPNXTPTR_SHIFT   (0U)
#define	SPI_SR_POPNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
#define	SPI_SR_RXCTR_MASK   (0xF0U)
#define	SPI_SR_RXCTR_SHIFT   (4U)
#define	SPI_SR_RXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
#define	SPI_SR_TXNXTPTR_MASK   (0xF00U)
#define	SPI_SR_TXNXTPTR_SHIFT   (8U)
#define	SPI_SR_TXNXTPTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
#define	SPI_SR_TXCTR_MASK   (0xF000U)
#define	SPI_SR_TXCTR_SHIFT   (12U)
#define	SPI_SR_TXCTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
#define	SPI_SR_RFDF_MASK   (0x20000U)
#define	SPI_SR_RFDF_SHIFT   (17U)
#define	SPI_SR_RFDF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
#define	SPI_SR_RFOF_MASK   (0x80000U)
#define	SPI_SR_RFOF_SHIFT   (19U)
#define	SPI_SR_RFOF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
#define	SPI_SR_TFFF_MASK   (0x2000000U)
#define	SPI_SR_TFFF_SHIFT   (25U)
#define	SPI_SR_TFFF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
#define	SPI_SR_TFUF_MASK   (0x8000000U)
#define	SPI_SR_TFUF_SHIFT   (27U)
#define	SPI_SR_TFUF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
#define	SPI_SR_EOQF_MASK   (0x10000000U)
#define	SPI_SR_EOQF_SHIFT   (28U)
#define	SPI_SR_EOQF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
#define	SPI_SR_TXRXS_MASK   (0x40000000U)
#define	SPI_SR_TXRXS_SHIFT   (30U)
#define	SPI_SR_TXRXS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
#define	SPI_SR_TCF_MASK   (0x80000000U)
#define	SPI_SR_TCF_SHIFT   (31U)
#define	SPI_SR_TCF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)

RSER - DMA/Interrupt Request Select and Enable Register
#define	SPI_RSER_RFDF_DIRS_MASK   (0x10000U)
#define	SPI_RSER_RFDF_DIRS_SHIFT   (16U)
#define	SPI_RSER_RFDF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
#define	SPI_RSER_RFDF_RE_MASK   (0x20000U)
#define	SPI_RSER_RFDF_RE_SHIFT   (17U)
#define	SPI_RSER_RFDF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
#define	SPI_RSER_RFOF_RE_MASK   (0x80000U)
#define	SPI_RSER_RFOF_RE_SHIFT   (19U)
#define	SPI_RSER_RFOF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
#define	SPI_RSER_TFFF_DIRS_MASK   (0x1000000U)
#define	SPI_RSER_TFFF_DIRS_SHIFT   (24U)
#define	SPI_RSER_TFFF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
#define	SPI_RSER_TFFF_RE_MASK   (0x2000000U)
#define	SPI_RSER_TFFF_RE_SHIFT   (25U)
#define	SPI_RSER_TFFF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
#define	SPI_RSER_TFUF_RE_MASK   (0x8000000U)
#define	SPI_RSER_TFUF_RE_SHIFT   (27U)
#define	SPI_RSER_TFUF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
#define	SPI_RSER_EOQF_RE_MASK   (0x10000000U)
#define	SPI_RSER_EOQF_RE_SHIFT   (28U)
#define	SPI_RSER_EOQF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
#define	SPI_RSER_TCF_RE_MASK   (0x80000000U)
#define	SPI_RSER_TCF_RE_SHIFT   (31U)
#define	SPI_RSER_TCF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
#define	SPI_RSER_RFDF_DIRS_MASK   0x10000u
#define	SPI_RSER_RFDF_DIRS_SHIFT   16
#define	SPI_RSER_RFDF_RE_MASK   0x20000u
#define	SPI_RSER_RFDF_RE_SHIFT   17
#define	SPI_RSER_RFOF_RE_MASK   0x80000u
#define	SPI_RSER_RFOF_RE_SHIFT   19
#define	SPI_RSER_TFFF_DIRS_MASK   0x1000000u
#define	SPI_RSER_TFFF_DIRS_SHIFT   24
#define	SPI_RSER_TFFF_RE_MASK   0x2000000u
#define	SPI_RSER_TFFF_RE_SHIFT   25
#define	SPI_RSER_TFUF_RE_MASK   0x8000000u
#define	SPI_RSER_TFUF_RE_SHIFT   27
#define	SPI_RSER_EOQF_RE_MASK   0x10000000u
#define	SPI_RSER_EOQF_RE_SHIFT   28
#define	SPI_RSER_TCF_RE_MASK   0x80000000u
#define	SPI_RSER_TCF_RE_SHIFT   31
#define	SPI_RSER_RFDF_DIRS_MASK   (0x10000U)
#define	SPI_RSER_RFDF_DIRS_SHIFT   (16U)
#define	SPI_RSER_RFDF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
#define	SPI_RSER_RFDF_RE_MASK   (0x20000U)
#define	SPI_RSER_RFDF_RE_SHIFT   (17U)
#define	SPI_RSER_RFDF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
#define	SPI_RSER_RFOF_RE_MASK   (0x80000U)
#define	SPI_RSER_RFOF_RE_SHIFT   (19U)
#define	SPI_RSER_RFOF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
#define	SPI_RSER_TFFF_DIRS_MASK   (0x1000000U)
#define	SPI_RSER_TFFF_DIRS_SHIFT   (24U)
#define	SPI_RSER_TFFF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
#define	SPI_RSER_TFFF_RE_MASK   (0x2000000U)
#define	SPI_RSER_TFFF_RE_SHIFT   (25U)
#define	SPI_RSER_TFFF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
#define	SPI_RSER_TFUF_RE_MASK   (0x8000000U)
#define	SPI_RSER_TFUF_RE_SHIFT   (27U)
#define	SPI_RSER_TFUF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
#define	SPI_RSER_EOQF_RE_MASK   (0x10000000U)
#define	SPI_RSER_EOQF_RE_SHIFT   (28U)
#define	SPI_RSER_EOQF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
#define	SPI_RSER_TCF_RE_MASK   (0x80000000U)
#define	SPI_RSER_TCF_RE_SHIFT   (31U)
#define	SPI_RSER_TCF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
#define	SPI_RSER_RFDF_DIRS_MASK   (0x10000U)
#define	SPI_RSER_RFDF_DIRS_SHIFT   (16U)
#define	SPI_RSER_RFDF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
#define	SPI_RSER_RFDF_RE_MASK   (0x20000U)
#define	SPI_RSER_RFDF_RE_SHIFT   (17U)
#define	SPI_RSER_RFDF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
#define	SPI_RSER_RFOF_RE_MASK   (0x80000U)
#define	SPI_RSER_RFOF_RE_SHIFT   (19U)
#define	SPI_RSER_RFOF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
#define	SPI_RSER_TFFF_DIRS_MASK   (0x1000000U)
#define	SPI_RSER_TFFF_DIRS_SHIFT   (24U)
#define	SPI_RSER_TFFF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
#define	SPI_RSER_TFFF_RE_MASK   (0x2000000U)
#define	SPI_RSER_TFFF_RE_SHIFT   (25U)
#define	SPI_RSER_TFFF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
#define	SPI_RSER_TFUF_RE_MASK   (0x8000000U)
#define	SPI_RSER_TFUF_RE_SHIFT   (27U)
#define	SPI_RSER_TFUF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
#define	SPI_RSER_EOQF_RE_MASK   (0x10000000U)
#define	SPI_RSER_EOQF_RE_SHIFT   (28U)
#define	SPI_RSER_EOQF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
#define	SPI_RSER_TCF_RE_MASK   (0x80000000U)
#define	SPI_RSER_TCF_RE_SHIFT   (31U)
#define	SPI_RSER_TCF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
#define	SPI_RSER_RFDF_DIRS_MASK   (0x10000U)
#define	SPI_RSER_RFDF_DIRS_SHIFT   (16U)
#define	SPI_RSER_RFDF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
#define	SPI_RSER_RFDF_RE_MASK   (0x20000U)
#define	SPI_RSER_RFDF_RE_SHIFT   (17U)
#define	SPI_RSER_RFDF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
#define	SPI_RSER_RFOF_RE_MASK   (0x80000U)
#define	SPI_RSER_RFOF_RE_SHIFT   (19U)
#define	SPI_RSER_RFOF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
#define	SPI_RSER_TFFF_DIRS_MASK   (0x1000000U)
#define	SPI_RSER_TFFF_DIRS_SHIFT   (24U)
#define	SPI_RSER_TFFF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
#define	SPI_RSER_TFFF_RE_MASK   (0x2000000U)
#define	SPI_RSER_TFFF_RE_SHIFT   (25U)
#define	SPI_RSER_TFFF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
#define	SPI_RSER_TFUF_RE_MASK   (0x8000000U)
#define	SPI_RSER_TFUF_RE_SHIFT   (27U)
#define	SPI_RSER_TFUF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
#define	SPI_RSER_EOQF_RE_MASK   (0x10000000U)
#define	SPI_RSER_EOQF_RE_SHIFT   (28U)
#define	SPI_RSER_EOQF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
#define	SPI_RSER_TCF_RE_MASK   (0x80000000U)
#define	SPI_RSER_TCF_RE_SHIFT   (31U)
#define	SPI_RSER_TCF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
#define	SPI_RSER_RFDF_DIRS_MASK   (0x10000U)
#define	SPI_RSER_RFDF_DIRS_SHIFT   (16U)
#define	SPI_RSER_RFDF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
#define	SPI_RSER_RFDF_RE_MASK   (0x20000U)
#define	SPI_RSER_RFDF_RE_SHIFT   (17U)
#define	SPI_RSER_RFDF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
#define	SPI_RSER_RFOF_RE_MASK   (0x80000U)
#define	SPI_RSER_RFOF_RE_SHIFT   (19U)
#define	SPI_RSER_RFOF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
#define	SPI_RSER_TFFF_DIRS_MASK   (0x1000000U)
#define	SPI_RSER_TFFF_DIRS_SHIFT   (24U)
#define	SPI_RSER_TFFF_DIRS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
#define	SPI_RSER_TFFF_RE_MASK   (0x2000000U)
#define	SPI_RSER_TFFF_RE_SHIFT   (25U)
#define	SPI_RSER_TFFF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
#define	SPI_RSER_TFUF_RE_MASK   (0x8000000U)
#define	SPI_RSER_TFUF_RE_SHIFT   (27U)
#define	SPI_RSER_TFUF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
#define	SPI_RSER_EOQF_RE_MASK   (0x10000000U)
#define	SPI_RSER_EOQF_RE_SHIFT   (28U)
#define	SPI_RSER_EOQF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
#define	SPI_RSER_TCF_RE_MASK   (0x80000000U)
#define	SPI_RSER_TCF_RE_SHIFT   (31U)
#define	SPI_RSER_TCF_RE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)

PUSHR - PUSH TX FIFO Register In Master Mode
#define	SPI_PUSHR_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
#define	SPI_PUSHR_PCS_MASK   (0x3F0000U)
#define	SPI_PUSHR_PCS_SHIFT   (16U)
#define	SPI_PUSHR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
#define	SPI_PUSHR_CTCNT_MASK   (0x4000000U)
#define	SPI_PUSHR_CTCNT_SHIFT   (26U)
#define	SPI_PUSHR_CTCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
#define	SPI_PUSHR_EOQ_MASK   (0x8000000U)
#define	SPI_PUSHR_EOQ_SHIFT   (27U)
#define	SPI_PUSHR_EOQ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
#define	SPI_PUSHR_CTAS_MASK   (0x70000000U)
#define	SPI_PUSHR_CTAS_SHIFT   (28U)
#define	SPI_PUSHR_CTAS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
#define	SPI_PUSHR_CONT_MASK   (0x80000000U)
#define	SPI_PUSHR_CONT_SHIFT   (31U)
#define	SPI_PUSHR_CONT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
#define	SPI_PUSHR_TXDATA_MASK   0xFFFFu
#define	SPI_PUSHR_TXDATA_SHIFT   0
#define	SPI_PUSHR_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
#define	SPI_PUSHR_PCS_MASK   0x3F0000u
#define	SPI_PUSHR_PCS_SHIFT   16
#define	SPI_PUSHR_PCS(x)   (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
#define	SPI_PUSHR_CTCNT_MASK   0x4000000u
#define	SPI_PUSHR_CTCNT_SHIFT   26
#define	SPI_PUSHR_EOQ_MASK   0x8000000u
#define	SPI_PUSHR_EOQ_SHIFT   27
#define	SPI_PUSHR_CTAS_MASK   0x70000000u
#define	SPI_PUSHR_CTAS_SHIFT   28
#define	SPI_PUSHR_CTAS(x)   (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
#define	SPI_PUSHR_CONT_MASK   0x80000000u
#define	SPI_PUSHR_CONT_SHIFT   31
#define	SPI_PUSHR_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
#define	SPI_PUSHR_PCS_MASK   (0x3F0000U)
#define	SPI_PUSHR_PCS_SHIFT   (16U)
#define	SPI_PUSHR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
#define	SPI_PUSHR_CTCNT_MASK   (0x4000000U)
#define	SPI_PUSHR_CTCNT_SHIFT   (26U)
#define	SPI_PUSHR_CTCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
#define	SPI_PUSHR_EOQ_MASK   (0x8000000U)
#define	SPI_PUSHR_EOQ_SHIFT   (27U)
#define	SPI_PUSHR_EOQ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
#define	SPI_PUSHR_CTAS_MASK   (0x70000000U)
#define	SPI_PUSHR_CTAS_SHIFT   (28U)
#define	SPI_PUSHR_CTAS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
#define	SPI_PUSHR_CONT_MASK   (0x80000000U)
#define	SPI_PUSHR_CONT_SHIFT   (31U)
#define	SPI_PUSHR_CONT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
#define	SPI_PUSHR_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
#define	SPI_PUSHR_PCS_MASK   (0x3F0000U)
#define	SPI_PUSHR_PCS_SHIFT   (16U)
#define	SPI_PUSHR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
#define	SPI_PUSHR_CTCNT_MASK   (0x4000000U)
#define	SPI_PUSHR_CTCNT_SHIFT   (26U)
#define	SPI_PUSHR_CTCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
#define	SPI_PUSHR_EOQ_MASK   (0x8000000U)
#define	SPI_PUSHR_EOQ_SHIFT   (27U)
#define	SPI_PUSHR_EOQ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
#define	SPI_PUSHR_CTAS_MASK   (0x70000000U)
#define	SPI_PUSHR_CTAS_SHIFT   (28U)
#define	SPI_PUSHR_CTAS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
#define	SPI_PUSHR_CONT_MASK   (0x80000000U)
#define	SPI_PUSHR_CONT_SHIFT   (31U)
#define	SPI_PUSHR_CONT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
#define	SPI_PUSHR_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
#define	SPI_PUSHR_PCS_MASK   (0x3F0000U)
#define	SPI_PUSHR_PCS_SHIFT   (16U)
#define	SPI_PUSHR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
#define	SPI_PUSHR_CTCNT_MASK   (0x4000000U)
#define	SPI_PUSHR_CTCNT_SHIFT   (26U)
#define	SPI_PUSHR_CTCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
#define	SPI_PUSHR_EOQ_MASK   (0x8000000U)
#define	SPI_PUSHR_EOQ_SHIFT   (27U)
#define	SPI_PUSHR_EOQ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
#define	SPI_PUSHR_CTAS_MASK   (0x70000000U)
#define	SPI_PUSHR_CTAS_SHIFT   (28U)
#define	SPI_PUSHR_CTAS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
#define	SPI_PUSHR_CONT_MASK   (0x80000000U)
#define	SPI_PUSHR_CONT_SHIFT   (31U)
#define	SPI_PUSHR_CONT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
#define	SPI_PUSHR_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
#define	SPI_PUSHR_PCS_MASK   (0x3F0000U)
#define	SPI_PUSHR_PCS_SHIFT   (16U)
#define	SPI_PUSHR_PCS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
#define	SPI_PUSHR_CTCNT_MASK   (0x4000000U)
#define	SPI_PUSHR_CTCNT_SHIFT   (26U)
#define	SPI_PUSHR_CTCNT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
#define	SPI_PUSHR_EOQ_MASK   (0x8000000U)
#define	SPI_PUSHR_EOQ_SHIFT   (27U)
#define	SPI_PUSHR_EOQ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
#define	SPI_PUSHR_CTAS_MASK   (0x70000000U)
#define	SPI_PUSHR_CTAS_SHIFT   (28U)
#define	SPI_PUSHR_CTAS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
#define	SPI_PUSHR_CONT_MASK   (0x80000000U)
#define	SPI_PUSHR_CONT_SHIFT   (31U)
#define	SPI_PUSHR_CONT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)

PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
#define	SPI_PUSHR_SLAVE_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_SLAVE_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
#define	SPI_PUSHR_SLAVE_TXDATA_MASK   0xFFFFFFFFu
#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT   0
#define	SPI_PUSHR_SLAVE_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
#define	SPI_PUSHR_SLAVE_TXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_SLAVE_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
#define	SPI_PUSHR_SLAVE_TXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_SLAVE_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
#define	SPI_PUSHR_SLAVE_TXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_SLAVE_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
#define	SPI_PUSHR_SLAVE_TXDATA_MASK   (0xFFFFU)
#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT   (0U)
#define	SPI_PUSHR_SLAVE_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)

POPR - POP RX FIFO Register
#define	SPI_POPR_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_POPR_RXDATA_SHIFT   (0U)
#define	SPI_POPR_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
#define	SPI_POPR_RXDATA_MASK   0xFFFFFFFFu
#define	SPI_POPR_RXDATA_SHIFT   0
#define	SPI_POPR_RXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
#define	SPI_POPR_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_POPR_RXDATA_SHIFT   (0U)
#define	SPI_POPR_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
#define	SPI_POPR_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_POPR_RXDATA_SHIFT   (0U)
#define	SPI_POPR_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
#define	SPI_POPR_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_POPR_RXDATA_SHIFT   (0U)
#define	SPI_POPR_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
#define	SPI_POPR_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_POPR_RXDATA_SHIFT   (0U)
#define	SPI_POPR_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)

TXFR0 - Transmit FIFO Registers
#define	SPI_TXFR0_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR0_TXDATA_SHIFT   (0U)
#define	SPI_TXFR0_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
#define	SPI_TXFR0_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR0_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
#define	SPI_TXFR0_TXDATA_MASK   0xFFFFu
#define	SPI_TXFR0_TXDATA_SHIFT   0
#define	SPI_TXFR0_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
#define	SPI_TXFR0_TXCMD_TXDATA_MASK   0xFFFF0000u
#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT   16
#define	SPI_TXFR0_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
#define	SPI_TXFR0_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR0_TXDATA_SHIFT   (0U)
#define	SPI_TXFR0_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
#define	SPI_TXFR0_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR0_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
#define	SPI_TXFR0_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR0_TXDATA_SHIFT   (0U)
#define	SPI_TXFR0_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
#define	SPI_TXFR0_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR0_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
#define	SPI_TXFR0_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR0_TXDATA_SHIFT   (0U)
#define	SPI_TXFR0_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
#define	SPI_TXFR0_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR0_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
#define	SPI_TXFR0_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR0_TXDATA_SHIFT   (0U)
#define	SPI_TXFR0_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
#define	SPI_TXFR0_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR0_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)

TXFR1 - Transmit FIFO Registers
#define	SPI_TXFR1_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR1_TXDATA_SHIFT   (0U)
#define	SPI_TXFR1_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
#define	SPI_TXFR1_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR1_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
#define	SPI_TXFR1_TXDATA_MASK   0xFFFFu
#define	SPI_TXFR1_TXDATA_SHIFT   0
#define	SPI_TXFR1_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
#define	SPI_TXFR1_TXCMD_TXDATA_MASK   0xFFFF0000u
#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT   16
#define	SPI_TXFR1_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
#define	SPI_TXFR1_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR1_TXDATA_SHIFT   (0U)
#define	SPI_TXFR1_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
#define	SPI_TXFR1_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR1_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
#define	SPI_TXFR1_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR1_TXDATA_SHIFT   (0U)
#define	SPI_TXFR1_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
#define	SPI_TXFR1_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR1_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
#define	SPI_TXFR1_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR1_TXDATA_SHIFT   (0U)
#define	SPI_TXFR1_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
#define	SPI_TXFR1_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR1_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
#define	SPI_TXFR1_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR1_TXDATA_SHIFT   (0U)
#define	SPI_TXFR1_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
#define	SPI_TXFR1_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR1_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)

TXFR2 - Transmit FIFO Registers
#define	SPI_TXFR2_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR2_TXDATA_SHIFT   (0U)
#define	SPI_TXFR2_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
#define	SPI_TXFR2_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR2_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
#define	SPI_TXFR2_TXDATA_MASK   0xFFFFu
#define	SPI_TXFR2_TXDATA_SHIFT   0
#define	SPI_TXFR2_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
#define	SPI_TXFR2_TXCMD_TXDATA_MASK   0xFFFF0000u
#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT   16
#define	SPI_TXFR2_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
#define	SPI_TXFR2_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR2_TXDATA_SHIFT   (0U)
#define	SPI_TXFR2_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
#define	SPI_TXFR2_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR2_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
#define	SPI_TXFR2_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR2_TXDATA_SHIFT   (0U)
#define	SPI_TXFR2_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
#define	SPI_TXFR2_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR2_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
#define	SPI_TXFR2_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR2_TXDATA_SHIFT   (0U)
#define	SPI_TXFR2_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
#define	SPI_TXFR2_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR2_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
#define	SPI_TXFR2_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR2_TXDATA_SHIFT   (0U)
#define	SPI_TXFR2_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
#define	SPI_TXFR2_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR2_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)

TXFR3 - Transmit FIFO Registers
#define	SPI_TXFR3_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR3_TXDATA_SHIFT   (0U)
#define	SPI_TXFR3_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
#define	SPI_TXFR3_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR3_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
#define	SPI_TXFR3_TXDATA_MASK   0xFFFFu
#define	SPI_TXFR3_TXDATA_SHIFT   0
#define	SPI_TXFR3_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
#define	SPI_TXFR3_TXCMD_TXDATA_MASK   0xFFFF0000u
#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT   16
#define	SPI_TXFR3_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
#define	SPI_TXFR3_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR3_TXDATA_SHIFT   (0U)
#define	SPI_TXFR3_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
#define	SPI_TXFR3_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR3_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
#define	SPI_TXFR3_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR3_TXDATA_SHIFT   (0U)
#define	SPI_TXFR3_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
#define	SPI_TXFR3_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR3_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
#define	SPI_TXFR3_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR3_TXDATA_SHIFT   (0U)
#define	SPI_TXFR3_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
#define	SPI_TXFR3_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR3_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
#define	SPI_TXFR3_TXDATA_MASK   (0xFFFFU)
#define	SPI_TXFR3_TXDATA_SHIFT   (0U)
#define	SPI_TXFR3_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
#define	SPI_TXFR3_TXCMD_TXDATA_MASK   (0xFFFF0000U)
#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT   (16U)
#define	SPI_TXFR3_TXCMD_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)

RXFR0 - Receive FIFO Registers
#define	SPI_RXFR0_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR0_RXDATA_SHIFT   (0U)
#define	SPI_RXFR0_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
#define	SPI_RXFR0_RXDATA_MASK   0xFFFFFFFFu
#define	SPI_RXFR0_RXDATA_SHIFT   0
#define	SPI_RXFR0_RXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
#define	SPI_RXFR0_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR0_RXDATA_SHIFT   (0U)
#define	SPI_RXFR0_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
#define	SPI_RXFR0_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR0_RXDATA_SHIFT   (0U)
#define	SPI_RXFR0_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
#define	SPI_RXFR0_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR0_RXDATA_SHIFT   (0U)
#define	SPI_RXFR0_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
#define	SPI_RXFR0_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR0_RXDATA_SHIFT   (0U)
#define	SPI_RXFR0_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)

RXFR1 - Receive FIFO Registers
#define	SPI_RXFR1_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR1_RXDATA_SHIFT   (0U)
#define	SPI_RXFR1_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
#define	SPI_RXFR1_RXDATA_MASK   0xFFFFFFFFu
#define	SPI_RXFR1_RXDATA_SHIFT   0
#define	SPI_RXFR1_RXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
#define	SPI_RXFR1_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR1_RXDATA_SHIFT   (0U)
#define	SPI_RXFR1_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
#define	SPI_RXFR1_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR1_RXDATA_SHIFT   (0U)
#define	SPI_RXFR1_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
#define	SPI_RXFR1_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR1_RXDATA_SHIFT   (0U)
#define	SPI_RXFR1_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
#define	SPI_RXFR1_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR1_RXDATA_SHIFT   (0U)
#define	SPI_RXFR1_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)

RXFR2 - Receive FIFO Registers
#define	SPI_RXFR2_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR2_RXDATA_SHIFT   (0U)
#define	SPI_RXFR2_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
#define	SPI_RXFR2_RXDATA_MASK   0xFFFFFFFFu
#define	SPI_RXFR2_RXDATA_SHIFT   0
#define	SPI_RXFR2_RXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
#define	SPI_RXFR2_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR2_RXDATA_SHIFT   (0U)
#define	SPI_RXFR2_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
#define	SPI_RXFR2_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR2_RXDATA_SHIFT   (0U)
#define	SPI_RXFR2_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
#define	SPI_RXFR2_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR2_RXDATA_SHIFT   (0U)
#define	SPI_RXFR2_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
#define	SPI_RXFR2_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR2_RXDATA_SHIFT   (0U)
#define	SPI_RXFR2_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)

RXFR3 - Receive FIFO Registers
#define	SPI_RXFR3_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR3_RXDATA_SHIFT   (0U)
#define	SPI_RXFR3_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
#define	SPI_RXFR3_RXDATA_MASK   0xFFFFFFFFu
#define	SPI_RXFR3_RXDATA_SHIFT   0
#define	SPI_RXFR3_RXDATA(x)   (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
#define	SPI_RXFR3_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR3_RXDATA_SHIFT   (0U)
#define	SPI_RXFR3_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
#define	SPI_RXFR3_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR3_RXDATA_SHIFT   (0U)
#define	SPI_RXFR3_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
#define	SPI_RXFR3_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR3_RXDATA_SHIFT   (0U)
#define	SPI_RXFR3_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
#define	SPI_RXFR3_RXDATA_MASK   (0xFFFFFFFFU)
#define	SPI_RXFR3_RXDATA_SHIFT   (0U)
#define	SPI_RXFR3_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)

Macro Definition Documentation

SPI0

#define SPI0   ((SPI_Type *)SPI0_BASE)

Peripheral SPI0 base pointer

SPI0_BASE

#define SPI0_BASE   (0x4002C000u)

Peripheral SPI0 base address

SPI1

#define SPI1   ((SPI_Type *)SPI1_BASE)

Peripheral SPI1 base pointer

SPI1_BASE

#define SPI1_BASE   (0x4002D000u)

Peripheral SPI1 base address

SPI2

#define SPI2   ((SPI_Type *)SPI2_BASE)

Peripheral SPI2 base pointer

SPI2_BASE

#define SPI2_BASE   (0x400AC000u)

Peripheral SPI2 base address

SPI_BASE_ADDRS

#define SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE, SPI2_BASE }

Array initializer of SPI peripheral base addresses

SPI_BASE_PTRS

#define SPI_BASE_PTRS   { SPI0, SPI1, SPI2 }

Array initializer of SPI peripheral base pointers

SPI_CTAR_CPHA [1/5]

#define SPI_CTAR_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_CPHA [2/5]

#define SPI_CTAR_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_CPHA [3/5]

#define SPI_CTAR_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_CPHA [4/5]

#define SPI_CTAR_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_CPHA [5/5]

#define SPI_CTAR_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_CPOL [1/5]

#define SPI_CTAR_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_CPOL [2/5]

#define SPI_CTAR_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_CPOL [3/5]

#define SPI_CTAR_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_CPOL [4/5]

#define SPI_CTAR_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_CPOL [5/5]

#define SPI_CTAR_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_DBR [1/5]

#define SPI_CTAR_DBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)

DBR - Double Baud Rate 0b0..The baud rate is computed normally with a 50/50 duty cycle. 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

SPI_CTAR_DBR [2/5]

#define SPI_CTAR_DBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)

DBR - Double Baud Rate 0b0..The baud rate is computed normally with a 50/50 duty cycle. 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

SPI_CTAR_DBR [3/5]

#define SPI_CTAR_DBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)

DBR - Double Baud Rate 0b0..The baud rate is computed normally with a 50/50 duty cycle. 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

SPI_CTAR_DBR [4/5]

#define SPI_CTAR_DBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)

DBR - Double Baud Rate 0b0..The baud rate is computed normally with a 50/50 duty cycle. 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

SPI_CTAR_DBR [5/5]

#define SPI_CTAR_DBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)

DBR - Double Baud Rate 0b0..The baud rate is computed normally with a 50/50 duty cycle. 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

SPI_CTAR_LSBFE [1/5]

#define SPI_CTAR_LSBFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)

LSBFE - LSB First 0b0..Data is transferred MSB first. 0b1..Data is transferred LSB first.

SPI_CTAR_LSBFE [2/5]

#define SPI_CTAR_LSBFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)

LSBFE - LSB First 0b0..Data is transferred MSB first. 0b1..Data is transferred LSB first.

SPI_CTAR_LSBFE [3/5]

#define SPI_CTAR_LSBFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)

LSBFE - LSB First 0b0..Data is transferred MSB first. 0b1..Data is transferred LSB first.

SPI_CTAR_LSBFE [4/5]

#define SPI_CTAR_LSBFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)

LSBFE - LSB First 0b0..Data is transferred MSB first. 0b1..Data is transferred LSB first.

SPI_CTAR_LSBFE [5/5]

#define SPI_CTAR_LSBFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)

LSBFE - LSB First 0b0..Data is transferred MSB first. 0b1..Data is transferred LSB first.

SPI_CTAR_PASC [1/6]

#define SPI_CTAR_PASC

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)

PASC - After SCK Delay Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PASC [2/6]

#define SPI_CTAR_PASC

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)

PASC - After SCK Delay Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PASC [3/6]

#define SPI_CTAR_PASC

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)

PASC - After SCK Delay Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PASC [4/6]

#define SPI_CTAR_PASC

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)

PASC - After SCK Delay Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PASC [5/6]

#define SPI_CTAR_PASC

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)

PASC - After SCK Delay Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PASC [6/6]

#define SPI_CTAR_PASC

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)

PASC - After SCK Delay Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PBR [1/6]

#define SPI_CTAR_PBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)

PBR - Baud Rate Prescaler 0b00..Baud Rate Prescaler value is 2. 0b01..Baud Rate Prescaler value is 3. 0b10..Baud Rate Prescaler value is 5. 0b11..Baud Rate Prescaler value is 7.

SPI_CTAR_PBR [2/6]

#define SPI_CTAR_PBR

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)

PBR - Baud Rate Prescaler 0b00..Baud Rate Prescaler value is 2. 0b01..Baud Rate Prescaler value is 3. 0b10..Baud Rate Prescaler value is 5. 0b11..Baud Rate Prescaler value is 7.

SPI_CTAR_PBR [3/6]

#define SPI_CTAR_PBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)

PBR - Baud Rate Prescaler 0b00..Baud Rate Prescaler value is 2. 0b01..Baud Rate Prescaler value is 3. 0b10..Baud Rate Prescaler value is 5. 0b11..Baud Rate Prescaler value is 7.

SPI_CTAR_PBR [4/6]

#define SPI_CTAR_PBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)

PBR - Baud Rate Prescaler 0b00..Baud Rate Prescaler value is 2. 0b01..Baud Rate Prescaler value is 3. 0b10..Baud Rate Prescaler value is 5. 0b11..Baud Rate Prescaler value is 7.

SPI_CTAR_PBR [5/6]

#define SPI_CTAR_PBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)

PBR - Baud Rate Prescaler 0b00..Baud Rate Prescaler value is 2. 0b01..Baud Rate Prescaler value is 3. 0b10..Baud Rate Prescaler value is 5. 0b11..Baud Rate Prescaler value is 7.

SPI_CTAR_PBR [6/6]

#define SPI_CTAR_PBR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)

PBR - Baud Rate Prescaler 0b00..Baud Rate Prescaler value is 2. 0b01..Baud Rate Prescaler value is 3. 0b10..Baud Rate Prescaler value is 5. 0b11..Baud Rate Prescaler value is 7.

SPI_CTAR_PCSSCK [1/6]

#define SPI_CTAR_PCSSCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)

PCSSCK - PCS to SCK Delay Prescaler 0b00..PCS to SCK Prescaler value is 1. 0b01..PCS to SCK Prescaler value is 3. 0b10..PCS to SCK Prescaler value is 5. 0b11..PCS to SCK Prescaler value is 7.

SPI_CTAR_PCSSCK [2/6]

#define SPI_CTAR_PCSSCK

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)

PCSSCK - PCS to SCK Delay Prescaler 0b00..PCS to SCK Prescaler value is 1. 0b01..PCS to SCK Prescaler value is 3. 0b10..PCS to SCK Prescaler value is 5. 0b11..PCS to SCK Prescaler value is 7.

SPI_CTAR_PCSSCK [3/6]

#define SPI_CTAR_PCSSCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)

PCSSCK - PCS to SCK Delay Prescaler 0b00..PCS to SCK Prescaler value is 1. 0b01..PCS to SCK Prescaler value is 3. 0b10..PCS to SCK Prescaler value is 5. 0b11..PCS to SCK Prescaler value is 7.

SPI_CTAR_PCSSCK [4/6]

#define SPI_CTAR_PCSSCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)

PCSSCK - PCS to SCK Delay Prescaler 0b00..PCS to SCK Prescaler value is 1. 0b01..PCS to SCK Prescaler value is 3. 0b10..PCS to SCK Prescaler value is 5. 0b11..PCS to SCK Prescaler value is 7.

SPI_CTAR_PCSSCK [5/6]

#define SPI_CTAR_PCSSCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)

PCSSCK - PCS to SCK Delay Prescaler 0b00..PCS to SCK Prescaler value is 1. 0b01..PCS to SCK Prescaler value is 3. 0b10..PCS to SCK Prescaler value is 5. 0b11..PCS to SCK Prescaler value is 7.

SPI_CTAR_PCSSCK [6/6]

#define SPI_CTAR_PCSSCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)

PCSSCK - PCS to SCK Delay Prescaler 0b00..PCS to SCK Prescaler value is 1. 0b01..PCS to SCK Prescaler value is 3. 0b10..PCS to SCK Prescaler value is 5. 0b11..PCS to SCK Prescaler value is 7.

SPI_CTAR_PDT [1/6]

#define SPI_CTAR_PDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)

PDT - Delay after Transfer Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PDT [2/6]

#define SPI_CTAR_PDT

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)

PDT - Delay after Transfer Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PDT [3/6]

#define SPI_CTAR_PDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)

PDT - Delay after Transfer Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PDT [4/6]

#define SPI_CTAR_PDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)

PDT - Delay after Transfer Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PDT [5/6]

#define SPI_CTAR_PDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)

PDT - Delay after Transfer Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_PDT [6/6]

#define SPI_CTAR_PDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)

PDT - Delay after Transfer Prescaler 0b00..Delay after Transfer Prescaler value is 1. 0b01..Delay after Transfer Prescaler value is 3. 0b10..Delay after Transfer Prescaler value is 5. 0b11..Delay after Transfer Prescaler value is 7.

SPI_CTAR_SLAVE_CPHA [1/5]

#define SPI_CTAR_SLAVE_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_SLAVE_CPHA [2/5]

#define SPI_CTAR_SLAVE_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_SLAVE_CPHA [3/5]

#define SPI_CTAR_SLAVE_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_SLAVE_CPHA [4/5]

#define SPI_CTAR_SLAVE_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_SLAVE_CPHA [5/5]

#define SPI_CTAR_SLAVE_CPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 0b1..Data is changed on the leading edge of SCK and captured on the following edge.

SPI_CTAR_SLAVE_CPOL [1/5]

#define SPI_CTAR_SLAVE_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_SLAVE_CPOL [2/5]

#define SPI_CTAR_SLAVE_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_SLAVE_CPOL [3/5]

#define SPI_CTAR_SLAVE_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_SLAVE_CPOL [4/5]

#define SPI_CTAR_SLAVE_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_CTAR_SLAVE_CPOL [5/5]

#define SPI_CTAR_SLAVE_CPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low. 0b1..The inactive state value of SCK is high.

SPI_IRQS

#define SPI_IRQS   { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }

Interrupt vectors for the SPI peripheral type

SPI_MCR_CLR_RXF [1/5]

#define SPI_MCR_CLR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

SPI_MCR_CLR_RXF [2/5]

#define SPI_MCR_CLR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

SPI_MCR_CLR_RXF [3/5]

#define SPI_MCR_CLR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

SPI_MCR_CLR_RXF [4/5]

#define SPI_MCR_CLR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

SPI_MCR_CLR_RXF [5/5]

#define SPI_MCR_CLR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

SPI_MCR_CLR_TXF [1/5]

#define SPI_MCR_CLR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

SPI_MCR_CLR_TXF [2/5]

#define SPI_MCR_CLR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

SPI_MCR_CLR_TXF [3/5]

#define SPI_MCR_CLR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

SPI_MCR_CLR_TXF [4/5]

#define SPI_MCR_CLR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

SPI_MCR_CLR_TXF [5/5]

#define SPI_MCR_CLR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

SPI_MCR_CONT_SCKE [1/5]

#define SPI_MCR_CONT_SCKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

SPI_MCR_CONT_SCKE [2/5]

#define SPI_MCR_CONT_SCKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

SPI_MCR_CONT_SCKE [3/5]

#define SPI_MCR_CONT_SCKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

SPI_MCR_CONT_SCKE [4/5]

#define SPI_MCR_CONT_SCKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

SPI_MCR_CONT_SCKE [5/5]

#define SPI_MCR_CONT_SCKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

SPI_MCR_DCONF [1/6]

#define SPI_MCR_DCONF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

SPI_MCR_DCONF [2/6]

#define SPI_MCR_DCONF

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

SPI_MCR_DCONF [3/6]

#define SPI_MCR_DCONF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

SPI_MCR_DCONF [4/6]

#define SPI_MCR_DCONF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

SPI_MCR_DCONF [5/6]

#define SPI_MCR_DCONF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

SPI_MCR_DCONF [6/6]

#define SPI_MCR_DCONF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

SPI_MCR_DIS_RXF [1/5]

#define SPI_MCR_DIS_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

SPI_MCR_DIS_RXF [2/5]

#define SPI_MCR_DIS_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

SPI_MCR_DIS_RXF [3/5]

#define SPI_MCR_DIS_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

SPI_MCR_DIS_RXF [4/5]

#define SPI_MCR_DIS_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

SPI_MCR_DIS_RXF [5/5]

#define SPI_MCR_DIS_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

SPI_MCR_DIS_TXF [1/5]

#define SPI_MCR_DIS_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

SPI_MCR_DIS_TXF [2/5]

#define SPI_MCR_DIS_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

SPI_MCR_DIS_TXF [3/5]

#define SPI_MCR_DIS_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

SPI_MCR_DIS_TXF [4/5]

#define SPI_MCR_DIS_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

SPI_MCR_DIS_TXF [5/5]

#define SPI_MCR_DIS_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

SPI_MCR_DOZE [1/5]

#define SPI_MCR_DOZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

SPI_MCR_DOZE [2/5]

#define SPI_MCR_DOZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

SPI_MCR_DOZE [3/5]

#define SPI_MCR_DOZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

SPI_MCR_DOZE [4/5]

#define SPI_MCR_DOZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

SPI_MCR_DOZE [5/5]

#define SPI_MCR_DOZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

SPI_MCR_FRZ [1/5]

#define SPI_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

SPI_MCR_FRZ [2/5]

#define SPI_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

SPI_MCR_FRZ [3/5]

#define SPI_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

SPI_MCR_FRZ [4/5]

#define SPI_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

SPI_MCR_FRZ [5/5]

#define SPI_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

SPI_MCR_HALT [1/5]

#define SPI_MCR_HALT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

SPI_MCR_HALT [2/5]

#define SPI_MCR_HALT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

SPI_MCR_HALT [3/5]

#define SPI_MCR_HALT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

SPI_MCR_HALT [4/5]

#define SPI_MCR_HALT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

SPI_MCR_HALT [5/5]

#define SPI_MCR_HALT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

SPI_MCR_MDIS [1/5]

#define SPI_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

SPI_MCR_MDIS [2/5]

#define SPI_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

SPI_MCR_MDIS [3/5]

#define SPI_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

SPI_MCR_MDIS [4/5]

#define SPI_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

SPI_MCR_MDIS [5/5]

#define SPI_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

SPI_MCR_MSTR [1/5]

#define SPI_MCR_MSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

SPI_MCR_MSTR [2/5]

#define SPI_MCR_MSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

SPI_MCR_MSTR [3/5]

#define SPI_MCR_MSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

SPI_MCR_MSTR [4/5]

#define SPI_MCR_MSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

SPI_MCR_MSTR [5/5]

#define SPI_MCR_MSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

SPI_MCR_MTFE [1/5]

#define SPI_MCR_MTFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Timing Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

SPI_MCR_MTFE [2/5]

#define SPI_MCR_MTFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Timing Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

SPI_MCR_MTFE [3/5]

#define SPI_MCR_MTFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

SPI_MCR_MTFE [4/5]

#define SPI_MCR_MTFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

SPI_MCR_MTFE [5/5]

#define SPI_MCR_MTFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

SPI_MCR_PCSIS [1/6]

#define SPI_MCR_PCSIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

SPI_MCR_PCSIS [2/6]

#define SPI_MCR_PCSIS

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

SPI_MCR_PCSIS [3/6]

#define SPI_MCR_PCSIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

SPI_MCR_PCSIS [4/6]

#define SPI_MCR_PCSIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

SPI_MCR_PCSIS [5/6]

#define SPI_MCR_PCSIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

SPI_MCR_PCSIS [6/6]

#define SPI_MCR_PCSIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

SPI_MCR_PCSSE [1/5]

#define SPI_MCR_PCSSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

SPI_MCR_PCSSE [2/5]

#define SPI_MCR_PCSSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

SPI_MCR_PCSSE [3/5]

#define SPI_MCR_PCSSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

SPI_MCR_PCSSE [4/5]

#define SPI_MCR_PCSSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

SPI_MCR_PCSSE [5/5]

#define SPI_MCR_PCSSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

SPI_MCR_ROOE [1/5]

#define SPI_MCR_ROOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

SPI_MCR_ROOE [2/5]

#define SPI_MCR_ROOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

SPI_MCR_ROOE [3/5]

#define SPI_MCR_ROOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

SPI_MCR_ROOE [4/5]

#define SPI_MCR_ROOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

SPI_MCR_ROOE [5/5]

#define SPI_MCR_ROOE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

SPI_MCR_SMPL_PT [1/6]

#define SPI_MCR_SMPL_PT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

SPI_MCR_SMPL_PT [2/6]

#define SPI_MCR_SMPL_PT

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

SPI_MCR_SMPL_PT [3/6]

#define SPI_MCR_SMPL_PT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

SPI_MCR_SMPL_PT [4/6]

#define SPI_MCR_SMPL_PT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

SPI_MCR_SMPL_PT [5/6]

#define SPI_MCR_SMPL_PT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

SPI_MCR_SMPL_PT [6/6]

#define SPI_MCR_SMPL_PT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

SPI_PUSHR_CONT [1/5]

#define SPI_PUSHR_CONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)

CONT - Continuous Peripheral Chip Select Enable 0b0..Return PCSn signals to their inactive state between transfers. 0b1..Keep PCSn signals asserted between transfers.

SPI_PUSHR_CONT [2/5]

#define SPI_PUSHR_CONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)

CONT - Continuous Peripheral Chip Select Enable 0b0..Return PCSn signals to their inactive state between transfers. 0b1..Keep PCSn signals asserted between transfers.

SPI_PUSHR_CONT [3/5]

#define SPI_PUSHR_CONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)

CONT - Continuous Peripheral Chip Select Enable 0b0..Return PCSn signals to their inactive state between transfers. 0b1..Keep PCSn signals asserted between transfers.

SPI_PUSHR_CONT [4/5]

#define SPI_PUSHR_CONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)

CONT - Continuous Peripheral Chip Select Enable 0b0..Return PCSn signals to their inactive state between transfers. 0b1..Keep PCSn signals asserted between transfers.

SPI_PUSHR_CONT [5/5]

#define SPI_PUSHR_CONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)

CONT - Continuous Peripheral Chip Select Enable 0b0..Return PCSn signals to their inactive state between transfers. 0b1..Keep PCSn signals asserted between transfers.

SPI_PUSHR_CTAS [1/6]

#define SPI_PUSHR_CTAS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)

CTAS - Clock and Transfer Attributes Select 0b000..CTAR0 0b001..CTAR1 0b010..Reserved 0b011..Reserved 0b100..Reserved 0b101..Reserved 0b110..Reserved 0b111..Reserved

SPI_PUSHR_CTAS [2/6]

#define SPI_PUSHR_CTAS

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)

CTAS - Clock and Transfer Attributes Select 0b000..CTAR0 0b001..CTAR1 0b010..Reserved 0b011..Reserved 0b100..Reserved 0b101..Reserved 0b110..Reserved 0b111..Reserved

SPI_PUSHR_CTAS [3/6]

#define SPI_PUSHR_CTAS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)

CTAS - Clock and Transfer Attributes Select 0b000..CTAR0 0b001..CTAR1 0b010..Reserved 0b011..Reserved 0b100..Reserved 0b101..Reserved 0b110..Reserved 0b111..Reserved

SPI_PUSHR_CTAS [4/6]

#define SPI_PUSHR_CTAS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)

CTAS - Clock and Transfer Attributes Select 0b000..CTAR0 0b001..CTAR1 0b010..Reserved 0b011..Reserved 0b100..Reserved 0b101..Reserved 0b110..Reserved 0b111..Reserved

SPI_PUSHR_CTAS [5/6]

#define SPI_PUSHR_CTAS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)

CTAS - Clock and Transfer Attributes Select 0b000..CTAR0 0b001..CTAR1 0b010..Reserved 0b011..Reserved 0b100..Reserved 0b101..Reserved 0b110..Reserved 0b111..Reserved

SPI_PUSHR_CTAS [6/6]

#define SPI_PUSHR_CTAS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)

CTAS - Clock and Transfer Attributes Select 0b000..CTAR0 0b001..CTAR1 0b010..Reserved 0b011..Reserved 0b100..Reserved 0b101..Reserved 0b110..Reserved 0b111..Reserved

SPI_PUSHR_CTCNT [1/5]

#define SPI_PUSHR_CTCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)

CTCNT - Clear Transfer Counter 0b0..Do not clear the TCR[TCNT] field. 0b1..Clear the TCR[TCNT] field.

SPI_PUSHR_CTCNT [2/5]

#define SPI_PUSHR_CTCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)

CTCNT - Clear Transfer Counter 0b0..Do not clear the TCR[TCNT] field. 0b1..Clear the TCR[TCNT] field.

SPI_PUSHR_CTCNT [3/5]

#define SPI_PUSHR_CTCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)

CTCNT - Clear Transfer Counter 0b0..Do not clear the TCR[TCNT] field. 0b1..Clear the TCR[TCNT] field.

SPI_PUSHR_CTCNT [4/5]

#define SPI_PUSHR_CTCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)

CTCNT - Clear Transfer Counter 0b0..Do not clear the TCR[TCNT] field. 0b1..Clear the TCR[TCNT] field.

SPI_PUSHR_CTCNT [5/5]

#define SPI_PUSHR_CTCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)

CTCNT - Clear Transfer Counter 0b0..Do not clear the TCR[TCNT] field. 0b1..Clear the TCR[TCNT] field.

SPI_PUSHR_EOQ [1/5]

#define SPI_PUSHR_EOQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)

EOQ - End Of Queue 0b0..The SPI data is not the last data to transfer. 0b1..The SPI data is the last data to transfer.

SPI_PUSHR_EOQ [2/5]

#define SPI_PUSHR_EOQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)

EOQ - End Of Queue 0b0..The SPI data is not the last data to transfer. 0b1..The SPI data is the last data to transfer.

SPI_PUSHR_EOQ [3/5]

#define SPI_PUSHR_EOQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)

EOQ - End Of Queue 0b0..The SPI data is not the last data to transfer. 0b1..The SPI data is the last data to transfer.

SPI_PUSHR_EOQ [4/5]

#define SPI_PUSHR_EOQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)

EOQ - End Of Queue 0b0..The SPI data is not the last data to transfer. 0b1..The SPI data is the last data to transfer.

SPI_PUSHR_EOQ [5/5]

#define SPI_PUSHR_EOQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)

EOQ - End Of Queue 0b0..The SPI data is not the last data to transfer. 0b1..The SPI data is the last data to transfer.

SPI_PUSHR_PCS [1/6]

#define SPI_PUSHR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)

PCS 0b000000..Negate the PCS[x] signal. 0b000001..Assert the PCS[x] signal.

SPI_PUSHR_PCS [2/6]

#define SPI_PUSHR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)

PCS 0b000000..Negate the PCS[x] signal. 0b000001..Assert the PCS[x] signal.

SPI_PUSHR_PCS [3/6]

#define SPI_PUSHR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)

PCS 0b000000..Negate the PCS[x] signal. 0b000001..Assert the PCS[x] signal.

SPI_PUSHR_PCS [4/6]

#define SPI_PUSHR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)

PCS 0b000000..Negate the PCS[x] signal. 0b000001..Assert the PCS[x] signal.

SPI_PUSHR_PCS [5/6]

#define SPI_PUSHR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)

PCS 0b000000..Negate the PCS[x] signal. 0b000001..Assert the PCS[x] signal.

SPI_PUSHR_PCS [6/6]

#define SPI_PUSHR_PCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)

PCS 0b000000..Negate the PCS[x] signal. 0b000001..Assert the PCS[x] signal.

SPI_RSER_EOQF_RE [1/5]

#define SPI_RSER_EOQF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)

EOQF_RE - Finished Request Enable 0b0..EOQF interrupt requests are disabled. 0b1..EOQF interrupt requests are enabled.

SPI_RSER_EOQF_RE [2/5]

#define SPI_RSER_EOQF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)

EOQF_RE - Finished Request Enable 0b0..EOQF interrupt requests are disabled. 0b1..EOQF interrupt requests are enabled.

SPI_RSER_EOQF_RE [3/5]

#define SPI_RSER_EOQF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)

EOQF_RE - Finished Request Enable 0b0..EOQF interrupt requests are disabled. 0b1..EOQF interrupt requests are enabled.

SPI_RSER_EOQF_RE [4/5]

#define SPI_RSER_EOQF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)

EOQF_RE - Finished Request Enable 0b0..EOQF interrupt requests are disabled. 0b1..EOQF interrupt requests are enabled.

SPI_RSER_EOQF_RE [5/5]

#define SPI_RSER_EOQF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)

EOQF_RE - Finished Request Enable 0b0..EOQF interrupt requests are disabled. 0b1..EOQF interrupt requests are enabled.

SPI_RSER_RFDF_DIRS [1/5]

#define SPI_RSER_RFDF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)

RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select 0b0..Interrupt request. 0b1..DMA request.

SPI_RSER_RFDF_DIRS [2/5]

#define SPI_RSER_RFDF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)

RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select 0b0..Interrupt request. 0b1..DMA request.

SPI_RSER_RFDF_DIRS [3/5]

#define SPI_RSER_RFDF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)

RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select 0b0..Interrupt request. 0b1..DMA request.

SPI_RSER_RFDF_DIRS [4/5]

#define SPI_RSER_RFDF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)

RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select 0b0..Interrupt request. 0b1..DMA request.

SPI_RSER_RFDF_DIRS [5/5]

#define SPI_RSER_RFDF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)

RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select 0b0..Interrupt request. 0b1..DMA request.

SPI_RSER_RFDF_RE [1/5]

#define SPI_RSER_RFDF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)

RFDF_RE - Receive FIFO Drain Request Enable 0b0..RFDF interrupt or DMA requests are disabled. 0b1..RFDF interrupt or DMA requests are enabled.

SPI_RSER_RFDF_RE [2/5]

#define SPI_RSER_RFDF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)

RFDF_RE - Receive FIFO Drain Request Enable 0b0..RFDF interrupt or DMA requests are disabled. 0b1..RFDF interrupt or DMA requests are enabled.

SPI_RSER_RFDF_RE [3/5]

#define SPI_RSER_RFDF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)

RFDF_RE - Receive FIFO Drain Request Enable 0b0..RFDF interrupt or DMA requests are disabled. 0b1..RFDF interrupt or DMA requests are enabled.

SPI_RSER_RFDF_RE [4/5]

#define SPI_RSER_RFDF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)

RFDF_RE - Receive FIFO Drain Request Enable 0b0..RFDF interrupt or DMA requests are disabled. 0b1..RFDF interrupt or DMA requests are enabled.

SPI_RSER_RFDF_RE [5/5]

#define SPI_RSER_RFDF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)

RFDF_RE - Receive FIFO Drain Request Enable 0b0..RFDF interrupt or DMA requests are disabled. 0b1..RFDF interrupt or DMA requests are enabled.

SPI_RSER_RFOF_RE [1/5]

#define SPI_RSER_RFOF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)

RFOF_RE - Receive FIFO Overflow Request Enable 0b0..RFOF interrupt requests are disabled. 0b1..RFOF interrupt requests are enabled.

SPI_RSER_RFOF_RE [2/5]

#define SPI_RSER_RFOF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)

RFOF_RE - Receive FIFO Overflow Request Enable 0b0..RFOF interrupt requests are disabled. 0b1..RFOF interrupt requests are enabled.

SPI_RSER_RFOF_RE [3/5]

#define SPI_RSER_RFOF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)

RFOF_RE - Receive FIFO Overflow Request Enable 0b0..RFOF interrupt requests are disabled. 0b1..RFOF interrupt requests are enabled.

SPI_RSER_RFOF_RE [4/5]

#define SPI_RSER_RFOF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)

RFOF_RE - Receive FIFO Overflow Request Enable 0b0..RFOF interrupt requests are disabled. 0b1..RFOF interrupt requests are enabled.

SPI_RSER_RFOF_RE [5/5]

#define SPI_RSER_RFOF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)

RFOF_RE - Receive FIFO Overflow Request Enable 0b0..RFOF interrupt requests are disabled. 0b1..RFOF interrupt requests are enabled.

SPI_RSER_TCF_RE [1/5]

#define SPI_RSER_TCF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)

TCF_RE - Transmission Complete Request Enable 0b0..TCF interrupt requests are disabled. 0b1..TCF interrupt requests are enabled.

SPI_RSER_TCF_RE [2/5]

#define SPI_RSER_TCF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)

TCF_RE - Transmission Complete Request Enable 0b0..TCF interrupt requests are disabled. 0b1..TCF interrupt requests are enabled.

SPI_RSER_TCF_RE [3/5]

#define SPI_RSER_TCF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)

TCF_RE - Transmission Complete Request Enable 0b0..TCF interrupt requests are disabled. 0b1..TCF interrupt requests are enabled.

SPI_RSER_TCF_RE [4/5]

#define SPI_RSER_TCF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)

TCF_RE - Transmission Complete Request Enable 0b0..TCF interrupt requests are disabled. 0b1..TCF interrupt requests are enabled.

SPI_RSER_TCF_RE [5/5]

#define SPI_RSER_TCF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)

TCF_RE - Transmission Complete Request Enable 0b0..TCF interrupt requests are disabled. 0b1..TCF interrupt requests are enabled.

SPI_RSER_TFFF_DIRS [1/5]

#define SPI_RSER_TFFF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)

TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select 0b0..TFFF flag generates interrupt requests. 0b1..TFFF flag generates DMA requests.

SPI_RSER_TFFF_DIRS [2/5]

#define SPI_RSER_TFFF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)

TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select 0b0..TFFF flag generates interrupt requests. 0b1..TFFF flag generates DMA requests.

SPI_RSER_TFFF_DIRS [3/5]

#define SPI_RSER_TFFF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)

TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select 0b0..TFFF flag generates interrupt requests. 0b1..TFFF flag generates DMA requests.

SPI_RSER_TFFF_DIRS [4/5]

#define SPI_RSER_TFFF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)

TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select 0b0..TFFF flag generates interrupt requests. 0b1..TFFF flag generates DMA requests.

SPI_RSER_TFFF_DIRS [5/5]

#define SPI_RSER_TFFF_DIRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)

TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select 0b0..TFFF flag generates interrupt requests. 0b1..TFFF flag generates DMA requests.

SPI_RSER_TFFF_RE [1/5]

#define SPI_RSER_TFFF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)

TFFF_RE - Transmit FIFO Fill Request Enable 0b0..TFFF interrupts or DMA requests are disabled. 0b1..TFFF interrupts or DMA requests are enabled.

SPI_RSER_TFFF_RE [2/5]

#define SPI_RSER_TFFF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)

TFFF_RE - Transmit FIFO Fill Request Enable 0b0..TFFF interrupts or DMA requests are disabled. 0b1..TFFF interrupts or DMA requests are enabled.

SPI_RSER_TFFF_RE [3/5]

#define SPI_RSER_TFFF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)

TFFF_RE - Transmit FIFO Fill Request Enable 0b0..TFFF interrupts or DMA requests are disabled. 0b1..TFFF interrupts or DMA requests are enabled.

SPI_RSER_TFFF_RE [4/5]

#define SPI_RSER_TFFF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)

TFFF_RE - Transmit FIFO Fill Request Enable 0b0..TFFF interrupts or DMA requests are disabled. 0b1..TFFF interrupts or DMA requests are enabled.

SPI_RSER_TFFF_RE [5/5]

#define SPI_RSER_TFFF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)

TFFF_RE - Transmit FIFO Fill Request Enable 0b0..TFFF interrupts or DMA requests are disabled. 0b1..TFFF interrupts or DMA requests are enabled.

SPI_RSER_TFUF_RE [1/5]

#define SPI_RSER_TFUF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)

TFUF_RE - Transmit FIFO Underflow Request Enable 0b0..TFUF interrupt requests are disabled. 0b1..TFUF interrupt requests are enabled.

SPI_RSER_TFUF_RE [2/5]

#define SPI_RSER_TFUF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)

TFUF_RE - Transmit FIFO Underflow Request Enable 0b0..TFUF interrupt requests are disabled. 0b1..TFUF interrupt requests are enabled.

SPI_RSER_TFUF_RE [3/5]

#define SPI_RSER_TFUF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)

TFUF_RE - Transmit FIFO Underflow Request Enable 0b0..TFUF interrupt requests are disabled. 0b1..TFUF interrupt requests are enabled.

SPI_RSER_TFUF_RE [4/5]

#define SPI_RSER_TFUF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)

TFUF_RE - Transmit FIFO Underflow Request Enable 0b0..TFUF interrupt requests are disabled. 0b1..TFUF interrupt requests are enabled.

SPI_RSER_TFUF_RE [5/5]

#define SPI_RSER_TFUF_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)

TFUF_RE - Transmit FIFO Underflow Request Enable 0b0..TFUF interrupt requests are disabled. 0b1..TFUF interrupt requests are enabled.

SPI_SR_EOQF [1/5]

#define SPI_SR_EOQF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)

EOQF - End of Queue Flag 0b0..EOQ is not set in the executing command. 0b1..EOQ is set in the executing SPI command.

SPI_SR_EOQF [2/5]

#define SPI_SR_EOQF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)

EOQF - End of Queue Flag 0b0..EOQ is not set in the executing command. 0b1..EOQ is set in the executing SPI command.

SPI_SR_EOQF [3/5]

#define SPI_SR_EOQF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)

EOQF - End of Queue Flag 0b0..EOQ is not set in the executing command. 0b1..EOQ is set in the executing SPI command.

SPI_SR_EOQF [4/5]

#define SPI_SR_EOQF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)

EOQF - End of Queue Flag 0b0..EOQ is not set in the executing command. 0b1..EOQ is set in the executing SPI command.

SPI_SR_EOQF [5/5]

#define SPI_SR_EOQF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)

EOQF - End of Queue Flag 0b0..EOQ is not set in the executing command. 0b1..EOQ is set in the executing SPI command.

SPI_SR_RFDF [1/5]

#define SPI_SR_RFDF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)

RFDF - Receive FIFO Drain Flag 0b0..RX FIFO is empty. 0b1..RX FIFO is not empty.

SPI_SR_RFDF [2/5]

#define SPI_SR_RFDF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)

RFDF - Receive FIFO Drain Flag 0b0..RX FIFO is empty. 0b1..RX FIFO is not empty.

SPI_SR_RFDF [3/5]

#define SPI_SR_RFDF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)

RFDF - Receive FIFO Drain Flag 0b0..RX FIFO is empty. 0b1..RX FIFO is not empty.

SPI_SR_RFDF [4/5]

#define SPI_SR_RFDF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)

RFDF - Receive FIFO Drain Flag 0b0..RX FIFO is empty. 0b1..RX FIFO is not empty.

SPI_SR_RFDF [5/5]

#define SPI_SR_RFDF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)

RFDF - Receive FIFO Drain Flag 0b0..RX FIFO is empty. 0b1..RX FIFO is not empty.

SPI_SR_RFOF [1/5]

#define SPI_SR_RFOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)

RFOF - Receive FIFO Overflow Flag 0b0..No Rx FIFO overflow. 0b1..Rx FIFO overflow has occurred.

SPI_SR_RFOF [2/5]

#define SPI_SR_RFOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)

RFOF - Receive FIFO Overflow Flag 0b0..No Rx FIFO overflow. 0b1..Rx FIFO overflow has occurred.

SPI_SR_RFOF [3/5]

#define SPI_SR_RFOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)

RFOF - Receive FIFO Overflow Flag 0b0..No Rx FIFO overflow. 0b1..Rx FIFO overflow has occurred.

SPI_SR_RFOF [4/5]

#define SPI_SR_RFOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)

RFOF - Receive FIFO Overflow Flag 0b0..No Rx FIFO overflow. 0b1..Rx FIFO overflow has occurred.

SPI_SR_RFOF [5/5]

#define SPI_SR_RFOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)

RFOF - Receive FIFO Overflow Flag 0b0..No Rx FIFO overflow. 0b1..Rx FIFO overflow has occurred.

SPI_SR_TCF [1/5]

#define SPI_SR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer not complete. 0b1..Transfer complete.

SPI_SR_TCF [2/5]

#define SPI_SR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer not complete. 0b1..Transfer complete.

SPI_SR_TCF [3/5]

#define SPI_SR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer not complete. 0b1..Transfer complete.

SPI_SR_TCF [4/5]

#define SPI_SR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer not complete. 0b1..Transfer complete.

SPI_SR_TCF [5/5]

#define SPI_SR_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)

TCF - Transfer Complete Flag 0b0..Transfer not complete. 0b1..Transfer complete.

SPI_SR_TFFF [1/5]

#define SPI_SR_TFFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)

TFFF - Transmit FIFO Fill Flag 0b0..TX FIFO is full. 0b1..TX FIFO is not full.

SPI_SR_TFFF [2/5]

#define SPI_SR_TFFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)

TFFF - Transmit FIFO Fill Flag 0b0..TX FIFO is full. 0b1..TX FIFO is not full.

SPI_SR_TFFF [3/5]

#define SPI_SR_TFFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)

TFFF - Transmit FIFO Fill Flag 0b0..TX FIFO is full. 0b1..TX FIFO is not full.

SPI_SR_TFFF [4/5]

#define SPI_SR_TFFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)

TFFF - Transmit FIFO Fill Flag 0b0..TX FIFO is full. 0b1..TX FIFO is not full.

SPI_SR_TFFF [5/5]

#define SPI_SR_TFFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)

TFFF - Transmit FIFO Fill Flag 0b0..TX FIFO is full. 0b1..TX FIFO is not full.

SPI_SR_TFUF [1/5]

#define SPI_SR_TFUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)

TFUF - Transmit FIFO Underflow Flag 0b0..No TX FIFO underflow. 0b1..TX FIFO underflow has occurred.

SPI_SR_TFUF [2/5]

#define SPI_SR_TFUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)

TFUF - Transmit FIFO Underflow Flag 0b0..No TX FIFO underflow. 0b1..TX FIFO underflow has occurred.

SPI_SR_TFUF [3/5]

#define SPI_SR_TFUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)

TFUF - Transmit FIFO Underflow Flag 0b0..No TX FIFO underflow. 0b1..TX FIFO underflow has occurred.

SPI_SR_TFUF [4/5]

#define SPI_SR_TFUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)

TFUF - Transmit FIFO Underflow Flag 0b0..No TX FIFO underflow. 0b1..TX FIFO underflow has occurred.

SPI_SR_TFUF [5/5]

#define SPI_SR_TFUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)

TFUF - Transmit FIFO Underflow Flag 0b0..No TX FIFO underflow. 0b1..TX FIFO underflow has occurred.

SPI_SR_TXRXS [1/5]

#define SPI_SR_TXRXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)

TXRXS - TX and RX Status 0b0..Transmit and receive operations are disabled (The module is in Stopped state). 0b1..Transmit and receive operations are enabled (The module is in Running state).

SPI_SR_TXRXS [2/5]

#define SPI_SR_TXRXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)

TXRXS - TX and RX Status 0b0..Transmit and receive operations are disabled (The module is in Stopped state). 0b1..Transmit and receive operations are enabled (The module is in Running state).

SPI_SR_TXRXS [3/5]

#define SPI_SR_TXRXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)

TXRXS - TX and RX Status 0b0..Transmit and receive operations are disabled (The module is in Stopped state). 0b1..Transmit and receive operations are enabled (The module is in Running state).

SPI_SR_TXRXS [4/5]

#define SPI_SR_TXRXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)

TXRXS - TX and RX Status 0b0..Transmit and receive operations are disabled (The module is in Stopped state). 0b1..Transmit and receive operations are enabled (The module is in Running state).

SPI_SR_TXRXS [5/5]

#define SPI_SR_TXRXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)

TXRXS - TX and RX Status 0b0..Transmit and receive operations are disabled (The module is in Stopped state). 0b1..Transmit and receive operations are enabled (The module is in Running state).