SYSMPU Register Masks

Macros
#define	SYSMPU_BASE   (0x4000D000u)
#define	SYSMPU   ((SYSMPU_Type *)SYSMPU_BASE)
#define	SYSMPU_BASE_ADDRS   { SYSMPU_BASE }
#define	SYSMPU_BASE_PTRS   { SYSMPU }
#define	SYSMPU_EAR_COUNT   (5U)
#define	SYSMPU_EDR_COUNT   (5U)
#define	SYSMPU_WORD_COUNT   (12U)
#define	SYSMPU_WORD_COUNT2   (4U)
#define	SYSMPU_RGDAAC_COUNT   (12U)
#define	SYSMPU_EAR_COUNT   (5U)
#define	SYSMPU_EDR_COUNT   (5U)
#define	SYSMPU_WORD_COUNT   (12U)
#define	SYSMPU_WORD_COUNT2   (4U)
#define	SYSMPU_RGDAAC_COUNT   (12U)
#define	SYSMPU_EAR_COUNT   (5U)
#define	SYSMPU_EDR_COUNT   (5U)
#define	SYSMPU_WORD_COUNT   (12U)
#define	SYSMPU_WORD_COUNT2   (4U)
#define	SYSMPU_RGDAAC_COUNT   (12U)
#define	SYSMPU_EAR_COUNT   (5U)
#define	SYSMPU_EDR_COUNT   (5U)
#define	SYSMPU_WORD_COUNT   (12U)
#define	SYSMPU_WORD_COUNT2   (4U)
#define	SYSMPU_RGDAAC_COUNT   (12U)

CESR - Control/Error Status Register
#define	SYSMPU_CESR_VLD_MASK   (0x1U)
#define	SYSMPU_CESR_VLD_SHIFT   (0U)
#define	SYSMPU_CESR_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
#define	SYSMPU_CESR_NRGD_MASK   (0xF00U)
#define	SYSMPU_CESR_NRGD_SHIFT   (8U)
#define	SYSMPU_CESR_NRGD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
#define	SYSMPU_CESR_NSP_MASK   (0xF000U)
#define	SYSMPU_CESR_NSP_SHIFT   (12U)
#define	SYSMPU_CESR_NSP(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
#define	SYSMPU_CESR_HRL_MASK   (0xF0000U)
#define	SYSMPU_CESR_HRL_SHIFT   (16U)
#define	SYSMPU_CESR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
#define	SYSMPU_CESR_SPERR_MASK   (0xF8000000U)
#define	SYSMPU_CESR_SPERR_SHIFT   (27U)
#define	SYSMPU_CESR_SPERR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
#define	SYSMPU_CESR_VLD_MASK   (0x1U)
#define	SYSMPU_CESR_VLD_SHIFT   (0U)
#define	SYSMPU_CESR_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
#define	SYSMPU_CESR_NRGD_MASK   (0xF00U)
#define	SYSMPU_CESR_NRGD_SHIFT   (8U)
#define	SYSMPU_CESR_NRGD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
#define	SYSMPU_CESR_NSP_MASK   (0xF000U)
#define	SYSMPU_CESR_NSP_SHIFT   (12U)
#define	SYSMPU_CESR_NSP(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
#define	SYSMPU_CESR_HRL_MASK   (0xF0000U)
#define	SYSMPU_CESR_HRL_SHIFT   (16U)
#define	SYSMPU_CESR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
#define	SYSMPU_CESR_SPERR_MASK   (0xF8000000U)
#define	SYSMPU_CESR_SPERR_SHIFT   (27U)
#define	SYSMPU_CESR_SPERR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
#define	SYSMPU_CESR_VLD_MASK   (0x1U)
#define	SYSMPU_CESR_VLD_SHIFT   (0U)
#define	SYSMPU_CESR_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
#define	SYSMPU_CESR_NRGD_MASK   (0xF00U)
#define	SYSMPU_CESR_NRGD_SHIFT   (8U)
#define	SYSMPU_CESR_NRGD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
#define	SYSMPU_CESR_NSP_MASK   (0xF000U)
#define	SYSMPU_CESR_NSP_SHIFT   (12U)
#define	SYSMPU_CESR_NSP(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
#define	SYSMPU_CESR_HRL_MASK   (0xF0000U)
#define	SYSMPU_CESR_HRL_SHIFT   (16U)
#define	SYSMPU_CESR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
#define	SYSMPU_CESR_SPERR_MASK   (0xF8000000U)
#define	SYSMPU_CESR_SPERR_SHIFT   (27U)
#define	SYSMPU_CESR_SPERR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
#define	SYSMPU_CESR_VLD_MASK   (0x1U)
#define	SYSMPU_CESR_VLD_SHIFT   (0U)
#define	SYSMPU_CESR_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
#define	SYSMPU_CESR_NRGD_MASK   (0xF00U)
#define	SYSMPU_CESR_NRGD_SHIFT   (8U)
#define	SYSMPU_CESR_NRGD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
#define	SYSMPU_CESR_NSP_MASK   (0xF000U)
#define	SYSMPU_CESR_NSP_SHIFT   (12U)
#define	SYSMPU_CESR_NSP(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
#define	SYSMPU_CESR_HRL_MASK   (0xF0000U)
#define	SYSMPU_CESR_HRL_SHIFT   (16U)
#define	SYSMPU_CESR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
#define	SYSMPU_CESR_SPERR_MASK   (0xF8000000U)
#define	SYSMPU_CESR_SPERR_SHIFT   (27U)
#define	SYSMPU_CESR_SPERR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
#define	SYSMPU_CESR_VLD_MASK   (0x1U)
#define	SYSMPU_CESR_VLD_SHIFT   (0U)
#define	SYSMPU_CESR_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
#define	SYSMPU_CESR_NRGD_MASK   (0xF00U)
#define	SYSMPU_CESR_NRGD_SHIFT   (8U)
#define	SYSMPU_CESR_NRGD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
#define	SYSMPU_CESR_NSP_MASK   (0xF000U)
#define	SYSMPU_CESR_NSP_SHIFT   (12U)
#define	SYSMPU_CESR_NSP(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
#define	SYSMPU_CESR_HRL_MASK   (0xF0000U)
#define	SYSMPU_CESR_HRL_SHIFT   (16U)
#define	SYSMPU_CESR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
#define	SYSMPU_CESR_SPERR_MASK   (0xF8000000U)
#define	SYSMPU_CESR_SPERR_SHIFT   (27U)
#define	SYSMPU_CESR_SPERR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)

EAR - Error Address Register, slave port n
#define	SYSMPU_EAR_EADDR_MASK   (0xFFFFFFFFU)
#define	SYSMPU_EAR_EADDR_SHIFT   (0U)
#define	SYSMPU_EAR_EADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
#define	SYSMPU_EAR_EADDR_MASK   (0xFFFFFFFFU)
#define	SYSMPU_EAR_EADDR_SHIFT   (0U)
#define	SYSMPU_EAR_EADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
#define	SYSMPU_EAR_EADDR_MASK   (0xFFFFFFFFU)
#define	SYSMPU_EAR_EADDR_SHIFT   (0U)
#define	SYSMPU_EAR_EADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
#define	SYSMPU_EAR_EADDR_MASK   (0xFFFFFFFFU)
#define	SYSMPU_EAR_EADDR_SHIFT   (0U)
#define	SYSMPU_EAR_EADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
#define	SYSMPU_EAR_EADDR_MASK   (0xFFFFFFFFU)
#define	SYSMPU_EAR_EADDR_SHIFT   (0U)
#define	SYSMPU_EAR_EADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)

EAR - Error Address Register, slave port n
#define	SYSMPU_EAR_COUNT   (5U)

EDR - Error Detail Register, slave port n
#define	SYSMPU_EDR_ERW_MASK   (0x1U)
#define	SYSMPU_EDR_ERW_SHIFT   (0U)
#define	SYSMPU_EDR_ERW(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
#define	SYSMPU_EDR_EATTR_MASK   (0xEU)
#define	SYSMPU_EDR_EATTR_SHIFT   (1U)
#define	SYSMPU_EDR_EATTR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
#define	SYSMPU_EDR_EMN_MASK   (0xF0U)
#define	SYSMPU_EDR_EMN_SHIFT   (4U)
#define	SYSMPU_EDR_EMN(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
#define	SYSMPU_EDR_EACD_MASK   (0xFFFF0000U)
#define	SYSMPU_EDR_EACD_SHIFT   (16U)
#define	SYSMPU_EDR_EACD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
#define	SYSMPU_EDR_ERW_MASK   (0x1U)
#define	SYSMPU_EDR_ERW_SHIFT   (0U)
#define	SYSMPU_EDR_ERW(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
#define	SYSMPU_EDR_EATTR_MASK   (0xEU)
#define	SYSMPU_EDR_EATTR_SHIFT   (1U)
#define	SYSMPU_EDR_EATTR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
#define	SYSMPU_EDR_EMN_MASK   (0xF0U)
#define	SYSMPU_EDR_EMN_SHIFT   (4U)
#define	SYSMPU_EDR_EMN(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
#define	SYSMPU_EDR_EPID_MASK   (0xFF00U)
#define	SYSMPU_EDR_EPID_SHIFT   (8U)
#define	SYSMPU_EDR_EPID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
#define	SYSMPU_EDR_EACD_MASK   (0xFFFF0000U)
#define	SYSMPU_EDR_EACD_SHIFT   (16U)
#define	SYSMPU_EDR_EACD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
#define	SYSMPU_EDR_ERW_MASK   (0x1U)
#define	SYSMPU_EDR_ERW_SHIFT   (0U)
#define	SYSMPU_EDR_ERW(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
#define	SYSMPU_EDR_EATTR_MASK   (0xEU)
#define	SYSMPU_EDR_EATTR_SHIFT   (1U)
#define	SYSMPU_EDR_EATTR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
#define	SYSMPU_EDR_EMN_MASK   (0xF0U)
#define	SYSMPU_EDR_EMN_SHIFT   (4U)
#define	SYSMPU_EDR_EMN(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
#define	SYSMPU_EDR_EPID_MASK   (0xFF00U)
#define	SYSMPU_EDR_EPID_SHIFT   (8U)
#define	SYSMPU_EDR_EPID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
#define	SYSMPU_EDR_EACD_MASK   (0xFFFF0000U)
#define	SYSMPU_EDR_EACD_SHIFT   (16U)
#define	SYSMPU_EDR_EACD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
#define	SYSMPU_EDR_ERW_MASK   (0x1U)
#define	SYSMPU_EDR_ERW_SHIFT   (0U)
#define	SYSMPU_EDR_ERW(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
#define	SYSMPU_EDR_EATTR_MASK   (0xEU)
#define	SYSMPU_EDR_EATTR_SHIFT   (1U)
#define	SYSMPU_EDR_EATTR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
#define	SYSMPU_EDR_EMN_MASK   (0xF0U)
#define	SYSMPU_EDR_EMN_SHIFT   (4U)
#define	SYSMPU_EDR_EMN(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
#define	SYSMPU_EDR_EPID_MASK   (0xFF00U)
#define	SYSMPU_EDR_EPID_SHIFT   (8U)
#define	SYSMPU_EDR_EPID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
#define	SYSMPU_EDR_EACD_MASK   (0xFFFF0000U)
#define	SYSMPU_EDR_EACD_SHIFT   (16U)
#define	SYSMPU_EDR_EACD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
#define	SYSMPU_EDR_ERW_MASK   (0x1U)
#define	SYSMPU_EDR_ERW_SHIFT   (0U)
#define	SYSMPU_EDR_ERW(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
#define	SYSMPU_EDR_EATTR_MASK   (0xEU)
#define	SYSMPU_EDR_EATTR_SHIFT   (1U)
#define	SYSMPU_EDR_EATTR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
#define	SYSMPU_EDR_EMN_MASK   (0xF0U)
#define	SYSMPU_EDR_EMN_SHIFT   (4U)
#define	SYSMPU_EDR_EMN(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
#define	SYSMPU_EDR_EPID_MASK   (0xFF00U)
#define	SYSMPU_EDR_EPID_SHIFT   (8U)
#define	SYSMPU_EDR_EPID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
#define	SYSMPU_EDR_EACD_MASK   (0xFFFF0000U)
#define	SYSMPU_EDR_EACD_SHIFT   (16U)
#define	SYSMPU_EDR_EACD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)

EDR - Error Detail Register, slave port n
#define	SYSMPU_EDR_COUNT   (5U)

WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3
#define	SYSMPU_WORD_M0UM_MASK   (0x7U)
#define	SYSMPU_WORD_M0UM_SHIFT   (0U)
#define	SYSMPU_WORD_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
#define	SYSMPU_WORD_VLD_MASK   (0x1U)
#define	SYSMPU_WORD_VLD_SHIFT   (0U)
#define	SYSMPU_WORD_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
#define	SYSMPU_WORD_M0SM_MASK   (0x18U)
#define	SYSMPU_WORD_M0SM_SHIFT   (3U)
#define	SYSMPU_WORD_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
#define	SYSMPU_WORD_ENDADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_ENDADDR_SHIFT   (5U)
#define	SYSMPU_WORD_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
#define	SYSMPU_WORD_SRTADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_SRTADDR_SHIFT   (5U)
#define	SYSMPU_WORD_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
#define	SYSMPU_WORD_M1UM_MASK   (0x1C0U)
#define	SYSMPU_WORD_M1UM_SHIFT   (6U)
#define	SYSMPU_WORD_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
#define	SYSMPU_WORD_M1SM_MASK   (0x600U)
#define	SYSMPU_WORD_M1SM_SHIFT   (9U)
#define	SYSMPU_WORD_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
#define	SYSMPU_WORD_M2UM_MASK   (0x7000U)
#define	SYSMPU_WORD_M2UM_SHIFT   (12U)
#define	SYSMPU_WORD_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
#define	SYSMPU_WORD_M2SM_MASK   (0x18000U)
#define	SYSMPU_WORD_M2SM_SHIFT   (15U)
#define	SYSMPU_WORD_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
#define	SYSMPU_WORD_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_WORD_M3UM_SHIFT   (18U)
#define	SYSMPU_WORD_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
#define	SYSMPU_WORD_M3SM_MASK   (0x600000U)
#define	SYSMPU_WORD_M3SM_SHIFT   (21U)
#define	SYSMPU_WORD_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
#define	SYSMPU_WORD_M4WE_MASK   (0x1000000U)
#define	SYSMPU_WORD_M4WE_SHIFT   (24U)
#define	SYSMPU_WORD_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
#define	SYSMPU_WORD_M4RE_MASK   (0x2000000U)
#define	SYSMPU_WORD_M4RE_SHIFT   (25U)
#define	SYSMPU_WORD_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
#define	SYSMPU_WORD_M5WE_MASK   (0x4000000U)
#define	SYSMPU_WORD_M5WE_SHIFT   (26U)
#define	SYSMPU_WORD_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
#define	SYSMPU_WORD_M5RE_MASK   (0x8000000U)
#define	SYSMPU_WORD_M5RE_SHIFT   (27U)
#define	SYSMPU_WORD_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
#define	SYSMPU_WORD_M6WE_MASK   (0x10000000U)
#define	SYSMPU_WORD_M6WE_SHIFT   (28U)
#define	SYSMPU_WORD_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
#define	SYSMPU_WORD_M6RE_MASK   (0x20000000U)
#define	SYSMPU_WORD_M6RE_SHIFT   (29U)
#define	SYSMPU_WORD_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
#define	SYSMPU_WORD_M7WE_MASK   (0x40000000U)
#define	SYSMPU_WORD_M7WE_SHIFT   (30U)
#define	SYSMPU_WORD_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
#define	SYSMPU_WORD_M7RE_MASK   (0x80000000U)
#define	SYSMPU_WORD_M7RE_SHIFT   (31U)
#define	SYSMPU_WORD_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
#define	SYSMPU_WORD_M0UM_MASK   (0x7U)
#define	SYSMPU_WORD_M0UM_SHIFT   (0U)
#define	SYSMPU_WORD_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
#define	SYSMPU_WORD_VLD_MASK   (0x1U)
#define	SYSMPU_WORD_VLD_SHIFT   (0U)
#define	SYSMPU_WORD_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
#define	SYSMPU_WORD_M0SM_MASK   (0x18U)
#define	SYSMPU_WORD_M0SM_SHIFT   (3U)
#define	SYSMPU_WORD_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
#define	SYSMPU_WORD_ENDADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_ENDADDR_SHIFT   (5U)
#define	SYSMPU_WORD_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
#define	SYSMPU_WORD_M0PE_MASK   (0x20U)
#define	SYSMPU_WORD_M0PE_SHIFT   (5U)
#define	SYSMPU_WORD_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
#define	SYSMPU_WORD_SRTADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_SRTADDR_SHIFT   (5U)
#define	SYSMPU_WORD_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
#define	SYSMPU_WORD_M1UM_MASK   (0x1C0U)
#define	SYSMPU_WORD_M1UM_SHIFT   (6U)
#define	SYSMPU_WORD_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
#define	SYSMPU_WORD_M1SM_MASK   (0x600U)
#define	SYSMPU_WORD_M1SM_SHIFT   (9U)
#define	SYSMPU_WORD_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
#define	SYSMPU_WORD_M1PE_MASK   (0x800U)
#define	SYSMPU_WORD_M1PE_SHIFT   (11U)
#define	SYSMPU_WORD_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
#define	SYSMPU_WORD_M2UM_MASK   (0x7000U)
#define	SYSMPU_WORD_M2UM_SHIFT   (12U)
#define	SYSMPU_WORD_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
#define	SYSMPU_WORD_M2SM_MASK   (0x18000U)
#define	SYSMPU_WORD_M2SM_SHIFT   (15U)
#define	SYSMPU_WORD_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
#define	SYSMPU_WORD_PIDMASK_MASK   (0xFF0000U)
#define	SYSMPU_WORD_PIDMASK_SHIFT   (16U)
#define	SYSMPU_WORD_PIDMASK(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
#define	SYSMPU_WORD_M2PE_MASK   (0x20000U)
#define	SYSMPU_WORD_M2PE_SHIFT   (17U)
#define	SYSMPU_WORD_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
#define	SYSMPU_WORD_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_WORD_M3UM_SHIFT   (18U)
#define	SYSMPU_WORD_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
#define	SYSMPU_WORD_M3SM_MASK   (0x600000U)
#define	SYSMPU_WORD_M3SM_SHIFT   (21U)
#define	SYSMPU_WORD_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
#define	SYSMPU_WORD_M3PE_MASK   (0x800000U)
#define	SYSMPU_WORD_M3PE_SHIFT   (23U)
#define	SYSMPU_WORD_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
#define	SYSMPU_WORD_M4WE_MASK   (0x1000000U)
#define	SYSMPU_WORD_M4WE_SHIFT   (24U)
#define	SYSMPU_WORD_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
#define	SYSMPU_WORD_PID_MASK   (0xFF000000U)
#define	SYSMPU_WORD_PID_SHIFT   (24U)
#define	SYSMPU_WORD_PID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
#define	SYSMPU_WORD_M4RE_MASK   (0x2000000U)
#define	SYSMPU_WORD_M4RE_SHIFT   (25U)
#define	SYSMPU_WORD_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
#define	SYSMPU_WORD_M5WE_MASK   (0x4000000U)
#define	SYSMPU_WORD_M5WE_SHIFT   (26U)
#define	SYSMPU_WORD_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
#define	SYSMPU_WORD_M5RE_MASK   (0x8000000U)
#define	SYSMPU_WORD_M5RE_SHIFT   (27U)
#define	SYSMPU_WORD_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
#define	SYSMPU_WORD_M6WE_MASK   (0x10000000U)
#define	SYSMPU_WORD_M6WE_SHIFT   (28U)
#define	SYSMPU_WORD_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
#define	SYSMPU_WORD_M6RE_MASK   (0x20000000U)
#define	SYSMPU_WORD_M6RE_SHIFT   (29U)
#define	SYSMPU_WORD_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
#define	SYSMPU_WORD_M7WE_MASK   (0x40000000U)
#define	SYSMPU_WORD_M7WE_SHIFT   (30U)
#define	SYSMPU_WORD_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
#define	SYSMPU_WORD_M7RE_MASK   (0x80000000U)
#define	SYSMPU_WORD_M7RE_SHIFT   (31U)
#define	SYSMPU_WORD_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
#define	SYSMPU_WORD_M0UM_MASK   (0x7U)
#define	SYSMPU_WORD_M0UM_SHIFT   (0U)
#define	SYSMPU_WORD_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
#define	SYSMPU_WORD_VLD_MASK   (0x1U)
#define	SYSMPU_WORD_VLD_SHIFT   (0U)
#define	SYSMPU_WORD_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
#define	SYSMPU_WORD_M0SM_MASK   (0x18U)
#define	SYSMPU_WORD_M0SM_SHIFT   (3U)
#define	SYSMPU_WORD_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
#define	SYSMPU_WORD_ENDADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_ENDADDR_SHIFT   (5U)
#define	SYSMPU_WORD_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
#define	SYSMPU_WORD_M0PE_MASK   (0x20U)
#define	SYSMPU_WORD_M0PE_SHIFT   (5U)
#define	SYSMPU_WORD_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
#define	SYSMPU_WORD_SRTADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_SRTADDR_SHIFT   (5U)
#define	SYSMPU_WORD_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
#define	SYSMPU_WORD_M1UM_MASK   (0x1C0U)
#define	SYSMPU_WORD_M1UM_SHIFT   (6U)
#define	SYSMPU_WORD_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
#define	SYSMPU_WORD_M1SM_MASK   (0x600U)
#define	SYSMPU_WORD_M1SM_SHIFT   (9U)
#define	SYSMPU_WORD_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
#define	SYSMPU_WORD_M1PE_MASK   (0x800U)
#define	SYSMPU_WORD_M1PE_SHIFT   (11U)
#define	SYSMPU_WORD_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
#define	SYSMPU_WORD_M2UM_MASK   (0x7000U)
#define	SYSMPU_WORD_M2UM_SHIFT   (12U)
#define	SYSMPU_WORD_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
#define	SYSMPU_WORD_M2SM_MASK   (0x18000U)
#define	SYSMPU_WORD_M2SM_SHIFT   (15U)
#define	SYSMPU_WORD_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
#define	SYSMPU_WORD_PIDMASK_MASK   (0xFF0000U)
#define	SYSMPU_WORD_PIDMASK_SHIFT   (16U)
#define	SYSMPU_WORD_PIDMASK(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
#define	SYSMPU_WORD_M2PE_MASK   (0x20000U)
#define	SYSMPU_WORD_M2PE_SHIFT   (17U)
#define	SYSMPU_WORD_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
#define	SYSMPU_WORD_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_WORD_M3UM_SHIFT   (18U)
#define	SYSMPU_WORD_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
#define	SYSMPU_WORD_M3SM_MASK   (0x600000U)
#define	SYSMPU_WORD_M3SM_SHIFT   (21U)
#define	SYSMPU_WORD_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
#define	SYSMPU_WORD_M3PE_MASK   (0x800000U)
#define	SYSMPU_WORD_M3PE_SHIFT   (23U)
#define	SYSMPU_WORD_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
#define	SYSMPU_WORD_M4WE_MASK   (0x1000000U)
#define	SYSMPU_WORD_M4WE_SHIFT   (24U)
#define	SYSMPU_WORD_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
#define	SYSMPU_WORD_PID_MASK   (0xFF000000U)
#define	SYSMPU_WORD_PID_SHIFT   (24U)
#define	SYSMPU_WORD_PID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
#define	SYSMPU_WORD_M4RE_MASK   (0x2000000U)
#define	SYSMPU_WORD_M4RE_SHIFT   (25U)
#define	SYSMPU_WORD_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
#define	SYSMPU_WORD_M5WE_MASK   (0x4000000U)
#define	SYSMPU_WORD_M5WE_SHIFT   (26U)
#define	SYSMPU_WORD_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
#define	SYSMPU_WORD_M5RE_MASK   (0x8000000U)
#define	SYSMPU_WORD_M5RE_SHIFT   (27U)
#define	SYSMPU_WORD_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
#define	SYSMPU_WORD_M6WE_MASK   (0x10000000U)
#define	SYSMPU_WORD_M6WE_SHIFT   (28U)
#define	SYSMPU_WORD_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
#define	SYSMPU_WORD_M6RE_MASK   (0x20000000U)
#define	SYSMPU_WORD_M6RE_SHIFT   (29U)
#define	SYSMPU_WORD_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
#define	SYSMPU_WORD_M7WE_MASK   (0x40000000U)
#define	SYSMPU_WORD_M7WE_SHIFT   (30U)
#define	SYSMPU_WORD_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
#define	SYSMPU_WORD_M7RE_MASK   (0x80000000U)
#define	SYSMPU_WORD_M7RE_SHIFT   (31U)
#define	SYSMPU_WORD_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
#define	SYSMPU_WORD_M0UM_MASK   (0x7U)
#define	SYSMPU_WORD_M0UM_SHIFT   (0U)
#define	SYSMPU_WORD_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
#define	SYSMPU_WORD_VLD_MASK   (0x1U)
#define	SYSMPU_WORD_VLD_SHIFT   (0U)
#define	SYSMPU_WORD_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
#define	SYSMPU_WORD_M0SM_MASK   (0x18U)
#define	SYSMPU_WORD_M0SM_SHIFT   (3U)
#define	SYSMPU_WORD_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
#define	SYSMPU_WORD_ENDADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_ENDADDR_SHIFT   (5U)
#define	SYSMPU_WORD_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
#define	SYSMPU_WORD_M0PE_MASK   (0x20U)
#define	SYSMPU_WORD_M0PE_SHIFT   (5U)
#define	SYSMPU_WORD_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
#define	SYSMPU_WORD_SRTADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_SRTADDR_SHIFT   (5U)
#define	SYSMPU_WORD_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
#define	SYSMPU_WORD_M1UM_MASK   (0x1C0U)
#define	SYSMPU_WORD_M1UM_SHIFT   (6U)
#define	SYSMPU_WORD_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
#define	SYSMPU_WORD_M1SM_MASK   (0x600U)
#define	SYSMPU_WORD_M1SM_SHIFT   (9U)
#define	SYSMPU_WORD_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
#define	SYSMPU_WORD_M1PE_MASK   (0x800U)
#define	SYSMPU_WORD_M1PE_SHIFT   (11U)
#define	SYSMPU_WORD_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
#define	SYSMPU_WORD_M2UM_MASK   (0x7000U)
#define	SYSMPU_WORD_M2UM_SHIFT   (12U)
#define	SYSMPU_WORD_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
#define	SYSMPU_WORD_M2SM_MASK   (0x18000U)
#define	SYSMPU_WORD_M2SM_SHIFT   (15U)
#define	SYSMPU_WORD_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
#define	SYSMPU_WORD_PIDMASK_MASK   (0xFF0000U)
#define	SYSMPU_WORD_PIDMASK_SHIFT   (16U)
#define	SYSMPU_WORD_PIDMASK(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
#define	SYSMPU_WORD_M2PE_MASK   (0x20000U)
#define	SYSMPU_WORD_M2PE_SHIFT   (17U)
#define	SYSMPU_WORD_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
#define	SYSMPU_WORD_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_WORD_M3UM_SHIFT   (18U)
#define	SYSMPU_WORD_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
#define	SYSMPU_WORD_M3SM_MASK   (0x600000U)
#define	SYSMPU_WORD_M3SM_SHIFT   (21U)
#define	SYSMPU_WORD_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
#define	SYSMPU_WORD_M3PE_MASK   (0x800000U)
#define	SYSMPU_WORD_M3PE_SHIFT   (23U)
#define	SYSMPU_WORD_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
#define	SYSMPU_WORD_M4WE_MASK   (0x1000000U)
#define	SYSMPU_WORD_M4WE_SHIFT   (24U)
#define	SYSMPU_WORD_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
#define	SYSMPU_WORD_PID_MASK   (0xFF000000U)
#define	SYSMPU_WORD_PID_SHIFT   (24U)
#define	SYSMPU_WORD_PID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
#define	SYSMPU_WORD_M4RE_MASK   (0x2000000U)
#define	SYSMPU_WORD_M4RE_SHIFT   (25U)
#define	SYSMPU_WORD_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
#define	SYSMPU_WORD_M5WE_MASK   (0x4000000U)
#define	SYSMPU_WORD_M5WE_SHIFT   (26U)
#define	SYSMPU_WORD_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
#define	SYSMPU_WORD_M5RE_MASK   (0x8000000U)
#define	SYSMPU_WORD_M5RE_SHIFT   (27U)
#define	SYSMPU_WORD_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
#define	SYSMPU_WORD_M6WE_MASK   (0x10000000U)
#define	SYSMPU_WORD_M6WE_SHIFT   (28U)
#define	SYSMPU_WORD_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
#define	SYSMPU_WORD_M6RE_MASK   (0x20000000U)
#define	SYSMPU_WORD_M6RE_SHIFT   (29U)
#define	SYSMPU_WORD_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
#define	SYSMPU_WORD_M7WE_MASK   (0x40000000U)
#define	SYSMPU_WORD_M7WE_SHIFT   (30U)
#define	SYSMPU_WORD_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
#define	SYSMPU_WORD_M7RE_MASK   (0x80000000U)
#define	SYSMPU_WORD_M7RE_SHIFT   (31U)
#define	SYSMPU_WORD_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
#define	SYSMPU_WORD_M0UM_MASK   (0x7U)
#define	SYSMPU_WORD_M0UM_SHIFT   (0U)
#define	SYSMPU_WORD_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
#define	SYSMPU_WORD_VLD_MASK   (0x1U)
#define	SYSMPU_WORD_VLD_SHIFT   (0U)
#define	SYSMPU_WORD_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
#define	SYSMPU_WORD_M0SM_MASK   (0x18U)
#define	SYSMPU_WORD_M0SM_SHIFT   (3U)
#define	SYSMPU_WORD_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
#define	SYSMPU_WORD_ENDADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_ENDADDR_SHIFT   (5U)
#define	SYSMPU_WORD_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
#define	SYSMPU_WORD_M0PE_MASK   (0x20U)
#define	SYSMPU_WORD_M0PE_SHIFT   (5U)
#define	SYSMPU_WORD_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
#define	SYSMPU_WORD_SRTADDR_MASK   (0xFFFFFFE0U)
#define	SYSMPU_WORD_SRTADDR_SHIFT   (5U)
#define	SYSMPU_WORD_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
#define	SYSMPU_WORD_M1UM_MASK   (0x1C0U)
#define	SYSMPU_WORD_M1UM_SHIFT   (6U)
#define	SYSMPU_WORD_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
#define	SYSMPU_WORD_M1SM_MASK   (0x600U)
#define	SYSMPU_WORD_M1SM_SHIFT   (9U)
#define	SYSMPU_WORD_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
#define	SYSMPU_WORD_M1PE_MASK   (0x800U)
#define	SYSMPU_WORD_M1PE_SHIFT   (11U)
#define	SYSMPU_WORD_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
#define	SYSMPU_WORD_M2UM_MASK   (0x7000U)
#define	SYSMPU_WORD_M2UM_SHIFT   (12U)
#define	SYSMPU_WORD_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
#define	SYSMPU_WORD_M2SM_MASK   (0x18000U)
#define	SYSMPU_WORD_M2SM_SHIFT   (15U)
#define	SYSMPU_WORD_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
#define	SYSMPU_WORD_PIDMASK_MASK   (0xFF0000U)
#define	SYSMPU_WORD_PIDMASK_SHIFT   (16U)
#define	SYSMPU_WORD_PIDMASK(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
#define	SYSMPU_WORD_M2PE_MASK   (0x20000U)
#define	SYSMPU_WORD_M2PE_SHIFT   (17U)
#define	SYSMPU_WORD_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
#define	SYSMPU_WORD_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_WORD_M3UM_SHIFT   (18U)
#define	SYSMPU_WORD_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
#define	SYSMPU_WORD_M3SM_MASK   (0x600000U)
#define	SYSMPU_WORD_M3SM_SHIFT   (21U)
#define	SYSMPU_WORD_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
#define	SYSMPU_WORD_M3PE_MASK   (0x800000U)
#define	SYSMPU_WORD_M3PE_SHIFT   (23U)
#define	SYSMPU_WORD_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
#define	SYSMPU_WORD_M4WE_MASK   (0x1000000U)
#define	SYSMPU_WORD_M4WE_SHIFT   (24U)
#define	SYSMPU_WORD_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
#define	SYSMPU_WORD_PID_MASK   (0xFF000000U)
#define	SYSMPU_WORD_PID_SHIFT   (24U)
#define	SYSMPU_WORD_PID(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
#define	SYSMPU_WORD_M4RE_MASK   (0x2000000U)
#define	SYSMPU_WORD_M4RE_SHIFT   (25U)
#define	SYSMPU_WORD_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
#define	SYSMPU_WORD_M5WE_MASK   (0x4000000U)
#define	SYSMPU_WORD_M5WE_SHIFT   (26U)
#define	SYSMPU_WORD_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
#define	SYSMPU_WORD_M5RE_MASK   (0x8000000U)
#define	SYSMPU_WORD_M5RE_SHIFT   (27U)
#define	SYSMPU_WORD_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
#define	SYSMPU_WORD_M6WE_MASK   (0x10000000U)
#define	SYSMPU_WORD_M6WE_SHIFT   (28U)
#define	SYSMPU_WORD_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
#define	SYSMPU_WORD_M6RE_MASK   (0x20000000U)
#define	SYSMPU_WORD_M6RE_SHIFT   (29U)
#define	SYSMPU_WORD_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
#define	SYSMPU_WORD_M7WE_MASK   (0x40000000U)
#define	SYSMPU_WORD_M7WE_SHIFT   (30U)
#define	SYSMPU_WORD_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
#define	SYSMPU_WORD_M7RE_MASK   (0x80000000U)
#define	SYSMPU_WORD_M7RE_SHIFT   (31U)
#define	SYSMPU_WORD_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)

WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3
#define	SYSMPU_WORD_COUNT   (12U)
#define	SYSMPU_WORD_COUNT2   (4U)

RGDAAC - Region Descriptor Alternate Access Control n
#define	SYSMPU_RGDAAC_M0UM_MASK   (0x7U)
#define	SYSMPU_RGDAAC_M0UM_SHIFT   (0U)
#define	SYSMPU_RGDAAC_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
#define	SYSMPU_RGDAAC_M0SM_MASK   (0x18U)
#define	SYSMPU_RGDAAC_M0SM_SHIFT   (3U)
#define	SYSMPU_RGDAAC_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
#define	SYSMPU_RGDAAC_M1UM_MASK   (0x1C0U)
#define	SYSMPU_RGDAAC_M1UM_SHIFT   (6U)
#define	SYSMPU_RGDAAC_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
#define	SYSMPU_RGDAAC_M1SM_MASK   (0x600U)
#define	SYSMPU_RGDAAC_M1SM_SHIFT   (9U)
#define	SYSMPU_RGDAAC_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
#define	SYSMPU_RGDAAC_M2UM_MASK   (0x7000U)
#define	SYSMPU_RGDAAC_M2UM_SHIFT   (12U)
#define	SYSMPU_RGDAAC_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
#define	SYSMPU_RGDAAC_M2SM_MASK   (0x18000U)
#define	SYSMPU_RGDAAC_M2SM_SHIFT   (15U)
#define	SYSMPU_RGDAAC_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
#define	SYSMPU_RGDAAC_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_RGDAAC_M3UM_SHIFT   (18U)
#define	SYSMPU_RGDAAC_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
#define	SYSMPU_RGDAAC_M3SM_MASK   (0x600000U)
#define	SYSMPU_RGDAAC_M3SM_SHIFT   (21U)
#define	SYSMPU_RGDAAC_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
#define	SYSMPU_RGDAAC_M4WE_MASK   (0x1000000U)
#define	SYSMPU_RGDAAC_M4WE_SHIFT   (24U)
#define	SYSMPU_RGDAAC_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
#define	SYSMPU_RGDAAC_M4RE_MASK   (0x2000000U)
#define	SYSMPU_RGDAAC_M4RE_SHIFT   (25U)
#define	SYSMPU_RGDAAC_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
#define	SYSMPU_RGDAAC_M5WE_MASK   (0x4000000U)
#define	SYSMPU_RGDAAC_M5WE_SHIFT   (26U)
#define	SYSMPU_RGDAAC_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
#define	SYSMPU_RGDAAC_M5RE_MASK   (0x8000000U)
#define	SYSMPU_RGDAAC_M5RE_SHIFT   (27U)
#define	SYSMPU_RGDAAC_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
#define	SYSMPU_RGDAAC_M6WE_MASK   (0x10000000U)
#define	SYSMPU_RGDAAC_M6WE_SHIFT   (28U)
#define	SYSMPU_RGDAAC_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
#define	SYSMPU_RGDAAC_M6RE_MASK   (0x20000000U)
#define	SYSMPU_RGDAAC_M6RE_SHIFT   (29U)
#define	SYSMPU_RGDAAC_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
#define	SYSMPU_RGDAAC_M7WE_MASK   (0x40000000U)
#define	SYSMPU_RGDAAC_M7WE_SHIFT   (30U)
#define	SYSMPU_RGDAAC_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
#define	SYSMPU_RGDAAC_M7RE_MASK   (0x80000000U)
#define	SYSMPU_RGDAAC_M7RE_SHIFT   (31U)
#define	SYSMPU_RGDAAC_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
#define	SYSMPU_RGDAAC_M0UM_MASK   (0x7U)
#define	SYSMPU_RGDAAC_M0UM_SHIFT   (0U)
#define	SYSMPU_RGDAAC_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
#define	SYSMPU_RGDAAC_M0SM_MASK   (0x18U)
#define	SYSMPU_RGDAAC_M0SM_SHIFT   (3U)
#define	SYSMPU_RGDAAC_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
#define	SYSMPU_RGDAAC_M0PE_MASK   (0x20U)
#define	SYSMPU_RGDAAC_M0PE_SHIFT   (5U)
#define	SYSMPU_RGDAAC_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
#define	SYSMPU_RGDAAC_M1UM_MASK   (0x1C0U)
#define	SYSMPU_RGDAAC_M1UM_SHIFT   (6U)
#define	SYSMPU_RGDAAC_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
#define	SYSMPU_RGDAAC_M1SM_MASK   (0x600U)
#define	SYSMPU_RGDAAC_M1SM_SHIFT   (9U)
#define	SYSMPU_RGDAAC_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
#define	SYSMPU_RGDAAC_M1PE_MASK   (0x800U)
#define	SYSMPU_RGDAAC_M1PE_SHIFT   (11U)
#define	SYSMPU_RGDAAC_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
#define	SYSMPU_RGDAAC_M2UM_MASK   (0x7000U)
#define	SYSMPU_RGDAAC_M2UM_SHIFT   (12U)
#define	SYSMPU_RGDAAC_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
#define	SYSMPU_RGDAAC_M2SM_MASK   (0x18000U)
#define	SYSMPU_RGDAAC_M2SM_SHIFT   (15U)
#define	SYSMPU_RGDAAC_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
#define	SYSMPU_RGDAAC_M2PE_MASK   (0x20000U)
#define	SYSMPU_RGDAAC_M2PE_SHIFT   (17U)
#define	SYSMPU_RGDAAC_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
#define	SYSMPU_RGDAAC_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_RGDAAC_M3UM_SHIFT   (18U)
#define	SYSMPU_RGDAAC_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
#define	SYSMPU_RGDAAC_M3SM_MASK   (0x600000U)
#define	SYSMPU_RGDAAC_M3SM_SHIFT   (21U)
#define	SYSMPU_RGDAAC_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
#define	SYSMPU_RGDAAC_M3PE_MASK   (0x800000U)
#define	SYSMPU_RGDAAC_M3PE_SHIFT   (23U)
#define	SYSMPU_RGDAAC_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
#define	SYSMPU_RGDAAC_M4WE_MASK   (0x1000000U)
#define	SYSMPU_RGDAAC_M4WE_SHIFT   (24U)
#define	SYSMPU_RGDAAC_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
#define	SYSMPU_RGDAAC_M4RE_MASK   (0x2000000U)
#define	SYSMPU_RGDAAC_M4RE_SHIFT   (25U)
#define	SYSMPU_RGDAAC_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
#define	SYSMPU_RGDAAC_M5WE_MASK   (0x4000000U)
#define	SYSMPU_RGDAAC_M5WE_SHIFT   (26U)
#define	SYSMPU_RGDAAC_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
#define	SYSMPU_RGDAAC_M5RE_MASK   (0x8000000U)
#define	SYSMPU_RGDAAC_M5RE_SHIFT   (27U)
#define	SYSMPU_RGDAAC_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
#define	SYSMPU_RGDAAC_M6WE_MASK   (0x10000000U)
#define	SYSMPU_RGDAAC_M6WE_SHIFT   (28U)
#define	SYSMPU_RGDAAC_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
#define	SYSMPU_RGDAAC_M6RE_MASK   (0x20000000U)
#define	SYSMPU_RGDAAC_M6RE_SHIFT   (29U)
#define	SYSMPU_RGDAAC_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
#define	SYSMPU_RGDAAC_M7WE_MASK   (0x40000000U)
#define	SYSMPU_RGDAAC_M7WE_SHIFT   (30U)
#define	SYSMPU_RGDAAC_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
#define	SYSMPU_RGDAAC_M7RE_MASK   (0x80000000U)
#define	SYSMPU_RGDAAC_M7RE_SHIFT   (31U)
#define	SYSMPU_RGDAAC_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
#define	SYSMPU_RGDAAC_M0UM_MASK   (0x7U)
#define	SYSMPU_RGDAAC_M0UM_SHIFT   (0U)
#define	SYSMPU_RGDAAC_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
#define	SYSMPU_RGDAAC_M0SM_MASK   (0x18U)
#define	SYSMPU_RGDAAC_M0SM_SHIFT   (3U)
#define	SYSMPU_RGDAAC_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
#define	SYSMPU_RGDAAC_M0PE_MASK   (0x20U)
#define	SYSMPU_RGDAAC_M0PE_SHIFT   (5U)
#define	SYSMPU_RGDAAC_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
#define	SYSMPU_RGDAAC_M1UM_MASK   (0x1C0U)
#define	SYSMPU_RGDAAC_M1UM_SHIFT   (6U)
#define	SYSMPU_RGDAAC_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
#define	SYSMPU_RGDAAC_M1SM_MASK   (0x600U)
#define	SYSMPU_RGDAAC_M1SM_SHIFT   (9U)
#define	SYSMPU_RGDAAC_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
#define	SYSMPU_RGDAAC_M1PE_MASK   (0x800U)
#define	SYSMPU_RGDAAC_M1PE_SHIFT   (11U)
#define	SYSMPU_RGDAAC_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
#define	SYSMPU_RGDAAC_M2UM_MASK   (0x7000U)
#define	SYSMPU_RGDAAC_M2UM_SHIFT   (12U)
#define	SYSMPU_RGDAAC_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
#define	SYSMPU_RGDAAC_M2SM_MASK   (0x18000U)
#define	SYSMPU_RGDAAC_M2SM_SHIFT   (15U)
#define	SYSMPU_RGDAAC_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
#define	SYSMPU_RGDAAC_M2PE_MASK   (0x20000U)
#define	SYSMPU_RGDAAC_M2PE_SHIFT   (17U)
#define	SYSMPU_RGDAAC_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
#define	SYSMPU_RGDAAC_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_RGDAAC_M3UM_SHIFT   (18U)
#define	SYSMPU_RGDAAC_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
#define	SYSMPU_RGDAAC_M3SM_MASK   (0x600000U)
#define	SYSMPU_RGDAAC_M3SM_SHIFT   (21U)
#define	SYSMPU_RGDAAC_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
#define	SYSMPU_RGDAAC_M3PE_MASK   (0x800000U)
#define	SYSMPU_RGDAAC_M3PE_SHIFT   (23U)
#define	SYSMPU_RGDAAC_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
#define	SYSMPU_RGDAAC_M4WE_MASK   (0x1000000U)
#define	SYSMPU_RGDAAC_M4WE_SHIFT   (24U)
#define	SYSMPU_RGDAAC_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
#define	SYSMPU_RGDAAC_M4RE_MASK   (0x2000000U)
#define	SYSMPU_RGDAAC_M4RE_SHIFT   (25U)
#define	SYSMPU_RGDAAC_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
#define	SYSMPU_RGDAAC_M5WE_MASK   (0x4000000U)
#define	SYSMPU_RGDAAC_M5WE_SHIFT   (26U)
#define	SYSMPU_RGDAAC_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
#define	SYSMPU_RGDAAC_M5RE_MASK   (0x8000000U)
#define	SYSMPU_RGDAAC_M5RE_SHIFT   (27U)
#define	SYSMPU_RGDAAC_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
#define	SYSMPU_RGDAAC_M6WE_MASK   (0x10000000U)
#define	SYSMPU_RGDAAC_M6WE_SHIFT   (28U)
#define	SYSMPU_RGDAAC_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
#define	SYSMPU_RGDAAC_M6RE_MASK   (0x20000000U)
#define	SYSMPU_RGDAAC_M6RE_SHIFT   (29U)
#define	SYSMPU_RGDAAC_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
#define	SYSMPU_RGDAAC_M7WE_MASK   (0x40000000U)
#define	SYSMPU_RGDAAC_M7WE_SHIFT   (30U)
#define	SYSMPU_RGDAAC_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
#define	SYSMPU_RGDAAC_M7RE_MASK   (0x80000000U)
#define	SYSMPU_RGDAAC_M7RE_SHIFT   (31U)
#define	SYSMPU_RGDAAC_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
#define	SYSMPU_RGDAAC_M0UM_MASK   (0x7U)
#define	SYSMPU_RGDAAC_M0UM_SHIFT   (0U)
#define	SYSMPU_RGDAAC_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
#define	SYSMPU_RGDAAC_M0SM_MASK   (0x18U)
#define	SYSMPU_RGDAAC_M0SM_SHIFT   (3U)
#define	SYSMPU_RGDAAC_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
#define	SYSMPU_RGDAAC_M0PE_MASK   (0x20U)
#define	SYSMPU_RGDAAC_M0PE_SHIFT   (5U)
#define	SYSMPU_RGDAAC_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
#define	SYSMPU_RGDAAC_M1UM_MASK   (0x1C0U)
#define	SYSMPU_RGDAAC_M1UM_SHIFT   (6U)
#define	SYSMPU_RGDAAC_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
#define	SYSMPU_RGDAAC_M1SM_MASK   (0x600U)
#define	SYSMPU_RGDAAC_M1SM_SHIFT   (9U)
#define	SYSMPU_RGDAAC_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
#define	SYSMPU_RGDAAC_M1PE_MASK   (0x800U)
#define	SYSMPU_RGDAAC_M1PE_SHIFT   (11U)
#define	SYSMPU_RGDAAC_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
#define	SYSMPU_RGDAAC_M2UM_MASK   (0x7000U)
#define	SYSMPU_RGDAAC_M2UM_SHIFT   (12U)
#define	SYSMPU_RGDAAC_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
#define	SYSMPU_RGDAAC_M2SM_MASK   (0x18000U)
#define	SYSMPU_RGDAAC_M2SM_SHIFT   (15U)
#define	SYSMPU_RGDAAC_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
#define	SYSMPU_RGDAAC_M2PE_MASK   (0x20000U)
#define	SYSMPU_RGDAAC_M2PE_SHIFT   (17U)
#define	SYSMPU_RGDAAC_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
#define	SYSMPU_RGDAAC_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_RGDAAC_M3UM_SHIFT   (18U)
#define	SYSMPU_RGDAAC_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
#define	SYSMPU_RGDAAC_M3SM_MASK   (0x600000U)
#define	SYSMPU_RGDAAC_M3SM_SHIFT   (21U)
#define	SYSMPU_RGDAAC_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
#define	SYSMPU_RGDAAC_M3PE_MASK   (0x800000U)
#define	SYSMPU_RGDAAC_M3PE_SHIFT   (23U)
#define	SYSMPU_RGDAAC_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
#define	SYSMPU_RGDAAC_M4WE_MASK   (0x1000000U)
#define	SYSMPU_RGDAAC_M4WE_SHIFT   (24U)
#define	SYSMPU_RGDAAC_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
#define	SYSMPU_RGDAAC_M4RE_MASK   (0x2000000U)
#define	SYSMPU_RGDAAC_M4RE_SHIFT   (25U)
#define	SYSMPU_RGDAAC_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
#define	SYSMPU_RGDAAC_M5WE_MASK   (0x4000000U)
#define	SYSMPU_RGDAAC_M5WE_SHIFT   (26U)
#define	SYSMPU_RGDAAC_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
#define	SYSMPU_RGDAAC_M5RE_MASK   (0x8000000U)
#define	SYSMPU_RGDAAC_M5RE_SHIFT   (27U)
#define	SYSMPU_RGDAAC_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
#define	SYSMPU_RGDAAC_M6WE_MASK   (0x10000000U)
#define	SYSMPU_RGDAAC_M6WE_SHIFT   (28U)
#define	SYSMPU_RGDAAC_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
#define	SYSMPU_RGDAAC_M6RE_MASK   (0x20000000U)
#define	SYSMPU_RGDAAC_M6RE_SHIFT   (29U)
#define	SYSMPU_RGDAAC_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
#define	SYSMPU_RGDAAC_M7WE_MASK   (0x40000000U)
#define	SYSMPU_RGDAAC_M7WE_SHIFT   (30U)
#define	SYSMPU_RGDAAC_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
#define	SYSMPU_RGDAAC_M7RE_MASK   (0x80000000U)
#define	SYSMPU_RGDAAC_M7RE_SHIFT   (31U)
#define	SYSMPU_RGDAAC_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
#define	SYSMPU_RGDAAC_M0UM_MASK   (0x7U)
#define	SYSMPU_RGDAAC_M0UM_SHIFT   (0U)
#define	SYSMPU_RGDAAC_M0UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
#define	SYSMPU_RGDAAC_M0SM_MASK   (0x18U)
#define	SYSMPU_RGDAAC_M0SM_SHIFT   (3U)
#define	SYSMPU_RGDAAC_M0SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
#define	SYSMPU_RGDAAC_M0PE_MASK   (0x20U)
#define	SYSMPU_RGDAAC_M0PE_SHIFT   (5U)
#define	SYSMPU_RGDAAC_M0PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
#define	SYSMPU_RGDAAC_M1UM_MASK   (0x1C0U)
#define	SYSMPU_RGDAAC_M1UM_SHIFT   (6U)
#define	SYSMPU_RGDAAC_M1UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
#define	SYSMPU_RGDAAC_M1SM_MASK   (0x600U)
#define	SYSMPU_RGDAAC_M1SM_SHIFT   (9U)
#define	SYSMPU_RGDAAC_M1SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
#define	SYSMPU_RGDAAC_M1PE_MASK   (0x800U)
#define	SYSMPU_RGDAAC_M1PE_SHIFT   (11U)
#define	SYSMPU_RGDAAC_M1PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
#define	SYSMPU_RGDAAC_M2UM_MASK   (0x7000U)
#define	SYSMPU_RGDAAC_M2UM_SHIFT   (12U)
#define	SYSMPU_RGDAAC_M2UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
#define	SYSMPU_RGDAAC_M2SM_MASK   (0x18000U)
#define	SYSMPU_RGDAAC_M2SM_SHIFT   (15U)
#define	SYSMPU_RGDAAC_M2SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
#define	SYSMPU_RGDAAC_M2PE_MASK   (0x20000U)
#define	SYSMPU_RGDAAC_M2PE_SHIFT   (17U)
#define	SYSMPU_RGDAAC_M2PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
#define	SYSMPU_RGDAAC_M3UM_MASK   (0x1C0000U)
#define	SYSMPU_RGDAAC_M3UM_SHIFT   (18U)
#define	SYSMPU_RGDAAC_M3UM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
#define	SYSMPU_RGDAAC_M3SM_MASK   (0x600000U)
#define	SYSMPU_RGDAAC_M3SM_SHIFT   (21U)
#define	SYSMPU_RGDAAC_M3SM(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
#define	SYSMPU_RGDAAC_M3PE_MASK   (0x800000U)
#define	SYSMPU_RGDAAC_M3PE_SHIFT   (23U)
#define	SYSMPU_RGDAAC_M3PE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
#define	SYSMPU_RGDAAC_M4WE_MASK   (0x1000000U)
#define	SYSMPU_RGDAAC_M4WE_SHIFT   (24U)
#define	SYSMPU_RGDAAC_M4WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
#define	SYSMPU_RGDAAC_M4RE_MASK   (0x2000000U)
#define	SYSMPU_RGDAAC_M4RE_SHIFT   (25U)
#define	SYSMPU_RGDAAC_M4RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
#define	SYSMPU_RGDAAC_M5WE_MASK   (0x4000000U)
#define	SYSMPU_RGDAAC_M5WE_SHIFT   (26U)
#define	SYSMPU_RGDAAC_M5WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
#define	SYSMPU_RGDAAC_M5RE_MASK   (0x8000000U)
#define	SYSMPU_RGDAAC_M5RE_SHIFT   (27U)
#define	SYSMPU_RGDAAC_M5RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
#define	SYSMPU_RGDAAC_M6WE_MASK   (0x10000000U)
#define	SYSMPU_RGDAAC_M6WE_SHIFT   (28U)
#define	SYSMPU_RGDAAC_M6WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
#define	SYSMPU_RGDAAC_M6RE_MASK   (0x20000000U)
#define	SYSMPU_RGDAAC_M6RE_SHIFT   (29U)
#define	SYSMPU_RGDAAC_M6RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
#define	SYSMPU_RGDAAC_M7WE_MASK   (0x40000000U)
#define	SYSMPU_RGDAAC_M7WE_SHIFT   (30U)
#define	SYSMPU_RGDAAC_M7WE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
#define	SYSMPU_RGDAAC_M7RE_MASK   (0x80000000U)
#define	SYSMPU_RGDAAC_M7RE_SHIFT   (31U)
#define	SYSMPU_RGDAAC_M7RE(x)   (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)

RGDAAC - Region Descriptor Alternate Access Control n
#define	SYSMPU_RGDAAC_COUNT   (12U)

Macro Definition Documentation

SYSMPU

#define SYSMPU   ((SYSMPU_Type *)SYSMPU_BASE)

Peripheral SYSMPU base pointer

SYSMPU_BASE

#define SYSMPU_BASE   (0x4000D000u)

Peripheral SYSMPU base address

SYSMPU_BASE_ADDRS

#define SYSMPU_BASE_ADDRS   { SYSMPU_BASE }

Array initializer of SYSMPU peripheral base addresses

SYSMPU_BASE_PTRS

#define SYSMPU_BASE_PTRS   { SYSMPU }

Array initializer of SYSMPU peripheral base pointers

SYSMPU_CESR_NRGD [1/5]

#define SYSMPU_CESR_NRGD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)

NRGD - Number Of Region Descriptors 0b0000..8 region descriptors 0b0001..12 region descriptors 0b0010..16 region descriptors

SYSMPU_CESR_NRGD [2/5]

#define SYSMPU_CESR_NRGD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)

NRGD - Number Of Region Descriptors 0b0000..8 region descriptors 0b0001..12 region descriptors 0b0010..16 region descriptors

SYSMPU_CESR_NRGD [3/5]

#define SYSMPU_CESR_NRGD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)

NRGD - Number Of Region Descriptors 0b0000..8 region descriptors 0b0001..12 region descriptors 0b0010..16 region descriptors

SYSMPU_CESR_NRGD [4/5]

#define SYSMPU_CESR_NRGD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)

NRGD - Number Of Region Descriptors 0b0000..8 region descriptors 0b0001..12 region descriptors 0b0010..16 region descriptors

SYSMPU_CESR_NRGD [5/5]

#define SYSMPU_CESR_NRGD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)

NRGD - Number Of Region Descriptors 0b0000..8 region descriptors 0b0001..12 region descriptors 0b0010..16 region descriptors

SYSMPU_CESR_SPERR [1/5]

#define SYSMPU_CESR_SPERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)

SPERR - Slave Port n Error 0b00000..No error has occurred for slave port n. 0b00001..An error has occurred for slave port n.

SYSMPU_CESR_SPERR [2/5]

#define SYSMPU_CESR_SPERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)

SPERR - Slave Port n Error 0b00000..No error has occurred for slave port n. 0b00001..An error has occurred for slave port n.

SYSMPU_CESR_SPERR [3/5]

#define SYSMPU_CESR_SPERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)

SPERR - Slave Port n Error 0b00000..No error has occurred for slave port n. 0b00001..An error has occurred for slave port n.

SYSMPU_CESR_SPERR [4/5]

#define SYSMPU_CESR_SPERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)

SPERR - Slave Port n Error 0b00000..No error has occurred for slave port n. 0b00001..An error has occurred for slave port n.

SYSMPU_CESR_SPERR [5/5]

#define SYSMPU_CESR_SPERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)

SPERR - Slave Port n Error 0b00000..No error has occurred for slave port n. 0b00001..An error has occurred for slave port n.

SYSMPU_CESR_VLD [1/5]

#define SYSMPU_CESR_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)

VLD - Valid 0b0..MPU is disabled. All accesses from all bus masters are allowed. 0b1..MPU is enabled

SYSMPU_CESR_VLD [2/5]

#define SYSMPU_CESR_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)

VLD - Valid 0b0..MPU is disabled. All accesses from all bus masters are allowed. 0b1..MPU is enabled

SYSMPU_CESR_VLD [3/5]

#define SYSMPU_CESR_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)

VLD - Valid 0b0..MPU is disabled. All accesses from all bus masters are allowed. 0b1..MPU is enabled

SYSMPU_CESR_VLD [4/5]

#define SYSMPU_CESR_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)

VLD - Valid 0b0..MPU is disabled. All accesses from all bus masters are allowed. 0b1..MPU is enabled

SYSMPU_CESR_VLD [5/5]

#define SYSMPU_CESR_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)

VLD - Valid 0b0..MPU is disabled. All accesses from all bus masters are allowed. 0b1..MPU is enabled

SYSMPU_EDR_EATTR [1/5]

#define SYSMPU_EDR_EATTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)

EATTR - Error Attributes 0b000..User mode, instruction access 0b001..User mode, data access 0b010..Supervisor mode, instruction access 0b011..Supervisor mode, data access

SYSMPU_EDR_EATTR [2/5]

#define SYSMPU_EDR_EATTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)

EATTR - Error Attributes 0b000..User mode, instruction access 0b001..User mode, data access 0b010..Supervisor mode, instruction access 0b011..Supervisor mode, data access

SYSMPU_EDR_EATTR [3/5]

#define SYSMPU_EDR_EATTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)

EATTR - Error Attributes 0b000..User mode, instruction access 0b001..User mode, data access 0b010..Supervisor mode, instruction access 0b011..Supervisor mode, data access

SYSMPU_EDR_EATTR [4/5]

#define SYSMPU_EDR_EATTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)

EATTR - Error Attributes 0b000..User mode, instruction access 0b001..User mode, data access 0b010..Supervisor mode, instruction access 0b011..Supervisor mode, data access

SYSMPU_EDR_EATTR [5/5]

#define SYSMPU_EDR_EATTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)

EATTR - Error Attributes 0b000..User mode, instruction access 0b001..User mode, data access 0b010..Supervisor mode, instruction access 0b011..Supervisor mode, data access

SYSMPU_EDR_ERW [1/5]

#define SYSMPU_EDR_ERW

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)

ERW - Error Read/Write 0b0..Read 0b1..Write

SYSMPU_EDR_ERW [2/5]

#define SYSMPU_EDR_ERW

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)

ERW - Error Read/Write 0b0..Read 0b1..Write

SYSMPU_EDR_ERW [3/5]

#define SYSMPU_EDR_ERW

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)

ERW - Error Read/Write 0b0..Read 0b1..Write

SYSMPU_EDR_ERW [4/5]

#define SYSMPU_EDR_ERW

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)

ERW - Error Read/Write 0b0..Read 0b1..Write

SYSMPU_EDR_ERW [5/5]

#define SYSMPU_EDR_ERW

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)

ERW - Error Read/Write 0b0..Read 0b1..Write

SYSMPU_RGDAAC_M3PE [1/4]

#define SYSMPU_RGDAAC_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

SYSMPU_RGDAAC_M3PE [2/4]

#define SYSMPU_RGDAAC_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

SYSMPU_RGDAAC_M3PE [3/4]

#define SYSMPU_RGDAAC_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

SYSMPU_RGDAAC_M3PE [4/4]

#define SYSMPU_RGDAAC_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

SYSMPU_RGDAAC_M3SM [1/5]

#define SYSMPU_RGDAAC_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_RGDAAC_M3SM [2/5]

#define SYSMPU_RGDAAC_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_RGDAAC_M3SM [3/5]

#define SYSMPU_RGDAAC_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_RGDAAC_M3SM [4/5]

#define SYSMPU_RGDAAC_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_RGDAAC_M3SM [5/5]

#define SYSMPU_RGDAAC_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_RGDAAC_M3UM [1/5]

#define SYSMPU_RGDAAC_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_RGDAAC_M3UM [2/5]

#define SYSMPU_RGDAAC_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_RGDAAC_M3UM [3/5]

#define SYSMPU_RGDAAC_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_RGDAAC_M3UM [4/5]

#define SYSMPU_RGDAAC_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_RGDAAC_M3UM [5/5]

#define SYSMPU_RGDAAC_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_RGDAAC_M4RE [1/5]

#define SYSMPU_RGDAAC_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_RGDAAC_M4RE [2/5]

#define SYSMPU_RGDAAC_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_RGDAAC_M4RE [3/5]

#define SYSMPU_RGDAAC_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_RGDAAC_M4RE [4/5]

#define SYSMPU_RGDAAC_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_RGDAAC_M4RE [5/5]

#define SYSMPU_RGDAAC_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_RGDAAC_M4WE [1/5]

#define SYSMPU_RGDAAC_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_RGDAAC_M4WE [2/5]

#define SYSMPU_RGDAAC_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_RGDAAC_M4WE [3/5]

#define SYSMPU_RGDAAC_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_RGDAAC_M4WE [4/5]

#define SYSMPU_RGDAAC_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_RGDAAC_M4WE [5/5]

#define SYSMPU_RGDAAC_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_RGDAAC_M5RE [1/5]

#define SYSMPU_RGDAAC_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_RGDAAC_M5RE [2/5]

#define SYSMPU_RGDAAC_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_RGDAAC_M5RE [3/5]

#define SYSMPU_RGDAAC_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_RGDAAC_M5RE [4/5]

#define SYSMPU_RGDAAC_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_RGDAAC_M5RE [5/5]

#define SYSMPU_RGDAAC_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_RGDAAC_M5WE [1/5]

#define SYSMPU_RGDAAC_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_RGDAAC_M5WE [2/5]

#define SYSMPU_RGDAAC_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_RGDAAC_M5WE [3/5]

#define SYSMPU_RGDAAC_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_RGDAAC_M5WE [4/5]

#define SYSMPU_RGDAAC_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_RGDAAC_M5WE [5/5]

#define SYSMPU_RGDAAC_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_RGDAAC_M6RE [1/5]

#define SYSMPU_RGDAAC_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_RGDAAC_M6RE [2/5]

#define SYSMPU_RGDAAC_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_RGDAAC_M6RE [3/5]

#define SYSMPU_RGDAAC_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_RGDAAC_M6RE [4/5]

#define SYSMPU_RGDAAC_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_RGDAAC_M6RE [5/5]

#define SYSMPU_RGDAAC_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_RGDAAC_M6WE [1/5]

#define SYSMPU_RGDAAC_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_RGDAAC_M6WE [2/5]

#define SYSMPU_RGDAAC_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_RGDAAC_M6WE [3/5]

#define SYSMPU_RGDAAC_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_RGDAAC_M6WE [4/5]

#define SYSMPU_RGDAAC_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_RGDAAC_M6WE [5/5]

#define SYSMPU_RGDAAC_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_RGDAAC_M7RE [1/5]

#define SYSMPU_RGDAAC_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_RGDAAC_M7RE [2/5]

#define SYSMPU_RGDAAC_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_RGDAAC_M7RE [3/5]

#define SYSMPU_RGDAAC_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_RGDAAC_M7RE [4/5]

#define SYSMPU_RGDAAC_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_RGDAAC_M7RE [5/5]

#define SYSMPU_RGDAAC_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_RGDAAC_M7WE [1/5]

#define SYSMPU_RGDAAC_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_RGDAAC_M7WE [2/5]

#define SYSMPU_RGDAAC_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_RGDAAC_M7WE [3/5]

#define SYSMPU_RGDAAC_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_RGDAAC_M7WE [4/5]

#define SYSMPU_RGDAAC_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_RGDAAC_M7WE [5/5]

#define SYSMPU_RGDAAC_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_WORD_M3PE [1/4]

#define SYSMPU_WORD_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

SYSMPU_WORD_M3PE [2/4]

#define SYSMPU_WORD_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

SYSMPU_WORD_M3PE [3/4]

#define SYSMPU_WORD_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

SYSMPU_WORD_M3PE [4/4]

#define SYSMPU_WORD_M3PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)

M3PE - Bus Master 3 Process Identifier Enable 0b0..Do not include the process identifier in the evaluation 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

SYSMPU_WORD_M3SM [1/5]

#define SYSMPU_WORD_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_WORD_M3SM [2/5]

#define SYSMPU_WORD_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_WORD_M3SM [3/5]

#define SYSMPU_WORD_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_WORD_M3SM [4/5]

#define SYSMPU_WORD_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_WORD_M3SM [5/5]

#define SYSMPU_WORD_M3SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)

M3SM - Bus Master 3 Supervisor Mode Access Control 0b00..r/w/x; read, write and execute allowed 0b01..r/x; read and execute allowed, but no write 0b10..r/w; read and write allowed, but no execute 0b11..Same as User mode defined in M3UM

SYSMPU_WORD_M3UM [1/5]

#define SYSMPU_WORD_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_WORD_M3UM [2/5]

#define SYSMPU_WORD_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_WORD_M3UM [3/5]

#define SYSMPU_WORD_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_WORD_M3UM [4/5]

#define SYSMPU_WORD_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_WORD_M3UM [5/5]

#define SYSMPU_WORD_M3UM

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)

M3UM - Bus Master 3 User Mode Access Control 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 0b001..Allows the given access type to occur

SYSMPU_WORD_M4RE [1/5]

#define SYSMPU_WORD_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_WORD_M4RE [2/5]

#define SYSMPU_WORD_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_WORD_M4RE [3/5]

#define SYSMPU_WORD_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_WORD_M4RE [4/5]

#define SYSMPU_WORD_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_WORD_M4RE [5/5]

#define SYSMPU_WORD_M4RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)

M4RE - Bus Master 4 Read Enable 0b0..Bus master 4 reads terminate with an access error and the read is not performed 0b1..Bus master 4 reads allowed

SYSMPU_WORD_M4WE [1/5]

#define SYSMPU_WORD_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_WORD_M4WE [2/5]

#define SYSMPU_WORD_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_WORD_M4WE [3/5]

#define SYSMPU_WORD_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_WORD_M4WE [4/5]

#define SYSMPU_WORD_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_WORD_M4WE [5/5]

#define SYSMPU_WORD_M4WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)

M4WE - Bus Master 4 Write Enable 0b0..Bus master 4 writes terminate with an access error and the write is not performed 0b1..Bus master 4 writes allowed

SYSMPU_WORD_M5RE [1/5]

#define SYSMPU_WORD_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_WORD_M5RE [2/5]

#define SYSMPU_WORD_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_WORD_M5RE [3/5]

#define SYSMPU_WORD_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_WORD_M5RE [4/5]

#define SYSMPU_WORD_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_WORD_M5RE [5/5]

#define SYSMPU_WORD_M5RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)

M5RE - Bus Master 5 Read Enable 0b0..Bus master 5 reads terminate with an access error and the read is not performed 0b1..Bus master 5 reads allowed

SYSMPU_WORD_M5WE [1/5]

#define SYSMPU_WORD_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_WORD_M5WE [2/5]

#define SYSMPU_WORD_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_WORD_M5WE [3/5]

#define SYSMPU_WORD_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_WORD_M5WE [4/5]

#define SYSMPU_WORD_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_WORD_M5WE [5/5]

#define SYSMPU_WORD_M5WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)

M5WE - Bus Master 5 Write Enable 0b0..Bus master 5 writes terminate with an access error and the write is not performed 0b1..Bus master 5 writes allowed

SYSMPU_WORD_M6RE [1/5]

#define SYSMPU_WORD_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_WORD_M6RE [2/5]

#define SYSMPU_WORD_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_WORD_M6RE [3/5]

#define SYSMPU_WORD_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_WORD_M6RE [4/5]

#define SYSMPU_WORD_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_WORD_M6RE [5/5]

#define SYSMPU_WORD_M6RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)

M6RE - Bus Master 6 Read Enable 0b0..Bus master 6 reads terminate with an access error and the read is not performed 0b1..Bus master 6 reads allowed

SYSMPU_WORD_M6WE [1/5]

#define SYSMPU_WORD_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_WORD_M6WE [2/5]

#define SYSMPU_WORD_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_WORD_M6WE [3/5]

#define SYSMPU_WORD_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_WORD_M6WE [4/5]

#define SYSMPU_WORD_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_WORD_M6WE [5/5]

#define SYSMPU_WORD_M6WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)

M6WE - Bus Master 6 Write Enable 0b0..Bus master 6 writes terminate with an access error and the write is not performed 0b1..Bus master 6 writes allowed

SYSMPU_WORD_M7RE [1/5]

#define SYSMPU_WORD_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_WORD_M7RE [2/5]

#define SYSMPU_WORD_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_WORD_M7RE [3/5]

#define SYSMPU_WORD_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_WORD_M7RE [4/5]

#define SYSMPU_WORD_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_WORD_M7RE [5/5]

#define SYSMPU_WORD_M7RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)

M7RE - Bus Master 7 Read Enable 0b0..Bus master 7 reads terminate with an access error and the read is not performed 0b1..Bus master 7 reads allowed

SYSMPU_WORD_M7WE [1/5]

#define SYSMPU_WORD_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_WORD_M7WE [2/5]

#define SYSMPU_WORD_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_WORD_M7WE [3/5]

#define SYSMPU_WORD_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_WORD_M7WE [4/5]

#define SYSMPU_WORD_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_WORD_M7WE [5/5]

#define SYSMPU_WORD_M7WE

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)

M7WE - Bus Master 7 Write Enable 0b0..Bus master 7 writes terminate with an access error and the write is not performed 0b1..Bus master 7 writes allowed

SYSMPU_WORD_VLD [1/5]

#define SYSMPU_WORD_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)

VLD - Valid 0b0..Region descriptor is invalid 0b1..Region descriptor is valid

SYSMPU_WORD_VLD [2/5]

#define SYSMPU_WORD_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)

VLD - Valid 0b0..Region descriptor is invalid 0b1..Region descriptor is valid

SYSMPU_WORD_VLD [3/5]

#define SYSMPU_WORD_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)

VLD - Valid 0b0..Region descriptor is invalid 0b1..Region descriptor is valid

SYSMPU_WORD_VLD [4/5]

#define SYSMPU_WORD_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)

VLD - Valid 0b0..Region descriptor is invalid 0b1..Region descriptor is valid

SYSMPU_WORD_VLD [5/5]

#define SYSMPU_WORD_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)

VLD - Valid 0b0..Region descriptor is invalid 0b1..Region descriptor is valid