mikroSDK Reference Manual
Macros
TSI Register Masks
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Macros

#define TSI0_BASE   (0x40045000u)
 
#define TSI0   ((TSI_Type *)TSI0_BASE)
 
#define TSI_BASE_ADDRS   { TSI0_BASE }
 
#define TSI_BASE_PTRS   { TSI0 }
 
#define TSI_IRQS   { TSI0_IRQn }
 
#define TSI_GENCS_ERIE_MASK   0x20u
 
#define TSI_GENCS_ERIE_SHIFT   5
 
#define TSI_GENCS_TSIIE_MASK   0x40u
 
#define TSI_GENCS_TSIIE_SHIFT   6
 
#define TSI_GENCS_SWTS_MASK   0x100u
 
#define TSI_GENCS_SWTS_SHIFT   8
 
#define TSI_GENCS_OVRF_MASK   0x1000u
 
#define TSI_GENCS_OVRF_SHIFT   12
 
#define TSI_GENCS_EXTERF_MASK   0x2000u
 
#define TSI_GENCS_EXTERF_SHIFT   13
 
#define TSI_GENCS_LPSCNITV_MASK   0xF000000u
 
#define TSI_GENCS_LPSCNITV_SHIFT   24
 
#define TSI_GENCS_LPSCNITV(x)   (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
 
#define TSI_GENCS_LPCLKS_MASK   0x10000000u
 
#define TSI_GENCS_LPCLKS_SHIFT   28
 
#define TSI_SCANC_AMPSC_MASK   0x7u
 
#define TSI_SCANC_AMPSC_SHIFT   0
 
#define TSI_SCANC_AMPSC(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
 
#define TSI_SCANC_AMCLKS_MASK   0x18u
 
#define TSI_SCANC_AMCLKS_SHIFT   3
 
#define TSI_SCANC_AMCLKS(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
 
#define TSI_SCANC_AMCLKDIV_MASK   0x20u
 
#define TSI_SCANC_AMCLKDIV_SHIFT   5
 
#define TSI_SCANC_SMOD_MASK   0xFF00u
 
#define TSI_SCANC_SMOD_SHIFT   8
 
#define TSI_SCANC_SMOD(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
 
#define TSI_SCANC_DELVOL_MASK   0x70000u
 
#define TSI_SCANC_DELVOL_SHIFT   16
 
#define TSI_SCANC_DELVOL(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_DELVOL_SHIFT))&TSI_SCANC_DELVOL_MASK)
 
#define TSI_SCANC_EXTCHRG_MASK   0xF80000u
 
#define TSI_SCANC_EXTCHRG_SHIFT   19
 
#define TSI_SCANC_EXTCHRG(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
 
#define TSI_SCANC_CAPTRM_MASK   0x7000000u
 
#define TSI_SCANC_CAPTRM_SHIFT   24
 
#define TSI_SCANC_CAPTRM(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_CAPTRM_SHIFT))&TSI_SCANC_CAPTRM_MASK)
 
#define TSI_SCANC_REFCHRG_MASK   0xF8000000u
 
#define TSI_SCANC_REFCHRG_SHIFT   27
 
#define TSI_SCANC_REFCHRG(x)   (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
 
#define TSI_PEN_PEN0_MASK   0x1u
 
#define TSI_PEN_PEN0_SHIFT   0
 
#define TSI_PEN_PEN1_MASK   0x2u
 
#define TSI_PEN_PEN1_SHIFT   1
 
#define TSI_PEN_PEN2_MASK   0x4u
 
#define TSI_PEN_PEN2_SHIFT   2
 
#define TSI_PEN_PEN3_MASK   0x8u
 
#define TSI_PEN_PEN3_SHIFT   3
 
#define TSI_PEN_PEN4_MASK   0x10u
 
#define TSI_PEN_PEN4_SHIFT   4
 
#define TSI_PEN_PEN5_MASK   0x20u
 
#define TSI_PEN_PEN5_SHIFT   5
 
#define TSI_PEN_PEN6_MASK   0x40u
 
#define TSI_PEN_PEN6_SHIFT   6
 
#define TSI_PEN_PEN7_MASK   0x80u
 
#define TSI_PEN_PEN7_SHIFT   7
 
#define TSI_PEN_PEN8_MASK   0x100u
 
#define TSI_PEN_PEN8_SHIFT   8
 
#define TSI_PEN_PEN9_MASK   0x200u
 
#define TSI_PEN_PEN9_SHIFT   9
 
#define TSI_PEN_PEN10_MASK   0x400u
 
#define TSI_PEN_PEN10_SHIFT   10
 
#define TSI_PEN_PEN11_MASK   0x800u
 
#define TSI_PEN_PEN11_SHIFT   11
 
#define TSI_PEN_PEN12_MASK   0x1000u
 
#define TSI_PEN_PEN12_SHIFT   12
 
#define TSI_PEN_PEN13_MASK   0x2000u
 
#define TSI_PEN_PEN13_SHIFT   13
 
#define TSI_PEN_PEN14_MASK   0x4000u
 
#define TSI_PEN_PEN14_SHIFT   14
 
#define TSI_PEN_PEN15_MASK   0x8000u
 
#define TSI_PEN_PEN15_SHIFT   15
 
#define TSI_PEN_LPSP_MASK   0xF0000u
 
#define TSI_PEN_LPSP_SHIFT   16
 
#define TSI_PEN_LPSP(x)   (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
 
#define TSI_STATUS_ORNGF0_MASK   0x1u
 
#define TSI_STATUS_ORNGF0_SHIFT   0
 
#define TSI_STATUS_ORNGF1_MASK   0x2u
 
#define TSI_STATUS_ORNGF1_SHIFT   1
 
#define TSI_STATUS_ORNGF2_MASK   0x4u
 
#define TSI_STATUS_ORNGF2_SHIFT   2
 
#define TSI_STATUS_ORNGF3_MASK   0x8u
 
#define TSI_STATUS_ORNGF3_SHIFT   3
 
#define TSI_STATUS_ORNGF4_MASK   0x10u
 
#define TSI_STATUS_ORNGF4_SHIFT   4
 
#define TSI_STATUS_ORNGF5_MASK   0x20u
 
#define TSI_STATUS_ORNGF5_SHIFT   5
 
#define TSI_STATUS_ORNGF6_MASK   0x40u
 
#define TSI_STATUS_ORNGF6_SHIFT   6
 
#define TSI_STATUS_ORNGF7_MASK   0x80u
 
#define TSI_STATUS_ORNGF7_SHIFT   7
 
#define TSI_STATUS_ORNGF8_MASK   0x100u
 
#define TSI_STATUS_ORNGF8_SHIFT   8
 
#define TSI_STATUS_ORNGF9_MASK   0x200u
 
#define TSI_STATUS_ORNGF9_SHIFT   9
 
#define TSI_STATUS_ORNGF10_MASK   0x400u
 
#define TSI_STATUS_ORNGF10_SHIFT   10
 
#define TSI_STATUS_ORNGF11_MASK   0x800u
 
#define TSI_STATUS_ORNGF11_SHIFT   11
 
#define TSI_STATUS_ORNGF12_MASK   0x1000u
 
#define TSI_STATUS_ORNGF12_SHIFT   12
 
#define TSI_STATUS_ORNGF13_MASK   0x2000u
 
#define TSI_STATUS_ORNGF13_SHIFT   13
 
#define TSI_STATUS_ORNGF14_MASK   0x4000u
 
#define TSI_STATUS_ORNGF14_SHIFT   14
 
#define TSI_STATUS_ORNGF15_MASK   0x8000u
 
#define TSI_STATUS_ORNGF15_SHIFT   15
 
#define TSI_STATUS_ERROF0_MASK   0x10000u
 
#define TSI_STATUS_ERROF0_SHIFT   16
 
#define TSI_STATUS_ERROF1_MASK   0x20000u
 
#define TSI_STATUS_ERROF1_SHIFT   17
 
#define TSI_STATUS_ERROF2_MASK   0x40000u
 
#define TSI_STATUS_ERROF2_SHIFT   18
 
#define TSI_STATUS_ERROF3_MASK   0x80000u
 
#define TSI_STATUS_ERROF3_SHIFT   19
 
#define TSI_STATUS_ERROF4_MASK   0x100000u
 
#define TSI_STATUS_ERROF4_SHIFT   20
 
#define TSI_STATUS_ERROF5_MASK   0x200000u
 
#define TSI_STATUS_ERROF5_SHIFT   21
 
#define TSI_STATUS_ERROF6_MASK   0x400000u
 
#define TSI_STATUS_ERROF6_SHIFT   22
 
#define TSI_STATUS_ERROF7_MASK   0x800000u
 
#define TSI_STATUS_ERROF7_SHIFT   23
 
#define TSI_STATUS_ERROF8_MASK   0x1000000u
 
#define TSI_STATUS_ERROF8_SHIFT   24
 
#define TSI_STATUS_ERROF9_MASK   0x2000000u
 
#define TSI_STATUS_ERROF9_SHIFT   25
 
#define TSI_STATUS_ERROF10_MASK   0x4000000u
 
#define TSI_STATUS_ERROF10_SHIFT   26
 
#define TSI_STATUS_ERROF11_MASK   0x8000000u
 
#define TSI_STATUS_ERROF11_SHIFT   27
 
#define TSI_STATUS_ERROF12_MASK   0x10000000u
 
#define TSI_STATUS_ERROF12_SHIFT   28
 
#define TSI_STATUS_ERROF13_MASK   0x20000000u
 
#define TSI_STATUS_ERROF13_SHIFT   29
 
#define TSI_STATUS_ERROF14_MASK   0x40000000u
 
#define TSI_STATUS_ERROF14_SHIFT   30
 
#define TSI_STATUS_ERROF15_MASK   0x80000000u
 
#define TSI_STATUS_ERROF15_SHIFT   31
 
#define TSI_CNTR1_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR1_CNTN_SHIFT   0
 
#define TSI_CNTR1_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CNTN_SHIFT))&TSI_CNTR1_CNTN_MASK)
 
#define TSI_CNTR1_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR1_CNTN1_SHIFT   16
 
#define TSI_CNTR1_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CNTN1_SHIFT))&TSI_CNTR1_CNTN1_MASK)
 
#define TSI_CNTR3_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR3_CNTN_SHIFT   0
 
#define TSI_CNTR3_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CNTN_SHIFT))&TSI_CNTR3_CNTN_MASK)
 
#define TSI_CNTR3_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR3_CNTN1_SHIFT   16
 
#define TSI_CNTR3_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CNTN1_SHIFT))&TSI_CNTR3_CNTN1_MASK)
 
#define TSI_CNTR5_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR5_CNTN_SHIFT   0
 
#define TSI_CNTR5_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CNTN_SHIFT))&TSI_CNTR5_CNTN_MASK)
 
#define TSI_CNTR5_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR5_CNTN1_SHIFT   16
 
#define TSI_CNTR5_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CNTN1_SHIFT))&TSI_CNTR5_CNTN1_MASK)
 
#define TSI_CNTR7_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR7_CNTN_SHIFT   0
 
#define TSI_CNTR7_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CNTN_SHIFT))&TSI_CNTR7_CNTN_MASK)
 
#define TSI_CNTR7_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR7_CNTN1_SHIFT   16
 
#define TSI_CNTR7_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CNTN1_SHIFT))&TSI_CNTR7_CNTN1_MASK)
 
#define TSI_CNTR9_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR9_CNTN_SHIFT   0
 
#define TSI_CNTR9_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CNTN_SHIFT))&TSI_CNTR9_CNTN_MASK)
 
#define TSI_CNTR9_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR9_CNTN1_SHIFT   16
 
#define TSI_CNTR9_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CNTN1_SHIFT))&TSI_CNTR9_CNTN1_MASK)
 
#define TSI_CNTR11_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR11_CNTN_SHIFT   0
 
#define TSI_CNTR11_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CNTN_SHIFT))&TSI_CNTR11_CNTN_MASK)
 
#define TSI_CNTR11_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR11_CNTN1_SHIFT   16
 
#define TSI_CNTR11_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CNTN1_SHIFT))&TSI_CNTR11_CNTN1_MASK)
 
#define TSI_CNTR13_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR13_CNTN_SHIFT   0
 
#define TSI_CNTR13_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CNTN_SHIFT))&TSI_CNTR13_CNTN_MASK)
 
#define TSI_CNTR13_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR13_CNTN1_SHIFT   16
 
#define TSI_CNTR13_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CNTN1_SHIFT))&TSI_CNTR13_CNTN1_MASK)
 
#define TSI_CNTR15_CNTN_MASK   0xFFFFu
 
#define TSI_CNTR15_CNTN_SHIFT   0
 
#define TSI_CNTR15_CNTN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CNTN_SHIFT))&TSI_CNTR15_CNTN_MASK)
 
#define TSI_CNTR15_CNTN1_MASK   0xFFFF0000u
 
#define TSI_CNTR15_CNTN1_SHIFT   16
 
#define TSI_CNTR15_CNTN1(x)   (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CNTN1_SHIFT))&TSI_CNTR15_CNTN1_MASK)
 
#define TSI_THRESHLD_HTHH_MASK   0xFFFFu
 
#define TSI_THRESHLD_HTHH_SHIFT   0
 
#define TSI_THRESHLD_HTHH(x)   (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_HTHH_SHIFT))&TSI_THRESHLD_HTHH_MASK)
 
#define TSI_THRESHLD_LTHH_MASK   0xFFFF0000u
 
#define TSI_THRESHLD_LTHH_SHIFT   16
 
#define TSI_THRESHLD_LTHH(x)   (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_LTHH_SHIFT))&TSI_THRESHLD_LTHH_MASK)
 

GENCS - TSI General Control and Status Register

#define TSI_GENCS_STPE_MASK   (0x1U)
 
#define TSI_GENCS_STPE_SHIFT   (0U)
 
#define TSI_GENCS_STPE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
 
#define TSI_GENCS_STM_MASK   (0x2U)
 
#define TSI_GENCS_STM_SHIFT   (1U)
 
#define TSI_GENCS_STM(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
 
#define TSI_GENCS_ESOR_MASK   (0x10U)
 
#define TSI_GENCS_ESOR_SHIFT   (4U)
 
#define TSI_GENCS_ESOR(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
 
#define TSI_GENCS_TSIEN_MASK   (0x80U)
 
#define TSI_GENCS_TSIEN_SHIFT   (7U)
 
#define TSI_GENCS_TSIEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
 
#define TSI_GENCS_SCNIP_MASK   (0x200U)
 
#define TSI_GENCS_SCNIP_SHIFT   (9U)
 
#define TSI_GENCS_SCNIP(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
 
#define TSI_GENCS_OUTRGF_MASK   (0x4000U)
 
#define TSI_GENCS_OUTRGF_SHIFT   (14U)
 
#define TSI_GENCS_OUTRGF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
 
#define TSI_GENCS_EOSF_MASK   (0x8000U)
 
#define TSI_GENCS_EOSF_SHIFT   (15U)
 
#define TSI_GENCS_EOSF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
 
#define TSI_GENCS_PS_MASK   (0x70000U)
 
#define TSI_GENCS_PS_SHIFT   (16U)
 
#define TSI_GENCS_PS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
 
#define TSI_GENCS_NSCN_MASK   (0xF80000U)
 
#define TSI_GENCS_NSCN_SHIFT   (19U)
 
#define TSI_GENCS_NSCN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
 
#define TSI_GENCS_STPE_MASK   0x1u
 
#define TSI_GENCS_STPE_SHIFT   0
 
#define TSI_GENCS_STM_MASK   0x2u
 
#define TSI_GENCS_STM_SHIFT   1
 
#define TSI_GENCS_ESOR_MASK   0x10u
 
#define TSI_GENCS_ESOR_SHIFT   4
 
#define TSI_GENCS_TSIEN_MASK   0x80u
 
#define TSI_GENCS_TSIEN_SHIFT   7
 
#define TSI_GENCS_SCNIP_MASK   0x200u
 
#define TSI_GENCS_SCNIP_SHIFT   9
 
#define TSI_GENCS_OUTRGF_MASK   0x4000u
 
#define TSI_GENCS_OUTRGF_SHIFT   14
 
#define TSI_GENCS_EOSF_MASK   0x8000u
 
#define TSI_GENCS_EOSF_SHIFT   15
 
#define TSI_GENCS_PS_MASK   0x70000u
 
#define TSI_GENCS_PS_SHIFT   16
 
#define TSI_GENCS_PS(x)   (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
 
#define TSI_GENCS_NSCN_MASK   0xF80000u
 
#define TSI_GENCS_NSCN_SHIFT   19
 
#define TSI_GENCS_NSCN(x)   (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
 
#define TSI_GENCS_EOSDMEO_MASK   (0x1U)
 
#define TSI_GENCS_EOSDMEO_SHIFT   (0U)
 
#define TSI_GENCS_EOSDMEO(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
 
#define TSI_GENCS_CURSW_MASK   (0x2U)
 
#define TSI_GENCS_CURSW_SHIFT   (1U)
 
#define TSI_GENCS_CURSW(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
 
#define TSI_GENCS_EOSF_MASK   (0x4U)
 
#define TSI_GENCS_EOSF_SHIFT   (2U)
 
#define TSI_GENCS_EOSF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
 
#define TSI_GENCS_SCNIP_MASK   (0x8U)
 
#define TSI_GENCS_SCNIP_SHIFT   (3U)
 
#define TSI_GENCS_SCNIP(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
 
#define TSI_GENCS_STM_MASK   (0x10U)
 
#define TSI_GENCS_STM_SHIFT   (4U)
 
#define TSI_GENCS_STM(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
 
#define TSI_GENCS_STPE_MASK   (0x20U)
 
#define TSI_GENCS_STPE_SHIFT   (5U)
 
#define TSI_GENCS_STPE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
 
#define TSI_GENCS_TSIIEN_MASK   (0x40U)
 
#define TSI_GENCS_TSIIEN_SHIFT   (6U)
 
#define TSI_GENCS_TSIIEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
 
#define TSI_GENCS_TSIEN_MASK   (0x80U)
 
#define TSI_GENCS_TSIEN_SHIFT   (7U)
 
#define TSI_GENCS_TSIEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
 
#define TSI_GENCS_NSCN_MASK   (0x1F00U)
 
#define TSI_GENCS_NSCN_SHIFT   (8U)
 
#define TSI_GENCS_NSCN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
 
#define TSI_GENCS_PS_MASK   (0xE000U)
 
#define TSI_GENCS_PS_SHIFT   (13U)
 
#define TSI_GENCS_PS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
 
#define TSI_GENCS_EXTCHRG_MASK   (0x70000U)
 
#define TSI_GENCS_EXTCHRG_SHIFT   (16U)
 
#define TSI_GENCS_EXTCHRG(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
 
#define TSI_GENCS_DVOLT_MASK   (0x180000U)
 
#define TSI_GENCS_DVOLT_SHIFT   (19U)
 
#define TSI_GENCS_DVOLT(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
 
#define TSI_GENCS_REFCHRG_MASK   (0xE00000U)
 
#define TSI_GENCS_REFCHRG_SHIFT   (21U)
 
#define TSI_GENCS_REFCHRG(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
 
#define TSI_GENCS_MODE_MASK   (0xF000000U)
 
#define TSI_GENCS_MODE_SHIFT   (24U)
 
#define TSI_GENCS_MODE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
 
#define TSI_GENCS_ESOR_MASK   (0x10000000U)
 
#define TSI_GENCS_ESOR_SHIFT   (28U)
 
#define TSI_GENCS_ESOR(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
 
#define TSI_GENCS_OUTRGF_MASK   (0x80000000U)
 
#define TSI_GENCS_OUTRGF_SHIFT   (31U)
 
#define TSI_GENCS_OUTRGF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
 
#define TSI_GENCS_EOSDMEO_MASK   (0x1U)
 
#define TSI_GENCS_EOSDMEO_SHIFT   (0U)
 
#define TSI_GENCS_EOSDMEO(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
 
#define TSI_GENCS_CURSW_MASK   (0x2U)
 
#define TSI_GENCS_CURSW_SHIFT   (1U)
 
#define TSI_GENCS_CURSW(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
 
#define TSI_GENCS_EOSF_MASK   (0x4U)
 
#define TSI_GENCS_EOSF_SHIFT   (2U)
 
#define TSI_GENCS_EOSF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
 
#define TSI_GENCS_SCNIP_MASK   (0x8U)
 
#define TSI_GENCS_SCNIP_SHIFT   (3U)
 
#define TSI_GENCS_SCNIP(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
 
#define TSI_GENCS_STM_MASK   (0x10U)
 
#define TSI_GENCS_STM_SHIFT   (4U)
 
#define TSI_GENCS_STM(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
 
#define TSI_GENCS_STPE_MASK   (0x20U)
 
#define TSI_GENCS_STPE_SHIFT   (5U)
 
#define TSI_GENCS_STPE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
 
#define TSI_GENCS_TSIIEN_MASK   (0x40U)
 
#define TSI_GENCS_TSIIEN_SHIFT   (6U)
 
#define TSI_GENCS_TSIIEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
 
#define TSI_GENCS_TSIEN_MASK   (0x80U)
 
#define TSI_GENCS_TSIEN_SHIFT   (7U)
 
#define TSI_GENCS_TSIEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
 
#define TSI_GENCS_NSCN_MASK   (0x1F00U)
 
#define TSI_GENCS_NSCN_SHIFT   (8U)
 
#define TSI_GENCS_NSCN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
 
#define TSI_GENCS_PS_MASK   (0xE000U)
 
#define TSI_GENCS_PS_SHIFT   (13U)
 
#define TSI_GENCS_PS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
 
#define TSI_GENCS_EXTCHRG_MASK   (0x70000U)
 
#define TSI_GENCS_EXTCHRG_SHIFT   (16U)
 
#define TSI_GENCS_EXTCHRG(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
 
#define TSI_GENCS_DVOLT_MASK   (0x180000U)
 
#define TSI_GENCS_DVOLT_SHIFT   (19U)
 
#define TSI_GENCS_DVOLT(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
 
#define TSI_GENCS_REFCHRG_MASK   (0xE00000U)
 
#define TSI_GENCS_REFCHRG_SHIFT   (21U)
 
#define TSI_GENCS_REFCHRG(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
 
#define TSI_GENCS_MODE_MASK   (0xF000000U)
 
#define TSI_GENCS_MODE_SHIFT   (24U)
 
#define TSI_GENCS_MODE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
 
#define TSI_GENCS_ESOR_MASK   (0x10000000U)
 
#define TSI_GENCS_ESOR_SHIFT   (28U)
 
#define TSI_GENCS_ESOR(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
 
#define TSI_GENCS_OUTRGF_MASK   (0x80000000U)
 
#define TSI_GENCS_OUTRGF_SHIFT   (31U)
 
#define TSI_GENCS_OUTRGF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
 

GENCS - General Control and Status register

#define TSI_GENCS_ERIE_MASK   (0x20U)
 
#define TSI_GENCS_ERIE_SHIFT   (5U)
 
#define TSI_GENCS_ERIE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ERIE_SHIFT)) & TSI_GENCS_ERIE_MASK)
 
#define TSI_GENCS_TSIIE_MASK   (0x40U)
 
#define TSI_GENCS_TSIIE_SHIFT   (6U)
 
#define TSI_GENCS_TSIIE(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIE_SHIFT)) & TSI_GENCS_TSIIE_MASK)
 
#define TSI_GENCS_SWTS_MASK   (0x100U)
 
#define TSI_GENCS_SWTS_SHIFT   (8U)
 
#define TSI_GENCS_SWTS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK)
 
#define TSI_GENCS_OVRF_MASK   (0x1000U)
 
#define TSI_GENCS_OVRF_SHIFT   (12U)
 
#define TSI_GENCS_OVRF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OVRF_SHIFT)) & TSI_GENCS_OVRF_MASK)
 
#define TSI_GENCS_EXTERF_MASK   (0x2000U)
 
#define TSI_GENCS_EXTERF_SHIFT   (13U)
 
#define TSI_GENCS_EXTERF(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTERF_SHIFT)) & TSI_GENCS_EXTERF_MASK)
 
#define TSI_GENCS_LPSCNITV_MASK   (0xF000000U)
 
#define TSI_GENCS_LPSCNITV_SHIFT   (24U)
 
#define TSI_GENCS_LPSCNITV(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPSCNITV_SHIFT)) & TSI_GENCS_LPSCNITV_MASK)
 
#define TSI_GENCS_LPCLKS_MASK   (0x10000000U)
 
#define TSI_GENCS_LPCLKS_SHIFT   (28U)
 
#define TSI_GENCS_LPCLKS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPCLKS_SHIFT)) & TSI_GENCS_LPCLKS_MASK)
 

SCANC - SCAN Control register

#define TSI_SCANC_AMPSC_MASK   (0x7U)
 
#define TSI_SCANC_AMPSC_SHIFT   (0U)
 
#define TSI_SCANC_AMPSC(x)   (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMPSC_SHIFT)) & TSI_SCANC_AMPSC_MASK)
 
#define TSI_SCANC_AMCLKS_MASK   (0x18U)
 
#define TSI_SCANC_AMCLKS_SHIFT   (3U)
 
#define TSI_SCANC_AMCLKS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMCLKS_SHIFT)) & TSI_SCANC_AMCLKS_MASK)
 
#define TSI_SCANC_SMOD_MASK   (0xFF00U)
 
#define TSI_SCANC_SMOD_SHIFT   (8U)
 
#define TSI_SCANC_SMOD(x)   (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_SMOD_SHIFT)) & TSI_SCANC_SMOD_MASK)
 
#define TSI_SCANC_EXTCHRG_MASK   (0xF0000U)
 
#define TSI_SCANC_EXTCHRG_SHIFT   (16U)
 
#define TSI_SCANC_EXTCHRG(x)   (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_EXTCHRG_SHIFT)) & TSI_SCANC_EXTCHRG_MASK)
 
#define TSI_SCANC_REFCHRG_MASK   (0xF000000U)
 
#define TSI_SCANC_REFCHRG_SHIFT   (24U)
 
#define TSI_SCANC_REFCHRG(x)   (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_REFCHRG_SHIFT)) & TSI_SCANC_REFCHRG_MASK)
 

PEN - Pin Enable register

#define TSI_PEN_PEN0_MASK   (0x1U)
 
#define TSI_PEN_PEN0_SHIFT   (0U)
 
#define TSI_PEN_PEN0(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN0_SHIFT)) & TSI_PEN_PEN0_MASK)
 
#define TSI_PEN_PEN1_MASK   (0x2U)
 
#define TSI_PEN_PEN1_SHIFT   (1U)
 
#define TSI_PEN_PEN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN1_SHIFT)) & TSI_PEN_PEN1_MASK)
 
#define TSI_PEN_PEN2_MASK   (0x4U)
 
#define TSI_PEN_PEN2_SHIFT   (2U)
 
#define TSI_PEN_PEN2(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN2_SHIFT)) & TSI_PEN_PEN2_MASK)
 
#define TSI_PEN_PEN3_MASK   (0x8U)
 
#define TSI_PEN_PEN3_SHIFT   (3U)
 
#define TSI_PEN_PEN3(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN3_SHIFT)) & TSI_PEN_PEN3_MASK)
 
#define TSI_PEN_PEN4_MASK   (0x10U)
 
#define TSI_PEN_PEN4_SHIFT   (4U)
 
#define TSI_PEN_PEN4(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN4_SHIFT)) & TSI_PEN_PEN4_MASK)
 
#define TSI_PEN_PEN5_MASK   (0x20U)
 
#define TSI_PEN_PEN5_SHIFT   (5U)
 
#define TSI_PEN_PEN5(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN5_SHIFT)) & TSI_PEN_PEN5_MASK)
 
#define TSI_PEN_PEN6_MASK   (0x40U)
 
#define TSI_PEN_PEN6_SHIFT   (6U)
 
#define TSI_PEN_PEN6(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN6_SHIFT)) & TSI_PEN_PEN6_MASK)
 
#define TSI_PEN_PEN7_MASK   (0x80U)
 
#define TSI_PEN_PEN7_SHIFT   (7U)
 
#define TSI_PEN_PEN7(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN7_SHIFT)) & TSI_PEN_PEN7_MASK)
 
#define TSI_PEN_PEN8_MASK   (0x100U)
 
#define TSI_PEN_PEN8_SHIFT   (8U)
 
#define TSI_PEN_PEN8(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN8_SHIFT)) & TSI_PEN_PEN8_MASK)
 
#define TSI_PEN_PEN9_MASK   (0x200U)
 
#define TSI_PEN_PEN9_SHIFT   (9U)
 
#define TSI_PEN_PEN9(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN9_SHIFT)) & TSI_PEN_PEN9_MASK)
 
#define TSI_PEN_PEN10_MASK   (0x400U)
 
#define TSI_PEN_PEN10_SHIFT   (10U)
 
#define TSI_PEN_PEN10(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN10_SHIFT)) & TSI_PEN_PEN10_MASK)
 
#define TSI_PEN_PEN11_MASK   (0x800U)
 
#define TSI_PEN_PEN11_SHIFT   (11U)
 
#define TSI_PEN_PEN11(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN11_SHIFT)) & TSI_PEN_PEN11_MASK)
 
#define TSI_PEN_PEN12_MASK   (0x1000U)
 
#define TSI_PEN_PEN12_SHIFT   (12U)
 
#define TSI_PEN_PEN12(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN12_SHIFT)) & TSI_PEN_PEN12_MASK)
 
#define TSI_PEN_PEN13_MASK   (0x2000U)
 
#define TSI_PEN_PEN13_SHIFT   (13U)
 
#define TSI_PEN_PEN13(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN13_SHIFT)) & TSI_PEN_PEN13_MASK)
 
#define TSI_PEN_PEN14_MASK   (0x4000U)
 
#define TSI_PEN_PEN14_SHIFT   (14U)
 
#define TSI_PEN_PEN14(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN14_SHIFT)) & TSI_PEN_PEN14_MASK)
 
#define TSI_PEN_PEN15_MASK   (0x8000U)
 
#define TSI_PEN_PEN15_SHIFT   (15U)
 
#define TSI_PEN_PEN15(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN15_SHIFT)) & TSI_PEN_PEN15_MASK)
 
#define TSI_PEN_LPSP_MASK   (0xF0000U)
 
#define TSI_PEN_LPSP_SHIFT   (16U)
 
#define TSI_PEN_LPSP(x)   (((uint32_t)(((uint32_t)(x)) << TSI_PEN_LPSP_SHIFT)) & TSI_PEN_LPSP_MASK)
 

WUCNTR - Wake-Up Channel Counter Register

#define TSI_WUCNTR_WUCNT_MASK   (0xFFFFU)
 
#define TSI_WUCNTR_WUCNT_SHIFT   (0U)
 
#define TSI_WUCNTR_WUCNT(x)   (((uint32_t)(((uint32_t)(x)) << TSI_WUCNTR_WUCNT_SHIFT)) & TSI_WUCNTR_WUCNT_MASK)
 

CNTR1 - Counter Register

#define TSI_CNTR1_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR1_CTN1_SHIFT   (0U)
 
#define TSI_CNTR1_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN1_SHIFT)) & TSI_CNTR1_CTN1_MASK)
 
#define TSI_CNTR1_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR1_CTN_SHIFT   (16U)
 
#define TSI_CNTR1_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN_SHIFT)) & TSI_CNTR1_CTN_MASK)
 

CNTR3 - Counter Register

#define TSI_CNTR3_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR3_CTN1_SHIFT   (0U)
 
#define TSI_CNTR3_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN1_SHIFT)) & TSI_CNTR3_CTN1_MASK)
 
#define TSI_CNTR3_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR3_CTN_SHIFT   (16U)
 
#define TSI_CNTR3_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN_SHIFT)) & TSI_CNTR3_CTN_MASK)
 

CNTR5 - Counter Register

#define TSI_CNTR5_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR5_CTN1_SHIFT   (0U)
 
#define TSI_CNTR5_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN1_SHIFT)) & TSI_CNTR5_CTN1_MASK)
 
#define TSI_CNTR5_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR5_CTN_SHIFT   (16U)
 
#define TSI_CNTR5_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN_SHIFT)) & TSI_CNTR5_CTN_MASK)
 

CNTR7 - Counter Register

#define TSI_CNTR7_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR7_CTN1_SHIFT   (0U)
 
#define TSI_CNTR7_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN1_SHIFT)) & TSI_CNTR7_CTN1_MASK)
 
#define TSI_CNTR7_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR7_CTN_SHIFT   (16U)
 
#define TSI_CNTR7_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN_SHIFT)) & TSI_CNTR7_CTN_MASK)
 

CNTR9 - Counter Register

#define TSI_CNTR9_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR9_CTN1_SHIFT   (0U)
 
#define TSI_CNTR9_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN1_SHIFT)) & TSI_CNTR9_CTN1_MASK)
 
#define TSI_CNTR9_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR9_CTN_SHIFT   (16U)
 
#define TSI_CNTR9_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN_SHIFT)) & TSI_CNTR9_CTN_MASK)
 

CNTR11 - Counter Register

#define TSI_CNTR11_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR11_CTN1_SHIFT   (0U)
 
#define TSI_CNTR11_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN1_SHIFT)) & TSI_CNTR11_CTN1_MASK)
 
#define TSI_CNTR11_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR11_CTN_SHIFT   (16U)
 
#define TSI_CNTR11_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN_SHIFT)) & TSI_CNTR11_CTN_MASK)
 

CNTR13 - Counter Register

#define TSI_CNTR13_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR13_CTN1_SHIFT   (0U)
 
#define TSI_CNTR13_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN1_SHIFT)) & TSI_CNTR13_CTN1_MASK)
 
#define TSI_CNTR13_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR13_CTN_SHIFT   (16U)
 
#define TSI_CNTR13_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN_SHIFT)) & TSI_CNTR13_CTN_MASK)
 

CNTR15 - Counter Register

#define TSI_CNTR15_CTN1_MASK   (0xFFFFU)
 
#define TSI_CNTR15_CTN1_SHIFT   (0U)
 
#define TSI_CNTR15_CTN1(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN1_SHIFT)) & TSI_CNTR15_CTN1_MASK)
 
#define TSI_CNTR15_CTN_MASK   (0xFFFF0000U)
 
#define TSI_CNTR15_CTN_SHIFT   (16U)
 
#define TSI_CNTR15_CTN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN_SHIFT)) & TSI_CNTR15_CTN_MASK)
 

THRESHOLD - Low-Power Channel Threshold register

#define TSI_THRESHOLD_HTHH_MASK   (0xFFFFU)
 
#define TSI_THRESHOLD_HTHH_SHIFT   (0U)
 
#define TSI_THRESHOLD_HTHH(x)   (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_HTHH_SHIFT)) & TSI_THRESHOLD_HTHH_MASK)
 
#define TSI_THRESHOLD_LTHH_MASK   (0xFFFF0000U)
 
#define TSI_THRESHOLD_LTHH_SHIFT   (16U)
 
#define TSI_THRESHOLD_LTHH(x)   (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_LTHH_SHIFT)) & TSI_THRESHOLD_LTHH_MASK)
 

DATA - TSI DATA Register

#define TSI_DATA_TSICNT_MASK   (0xFFFFU)
 
#define TSI_DATA_TSICNT_SHIFT   (0U)
 
#define TSI_DATA_TSICNT(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
 
#define TSI_DATA_SWTS_MASK   (0x400000U)
 
#define TSI_DATA_SWTS_SHIFT   (22U)
 
#define TSI_DATA_SWTS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
 
#define TSI_DATA_DMAEN_MASK   (0x800000U)
 
#define TSI_DATA_DMAEN_SHIFT   (23U)
 
#define TSI_DATA_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
 
#define TSI_DATA_TSICH_MASK   (0xF0000000U)
 
#define TSI_DATA_TSICH_SHIFT   (28U)
 
#define TSI_DATA_TSICH(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
 
#define TSI_DATA_TSICNT_MASK   (0xFFFFU)
 
#define TSI_DATA_TSICNT_SHIFT   (0U)
 
#define TSI_DATA_TSICNT(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
 
#define TSI_DATA_SWTS_MASK   (0x400000U)
 
#define TSI_DATA_SWTS_SHIFT   (22U)
 
#define TSI_DATA_SWTS(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
 
#define TSI_DATA_DMAEN_MASK   (0x800000U)
 
#define TSI_DATA_DMAEN_SHIFT   (23U)
 
#define TSI_DATA_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
 
#define TSI_DATA_TSICH_MASK   (0xF0000000U)
 
#define TSI_DATA_TSICH_SHIFT   (28U)
 
#define TSI_DATA_TSICH(x)   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
 

TSHD - TSI Threshold Register

#define TSI_TSHD_THRESL_MASK   (0xFFFFU)
 
#define TSI_TSHD_THRESL_SHIFT   (0U)
 
#define TSI_TSHD_THRESL(x)   (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
 
#define TSI_TSHD_THRESH_MASK   (0xFFFF0000U)
 
#define TSI_TSHD_THRESH_SHIFT   (16U)
 
#define TSI_TSHD_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
 
#define TSI_TSHD_THRESL_MASK   (0xFFFFU)
 
#define TSI_TSHD_THRESL_SHIFT   (0U)
 
#define TSI_TSHD_THRESL(x)   (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
 
#define TSI_TSHD_THRESH_MASK   (0xFFFF0000U)
 
#define TSI_TSHD_THRESH_SHIFT   (16U)
 
#define TSI_TSHD_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
 

Macro Definition Documentation

◆ TSI0

#define TSI0   ((TSI_Type *)TSI0_BASE)

Peripheral TSI0 base pointer

◆ TSI0_BASE

#define TSI0_BASE   (0x40045000u)

Peripheral TSI0 base address

◆ TSI_BASE_ADDRS

#define TSI_BASE_ADDRS   { TSI0_BASE }

Array initializer of TSI peripheral base addresses

◆ TSI_BASE_PTRS

#define TSI_BASE_PTRS   { TSI0 }

Array initializer of TSI peripheral base pointers

◆ TSI_DATA_DMAEN [1/2]

#define TSI_DATA_DMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)

DMAEN - DMA Transfer Enabled 0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. 0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.

◆ TSI_DATA_DMAEN [2/2]

#define TSI_DATA_DMAEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)

DMAEN - DMA Transfer Enabled 0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. 0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.

◆ TSI_DATA_SWTS [1/2]

#define TSI_DATA_SWTS ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)

SWTS - Software Trigger Start 0b0..No effect. 0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH].

◆ TSI_DATA_SWTS [2/2]

#define TSI_DATA_SWTS ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)

SWTS - Software Trigger Start 0b0..No effect. 0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH].

◆ TSI_DATA_TSICH [1/2]

#define TSI_DATA_TSICH ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)

TSICH - TSICH 0b0000..Channel 0. 0b0001..Channel 1. 0b0010..Channel 2. 0b0011..Channel 3. 0b0100..Channel 4. 0b0101..Channel 5. 0b0110..Channel 6. 0b0111..Channel 7. 0b1000..Channel 8. 0b1001..Channel 9. 0b1010..Channel 10. 0b1011..Channel 11. 0b1100..Channel 12. 0b1101..Channel 13. 0b1110..Channel 14. 0b1111..Channel 15.

◆ TSI_DATA_TSICH [2/2]

#define TSI_DATA_TSICH ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)

TSICH - TSICH 0b0000..Channel 0. 0b0001..Channel 1. 0b0010..Channel 2. 0b0011..Channel 3. 0b0100..Channel 4. 0b0101..Channel 5. 0b0110..Channel 6. 0b0111..Channel 7. 0b1000..Channel 8. 0b1001..Channel 9. 0b1010..Channel 10. 0b1011..Channel 11. 0b1100..Channel 12. 0b1101..Channel 13. 0b1110..Channel 14. 0b1111..Channel 15.

◆ TSI_GENCS_CURSW [1/2]

#define TSI_GENCS_CURSW ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)

CURSW - CURSW 0b0..The current source pair are not swapped. 0b1..The current source pair are swapped.

◆ TSI_GENCS_CURSW [2/2]

#define TSI_GENCS_CURSW ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)

CURSW - CURSW 0b0..The current source pair are not swapped. 0b1..The current source pair are swapped.

◆ TSI_GENCS_DVOLT [1/2]

#define TSI_GENCS_DVOLT ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)

DVOLT - DVOLT 0b00..DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V. 0b01..DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V. 0b10..DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V. 0b11..DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.

◆ TSI_GENCS_DVOLT [2/2]

#define TSI_GENCS_DVOLT ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)

DVOLT - DVOLT 0b00..DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V. 0b01..DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V. 0b10..DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V. 0b11..DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.

◆ TSI_GENCS_EOSDMEO [1/2]

#define TSI_GENCS_EOSDMEO ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)

EOSDMEO - End-of-Scan DMA Transfer Request Enable Only 0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt. 0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.

◆ TSI_GENCS_EOSDMEO [2/2]

#define TSI_GENCS_EOSDMEO ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)

EOSDMEO - End-of-Scan DMA Transfer Request Enable Only 0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt. 0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.

◆ TSI_GENCS_EOSF [1/3]

#define TSI_GENCS_EOSF ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)

EOSF - End of Scan Flag 0b0..Scan not complete. 0b1..Scan complete.

◆ TSI_GENCS_EOSF [2/3]

#define TSI_GENCS_EOSF ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)

EOSF - End of Scan Flag 0b0..Scan not complete. 0b1..Scan complete.

◆ TSI_GENCS_EOSF [3/3]

#define TSI_GENCS_EOSF ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)

EOSF - End of Scan Flag 0b0..Scan not complete. 0b1..Scan complete.

◆ TSI_GENCS_ESOR [1/3]

#define TSI_GENCS_ESOR ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)

ESOR - End-of-scan or Out-of-Range Interrupt Selection 0b0..Out-of-range interrupt is allowed. 0b1..End-of-scan interrupt is allowed.

◆ TSI_GENCS_ESOR [2/3]

#define TSI_GENCS_ESOR ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)

ESOR - End-of-scan or Out-of-Range Interrupt Selection 0b0..Out-of-range interrupt is allowed. 0b1..End-of-scan interrupt is allowed.

◆ TSI_GENCS_ESOR [3/3]

#define TSI_GENCS_ESOR ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)

ESOR - End-of-scan or Out-of-Range Interrupt Selection 0b0..Out-of-range interrupt is allowed. 0b1..End-of-scan interrupt is allowed.

◆ TSI_GENCS_EXTCHRG [1/2]

#define TSI_GENCS_EXTCHRG ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)

EXTCHRG - EXTCHRG 0b000..500 nA. 0b001..1 uA. 0b010..2 uA. 0b011..4 uA. 0b100..8 uA. 0b101..16 uA. 0b110..32 uA. 0b111..64 uA.

◆ TSI_GENCS_EXTCHRG [2/2]

#define TSI_GENCS_EXTCHRG ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)

EXTCHRG - EXTCHRG 0b000..500 nA. 0b001..1 uA. 0b010..2 uA. 0b011..4 uA. 0b100..8 uA. 0b101..16 uA. 0b110..32 uA. 0b111..64 uA.

◆ TSI_GENCS_MODE [1/2]

#define TSI_GENCS_MODE ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)

MODE - TSI analog modes setup and status bits. 0b0000..Set TSI in capacitive sensing(non-noise detection) mode. 0b0100..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. 0b1000..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. 0b1100..Set TSI analog to work in automatic noise detection mode.

◆ TSI_GENCS_MODE [2/2]

#define TSI_GENCS_MODE ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)

MODE - TSI analog modes setup and status bits. 0b0000..Set TSI in capacitive sensing(non-noise detection) mode. 0b0100..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. 0b1000..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. 0b1100..Set TSI analog to work in automatic noise detection mode.

◆ TSI_GENCS_NSCN [1/4]

#define TSI_GENCS_NSCN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)

NSCN - NSCN 0b00000..Once per electrode 0b00001..Twice per electrode 0b00010..3 times per electrode 0b00011..4 times per electrode 0b00100..5 times per electrode 0b00101..6 times per electrode 0b00110..7 times per electrode 0b00111..8 times per electrode 0b01000..9 times per electrode 0b01001..10 times per electrode 0b01010..11 times per electrode 0b01011..12 times per electrode 0b01100..13 times per electrode 0b01101..14 times per electrode 0b01110..15 times per electrode 0b01111..16 times per electrode 0b10000..17 times per electrode 0b10001..18 times per electrode 0b10010..19 times per electrode 0b10011..20 times per electrode 0b10100..21 times per electrode 0b10101..22 times per electrode 0b10110..23 times per electrode 0b10111..24 times per electrode 0b11000..25 times per electrode 0b11001..26 times per electrode 0b11010..27 times per electrode 0b11011..28 times per electrode 0b11100..29 times per electrode 0b11101..30 times per electrode 0b11110..31 times per electrode 0b11111..32 times per electrode

◆ TSI_GENCS_NSCN [2/4]

#define TSI_GENCS_NSCN ( x)    (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)

NSCN - NSCN 0b00000..Once per electrode 0b00001..Twice per electrode 0b00010..3 times per electrode 0b00011..4 times per electrode 0b00100..5 times per electrode 0b00101..6 times per electrode 0b00110..7 times per electrode 0b00111..8 times per electrode 0b01000..9 times per electrode 0b01001..10 times per electrode 0b01010..11 times per electrode 0b01011..12 times per electrode 0b01100..13 times per electrode 0b01101..14 times per electrode 0b01110..15 times per electrode 0b01111..16 times per electrode 0b10000..17 times per electrode 0b10001..18 times per electrode 0b10010..19 times per electrode 0b10011..20 times per electrode 0b10100..21 times per electrode 0b10101..22 times per electrode 0b10110..23 times per electrode 0b10111..24 times per electrode 0b11000..25 times per electrode 0b11001..26 times per electrode 0b11010..27 times per electrode 0b11011..28 times per electrode 0b11100..29 times per electrode 0b11101..30 times per electrode 0b11110..31 times per electrode 0b11111..32 times per electrode

◆ TSI_GENCS_NSCN [3/4]

#define TSI_GENCS_NSCN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)

NSCN - NSCN 0b00000..Once per electrode 0b00001..Twice per electrode 0b00010..3 times per electrode 0b00011..4 times per electrode 0b00100..5 times per electrode 0b00101..6 times per electrode 0b00110..7 times per electrode 0b00111..8 times per electrode 0b01000..9 times per electrode 0b01001..10 times per electrode 0b01010..11 times per electrode 0b01011..12 times per electrode 0b01100..13 times per electrode 0b01101..14 times per electrode 0b01110..15 times per electrode 0b01111..16 times per electrode 0b10000..17 times per electrode 0b10001..18 times per electrode 0b10010..19 times per electrode 0b10011..20 times per electrode 0b10100..21 times per electrode 0b10101..22 times per electrode 0b10110..23 times per electrode 0b10111..24 times per electrode 0b11000..25 times per electrode 0b11001..26 times per electrode 0b11010..27 times per electrode 0b11011..28 times per electrode 0b11100..29 times per electrode 0b11101..30 times per electrode 0b11110..31 times per electrode 0b11111..32 times per electrode

◆ TSI_GENCS_NSCN [4/4]

#define TSI_GENCS_NSCN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)

NSCN - NSCN 0b00000..Once per electrode 0b00001..Twice per electrode 0b00010..3 times per electrode 0b00011..4 times per electrode 0b00100..5 times per electrode 0b00101..6 times per electrode 0b00110..7 times per electrode 0b00111..8 times per electrode 0b01000..9 times per electrode 0b01001..10 times per electrode 0b01010..11 times per electrode 0b01011..12 times per electrode 0b01100..13 times per electrode 0b01101..14 times per electrode 0b01110..15 times per electrode 0b01111..16 times per electrode 0b10000..17 times per electrode 0b10001..18 times per electrode 0b10010..19 times per electrode 0b10011..20 times per electrode 0b10100..21 times per electrode 0b10101..22 times per electrode 0b10110..23 times per electrode 0b10111..24 times per electrode 0b11000..25 times per electrode 0b11001..26 times per electrode 0b11010..27 times per electrode 0b11011..28 times per electrode 0b11100..29 times per electrode 0b11101..30 times per electrode 0b11110..31 times per electrode 0b11111..32 times per electrode

◆ TSI_GENCS_PS [1/4]

#define TSI_GENCS_PS ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)

PS - PS 0b000..Electrode Oscillator Frequency divided by 1 0b001..Electrode Oscillator Frequency divided by 2 0b010..Electrode Oscillator Frequency divided by 4 0b011..Electrode Oscillator Frequency divided by 8 0b100..Electrode Oscillator Frequency divided by 16 0b101..Electrode Oscillator Frequency divided by 32 0b110..Electrode Oscillator Frequency divided by 64 0b111..Electrode Oscillator Frequency divided by 128

◆ TSI_GENCS_PS [2/4]

#define TSI_GENCS_PS ( x)    (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)

PS - PS 0b000..Electrode Oscillator Frequency divided by 1 0b001..Electrode Oscillator Frequency divided by 2 0b010..Electrode Oscillator Frequency divided by 4 0b011..Electrode Oscillator Frequency divided by 8 0b100..Electrode Oscillator Frequency divided by 16 0b101..Electrode Oscillator Frequency divided by 32 0b110..Electrode Oscillator Frequency divided by 64 0b111..Electrode Oscillator Frequency divided by 128

◆ TSI_GENCS_PS [3/4]

#define TSI_GENCS_PS ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)

PS - PS 0b000..Electrode Oscillator Frequency divided by 1 0b001..Electrode Oscillator Frequency divided by 2 0b010..Electrode Oscillator Frequency divided by 4 0b011..Electrode Oscillator Frequency divided by 8 0b100..Electrode Oscillator Frequency divided by 16 0b101..Electrode Oscillator Frequency divided by 32 0b110..Electrode Oscillator Frequency divided by 64 0b111..Electrode Oscillator Frequency divided by 128

◆ TSI_GENCS_PS [4/4]

#define TSI_GENCS_PS ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)

PS - PS 0b000..Electrode Oscillator Frequency divided by 1 0b001..Electrode Oscillator Frequency divided by 2 0b010..Electrode Oscillator Frequency divided by 4 0b011..Electrode Oscillator Frequency divided by 8 0b100..Electrode Oscillator Frequency divided by 16 0b101..Electrode Oscillator Frequency divided by 32 0b110..Electrode Oscillator Frequency divided by 64 0b111..Electrode Oscillator Frequency divided by 128

◆ TSI_GENCS_REFCHRG [1/2]

#define TSI_GENCS_REFCHRG ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)

REFCHRG - REFCHRG 0b000..500 nA. 0b001..1 uA. 0b010..2 uA. 0b011..4 uA. 0b100..8 uA. 0b101..16 uA. 0b110..32 uA. 0b111..64 uA.

◆ TSI_GENCS_REFCHRG [2/2]

#define TSI_GENCS_REFCHRG ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)

REFCHRG - REFCHRG 0b000..500 nA. 0b001..1 uA. 0b010..2 uA. 0b011..4 uA. 0b100..8 uA. 0b101..16 uA. 0b110..32 uA. 0b111..64 uA.

◆ TSI_GENCS_SCNIP [1/3]

#define TSI_GENCS_SCNIP ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)

SCNIP - Scan In Progress Status 0b0..No scan in progress. 0b1..Scan in progress.

◆ TSI_GENCS_SCNIP [2/3]

#define TSI_GENCS_SCNIP ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)

SCNIP - Scan In Progress Status 0b0..No scan in progress. 0b1..Scan in progress.

◆ TSI_GENCS_SCNIP [3/3]

#define TSI_GENCS_SCNIP ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)

SCNIP - Scan In Progress Status 0b0..No scan in progress. 0b1..Scan in progress.

◆ TSI_GENCS_STM [1/3]

#define TSI_GENCS_STM ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)

STM - Scan Trigger Mode 0b0..Software trigger scan. 0b1..Hardware trigger scan.

◆ TSI_GENCS_STM [2/3]

#define TSI_GENCS_STM ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)

STM - Scan Trigger Mode 0b0..Software trigger scan. 0b1..Hardware trigger scan.

◆ TSI_GENCS_STM [3/3]

#define TSI_GENCS_STM ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)

STM - Scan Trigger Mode 0b0..Software trigger scan. 0b1..Hardware trigger scan.

◆ TSI_GENCS_STPE [1/3]

#define TSI_GENCS_STPE ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)

STPE - TSI STOP Enable 0b0..TSI is disabled when MCU goes into low power mode. 0b1..Allows TSI to continue running in all low power modes.

◆ TSI_GENCS_STPE [2/3]

#define TSI_GENCS_STPE ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)

STPE - TSI STOP Enable 0b0..TSI is disabled when MCU goes into low power mode. 0b1..Allows TSI to continue running in all low power modes.

◆ TSI_GENCS_STPE [3/3]

#define TSI_GENCS_STPE ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)

STPE - TSI STOP Enable 0b0..TSI is disabled when MCU goes into low power mode. 0b1..Allows TSI to continue running in all low power modes.

◆ TSI_GENCS_TSIEN [1/3]

#define TSI_GENCS_TSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)

TSIEN - Touch Sensing Input Module Enable 0b0..TSI module disabled. 0b1..TSI module enabled.

◆ TSI_GENCS_TSIEN [2/3]

#define TSI_GENCS_TSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)

TSIEN - Touch Sensing Input Module Enable 0b0..TSI module disabled. 0b1..TSI module enabled.

◆ TSI_GENCS_TSIEN [3/3]

#define TSI_GENCS_TSIEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)

TSIEN - Touch Sensing Input Module Enable 0b0..TSI module disabled. 0b1..TSI module enabled.

◆ TSI_GENCS_TSIIEN [1/2]

#define TSI_GENCS_TSIIEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)

TSIIEN - Touch Sensing Input Interrupt Enable 0b0..TSI interrupt is disabled. 0b1..TSI interrupt is enabled.

◆ TSI_GENCS_TSIIEN [2/2]

#define TSI_GENCS_TSIIEN ( x)    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)

TSIIEN - Touch Sensing Input Interrupt Enable 0b0..TSI interrupt is disabled. 0b1..TSI interrupt is enabled.

◆ TSI_IRQS

#define TSI_IRQS   { TSI0_IRQn }

Interrupt vectors for the TSI peripheral type