mikroSDK Reference Manual
MK60D10.h
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1/*
2** ###################################################################
3** Processors: MK60DN256VLL10
4** MK60DN256VLQ10
5** MK60DN256VMC10
6** MK60DN256VMD10
7** MK60DN512VLL10
8** MK60DN512VLQ10
9** MK60DN512VMC10
10** MK60DN512VMD10
11** MK60DX256VLL10
12** MK60DX256VLQ10
13** MK60DX256VMC10
14** MK60DX256VMD10
15**
16** Compilers: Keil ARM C/C++ Compiler
17** Freescale C/C++ for Embedded ARM
18** GNU C Compiler
19** IAR ANSI C/C++ Compiler for ARM
20** MCUXpresso Compiler
21**
22** Reference manual: K60P144M100SF2V2RM Rev. 2, Jun 2012
23** Version: rev. 1.9, 2015-07-29
24** Build: b170112
25**
26** Abstract:
27** CMSIS Peripheral Access Layer for MK60D10
28**
29** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
30** Copyright 2016 - 2017 NXP
31** Redistribution and use in source and binary forms, with or without modification,
32** are permitted provided that the following conditions are met:
33**
34** o Redistributions of source code must retain the above copyright notice, this list
35** of conditions and the following disclaimer.
36**
37** o Redistributions in binary form must reproduce the above copyright notice, this
38** list of conditions and the following disclaimer in the documentation and/or
39** other materials provided with the distribution.
40**
41** o Neither the name of the copyright holder nor the names of its
42** contributors may be used to endorse or promote products derived from this
43** software without specific prior written permission.
44**
45** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
46** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
47** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
48** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
49** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
51** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
52** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
54** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55**
56** http: www.nxp.com
57** mail: support@nxp.com
58**
59** Revisions:
60** - rev. 1.0 (2012-01-03)
61** Initial version
62** - rev. 1.1 (2012-04-13)
63** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
64** Added new #define symbols <peripheralType>_BASE_PTRS.
65** - rev. 1.2 (2012-07-09)
66** UART0 - Fixed register definition - CEA709.1-B (LON) registers added.
67** - rev. 1.3 (2012-10-29)
68** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012
69** - rev. 1.4 (2013-04-05)
70** Changed start of doxygen comment.
71** - rev. 1.5 (2013-06-24)
72** NV_FOPT register - NMI_DIS bit added.
73** SPI - PCSIS bit group in MCR register updated.
74** - rev. 1.6 (2014-07-23)
75** Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
76** Predefined SystemInit() implementation updated:
77** - External clock sources available on TWR board used.
78** - Added 1 ms waiting loop after entering FLL engaged MCG mode.
79** - rev. 1.7 (2014-08-28)
80** Update of startup files - possibility to override DefaultISR added.
81** - rev. 1.8 (2014-10-14)
82** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0
83** - rev. 1.9 (2015-07-29)
84** Correction of backward compatibility.
85**
86** ###################################################################
87*/
88
98#ifndef _MK60D10_H_
99#define _MK60D10_H_
103#define MCU_MEM_MAP_VERSION 0x0100U
105#define MCU_MEM_MAP_VERSION_MINOR 0x0009U
106
115#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
124#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
125#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
134#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
143#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
144
145/* ----------------------------------------------------------------------------
146 -- Interrupt vector numbers
147 ---------------------------------------------------------------------------- */
148
155#define NUMBER_OF_INT_VECTORS 120
157typedef enum IRQn {
158 /* Auxiliary constants */
159 NotAvail_IRQn = -128,
161 /* Core interrupts */
162 NonMaskableInt_IRQn = -14,
163 HardFault_IRQn = -13,
164 MemoryManagement_IRQn = -12,
165 BusFault_IRQn = -11,
166 UsageFault_IRQn = -10,
167 SVCall_IRQn = -5,
168 DebugMonitor_IRQn = -4,
169 PendSV_IRQn = -2,
170 SysTick_IRQn = -1,
172 /* Device specific interrupts */
173 DMA0_IRQn = 0,
174 DMA1_IRQn = 1,
175 DMA2_IRQn = 2,
176 DMA3_IRQn = 3,
177 DMA4_IRQn = 4,
178 DMA5_IRQn = 5,
179 DMA6_IRQn = 6,
180 DMA7_IRQn = 7,
181 DMA8_IRQn = 8,
182 DMA9_IRQn = 9,
183 DMA10_IRQn = 10,
184 DMA11_IRQn = 11,
185 DMA12_IRQn = 12,
186 DMA13_IRQn = 13,
187 DMA14_IRQn = 14,
188 DMA15_IRQn = 15,
189 DMA_Error_IRQn = 16,
190 MCM_IRQn = 17,
191 FTFL_IRQn = 18,
192 Read_Collision_IRQn = 19,
193 LVD_LVW_IRQn = 20,
194 LLWU_IRQn = 21,
195 WDOG_EWM_IRQn = 22,
196 RNG_IRQn = 23,
197 I2C0_IRQn = 24,
198 I2C1_IRQn = 25,
199 SPI0_IRQn = 26,
200 SPI1_IRQn = 27,
201 SPI2_IRQn = 28,
202 CAN0_ORed_Message_buffer_IRQn = 29,
203 CAN0_Bus_Off_IRQn = 30,
204 CAN0_Error_IRQn = 31,
205 CAN0_Tx_Warning_IRQn = 32,
206 CAN0_Rx_Warning_IRQn = 33,
207 CAN0_Wake_Up_IRQn = 34,
208 I2S0_Tx_IRQn = 35,
209 I2S0_Rx_IRQn = 36,
210 CAN1_ORed_Message_buffer_IRQn = 37,
211 CAN1_Bus_Off_IRQn = 38,
212 CAN1_Error_IRQn = 39,
213 CAN1_Tx_Warning_IRQn = 40,
214 CAN1_Rx_Warning_IRQn = 41,
215 CAN1_Wake_Up_IRQn = 42,
216 Reserved59_IRQn = 43,
217 UART0_LON_IRQn = 44,
218 UART0_RX_TX_IRQn = 45,
219 UART0_ERR_IRQn = 46,
220 UART1_RX_TX_IRQn = 47,
221 UART1_ERR_IRQn = 48,
222 UART2_RX_TX_IRQn = 49,
223 UART2_ERR_IRQn = 50,
224 UART3_RX_TX_IRQn = 51,
225 UART3_ERR_IRQn = 52,
226 UART4_RX_TX_IRQn = 53,
227 UART4_ERR_IRQn = 54,
228 UART5_RX_TX_IRQn = 55,
229 UART5_ERR_IRQn = 56,
230 ADC0_IRQn = 57,
231 ADC1_IRQn = 58,
232 CMP0_IRQn = 59,
233 CMP1_IRQn = 60,
234 CMP2_IRQn = 61,
235 FTM0_IRQn = 62,
236 FTM1_IRQn = 63,
237 FTM2_IRQn = 64,
238 CMT_IRQn = 65,
239 RTC_IRQn = 66,
240 RTC_Seconds_IRQn = 67,
241 PIT0_IRQn = 68,
242 PIT1_IRQn = 69,
243 PIT2_IRQn = 70,
244 PIT3_IRQn = 71,
245 PDB0_IRQn = 72,
246 USB0_IRQn = 73,
247 USBDCD_IRQn = 74,
248 ENET_1588_Timer_IRQn = 75,
249 ENET_Transmit_IRQn = 76,
250 ENET_Receive_IRQn = 77,
251 ENET_Error_IRQn = 78,
252 Reserved95_IRQn = 79,
253 SDHC_IRQn = 80,
254 DAC0_IRQn = 81,
255 DAC1_IRQn = 82,
256 TSI0_IRQn = 83,
257 MCG_IRQn = 84,
258 LPTMR0_IRQn = 85,
259 Reserved102_IRQn = 86,
260 PORTA_IRQn = 87,
261 PORTB_IRQn = 88,
262 PORTC_IRQn = 89,
263 PORTD_IRQn = 90,
264 PORTE_IRQn = 91,
265 Reserved108_IRQn = 92,
266 Reserved109_IRQn = 93,
267 SWI_IRQn = 94,
268 Reserved111_IRQn = 95,
269 Reserved112_IRQn = 96,
270 Reserved113_IRQn = 97,
271 Reserved114_IRQn = 98,
272 Reserved115_IRQn = 99,
273 Reserved116_IRQn = 100,
274 Reserved117_IRQn = 101,
275 Reserved118_IRQn = 102,
276 Reserved119_IRQn = 103
277} IRQn_Type;
278
281 /* end of group Interrupt_vector_numbers */
282
283
284/* ----------------------------------------------------------------------------
285 -- Cortex M4 Core Configuration
286 ---------------------------------------------------------------------------- */
287
293#define __MPU_PRESENT 0
294#define __NVIC_PRIO_BITS 4
295#define __Vendor_SysTickConfig 0
296#define __FPU_PRESENT 0
298#include "core_cm4.h" /* Core Peripheral Access Layer */
299#ifndef __PROJECT_MIKROSDK_MIKROE__
300// Note: Added for MikroE implementation.
301#include "system_MK60D10.h" /* Device specific configuration file */
302#endif
303
306 /* end of group Cortex_Core_Configuration */
307
308
309/* ----------------------------------------------------------------------------
310 -- Mapping Information
311 ---------------------------------------------------------------------------- */
312
324/*******************************************************************************
325 * Definitions
326 ******************************************************************************/
327
335typedef enum _dma_request_source
336{
337 kDmaRequestMux0Disable = 0|0x100U,
338 kDmaRequestMux0Reserved1 = 1|0x100U,
339 kDmaRequestMux0UART0Rx = 2|0x100U,
340 kDmaRequestMux0UART0Tx = 3|0x100U,
341 kDmaRequestMux0UART1Rx = 4|0x100U,
342 kDmaRequestMux0UART1Tx = 5|0x100U,
343 kDmaRequestMux0UART2Rx = 6|0x100U,
344 kDmaRequestMux0UART2Tx = 7|0x100U,
345 kDmaRequestMux0UART3Rx = 8|0x100U,
346 kDmaRequestMux0UART3Tx = 9|0x100U,
347 kDmaRequestMux0UART4Rx = 10|0x100U,
348 kDmaRequestMux0UART4Tx = 11|0x100U,
349 kDmaRequestMux0UART5Rx = 12|0x100U,
350 kDmaRequestMux0UART5Tx = 13|0x100U,
351 kDmaRequestMux0I2S0Rx = 14|0x100U,
352 kDmaRequestMux0I2S0Tx = 15|0x100U,
353 kDmaRequestMux0SPI0Rx = 16|0x100U,
354 kDmaRequestMux0SPI0Tx = 17|0x100U,
355 kDmaRequestMux0SPI1Rx = 18|0x100U,
356 kDmaRequestMux0SPI1Tx = 19|0x100U,
357 kDmaRequestMux0SPI2Rx = 20|0x100U,
358 kDmaRequestMux0SPI2Tx = 21|0x100U,
359 kDmaRequestMux0I2C0 = 22|0x100U,
360 kDmaRequestMux0I2C1 = 23|0x100U,
361 kDmaRequestMux0FTM0Channel0 = 24|0x100U,
362 kDmaRequestMux0FTM0Channel1 = 25|0x100U,
363 kDmaRequestMux0FTM0Channel2 = 26|0x100U,
364 kDmaRequestMux0FTM0Channel3 = 27|0x100U,
365 kDmaRequestMux0FTM0Channel4 = 28|0x100U,
366 kDmaRequestMux0FTM0Channel5 = 29|0x100U,
367 kDmaRequestMux0FTM0Channel6 = 30|0x100U,
368 kDmaRequestMux0FTM0Channel7 = 31|0x100U,
369 kDmaRequestMux0FTM1Channel0 = 32|0x100U,
370 kDmaRequestMux0FTM1Channel1 = 33|0x100U,
371 kDmaRequestMux0FTM2Channel0 = 34|0x100U,
372 kDmaRequestMux0FTM2Channel1 = 35|0x100U,
373 kDmaRequestMux0IEEE1588Timer0 = 36|0x100U,
374 kDmaRequestMux0IEEE1588Timer1 = 37|0x100U,
375 kDmaRequestMux0IEEE1588Timer2 = 38|0x100U,
376 kDmaRequestMux0IEEE1588Timer3 = 39|0x100U,
377 kDmaRequestMux0ADC0 = 40|0x100U,
378 kDmaRequestMux0ADC1 = 41|0x100U,
379 kDmaRequestMux0CMP0 = 42|0x100U,
380 kDmaRequestMux0CMP1 = 43|0x100U,
381 kDmaRequestMux0CMP2 = 44|0x100U,
382 kDmaRequestMux0DAC0 = 45|0x100U,
383 kDmaRequestMux0DAC1 = 46|0x100U,
384 kDmaRequestMux0CMT = 47|0x100U,
385 kDmaRequestMux0PDB0 = 48|0x100U,
386 kDmaRequestMux0PortA = 49|0x100U,
387 kDmaRequestMux0PortB = 50|0x100U,
388 kDmaRequestMux0PortC = 51|0x100U,
389 kDmaRequestMux0PortD = 52|0x100U,
390 kDmaRequestMux0PortE = 53|0x100U,
391 kDmaRequestMux0AlwaysOn54 = 54|0x100U,
392 kDmaRequestMux0AlwaysOn55 = 55|0x100U,
393 kDmaRequestMux0AlwaysOn56 = 56|0x100U,
394 kDmaRequestMux0AlwaysOn57 = 57|0x100U,
395 kDmaRequestMux0AlwaysOn58 = 58|0x100U,
396 kDmaRequestMux0AlwaysOn59 = 59|0x100U,
397 kDmaRequestMux0AlwaysOn60 = 60|0x100U,
398 kDmaRequestMux0AlwaysOn61 = 61|0x100U,
399 kDmaRequestMux0AlwaysOn62 = 62|0x100U,
400 kDmaRequestMux0AlwaysOn63 = 63|0x100U,
401} dma_request_source_t;
402
403/* @} */
404
405
408 /* end of group Mapping_Information */
409
410
411/* ----------------------------------------------------------------------------
412 -- Device Peripheral Access Layer
413 ---------------------------------------------------------------------------- */
414
421/*
422** Start of section using anonymous unions
423*/
424
425#if defined(__ARMCC_VERSION)
426 #pragma push
427 #pragma anon_unions
428#elif defined(__CWCC__)
429 #pragma push
430 #pragma cpp_extensions on
431#elif defined(__GNUC__)
432 /* anonymous unions are enabled by default */
433#elif defined(__IAR_SYSTEMS_ICC__)
434 #pragma language=extended
435#else
436 #error Not supported compiler type
437#endif
438
439/* ----------------------------------------------------------------------------
440 -- ADC Peripheral Access Layer
441 ---------------------------------------------------------------------------- */
442
449typedef struct {
450 __IO uint32_t SC1[2];
451 __IO uint32_t CFG1;
452 __IO uint32_t CFG2;
453 __I uint32_t R[2];
454 __IO uint32_t CV1;
455 __IO uint32_t CV2;
456 __IO uint32_t SC2;
457 __IO uint32_t SC3;
458 __IO uint32_t OFS;
459 __IO uint32_t PG;
460 __IO uint32_t MG;
461 __IO uint32_t CLPD;
462 __IO uint32_t CLPS;
463 __IO uint32_t CLP4;
464 __IO uint32_t CLP3;
465 __IO uint32_t CLP2;
466 __IO uint32_t CLP1;
467 __IO uint32_t CLP0;
468 __IO uint32_t PGA;
469 __IO uint32_t CLMD;
470 __IO uint32_t CLMS;
471 __IO uint32_t CLM4;
472 __IO uint32_t CLM3;
473 __IO uint32_t CLM2;
474 __IO uint32_t CLM1;
475 __IO uint32_t CLM0;
476} ADC_Type;
477
478/* ----------------------------------------------------------------------------
479 -- ADC Register Masks
480 ---------------------------------------------------------------------------- */
481
488#define ADC_SC1_ADCH_MASK (0x1FU)
489#define ADC_SC1_ADCH_SHIFT (0U)
490#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
491#define ADC_SC1_DIFF_MASK (0x20U)
492#define ADC_SC1_DIFF_SHIFT (5U)
493#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
494#define ADC_SC1_AIEN_MASK (0x40U)
495#define ADC_SC1_AIEN_SHIFT (6U)
496#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
497#define ADC_SC1_COCO_MASK (0x80U)
498#define ADC_SC1_COCO_SHIFT (7U)
499#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
500
501/* The count of ADC_SC1 */
502#define ADC_SC1_COUNT (2U)
503
505#define ADC_CFG1_ADICLK_MASK (0x3U)
506#define ADC_CFG1_ADICLK_SHIFT (0U)
507#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
508#define ADC_CFG1_MODE_MASK (0xCU)
509#define ADC_CFG1_MODE_SHIFT (2U)
510#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
511#define ADC_CFG1_ADLSMP_MASK (0x10U)
512#define ADC_CFG1_ADLSMP_SHIFT (4U)
513#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
514#define ADC_CFG1_ADIV_MASK (0x60U)
515#define ADC_CFG1_ADIV_SHIFT (5U)
516#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
517#define ADC_CFG1_ADLPC_MASK (0x80U)
518#define ADC_CFG1_ADLPC_SHIFT (7U)
519#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
520
522#define ADC_CFG2_ADLSTS_MASK (0x3U)
523#define ADC_CFG2_ADLSTS_SHIFT (0U)
524#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
525#define ADC_CFG2_ADHSC_MASK (0x4U)
526#define ADC_CFG2_ADHSC_SHIFT (2U)
527#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
528#define ADC_CFG2_ADACKEN_MASK (0x8U)
529#define ADC_CFG2_ADACKEN_SHIFT (3U)
530#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
531#define ADC_CFG2_MUXSEL_MASK (0x10U)
532#define ADC_CFG2_MUXSEL_SHIFT (4U)
533#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
534
536#define ADC_R_D_MASK (0xFFFFU)
537#define ADC_R_D_SHIFT (0U)
538#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
539
540/* The count of ADC_R */
541#define ADC_R_COUNT (2U)
542
544#define ADC_CV1_CV_MASK (0xFFFFU)
545#define ADC_CV1_CV_SHIFT (0U)
546#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
547
549#define ADC_CV2_CV_MASK (0xFFFFU)
550#define ADC_CV2_CV_SHIFT (0U)
551#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
552
554#define ADC_SC2_REFSEL_MASK (0x3U)
555#define ADC_SC2_REFSEL_SHIFT (0U)
556#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
557#define ADC_SC2_DMAEN_MASK (0x4U)
558#define ADC_SC2_DMAEN_SHIFT (2U)
559#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
560#define ADC_SC2_ACREN_MASK (0x8U)
561#define ADC_SC2_ACREN_SHIFT (3U)
562#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
563#define ADC_SC2_ACFGT_MASK (0x10U)
564#define ADC_SC2_ACFGT_SHIFT (4U)
565#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
566#define ADC_SC2_ACFE_MASK (0x20U)
567#define ADC_SC2_ACFE_SHIFT (5U)
568#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
569#define ADC_SC2_ADTRG_MASK (0x40U)
570#define ADC_SC2_ADTRG_SHIFT (6U)
571#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
572#define ADC_SC2_ADACT_MASK (0x80U)
573#define ADC_SC2_ADACT_SHIFT (7U)
574#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
575
577#define ADC_SC3_AVGS_MASK (0x3U)
578#define ADC_SC3_AVGS_SHIFT (0U)
579#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
580#define ADC_SC3_AVGE_MASK (0x4U)
581#define ADC_SC3_AVGE_SHIFT (2U)
582#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
583#define ADC_SC3_ADCO_MASK (0x8U)
584#define ADC_SC3_ADCO_SHIFT (3U)
585#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
586#define ADC_SC3_CALF_MASK (0x40U)
587#define ADC_SC3_CALF_SHIFT (6U)
588#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
589#define ADC_SC3_CAL_MASK (0x80U)
590#define ADC_SC3_CAL_SHIFT (7U)
591#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
592
594#define ADC_OFS_OFS_MASK (0xFFFFU)
595#define ADC_OFS_OFS_SHIFT (0U)
596#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
597
599#define ADC_PG_PG_MASK (0xFFFFU)
600#define ADC_PG_PG_SHIFT (0U)
601#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
602
604#define ADC_MG_MG_MASK (0xFFFFU)
605#define ADC_MG_MG_SHIFT (0U)
606#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
607
609#define ADC_CLPD_CLPD_MASK (0x3FU)
610#define ADC_CLPD_CLPD_SHIFT (0U)
611#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
612
614#define ADC_CLPS_CLPS_MASK (0x3FU)
615#define ADC_CLPS_CLPS_SHIFT (0U)
616#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
617
619#define ADC_CLP4_CLP4_MASK (0x3FFU)
620#define ADC_CLP4_CLP4_SHIFT (0U)
621#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
622
624#define ADC_CLP3_CLP3_MASK (0x1FFU)
625#define ADC_CLP3_CLP3_SHIFT (0U)
626#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
627
629#define ADC_CLP2_CLP2_MASK (0xFFU)
630#define ADC_CLP2_CLP2_SHIFT (0U)
631#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
632
634#define ADC_CLP1_CLP1_MASK (0x7FU)
635#define ADC_CLP1_CLP1_SHIFT (0U)
636#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
637
639#define ADC_CLP0_CLP0_MASK (0x3FU)
640#define ADC_CLP0_CLP0_SHIFT (0U)
641#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
642
644#define ADC_PGA_PGAG_MASK (0xF0000U)
645#define ADC_PGA_PGAG_SHIFT (16U)
646#define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGAG_SHIFT)) & ADC_PGA_PGAG_MASK)
647#define ADC_PGA_PGALPb_MASK (0x100000U)
648#define ADC_PGA_PGALPb_SHIFT (20U)
649#define ADC_PGA_PGALPb(x) (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGALPb_SHIFT)) & ADC_PGA_PGALPb_MASK)
650#define ADC_PGA_PGAEN_MASK (0x800000U)
651#define ADC_PGA_PGAEN_SHIFT (23U)
652#define ADC_PGA_PGAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGAEN_SHIFT)) & ADC_PGA_PGAEN_MASK)
653
655#define ADC_CLMD_CLMD_MASK (0x3FU)
656#define ADC_CLMD_CLMD_SHIFT (0U)
657#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
658
660#define ADC_CLMS_CLMS_MASK (0x3FU)
661#define ADC_CLMS_CLMS_SHIFT (0U)
662#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
663
665#define ADC_CLM4_CLM4_MASK (0x3FFU)
666#define ADC_CLM4_CLM4_SHIFT (0U)
667#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
668
670#define ADC_CLM3_CLM3_MASK (0x1FFU)
671#define ADC_CLM3_CLM3_SHIFT (0U)
672#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
673
675#define ADC_CLM2_CLM2_MASK (0xFFU)
676#define ADC_CLM2_CLM2_SHIFT (0U)
677#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
678
680#define ADC_CLM1_CLM1_MASK (0x7FU)
681#define ADC_CLM1_CLM1_SHIFT (0U)
682#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
683
685#define ADC_CLM0_CLM0_MASK (0x3FU)
686#define ADC_CLM0_CLM0_SHIFT (0U)
687#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
688
689
692 /* end of group ADC_Register_Masks */
693
694
695/* ADC - Peripheral instance base addresses */
697#define ADC0_BASE (0x4003B000u)
699#define ADC0 ((ADC_Type *)ADC0_BASE)
701#define ADC1_BASE (0x400BB000u)
703#define ADC1 ((ADC_Type *)ADC1_BASE)
705#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
707#define ADC_BASE_PTRS { ADC0, ADC1 }
709#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
710
713 /* end of group ADC_Peripheral_Access_Layer */
714
715
716/* ----------------------------------------------------------------------------
717 -- AIPS Peripheral Access Layer
718 ---------------------------------------------------------------------------- */
719
726typedef struct {
727 __IO uint32_t MPRA;
728 uint8_t RESERVED_0[28];
729 __IO uint32_t PACRA;
730 __IO uint32_t PACRB;
731 __IO uint32_t PACRC;
732 __IO uint32_t PACRD;
733 uint8_t RESERVED_1[16];
734 __IO uint32_t PACRE;
735 __IO uint32_t PACRF;
736 __IO uint32_t PACRG;
737 __IO uint32_t PACRH;
738 __IO uint32_t PACRI;
739 __IO uint32_t PACRJ;
740 __IO uint32_t PACRK;
741 __IO uint32_t PACRL;
742 __IO uint32_t PACRM;
743 __IO uint32_t PACRN;
744 __IO uint32_t PACRO;
745 __IO uint32_t PACRP;
746} AIPS_Type;
747
748/* ----------------------------------------------------------------------------
749 -- AIPS Register Masks
750 ---------------------------------------------------------------------------- */
751
758#define AIPS_MPRA_MPL5_MASK (0x100U)
759#define AIPS_MPRA_MPL5_SHIFT (8U)
760#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
761#define AIPS_MPRA_MTW5_MASK (0x200U)
762#define AIPS_MPRA_MTW5_SHIFT (9U)
763#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
764#define AIPS_MPRA_MTR5_MASK (0x400U)
765#define AIPS_MPRA_MTR5_SHIFT (10U)
766#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
767#define AIPS_MPRA_MPL4_MASK (0x1000U)
768#define AIPS_MPRA_MPL4_SHIFT (12U)
769#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
770#define AIPS_MPRA_MTW4_MASK (0x2000U)
771#define AIPS_MPRA_MTW4_SHIFT (13U)
772#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
773#define AIPS_MPRA_MTR4_MASK (0x4000U)
774#define AIPS_MPRA_MTR4_SHIFT (14U)
775#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
776#define AIPS_MPRA_MPL3_MASK (0x10000U)
777#define AIPS_MPRA_MPL3_SHIFT (16U)
778#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
779#define AIPS_MPRA_MTW3_MASK (0x20000U)
780#define AIPS_MPRA_MTW3_SHIFT (17U)
781#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
782#define AIPS_MPRA_MTR3_MASK (0x40000U)
783#define AIPS_MPRA_MTR3_SHIFT (18U)
784#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
785#define AIPS_MPRA_MPL2_MASK (0x100000U)
786#define AIPS_MPRA_MPL2_SHIFT (20U)
787#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
788#define AIPS_MPRA_MTW2_MASK (0x200000U)
789#define AIPS_MPRA_MTW2_SHIFT (21U)
790#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
791#define AIPS_MPRA_MTR2_MASK (0x400000U)
792#define AIPS_MPRA_MTR2_SHIFT (22U)
793#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
794#define AIPS_MPRA_MPL1_MASK (0x1000000U)
795#define AIPS_MPRA_MPL1_SHIFT (24U)
796#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
797#define AIPS_MPRA_MTW1_MASK (0x2000000U)
798#define AIPS_MPRA_MTW1_SHIFT (25U)
799#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
800#define AIPS_MPRA_MTR1_MASK (0x4000000U)
801#define AIPS_MPRA_MTR1_SHIFT (26U)
802#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
803#define AIPS_MPRA_MPL0_MASK (0x10000000U)
804#define AIPS_MPRA_MPL0_SHIFT (28U)
805#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
806#define AIPS_MPRA_MTW0_MASK (0x20000000U)
807#define AIPS_MPRA_MTW0_SHIFT (29U)
808#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
809#define AIPS_MPRA_MTR0_MASK (0x40000000U)
810#define AIPS_MPRA_MTR0_SHIFT (30U)
811#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
812
814#define AIPS_PACRA_TP7_MASK (0x1U)
815#define AIPS_PACRA_TP7_SHIFT (0U)
816#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
817#define AIPS_PACRA_WP7_MASK (0x2U)
818#define AIPS_PACRA_WP7_SHIFT (1U)
819#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
820#define AIPS_PACRA_SP7_MASK (0x4U)
821#define AIPS_PACRA_SP7_SHIFT (2U)
822#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
823#define AIPS_PACRA_TP6_MASK (0x10U)
824#define AIPS_PACRA_TP6_SHIFT (4U)
825#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
826#define AIPS_PACRA_WP6_MASK (0x20U)
827#define AIPS_PACRA_WP6_SHIFT (5U)
828#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
829#define AIPS_PACRA_SP6_MASK (0x40U)
830#define AIPS_PACRA_SP6_SHIFT (6U)
831#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
832#define AIPS_PACRA_TP5_MASK (0x100U)
833#define AIPS_PACRA_TP5_SHIFT (8U)
834#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
835#define AIPS_PACRA_WP5_MASK (0x200U)
836#define AIPS_PACRA_WP5_SHIFT (9U)
837#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
838#define AIPS_PACRA_SP5_MASK (0x400U)
839#define AIPS_PACRA_SP5_SHIFT (10U)
840#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
841#define AIPS_PACRA_TP4_MASK (0x1000U)
842#define AIPS_PACRA_TP4_SHIFT (12U)
843#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
844#define AIPS_PACRA_WP4_MASK (0x2000U)
845#define AIPS_PACRA_WP4_SHIFT (13U)
846#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
847#define AIPS_PACRA_SP4_MASK (0x4000U)
848#define AIPS_PACRA_SP4_SHIFT (14U)
849#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
850#define AIPS_PACRA_TP3_MASK (0x10000U)
851#define AIPS_PACRA_TP3_SHIFT (16U)
852#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
853#define AIPS_PACRA_WP3_MASK (0x20000U)
854#define AIPS_PACRA_WP3_SHIFT (17U)
855#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
856#define AIPS_PACRA_SP3_MASK (0x40000U)
857#define AIPS_PACRA_SP3_SHIFT (18U)
858#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
859#define AIPS_PACRA_TP2_MASK (0x100000U)
860#define AIPS_PACRA_TP2_SHIFT (20U)
861#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
862#define AIPS_PACRA_WP2_MASK (0x200000U)
863#define AIPS_PACRA_WP2_SHIFT (21U)
864#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
865#define AIPS_PACRA_SP2_MASK (0x400000U)
866#define AIPS_PACRA_SP2_SHIFT (22U)
867#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
868#define AIPS_PACRA_TP1_MASK (0x1000000U)
869#define AIPS_PACRA_TP1_SHIFT (24U)
870#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
871#define AIPS_PACRA_WP1_MASK (0x2000000U)
872#define AIPS_PACRA_WP1_SHIFT (25U)
873#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
874#define AIPS_PACRA_SP1_MASK (0x4000000U)
875#define AIPS_PACRA_SP1_SHIFT (26U)
876#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
877#define AIPS_PACRA_TP0_MASK (0x10000000U)
878#define AIPS_PACRA_TP0_SHIFT (28U)
879#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
880#define AIPS_PACRA_WP0_MASK (0x20000000U)
881#define AIPS_PACRA_WP0_SHIFT (29U)
882#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
883#define AIPS_PACRA_SP0_MASK (0x40000000U)
884#define AIPS_PACRA_SP0_SHIFT (30U)
885#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
886
888#define AIPS_PACRB_TP7_MASK (0x1U)
889#define AIPS_PACRB_TP7_SHIFT (0U)
890#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
891#define AIPS_PACRB_WP7_MASK (0x2U)
892#define AIPS_PACRB_WP7_SHIFT (1U)
893#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
894#define AIPS_PACRB_SP7_MASK (0x4U)
895#define AIPS_PACRB_SP7_SHIFT (2U)
896#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
897#define AIPS_PACRB_TP6_MASK (0x10U)
898#define AIPS_PACRB_TP6_SHIFT (4U)
899#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
900#define AIPS_PACRB_WP6_MASK (0x20U)
901#define AIPS_PACRB_WP6_SHIFT (5U)
902#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
903#define AIPS_PACRB_SP6_MASK (0x40U)
904#define AIPS_PACRB_SP6_SHIFT (6U)
905#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
906#define AIPS_PACRB_TP5_MASK (0x100U)
907#define AIPS_PACRB_TP5_SHIFT (8U)
908#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
909#define AIPS_PACRB_WP5_MASK (0x200U)
910#define AIPS_PACRB_WP5_SHIFT (9U)
911#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
912#define AIPS_PACRB_SP5_MASK (0x400U)
913#define AIPS_PACRB_SP5_SHIFT (10U)
914#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
915#define AIPS_PACRB_TP4_MASK (0x1000U)
916#define AIPS_PACRB_TP4_SHIFT (12U)
917#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
918#define AIPS_PACRB_WP4_MASK (0x2000U)
919#define AIPS_PACRB_WP4_SHIFT (13U)
920#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
921#define AIPS_PACRB_SP4_MASK (0x4000U)
922#define AIPS_PACRB_SP4_SHIFT (14U)
923#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
924#define AIPS_PACRB_TP3_MASK (0x10000U)
925#define AIPS_PACRB_TP3_SHIFT (16U)
926#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
927#define AIPS_PACRB_WP3_MASK (0x20000U)
928#define AIPS_PACRB_WP3_SHIFT (17U)
929#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
930#define AIPS_PACRB_SP3_MASK (0x40000U)
931#define AIPS_PACRB_SP3_SHIFT (18U)
932#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
933#define AIPS_PACRB_TP2_MASK (0x100000U)
934#define AIPS_PACRB_TP2_SHIFT (20U)
935#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
936#define AIPS_PACRB_WP2_MASK (0x200000U)
937#define AIPS_PACRB_WP2_SHIFT (21U)
938#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
939#define AIPS_PACRB_SP2_MASK (0x400000U)
940#define AIPS_PACRB_SP2_SHIFT (22U)
941#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
942#define AIPS_PACRB_TP1_MASK (0x1000000U)
943#define AIPS_PACRB_TP1_SHIFT (24U)
944#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
945#define AIPS_PACRB_WP1_MASK (0x2000000U)
946#define AIPS_PACRB_WP1_SHIFT (25U)
947#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
948#define AIPS_PACRB_SP1_MASK (0x4000000U)
949#define AIPS_PACRB_SP1_SHIFT (26U)
950#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
951#define AIPS_PACRB_TP0_MASK (0x10000000U)
952#define AIPS_PACRB_TP0_SHIFT (28U)
953#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
954#define AIPS_PACRB_WP0_MASK (0x20000000U)
955#define AIPS_PACRB_WP0_SHIFT (29U)
956#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
957#define AIPS_PACRB_SP0_MASK (0x40000000U)
958#define AIPS_PACRB_SP0_SHIFT (30U)
959#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
960
962#define AIPS_PACRC_TP7_MASK (0x1U)
963#define AIPS_PACRC_TP7_SHIFT (0U)
964#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
965#define AIPS_PACRC_WP7_MASK (0x2U)
966#define AIPS_PACRC_WP7_SHIFT (1U)
967#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
968#define AIPS_PACRC_SP7_MASK (0x4U)
969#define AIPS_PACRC_SP7_SHIFT (2U)
970#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
971#define AIPS_PACRC_TP6_MASK (0x10U)
972#define AIPS_PACRC_TP6_SHIFT (4U)
973#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
974#define AIPS_PACRC_WP6_MASK (0x20U)
975#define AIPS_PACRC_WP6_SHIFT (5U)
976#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
977#define AIPS_PACRC_SP6_MASK (0x40U)
978#define AIPS_PACRC_SP6_SHIFT (6U)
979#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
980#define AIPS_PACRC_TP5_MASK (0x100U)
981#define AIPS_PACRC_TP5_SHIFT (8U)
982#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
983#define AIPS_PACRC_WP5_MASK (0x200U)
984#define AIPS_PACRC_WP5_SHIFT (9U)
985#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
986#define AIPS_PACRC_SP5_MASK (0x400U)
987#define AIPS_PACRC_SP5_SHIFT (10U)
988#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
989#define AIPS_PACRC_TP4_MASK (0x1000U)
990#define AIPS_PACRC_TP4_SHIFT (12U)
991#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
992#define AIPS_PACRC_WP4_MASK (0x2000U)
993#define AIPS_PACRC_WP4_SHIFT (13U)
994#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
995#define AIPS_PACRC_SP4_MASK (0x4000U)
996#define AIPS_PACRC_SP4_SHIFT (14U)
997#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
998#define AIPS_PACRC_TP3_MASK (0x10000U)
999#define AIPS_PACRC_TP3_SHIFT (16U)
1000#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1001#define AIPS_PACRC_WP3_MASK (0x20000U)
1002#define AIPS_PACRC_WP3_SHIFT (17U)
1003#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1004#define AIPS_PACRC_SP3_MASK (0x40000U)
1005#define AIPS_PACRC_SP3_SHIFT (18U)
1006#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1007#define AIPS_PACRC_TP2_MASK (0x100000U)
1008#define AIPS_PACRC_TP2_SHIFT (20U)
1009#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1010#define AIPS_PACRC_WP2_MASK (0x200000U)
1011#define AIPS_PACRC_WP2_SHIFT (21U)
1012#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1013#define AIPS_PACRC_SP2_MASK (0x400000U)
1014#define AIPS_PACRC_SP2_SHIFT (22U)
1015#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1016#define AIPS_PACRC_TP1_MASK (0x1000000U)
1017#define AIPS_PACRC_TP1_SHIFT (24U)
1018#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1019#define AIPS_PACRC_WP1_MASK (0x2000000U)
1020#define AIPS_PACRC_WP1_SHIFT (25U)
1021#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1022#define AIPS_PACRC_SP1_MASK (0x4000000U)
1023#define AIPS_PACRC_SP1_SHIFT (26U)
1024#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1025#define AIPS_PACRC_TP0_MASK (0x10000000U)
1026#define AIPS_PACRC_TP0_SHIFT (28U)
1027#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1028#define AIPS_PACRC_WP0_MASK (0x20000000U)
1029#define AIPS_PACRC_WP0_SHIFT (29U)
1030#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1031#define AIPS_PACRC_SP0_MASK (0x40000000U)
1032#define AIPS_PACRC_SP0_SHIFT (30U)
1033#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1034
1036#define AIPS_PACRD_TP7_MASK (0x1U)
1037#define AIPS_PACRD_TP7_SHIFT (0U)
1038#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1039#define AIPS_PACRD_WP7_MASK (0x2U)
1040#define AIPS_PACRD_WP7_SHIFT (1U)
1041#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1042#define AIPS_PACRD_SP7_MASK (0x4U)
1043#define AIPS_PACRD_SP7_SHIFT (2U)
1044#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1045#define AIPS_PACRD_TP6_MASK (0x10U)
1046#define AIPS_PACRD_TP6_SHIFT (4U)
1047#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1048#define AIPS_PACRD_WP6_MASK (0x20U)
1049#define AIPS_PACRD_WP6_SHIFT (5U)
1050#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1051#define AIPS_PACRD_SP6_MASK (0x40U)
1052#define AIPS_PACRD_SP6_SHIFT (6U)
1053#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1054#define AIPS_PACRD_TP5_MASK (0x100U)
1055#define AIPS_PACRD_TP5_SHIFT (8U)
1056#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1057#define AIPS_PACRD_WP5_MASK (0x200U)
1058#define AIPS_PACRD_WP5_SHIFT (9U)
1059#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1060#define AIPS_PACRD_SP5_MASK (0x400U)
1061#define AIPS_PACRD_SP5_SHIFT (10U)
1062#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1063#define AIPS_PACRD_TP4_MASK (0x1000U)
1064#define AIPS_PACRD_TP4_SHIFT (12U)
1065#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1066#define AIPS_PACRD_WP4_MASK (0x2000U)
1067#define AIPS_PACRD_WP4_SHIFT (13U)
1068#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1069#define AIPS_PACRD_SP4_MASK (0x4000U)
1070#define AIPS_PACRD_SP4_SHIFT (14U)
1071#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1072#define AIPS_PACRD_TP3_MASK (0x10000U)
1073#define AIPS_PACRD_TP3_SHIFT (16U)
1074#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1075#define AIPS_PACRD_WP3_MASK (0x20000U)
1076#define AIPS_PACRD_WP3_SHIFT (17U)
1077#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1078#define AIPS_PACRD_SP3_MASK (0x40000U)
1079#define AIPS_PACRD_SP3_SHIFT (18U)
1080#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1081#define AIPS_PACRD_TP2_MASK (0x100000U)
1082#define AIPS_PACRD_TP2_SHIFT (20U)
1083#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1084#define AIPS_PACRD_WP2_MASK (0x200000U)
1085#define AIPS_PACRD_WP2_SHIFT (21U)
1086#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1087#define AIPS_PACRD_SP2_MASK (0x400000U)
1088#define AIPS_PACRD_SP2_SHIFT (22U)
1089#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1090#define AIPS_PACRD_TP1_MASK (0x1000000U)
1091#define AIPS_PACRD_TP1_SHIFT (24U)
1092#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1093#define AIPS_PACRD_WP1_MASK (0x2000000U)
1094#define AIPS_PACRD_WP1_SHIFT (25U)
1095#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1096#define AIPS_PACRD_SP1_MASK (0x4000000U)
1097#define AIPS_PACRD_SP1_SHIFT (26U)
1098#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1099#define AIPS_PACRD_TP0_MASK (0x10000000U)
1100#define AIPS_PACRD_TP0_SHIFT (28U)
1101#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1102#define AIPS_PACRD_WP0_MASK (0x20000000U)
1103#define AIPS_PACRD_WP0_SHIFT (29U)
1104#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1105#define AIPS_PACRD_SP0_MASK (0x40000000U)
1106#define AIPS_PACRD_SP0_SHIFT (30U)
1107#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1108
1110#define AIPS_PACRE_TP7_MASK (0x1U)
1111#define AIPS_PACRE_TP7_SHIFT (0U)
1112#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1113#define AIPS_PACRE_WP7_MASK (0x2U)
1114#define AIPS_PACRE_WP7_SHIFT (1U)
1115#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1116#define AIPS_PACRE_SP7_MASK (0x4U)
1117#define AIPS_PACRE_SP7_SHIFT (2U)
1118#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1119#define AIPS_PACRE_TP6_MASK (0x10U)
1120#define AIPS_PACRE_TP6_SHIFT (4U)
1121#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1122#define AIPS_PACRE_WP6_MASK (0x20U)
1123#define AIPS_PACRE_WP6_SHIFT (5U)
1124#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1125#define AIPS_PACRE_SP6_MASK (0x40U)
1126#define AIPS_PACRE_SP6_SHIFT (6U)
1127#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1128#define AIPS_PACRE_TP5_MASK (0x100U)
1129#define AIPS_PACRE_TP5_SHIFT (8U)
1130#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1131#define AIPS_PACRE_WP5_MASK (0x200U)
1132#define AIPS_PACRE_WP5_SHIFT (9U)
1133#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1134#define AIPS_PACRE_SP5_MASK (0x400U)
1135#define AIPS_PACRE_SP5_SHIFT (10U)
1136#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1137#define AIPS_PACRE_TP4_MASK (0x1000U)
1138#define AIPS_PACRE_TP4_SHIFT (12U)
1139#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1140#define AIPS_PACRE_WP4_MASK (0x2000U)
1141#define AIPS_PACRE_WP4_SHIFT (13U)
1142#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1143#define AIPS_PACRE_SP4_MASK (0x4000U)
1144#define AIPS_PACRE_SP4_SHIFT (14U)
1145#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1146#define AIPS_PACRE_TP3_MASK (0x10000U)
1147#define AIPS_PACRE_TP3_SHIFT (16U)
1148#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1149#define AIPS_PACRE_WP3_MASK (0x20000U)
1150#define AIPS_PACRE_WP3_SHIFT (17U)
1151#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1152#define AIPS_PACRE_SP3_MASK (0x40000U)
1153#define AIPS_PACRE_SP3_SHIFT (18U)
1154#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1155#define AIPS_PACRE_TP2_MASK (0x100000U)
1156#define AIPS_PACRE_TP2_SHIFT (20U)
1157#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1158#define AIPS_PACRE_WP2_MASK (0x200000U)
1159#define AIPS_PACRE_WP2_SHIFT (21U)
1160#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1161#define AIPS_PACRE_SP2_MASK (0x400000U)
1162#define AIPS_PACRE_SP2_SHIFT (22U)
1163#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1164#define AIPS_PACRE_TP1_MASK (0x1000000U)
1165#define AIPS_PACRE_TP1_SHIFT (24U)
1166#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1167#define AIPS_PACRE_WP1_MASK (0x2000000U)
1168#define AIPS_PACRE_WP1_SHIFT (25U)
1169#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1170#define AIPS_PACRE_SP1_MASK (0x4000000U)
1171#define AIPS_PACRE_SP1_SHIFT (26U)
1172#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1173#define AIPS_PACRE_TP0_MASK (0x10000000U)
1174#define AIPS_PACRE_TP0_SHIFT (28U)
1175#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1176#define AIPS_PACRE_WP0_MASK (0x20000000U)
1177#define AIPS_PACRE_WP0_SHIFT (29U)
1178#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1179#define AIPS_PACRE_SP0_MASK (0x40000000U)
1180#define AIPS_PACRE_SP0_SHIFT (30U)
1181#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1182
1184#define AIPS_PACRF_TP7_MASK (0x1U)
1185#define AIPS_PACRF_TP7_SHIFT (0U)
1186#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1187#define AIPS_PACRF_WP7_MASK (0x2U)
1188#define AIPS_PACRF_WP7_SHIFT (1U)
1189#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1190#define AIPS_PACRF_SP7_MASK (0x4U)
1191#define AIPS_PACRF_SP7_SHIFT (2U)
1192#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1193#define AIPS_PACRF_TP6_MASK (0x10U)
1194#define AIPS_PACRF_TP6_SHIFT (4U)
1195#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1196#define AIPS_PACRF_WP6_MASK (0x20U)
1197#define AIPS_PACRF_WP6_SHIFT (5U)
1198#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1199#define AIPS_PACRF_SP6_MASK (0x40U)
1200#define AIPS_PACRF_SP6_SHIFT (6U)
1201#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1202#define AIPS_PACRF_TP5_MASK (0x100U)
1203#define AIPS_PACRF_TP5_SHIFT (8U)
1204#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1205#define AIPS_PACRF_WP5_MASK (0x200U)
1206#define AIPS_PACRF_WP5_SHIFT (9U)
1207#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1208#define AIPS_PACRF_SP5_MASK (0x400U)
1209#define AIPS_PACRF_SP5_SHIFT (10U)
1210#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1211#define AIPS_PACRF_TP4_MASK (0x1000U)
1212#define AIPS_PACRF_TP4_SHIFT (12U)
1213#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
1214#define AIPS_PACRF_WP4_MASK (0x2000U)
1215#define AIPS_PACRF_WP4_SHIFT (13U)
1216#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
1217#define AIPS_PACRF_SP4_MASK (0x4000U)
1218#define AIPS_PACRF_SP4_SHIFT (14U)
1219#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
1220#define AIPS_PACRF_TP3_MASK (0x10000U)
1221#define AIPS_PACRF_TP3_SHIFT (16U)
1222#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
1223#define AIPS_PACRF_WP3_MASK (0x20000U)
1224#define AIPS_PACRF_WP3_SHIFT (17U)
1225#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
1226#define AIPS_PACRF_SP3_MASK (0x40000U)
1227#define AIPS_PACRF_SP3_SHIFT (18U)
1228#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
1229#define AIPS_PACRF_TP2_MASK (0x100000U)
1230#define AIPS_PACRF_TP2_SHIFT (20U)
1231#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
1232#define AIPS_PACRF_WP2_MASK (0x200000U)
1233#define AIPS_PACRF_WP2_SHIFT (21U)
1234#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
1235#define AIPS_PACRF_SP2_MASK (0x400000U)
1236#define AIPS_PACRF_SP2_SHIFT (22U)
1237#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
1238#define AIPS_PACRF_TP1_MASK (0x1000000U)
1239#define AIPS_PACRF_TP1_SHIFT (24U)
1240#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
1241#define AIPS_PACRF_WP1_MASK (0x2000000U)
1242#define AIPS_PACRF_WP1_SHIFT (25U)
1243#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
1244#define AIPS_PACRF_SP1_MASK (0x4000000U)
1245#define AIPS_PACRF_SP1_SHIFT (26U)
1246#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
1247#define AIPS_PACRF_TP0_MASK (0x10000000U)
1248#define AIPS_PACRF_TP0_SHIFT (28U)
1249#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
1250#define AIPS_PACRF_WP0_MASK (0x20000000U)
1251#define AIPS_PACRF_WP0_SHIFT (29U)
1252#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
1253#define AIPS_PACRF_SP0_MASK (0x40000000U)
1254#define AIPS_PACRF_SP0_SHIFT (30U)
1255#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
1256
1258#define AIPS_PACRG_TP7_MASK (0x1U)
1259#define AIPS_PACRG_TP7_SHIFT (0U)
1260#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
1261#define AIPS_PACRG_WP7_MASK (0x2U)
1262#define AIPS_PACRG_WP7_SHIFT (1U)
1263#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
1264#define AIPS_PACRG_SP7_MASK (0x4U)
1265#define AIPS_PACRG_SP7_SHIFT (2U)
1266#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
1267#define AIPS_PACRG_TP6_MASK (0x10U)
1268#define AIPS_PACRG_TP6_SHIFT (4U)
1269#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
1270#define AIPS_PACRG_WP6_MASK (0x20U)
1271#define AIPS_PACRG_WP6_SHIFT (5U)
1272#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
1273#define AIPS_PACRG_SP6_MASK (0x40U)
1274#define AIPS_PACRG_SP6_SHIFT (6U)
1275#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
1276#define AIPS_PACRG_TP5_MASK (0x100U)
1277#define AIPS_PACRG_TP5_SHIFT (8U)
1278#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
1279#define AIPS_PACRG_WP5_MASK (0x200U)
1280#define AIPS_PACRG_WP5_SHIFT (9U)
1281#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
1282#define AIPS_PACRG_SP5_MASK (0x400U)
1283#define AIPS_PACRG_SP5_SHIFT (10U)
1284#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
1285#define AIPS_PACRG_TP4_MASK (0x1000U)
1286#define AIPS_PACRG_TP4_SHIFT (12U)
1287#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
1288#define AIPS_PACRG_WP4_MASK (0x2000U)
1289#define AIPS_PACRG_WP4_SHIFT (13U)
1290#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
1291#define AIPS_PACRG_SP4_MASK (0x4000U)
1292#define AIPS_PACRG_SP4_SHIFT (14U)
1293#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
1294#define AIPS_PACRG_TP3_MASK (0x10000U)
1295#define AIPS_PACRG_TP3_SHIFT (16U)
1296#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
1297#define AIPS_PACRG_WP3_MASK (0x20000U)
1298#define AIPS_PACRG_WP3_SHIFT (17U)
1299#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
1300#define AIPS_PACRG_SP3_MASK (0x40000U)
1301#define AIPS_PACRG_SP3_SHIFT (18U)
1302#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
1303#define AIPS_PACRG_TP2_MASK (0x100000U)
1304#define AIPS_PACRG_TP2_SHIFT (20U)
1305#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
1306#define AIPS_PACRG_WP2_MASK (0x200000U)
1307#define AIPS_PACRG_WP2_SHIFT (21U)
1308#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
1309#define AIPS_PACRG_SP2_MASK (0x400000U)
1310#define AIPS_PACRG_SP2_SHIFT (22U)
1311#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
1312#define AIPS_PACRG_TP1_MASK (0x1000000U)
1313#define AIPS_PACRG_TP1_SHIFT (24U)
1314#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
1315#define AIPS_PACRG_WP1_MASK (0x2000000U)
1316#define AIPS_PACRG_WP1_SHIFT (25U)
1317#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
1318#define AIPS_PACRG_SP1_MASK (0x4000000U)
1319#define AIPS_PACRG_SP1_SHIFT (26U)
1320#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
1321#define AIPS_PACRG_TP0_MASK (0x10000000U)
1322#define AIPS_PACRG_TP0_SHIFT (28U)
1323#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
1324#define AIPS_PACRG_WP0_MASK (0x20000000U)
1325#define AIPS_PACRG_WP0_SHIFT (29U)
1326#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
1327#define AIPS_PACRG_SP0_MASK (0x40000000U)
1328#define AIPS_PACRG_SP0_SHIFT (30U)
1329#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
1330
1332#define AIPS_PACRH_TP7_MASK (0x1U)
1333#define AIPS_PACRH_TP7_SHIFT (0U)
1334#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
1335#define AIPS_PACRH_WP7_MASK (0x2U)
1336#define AIPS_PACRH_WP7_SHIFT (1U)
1337#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
1338#define AIPS_PACRH_SP7_MASK (0x4U)
1339#define AIPS_PACRH_SP7_SHIFT (2U)
1340#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
1341#define AIPS_PACRH_TP6_MASK (0x10U)
1342#define AIPS_PACRH_TP6_SHIFT (4U)
1343#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
1344#define AIPS_PACRH_WP6_MASK (0x20U)
1345#define AIPS_PACRH_WP6_SHIFT (5U)
1346#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
1347#define AIPS_PACRH_SP6_MASK (0x40U)
1348#define AIPS_PACRH_SP6_SHIFT (6U)
1349#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
1350#define AIPS_PACRH_TP5_MASK (0x100U)
1351#define AIPS_PACRH_TP5_SHIFT (8U)
1352#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
1353#define AIPS_PACRH_WP5_MASK (0x200U)
1354#define AIPS_PACRH_WP5_SHIFT (9U)
1355#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
1356#define AIPS_PACRH_SP5_MASK (0x400U)
1357#define AIPS_PACRH_SP5_SHIFT (10U)
1358#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
1359#define AIPS_PACRH_TP4_MASK (0x1000U)
1360#define AIPS_PACRH_TP4_SHIFT (12U)
1361#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
1362#define AIPS_PACRH_WP4_MASK (0x2000U)
1363#define AIPS_PACRH_WP4_SHIFT (13U)
1364#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
1365#define AIPS_PACRH_SP4_MASK (0x4000U)
1366#define AIPS_PACRH_SP4_SHIFT (14U)
1367#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
1368#define AIPS_PACRH_TP3_MASK (0x10000U)
1369#define AIPS_PACRH_TP3_SHIFT (16U)
1370#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
1371#define AIPS_PACRH_WP3_MASK (0x20000U)
1372#define AIPS_PACRH_WP3_SHIFT (17U)
1373#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
1374#define AIPS_PACRH_SP3_MASK (0x40000U)
1375#define AIPS_PACRH_SP3_SHIFT (18U)
1376#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
1377#define AIPS_PACRH_TP2_MASK (0x100000U)
1378#define AIPS_PACRH_TP2_SHIFT (20U)
1379#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
1380#define AIPS_PACRH_WP2_MASK (0x200000U)
1381#define AIPS_PACRH_WP2_SHIFT (21U)
1382#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
1383#define AIPS_PACRH_SP2_MASK (0x400000U)
1384#define AIPS_PACRH_SP2_SHIFT (22U)
1385#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
1386#define AIPS_PACRH_TP1_MASK (0x1000000U)
1387#define AIPS_PACRH_TP1_SHIFT (24U)
1388#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
1389#define AIPS_PACRH_WP1_MASK (0x2000000U)
1390#define AIPS_PACRH_WP1_SHIFT (25U)
1391#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
1392#define AIPS_PACRH_SP1_MASK (0x4000000U)
1393#define AIPS_PACRH_SP1_SHIFT (26U)
1394#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
1395#define AIPS_PACRH_TP0_MASK (0x10000000U)
1396#define AIPS_PACRH_TP0_SHIFT (28U)
1397#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
1398#define AIPS_PACRH_WP0_MASK (0x20000000U)
1399#define AIPS_PACRH_WP0_SHIFT (29U)
1400#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
1401#define AIPS_PACRH_SP0_MASK (0x40000000U)
1402#define AIPS_PACRH_SP0_SHIFT (30U)
1403#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
1404
1406#define AIPS_PACRI_TP7_MASK (0x1U)
1407#define AIPS_PACRI_TP7_SHIFT (0U)
1408#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
1409#define AIPS_PACRI_WP7_MASK (0x2U)
1410#define AIPS_PACRI_WP7_SHIFT (1U)
1411#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
1412#define AIPS_PACRI_SP7_MASK (0x4U)
1413#define AIPS_PACRI_SP7_SHIFT (2U)
1414#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
1415#define AIPS_PACRI_TP6_MASK (0x10U)
1416#define AIPS_PACRI_TP6_SHIFT (4U)
1417#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
1418#define AIPS_PACRI_WP6_MASK (0x20U)
1419#define AIPS_PACRI_WP6_SHIFT (5U)
1420#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
1421#define AIPS_PACRI_SP6_MASK (0x40U)
1422#define AIPS_PACRI_SP6_SHIFT (6U)
1423#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
1424#define AIPS_PACRI_TP5_MASK (0x100U)
1425#define AIPS_PACRI_TP5_SHIFT (8U)
1426#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
1427#define AIPS_PACRI_WP5_MASK (0x200U)
1428#define AIPS_PACRI_WP5_SHIFT (9U)
1429#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
1430#define AIPS_PACRI_SP5_MASK (0x400U)
1431#define AIPS_PACRI_SP5_SHIFT (10U)
1432#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
1433#define AIPS_PACRI_TP4_MASK (0x1000U)
1434#define AIPS_PACRI_TP4_SHIFT (12U)
1435#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
1436#define AIPS_PACRI_WP4_MASK (0x2000U)
1437#define AIPS_PACRI_WP4_SHIFT (13U)
1438#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
1439#define AIPS_PACRI_SP4_MASK (0x4000U)
1440#define AIPS_PACRI_SP4_SHIFT (14U)
1441#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
1442#define AIPS_PACRI_TP3_MASK (0x10000U)
1443#define AIPS_PACRI_TP3_SHIFT (16U)
1444#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
1445#define AIPS_PACRI_WP3_MASK (0x20000U)
1446#define AIPS_PACRI_WP3_SHIFT (17U)
1447#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
1448#define AIPS_PACRI_SP3_MASK (0x40000U)
1449#define AIPS_PACRI_SP3_SHIFT (18U)
1450#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
1451#define AIPS_PACRI_TP2_MASK (0x100000U)
1452#define AIPS_PACRI_TP2_SHIFT (20U)
1453#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
1454#define AIPS_PACRI_WP2_MASK (0x200000U)
1455#define AIPS_PACRI_WP2_SHIFT (21U)
1456#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
1457#define AIPS_PACRI_SP2_MASK (0x400000U)
1458#define AIPS_PACRI_SP2_SHIFT (22U)
1459#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
1460#define AIPS_PACRI_TP1_MASK (0x1000000U)
1461#define AIPS_PACRI_TP1_SHIFT (24U)
1462#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
1463#define AIPS_PACRI_WP1_MASK (0x2000000U)
1464#define AIPS_PACRI_WP1_SHIFT (25U)
1465#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
1466#define AIPS_PACRI_SP1_MASK (0x4000000U)
1467#define AIPS_PACRI_SP1_SHIFT (26U)
1468#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
1469#define AIPS_PACRI_TP0_MASK (0x10000000U)
1470#define AIPS_PACRI_TP0_SHIFT (28U)
1471#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
1472#define AIPS_PACRI_WP0_MASK (0x20000000U)
1473#define AIPS_PACRI_WP0_SHIFT (29U)
1474#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
1475#define AIPS_PACRI_SP0_MASK (0x40000000U)
1476#define AIPS_PACRI_SP0_SHIFT (30U)
1477#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
1478
1480#define AIPS_PACRJ_TP7_MASK (0x1U)
1481#define AIPS_PACRJ_TP7_SHIFT (0U)
1482#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
1483#define AIPS_PACRJ_WP7_MASK (0x2U)
1484#define AIPS_PACRJ_WP7_SHIFT (1U)
1485#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
1486#define AIPS_PACRJ_SP7_MASK (0x4U)
1487#define AIPS_PACRJ_SP7_SHIFT (2U)
1488#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
1489#define AIPS_PACRJ_TP6_MASK (0x10U)
1490#define AIPS_PACRJ_TP6_SHIFT (4U)
1491#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
1492#define AIPS_PACRJ_WP6_MASK (0x20U)
1493#define AIPS_PACRJ_WP6_SHIFT (5U)
1494#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
1495#define AIPS_PACRJ_SP6_MASK (0x40U)
1496#define AIPS_PACRJ_SP6_SHIFT (6U)
1497#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
1498#define AIPS_PACRJ_TP5_MASK (0x100U)
1499#define AIPS_PACRJ_TP5_SHIFT (8U)
1500#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
1501#define AIPS_PACRJ_WP5_MASK (0x200U)
1502#define AIPS_PACRJ_WP5_SHIFT (9U)
1503#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
1504#define AIPS_PACRJ_SP5_MASK (0x400U)
1505#define AIPS_PACRJ_SP5_SHIFT (10U)
1506#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
1507#define AIPS_PACRJ_TP4_MASK (0x1000U)
1508#define AIPS_PACRJ_TP4_SHIFT (12U)
1509#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
1510#define AIPS_PACRJ_WP4_MASK (0x2000U)
1511#define AIPS_PACRJ_WP4_SHIFT (13U)
1512#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
1513#define AIPS_PACRJ_SP4_MASK (0x4000U)
1514#define AIPS_PACRJ_SP4_SHIFT (14U)
1515#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
1516#define AIPS_PACRJ_TP3_MASK (0x10000U)
1517#define AIPS_PACRJ_TP3_SHIFT (16U)
1518#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
1519#define AIPS_PACRJ_WP3_MASK (0x20000U)
1520#define AIPS_PACRJ_WP3_SHIFT (17U)
1521#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
1522#define AIPS_PACRJ_SP3_MASK (0x40000U)
1523#define AIPS_PACRJ_SP3_SHIFT (18U)
1524#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
1525#define AIPS_PACRJ_TP2_MASK (0x100000U)
1526#define AIPS_PACRJ_TP2_SHIFT (20U)
1527#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
1528#define AIPS_PACRJ_WP2_MASK (0x200000U)
1529#define AIPS_PACRJ_WP2_SHIFT (21U)
1530#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
1531#define AIPS_PACRJ_SP2_MASK (0x400000U)
1532#define AIPS_PACRJ_SP2_SHIFT (22U)
1533#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
1534#define AIPS_PACRJ_TP1_MASK (0x1000000U)
1535#define AIPS_PACRJ_TP1_SHIFT (24U)
1536#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
1537#define AIPS_PACRJ_WP1_MASK (0x2000000U)
1538#define AIPS_PACRJ_WP1_SHIFT (25U)
1539#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
1540#define AIPS_PACRJ_SP1_MASK (0x4000000U)
1541#define AIPS_PACRJ_SP1_SHIFT (26U)
1542#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
1543#define AIPS_PACRJ_TP0_MASK (0x10000000U)
1544#define AIPS_PACRJ_TP0_SHIFT (28U)
1545#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
1546#define AIPS_PACRJ_WP0_MASK (0x20000000U)
1547#define AIPS_PACRJ_WP0_SHIFT (29U)
1548#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
1549#define AIPS_PACRJ_SP0_MASK (0x40000000U)
1550#define AIPS_PACRJ_SP0_SHIFT (30U)
1551#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
1552
1554#define AIPS_PACRK_TP7_MASK (0x1U)
1555#define AIPS_PACRK_TP7_SHIFT (0U)
1556#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
1557#define AIPS_PACRK_WP7_MASK (0x2U)
1558#define AIPS_PACRK_WP7_SHIFT (1U)
1559#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
1560#define AIPS_PACRK_SP7_MASK (0x4U)
1561#define AIPS_PACRK_SP7_SHIFT (2U)
1562#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
1563#define AIPS_PACRK_TP6_MASK (0x10U)
1564#define AIPS_PACRK_TP6_SHIFT (4U)
1565#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
1566#define AIPS_PACRK_WP6_MASK (0x20U)
1567#define AIPS_PACRK_WP6_SHIFT (5U)
1568#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
1569#define AIPS_PACRK_SP6_MASK (0x40U)
1570#define AIPS_PACRK_SP6_SHIFT (6U)
1571#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
1572#define AIPS_PACRK_TP5_MASK (0x100U)
1573#define AIPS_PACRK_TP5_SHIFT (8U)
1574#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
1575#define AIPS_PACRK_WP5_MASK (0x200U)
1576#define AIPS_PACRK_WP5_SHIFT (9U)
1577#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
1578#define AIPS_PACRK_SP5_MASK (0x400U)
1579#define AIPS_PACRK_SP5_SHIFT (10U)
1580#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
1581#define AIPS_PACRK_TP4_MASK (0x1000U)
1582#define AIPS_PACRK_TP4_SHIFT (12U)
1583#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
1584#define AIPS_PACRK_WP4_MASK (0x2000U)
1585#define AIPS_PACRK_WP4_SHIFT (13U)
1586#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
1587#define AIPS_PACRK_SP4_MASK (0x4000U)
1588#define AIPS_PACRK_SP4_SHIFT (14U)
1589#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
1590#define AIPS_PACRK_TP3_MASK (0x10000U)
1591#define AIPS_PACRK_TP3_SHIFT (16U)
1592#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
1593#define AIPS_PACRK_WP3_MASK (0x20000U)
1594#define AIPS_PACRK_WP3_SHIFT (17U)
1595#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
1596#define AIPS_PACRK_SP3_MASK (0x40000U)
1597#define AIPS_PACRK_SP3_SHIFT (18U)
1598#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
1599#define AIPS_PACRK_TP2_MASK (0x100000U)
1600#define AIPS_PACRK_TP2_SHIFT (20U)
1601#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
1602#define AIPS_PACRK_WP2_MASK (0x200000U)
1603#define AIPS_PACRK_WP2_SHIFT (21U)
1604#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
1605#define AIPS_PACRK_SP2_MASK (0x400000U)
1606#define AIPS_PACRK_SP2_SHIFT (22U)
1607#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
1608#define AIPS_PACRK_TP1_MASK (0x1000000U)
1609#define AIPS_PACRK_TP1_SHIFT (24U)
1610#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
1611#define AIPS_PACRK_WP1_MASK (0x2000000U)
1612#define AIPS_PACRK_WP1_SHIFT (25U)
1613#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
1614#define AIPS_PACRK_SP1_MASK (0x4000000U)
1615#define AIPS_PACRK_SP1_SHIFT (26U)
1616#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
1617#define AIPS_PACRK_TP0_MASK (0x10000000U)
1618#define AIPS_PACRK_TP0_SHIFT (28U)
1619#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
1620#define AIPS_PACRK_WP0_MASK (0x20000000U)
1621#define AIPS_PACRK_WP0_SHIFT (29U)
1622#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
1623#define AIPS_PACRK_SP0_MASK (0x40000000U)
1624#define AIPS_PACRK_SP0_SHIFT (30U)
1625#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
1626
1628#define AIPS_PACRL_TP7_MASK (0x1U)
1629#define AIPS_PACRL_TP7_SHIFT (0U)
1630#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
1631#define AIPS_PACRL_WP7_MASK (0x2U)
1632#define AIPS_PACRL_WP7_SHIFT (1U)
1633#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
1634#define AIPS_PACRL_SP7_MASK (0x4U)
1635#define AIPS_PACRL_SP7_SHIFT (2U)
1636#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
1637#define AIPS_PACRL_TP6_MASK (0x10U)
1638#define AIPS_PACRL_TP6_SHIFT (4U)
1639#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
1640#define AIPS_PACRL_WP6_MASK (0x20U)
1641#define AIPS_PACRL_WP6_SHIFT (5U)
1642#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
1643#define AIPS_PACRL_SP6_MASK (0x40U)
1644#define AIPS_PACRL_SP6_SHIFT (6U)
1645#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
1646#define AIPS_PACRL_TP5_MASK (0x100U)
1647#define AIPS_PACRL_TP5_SHIFT (8U)
1648#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
1649#define AIPS_PACRL_WP5_MASK (0x200U)
1650#define AIPS_PACRL_WP5_SHIFT (9U)
1651#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
1652#define AIPS_PACRL_SP5_MASK (0x400U)
1653#define AIPS_PACRL_SP5_SHIFT (10U)
1654#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
1655#define AIPS_PACRL_TP4_MASK (0x1000U)
1656#define AIPS_PACRL_TP4_SHIFT (12U)
1657#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
1658#define AIPS_PACRL_WP4_MASK (0x2000U)
1659#define AIPS_PACRL_WP4_SHIFT (13U)
1660#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
1661#define AIPS_PACRL_SP4_MASK (0x4000U)
1662#define AIPS_PACRL_SP4_SHIFT (14U)
1663#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
1664#define AIPS_PACRL_TP3_MASK (0x10000U)
1665#define AIPS_PACRL_TP3_SHIFT (16U)
1666#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
1667#define AIPS_PACRL_WP3_MASK (0x20000U)
1668#define AIPS_PACRL_WP3_SHIFT (17U)
1669#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
1670#define AIPS_PACRL_SP3_MASK (0x40000U)
1671#define AIPS_PACRL_SP3_SHIFT (18U)
1672#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
1673#define AIPS_PACRL_TP2_MASK (0x100000U)
1674#define AIPS_PACRL_TP2_SHIFT (20U)
1675#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
1676#define AIPS_PACRL_WP2_MASK (0x200000U)
1677#define AIPS_PACRL_WP2_SHIFT (21U)
1678#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
1679#define AIPS_PACRL_SP2_MASK (0x400000U)
1680#define AIPS_PACRL_SP2_SHIFT (22U)
1681#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
1682#define AIPS_PACRL_TP1_MASK (0x1000000U)
1683#define AIPS_PACRL_TP1_SHIFT (24U)
1684#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
1685#define AIPS_PACRL_WP1_MASK (0x2000000U)
1686#define AIPS_PACRL_WP1_SHIFT (25U)
1687#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
1688#define AIPS_PACRL_SP1_MASK (0x4000000U)
1689#define AIPS_PACRL_SP1_SHIFT (26U)
1690#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
1691#define AIPS_PACRL_TP0_MASK (0x10000000U)
1692#define AIPS_PACRL_TP0_SHIFT (28U)
1693#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
1694#define AIPS_PACRL_WP0_MASK (0x20000000U)
1695#define AIPS_PACRL_WP0_SHIFT (29U)
1696#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
1697#define AIPS_PACRL_SP0_MASK (0x40000000U)
1698#define AIPS_PACRL_SP0_SHIFT (30U)
1699#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
1700
1702#define AIPS_PACRM_TP7_MASK (0x1U)
1703#define AIPS_PACRM_TP7_SHIFT (0U)
1704#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
1705#define AIPS_PACRM_WP7_MASK (0x2U)
1706#define AIPS_PACRM_WP7_SHIFT (1U)
1707#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
1708#define AIPS_PACRM_SP7_MASK (0x4U)
1709#define AIPS_PACRM_SP7_SHIFT (2U)
1710#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
1711#define AIPS_PACRM_TP6_MASK (0x10U)
1712#define AIPS_PACRM_TP6_SHIFT (4U)
1713#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
1714#define AIPS_PACRM_WP6_MASK (0x20U)
1715#define AIPS_PACRM_WP6_SHIFT (5U)
1716#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
1717#define AIPS_PACRM_SP6_MASK (0x40U)
1718#define AIPS_PACRM_SP6_SHIFT (6U)
1719#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
1720#define AIPS_PACRM_TP5_MASK (0x100U)
1721#define AIPS_PACRM_TP5_SHIFT (8U)
1722#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
1723#define AIPS_PACRM_WP5_MASK (0x200U)
1724#define AIPS_PACRM_WP5_SHIFT (9U)
1725#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
1726#define AIPS_PACRM_SP5_MASK (0x400U)
1727#define AIPS_PACRM_SP5_SHIFT (10U)
1728#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
1729#define AIPS_PACRM_TP4_MASK (0x1000U)
1730#define AIPS_PACRM_TP4_SHIFT (12U)
1731#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
1732#define AIPS_PACRM_WP4_MASK (0x2000U)
1733#define AIPS_PACRM_WP4_SHIFT (13U)
1734#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
1735#define AIPS_PACRM_SP4_MASK (0x4000U)
1736#define AIPS_PACRM_SP4_SHIFT (14U)
1737#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
1738#define AIPS_PACRM_TP3_MASK (0x10000U)
1739#define AIPS_PACRM_TP3_SHIFT (16U)
1740#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
1741#define AIPS_PACRM_WP3_MASK (0x20000U)
1742#define AIPS_PACRM_WP3_SHIFT (17U)
1743#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
1744#define AIPS_PACRM_SP3_MASK (0x40000U)
1745#define AIPS_PACRM_SP3_SHIFT (18U)
1746#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
1747#define AIPS_PACRM_TP2_MASK (0x100000U)
1748#define AIPS_PACRM_TP2_SHIFT (20U)
1749#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
1750#define AIPS_PACRM_WP2_MASK (0x200000U)
1751#define AIPS_PACRM_WP2_SHIFT (21U)
1752#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
1753#define AIPS_PACRM_SP2_MASK (0x400000U)
1754#define AIPS_PACRM_SP2_SHIFT (22U)
1755#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
1756#define AIPS_PACRM_TP1_MASK (0x1000000U)
1757#define AIPS_PACRM_TP1_SHIFT (24U)
1758#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
1759#define AIPS_PACRM_WP1_MASK (0x2000000U)
1760#define AIPS_PACRM_WP1_SHIFT (25U)
1761#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
1762#define AIPS_PACRM_SP1_MASK (0x4000000U)
1763#define AIPS_PACRM_SP1_SHIFT (26U)
1764#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
1765#define AIPS_PACRM_TP0_MASK (0x10000000U)
1766#define AIPS_PACRM_TP0_SHIFT (28U)
1767#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
1768#define AIPS_PACRM_WP0_MASK (0x20000000U)
1769#define AIPS_PACRM_WP0_SHIFT (29U)
1770#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
1771#define AIPS_PACRM_SP0_MASK (0x40000000U)
1772#define AIPS_PACRM_SP0_SHIFT (30U)
1773#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
1774
1776#define AIPS_PACRN_TP7_MASK (0x1U)
1777#define AIPS_PACRN_TP7_SHIFT (0U)
1778#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
1779#define AIPS_PACRN_WP7_MASK (0x2U)
1780#define AIPS_PACRN_WP7_SHIFT (1U)
1781#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
1782#define AIPS_PACRN_SP7_MASK (0x4U)
1783#define AIPS_PACRN_SP7_SHIFT (2U)
1784#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
1785#define AIPS_PACRN_TP6_MASK (0x10U)
1786#define AIPS_PACRN_TP6_SHIFT (4U)
1787#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
1788#define AIPS_PACRN_WP6_MASK (0x20U)
1789#define AIPS_PACRN_WP6_SHIFT (5U)
1790#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
1791#define AIPS_PACRN_SP6_MASK (0x40U)
1792#define AIPS_PACRN_SP6_SHIFT (6U)
1793#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
1794#define AIPS_PACRN_TP5_MASK (0x100U)
1795#define AIPS_PACRN_TP5_SHIFT (8U)
1796#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
1797#define AIPS_PACRN_WP5_MASK (0x200U)
1798#define AIPS_PACRN_WP5_SHIFT (9U)
1799#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
1800#define AIPS_PACRN_SP5_MASK (0x400U)
1801#define AIPS_PACRN_SP5_SHIFT (10U)
1802#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
1803#define AIPS_PACRN_TP4_MASK (0x1000U)
1804#define AIPS_PACRN_TP4_SHIFT (12U)
1805#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
1806#define AIPS_PACRN_WP4_MASK (0x2000U)
1807#define AIPS_PACRN_WP4_SHIFT (13U)
1808#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
1809#define AIPS_PACRN_SP4_MASK (0x4000U)
1810#define AIPS_PACRN_SP4_SHIFT (14U)
1811#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
1812#define AIPS_PACRN_TP3_MASK (0x10000U)
1813#define AIPS_PACRN_TP3_SHIFT (16U)
1814#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
1815#define AIPS_PACRN_WP3_MASK (0x20000U)
1816#define AIPS_PACRN_WP3_SHIFT (17U)
1817#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
1818#define AIPS_PACRN_SP3_MASK (0x40000U)
1819#define AIPS_PACRN_SP3_SHIFT (18U)
1820#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
1821#define AIPS_PACRN_TP2_MASK (0x100000U)
1822#define AIPS_PACRN_TP2_SHIFT (20U)
1823#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
1824#define AIPS_PACRN_WP2_MASK (0x200000U)
1825#define AIPS_PACRN_WP2_SHIFT (21U)
1826#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
1827#define AIPS_PACRN_SP2_MASK (0x400000U)
1828#define AIPS_PACRN_SP2_SHIFT (22U)
1829#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
1830#define AIPS_PACRN_TP1_MASK (0x1000000U)
1831#define AIPS_PACRN_TP1_SHIFT (24U)
1832#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
1833#define AIPS_PACRN_WP1_MASK (0x2000000U)
1834#define AIPS_PACRN_WP1_SHIFT (25U)
1835#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
1836#define AIPS_PACRN_SP1_MASK (0x4000000U)
1837#define AIPS_PACRN_SP1_SHIFT (26U)
1838#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
1839#define AIPS_PACRN_TP0_MASK (0x10000000U)
1840#define AIPS_PACRN_TP0_SHIFT (28U)
1841#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
1842#define AIPS_PACRN_WP0_MASK (0x20000000U)
1843#define AIPS_PACRN_WP0_SHIFT (29U)
1844#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
1845#define AIPS_PACRN_SP0_MASK (0x40000000U)
1846#define AIPS_PACRN_SP0_SHIFT (30U)
1847#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
1848
1850#define AIPS_PACRO_TP7_MASK (0x1U)
1851#define AIPS_PACRO_TP7_SHIFT (0U)
1852#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
1853#define AIPS_PACRO_WP7_MASK (0x2U)
1854#define AIPS_PACRO_WP7_SHIFT (1U)
1855#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
1856#define AIPS_PACRO_SP7_MASK (0x4U)
1857#define AIPS_PACRO_SP7_SHIFT (2U)
1858#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
1859#define AIPS_PACRO_TP6_MASK (0x10U)
1860#define AIPS_PACRO_TP6_SHIFT (4U)
1861#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
1862#define AIPS_PACRO_WP6_MASK (0x20U)
1863#define AIPS_PACRO_WP6_SHIFT (5U)
1864#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
1865#define AIPS_PACRO_SP6_MASK (0x40U)
1866#define AIPS_PACRO_SP6_SHIFT (6U)
1867#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
1868#define AIPS_PACRO_TP5_MASK (0x100U)
1869#define AIPS_PACRO_TP5_SHIFT (8U)
1870#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
1871#define AIPS_PACRO_WP5_MASK (0x200U)
1872#define AIPS_PACRO_WP5_SHIFT (9U)
1873#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
1874#define AIPS_PACRO_SP5_MASK (0x400U)
1875#define AIPS_PACRO_SP5_SHIFT (10U)
1876#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
1877#define AIPS_PACRO_TP4_MASK (0x1000U)
1878#define AIPS_PACRO_TP4_SHIFT (12U)
1879#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
1880#define AIPS_PACRO_WP4_MASK (0x2000U)
1881#define AIPS_PACRO_WP4_SHIFT (13U)
1882#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
1883#define AIPS_PACRO_SP4_MASK (0x4000U)
1884#define AIPS_PACRO_SP4_SHIFT (14U)
1885#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
1886#define AIPS_PACRO_TP3_MASK (0x10000U)
1887#define AIPS_PACRO_TP3_SHIFT (16U)
1888#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
1889#define AIPS_PACRO_WP3_MASK (0x20000U)
1890#define AIPS_PACRO_WP3_SHIFT (17U)
1891#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
1892#define AIPS_PACRO_SP3_MASK (0x40000U)
1893#define AIPS_PACRO_SP3_SHIFT (18U)
1894#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
1895#define AIPS_PACRO_TP2_MASK (0x100000U)
1896#define AIPS_PACRO_TP2_SHIFT (20U)
1897#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
1898#define AIPS_PACRO_WP2_MASK (0x200000U)
1899#define AIPS_PACRO_WP2_SHIFT (21U)
1900#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
1901#define AIPS_PACRO_SP2_MASK (0x400000U)
1902#define AIPS_PACRO_SP2_SHIFT (22U)
1903#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
1904#define AIPS_PACRO_TP1_MASK (0x1000000U)
1905#define AIPS_PACRO_TP1_SHIFT (24U)
1906#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
1907#define AIPS_PACRO_WP1_MASK (0x2000000U)
1908#define AIPS_PACRO_WP1_SHIFT (25U)
1909#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
1910#define AIPS_PACRO_SP1_MASK (0x4000000U)
1911#define AIPS_PACRO_SP1_SHIFT (26U)
1912#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
1913#define AIPS_PACRO_TP0_MASK (0x10000000U)
1914#define AIPS_PACRO_TP0_SHIFT (28U)
1915#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
1916#define AIPS_PACRO_WP0_MASK (0x20000000U)
1917#define AIPS_PACRO_WP0_SHIFT (29U)
1918#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
1919#define AIPS_PACRO_SP0_MASK (0x40000000U)
1920#define AIPS_PACRO_SP0_SHIFT (30U)
1921#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
1922
1924#define AIPS_PACRP_TP7_MASK (0x1U)
1925#define AIPS_PACRP_TP7_SHIFT (0U)
1926#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
1927#define AIPS_PACRP_WP7_MASK (0x2U)
1928#define AIPS_PACRP_WP7_SHIFT (1U)
1929#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
1930#define AIPS_PACRP_SP7_MASK (0x4U)
1931#define AIPS_PACRP_SP7_SHIFT (2U)
1932#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
1933#define AIPS_PACRP_TP6_MASK (0x10U)
1934#define AIPS_PACRP_TP6_SHIFT (4U)
1935#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
1936#define AIPS_PACRP_WP6_MASK (0x20U)
1937#define AIPS_PACRP_WP6_SHIFT (5U)
1938#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
1939#define AIPS_PACRP_SP6_MASK (0x40U)
1940#define AIPS_PACRP_SP6_SHIFT (6U)
1941#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
1942#define AIPS_PACRP_TP5_MASK (0x100U)
1943#define AIPS_PACRP_TP5_SHIFT (8U)
1944#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
1945#define AIPS_PACRP_WP5_MASK (0x200U)
1946#define AIPS_PACRP_WP5_SHIFT (9U)
1947#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
1948#define AIPS_PACRP_SP5_MASK (0x400U)
1949#define AIPS_PACRP_SP5_SHIFT (10U)
1950#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
1951#define AIPS_PACRP_TP4_MASK (0x1000U)
1952#define AIPS_PACRP_TP4_SHIFT (12U)
1953#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
1954#define AIPS_PACRP_WP4_MASK (0x2000U)
1955#define AIPS_PACRP_WP4_SHIFT (13U)
1956#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
1957#define AIPS_PACRP_SP4_MASK (0x4000U)
1958#define AIPS_PACRP_SP4_SHIFT (14U)
1959#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
1960#define AIPS_PACRP_TP3_MASK (0x10000U)
1961#define AIPS_PACRP_TP3_SHIFT (16U)
1962#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
1963#define AIPS_PACRP_WP3_MASK (0x20000U)
1964#define AIPS_PACRP_WP3_SHIFT (17U)
1965#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
1966#define AIPS_PACRP_SP3_MASK (0x40000U)
1967#define AIPS_PACRP_SP3_SHIFT (18U)
1968#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
1969#define AIPS_PACRP_TP2_MASK (0x100000U)
1970#define AIPS_PACRP_TP2_SHIFT (20U)
1971#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
1972#define AIPS_PACRP_WP2_MASK (0x200000U)
1973#define AIPS_PACRP_WP2_SHIFT (21U)
1974#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
1975#define AIPS_PACRP_SP2_MASK (0x400000U)
1976#define AIPS_PACRP_SP2_SHIFT (22U)
1977#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
1978#define AIPS_PACRP_TP1_MASK (0x1000000U)
1979#define AIPS_PACRP_TP1_SHIFT (24U)
1980#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
1981#define AIPS_PACRP_WP1_MASK (0x2000000U)
1982#define AIPS_PACRP_WP1_SHIFT (25U)
1983#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
1984#define AIPS_PACRP_SP1_MASK (0x4000000U)
1985#define AIPS_PACRP_SP1_SHIFT (26U)
1986#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
1987#define AIPS_PACRP_TP0_MASK (0x10000000U)
1988#define AIPS_PACRP_TP0_SHIFT (28U)
1989#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
1990#define AIPS_PACRP_WP0_MASK (0x20000000U)
1991#define AIPS_PACRP_WP0_SHIFT (29U)
1992#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
1993#define AIPS_PACRP_SP0_MASK (0x40000000U)
1994#define AIPS_PACRP_SP0_SHIFT (30U)
1995#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
1996
1997
2000 /* end of group AIPS_Register_Masks */
2001
2002
2003/* AIPS - Peripheral instance base addresses */
2005#define AIPS0_BASE (0x40000000u)
2007#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
2009#define AIPS1_BASE (0x40080000u)
2011#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
2013#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
2015#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
2016
2019 /* end of group AIPS_Peripheral_Access_Layer */
2020
2021
2022/* ----------------------------------------------------------------------------
2023 -- AXBS Peripheral Access Layer
2024 ---------------------------------------------------------------------------- */
2025
2032typedef struct {
2033 struct { /* offset: 0x0, array step: 0x100 */
2034 __IO uint32_t PRS;
2035 uint8_t RESERVED_0[12];
2036 __IO uint32_t CRS;
2037 uint8_t RESERVED_1[236];
2038 } SLAVE[5];
2039 uint8_t RESERVED_0[768];
2040 __IO uint32_t MGPCR0;
2041 uint8_t RESERVED_1[252];
2042 __IO uint32_t MGPCR1;
2043 uint8_t RESERVED_2[252];
2044 __IO uint32_t MGPCR2;
2045 uint8_t RESERVED_3[252];
2046 __IO uint32_t MGPCR3;
2047 uint8_t RESERVED_4[252];
2048 __IO uint32_t MGPCR4;
2049 uint8_t RESERVED_5[252];
2050 __IO uint32_t MGPCR5;
2051} AXBS_Type;
2052
2053/* ----------------------------------------------------------------------------
2054 -- AXBS Register Masks
2055 ---------------------------------------------------------------------------- */
2056
2063#define AXBS_PRS_M0_MASK (0x7U)
2064#define AXBS_PRS_M0_SHIFT (0U)
2065#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
2066#define AXBS_PRS_M1_MASK (0x70U)
2067#define AXBS_PRS_M1_SHIFT (4U)
2068#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
2069#define AXBS_PRS_M2_MASK (0x700U)
2070#define AXBS_PRS_M2_SHIFT (8U)
2071#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
2072#define AXBS_PRS_M3_MASK (0x7000U)
2073#define AXBS_PRS_M3_SHIFT (12U)
2074#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
2075#define AXBS_PRS_M4_MASK (0x70000U)
2076#define AXBS_PRS_M4_SHIFT (16U)
2077#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
2078#define AXBS_PRS_M5_MASK (0x700000U)
2079#define AXBS_PRS_M5_SHIFT (20U)
2080#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
2081
2082/* The count of AXBS_PRS */
2083#define AXBS_PRS_COUNT (5U)
2084
2086#define AXBS_CRS_PARK_MASK (0x7U)
2087#define AXBS_CRS_PARK_SHIFT (0U)
2088#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
2089#define AXBS_CRS_PCTL_MASK (0x30U)
2090#define AXBS_CRS_PCTL_SHIFT (4U)
2091#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
2092#define AXBS_CRS_ARB_MASK (0x300U)
2093#define AXBS_CRS_ARB_SHIFT (8U)
2094#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
2095#define AXBS_CRS_HLP_MASK (0x40000000U)
2096#define AXBS_CRS_HLP_SHIFT (30U)
2097#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
2098#define AXBS_CRS_RO_MASK (0x80000000U)
2099#define AXBS_CRS_RO_SHIFT (31U)
2100#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
2101
2102/* The count of AXBS_CRS */
2103#define AXBS_CRS_COUNT (5U)
2104
2106#define AXBS_MGPCR0_AULB_MASK (0x7U)
2107#define AXBS_MGPCR0_AULB_SHIFT (0U)
2108#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
2109
2111#define AXBS_MGPCR1_AULB_MASK (0x7U)
2112#define AXBS_MGPCR1_AULB_SHIFT (0U)
2113#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
2114
2116#define AXBS_MGPCR2_AULB_MASK (0x7U)
2117#define AXBS_MGPCR2_AULB_SHIFT (0U)
2118#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
2119
2121#define AXBS_MGPCR3_AULB_MASK (0x7U)
2122#define AXBS_MGPCR3_AULB_SHIFT (0U)
2123#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
2124
2126#define AXBS_MGPCR4_AULB_MASK (0x7U)
2127#define AXBS_MGPCR4_AULB_SHIFT (0U)
2128#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
2129
2131#define AXBS_MGPCR5_AULB_MASK (0x7U)
2132#define AXBS_MGPCR5_AULB_SHIFT (0U)
2133#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
2134
2135
2138 /* end of group AXBS_Register_Masks */
2139
2140
2141/* AXBS - Peripheral instance base addresses */
2143#define AXBS_BASE (0x40004000u)
2145#define AXBS ((AXBS_Type *)AXBS_BASE)
2147#define AXBS_BASE_ADDRS { AXBS_BASE }
2149#define AXBS_BASE_PTRS { AXBS }
2150
2153 /* end of group AXBS_Peripheral_Access_Layer */
2154
2155
2156/* ----------------------------------------------------------------------------
2157 -- CAN Peripheral Access Layer
2158 ---------------------------------------------------------------------------- */
2159
2166typedef struct {
2167 __IO uint32_t MCR;
2168 __IO uint32_t CTRL1;
2169 __IO uint32_t TIMER;
2170 uint8_t RESERVED_0[4];
2171 __IO uint32_t RXMGMASK;
2172 __IO uint32_t RX14MASK;
2173 __IO uint32_t RX15MASK;
2174 __IO uint32_t ECR;
2175 __IO uint32_t ESR1;
2176 uint8_t RESERVED_1[4];
2177 __IO uint32_t IMASK1;
2178 uint8_t RESERVED_2[4];
2179 __IO uint32_t IFLAG1;
2180 __IO uint32_t CTRL2;
2181 __I uint32_t ESR2;
2182 uint8_t RESERVED_3[8];
2183 __I uint32_t CRCR;
2184 __IO uint32_t RXFGMASK;
2185 __I uint32_t RXFIR;
2186 uint8_t RESERVED_4[48];
2187 struct { /* offset: 0x80, array step: 0x10 */
2188 __IO uint32_t CS;
2189 __IO uint32_t ID;
2190 __IO uint32_t WORD0;
2191 __IO uint32_t WORD1;
2192 } MB[16];
2193 uint8_t RESERVED_5[1792];
2194 __IO uint32_t RXIMR[16];
2195} CAN_Type;
2196
2197/* ----------------------------------------------------------------------------
2198 -- CAN Register Masks
2199 ---------------------------------------------------------------------------- */
2200
2207#define CAN_MCR_MAXMB_MASK (0x7FU)
2208#define CAN_MCR_MAXMB_SHIFT (0U)
2209#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
2210#define CAN_MCR_IDAM_MASK (0x300U)
2211#define CAN_MCR_IDAM_SHIFT (8U)
2212#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
2213#define CAN_MCR_AEN_MASK (0x1000U)
2214#define CAN_MCR_AEN_SHIFT (12U)
2215#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
2216#define CAN_MCR_LPRIOEN_MASK (0x2000U)
2217#define CAN_MCR_LPRIOEN_SHIFT (13U)
2218#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
2219#define CAN_MCR_IRMQ_MASK (0x10000U)
2220#define CAN_MCR_IRMQ_SHIFT (16U)
2221#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
2222#define CAN_MCR_SRXDIS_MASK (0x20000U)
2223#define CAN_MCR_SRXDIS_SHIFT (17U)
2224#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
2225#define CAN_MCR_WAKSRC_MASK (0x80000U)
2226#define CAN_MCR_WAKSRC_SHIFT (19U)
2227#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
2228#define CAN_MCR_LPMACK_MASK (0x100000U)
2229#define CAN_MCR_LPMACK_SHIFT (20U)
2230#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
2231#define CAN_MCR_WRNEN_MASK (0x200000U)
2232#define CAN_MCR_WRNEN_SHIFT (21U)
2233#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
2234#define CAN_MCR_SLFWAK_MASK (0x400000U)
2235#define CAN_MCR_SLFWAK_SHIFT (22U)
2236#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
2237#define CAN_MCR_SUPV_MASK (0x800000U)
2238#define CAN_MCR_SUPV_SHIFT (23U)
2239#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
2240#define CAN_MCR_FRZACK_MASK (0x1000000U)
2241#define CAN_MCR_FRZACK_SHIFT (24U)
2242#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
2243#define CAN_MCR_SOFTRST_MASK (0x2000000U)
2244#define CAN_MCR_SOFTRST_SHIFT (25U)
2245#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
2246#define CAN_MCR_WAKMSK_MASK (0x4000000U)
2247#define CAN_MCR_WAKMSK_SHIFT (26U)
2248#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
2249#define CAN_MCR_NOTRDY_MASK (0x8000000U)
2250#define CAN_MCR_NOTRDY_SHIFT (27U)
2251#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
2252#define CAN_MCR_HALT_MASK (0x10000000U)
2253#define CAN_MCR_HALT_SHIFT (28U)
2254#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
2255#define CAN_MCR_RFEN_MASK (0x20000000U)
2256#define CAN_MCR_RFEN_SHIFT (29U)
2257#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
2258#define CAN_MCR_FRZ_MASK (0x40000000U)
2259#define CAN_MCR_FRZ_SHIFT (30U)
2260#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
2261#define CAN_MCR_MDIS_MASK (0x80000000U)
2262#define CAN_MCR_MDIS_SHIFT (31U)
2263#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
2264
2266#define CAN_CTRL1_PROPSEG_MASK (0x7U)
2267#define CAN_CTRL1_PROPSEG_SHIFT (0U)
2268#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
2269#define CAN_CTRL1_LOM_MASK (0x8U)
2270#define CAN_CTRL1_LOM_SHIFT (3U)
2271#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
2272#define CAN_CTRL1_LBUF_MASK (0x10U)
2273#define CAN_CTRL1_LBUF_SHIFT (4U)
2274#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
2275#define CAN_CTRL1_TSYN_MASK (0x20U)
2276#define CAN_CTRL1_TSYN_SHIFT (5U)
2277#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
2278#define CAN_CTRL1_BOFFREC_MASK (0x40U)
2279#define CAN_CTRL1_BOFFREC_SHIFT (6U)
2280#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
2281#define CAN_CTRL1_SMP_MASK (0x80U)
2282#define CAN_CTRL1_SMP_SHIFT (7U)
2283#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
2284#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
2285#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
2286#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
2287#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
2288#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
2289#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
2290#define CAN_CTRL1_LPB_MASK (0x1000U)
2291#define CAN_CTRL1_LPB_SHIFT (12U)
2292#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
2293#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
2294#define CAN_CTRL1_CLKSRC_SHIFT (13U)
2295#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
2296#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
2297#define CAN_CTRL1_ERRMSK_SHIFT (14U)
2298#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
2299#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
2300#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
2301#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
2302#define CAN_CTRL1_PSEG2_MASK (0x70000U)
2303#define CAN_CTRL1_PSEG2_SHIFT (16U)
2304#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
2305#define CAN_CTRL1_PSEG1_MASK (0x380000U)
2306#define CAN_CTRL1_PSEG1_SHIFT (19U)
2307#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
2308#define CAN_CTRL1_RJW_MASK (0xC00000U)
2309#define CAN_CTRL1_RJW_SHIFT (22U)
2310#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
2311#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
2312#define CAN_CTRL1_PRESDIV_SHIFT (24U)
2313#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
2314
2316#define CAN_TIMER_TIMER_MASK (0xFFFFU)
2317#define CAN_TIMER_TIMER_SHIFT (0U)
2318#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
2319
2321#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
2322#define CAN_RXMGMASK_MG_SHIFT (0U)
2323#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
2324
2326#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
2327#define CAN_RX14MASK_RX14M_SHIFT (0U)
2328#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
2329
2331#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
2332#define CAN_RX15MASK_RX15M_SHIFT (0U)
2333#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
2334
2336#define CAN_ECR_TXERRCNT_MASK (0xFFU)
2337#define CAN_ECR_TXERRCNT_SHIFT (0U)
2338#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
2339#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
2340#define CAN_ECR_RXERRCNT_SHIFT (8U)
2341#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
2342
2344#define CAN_ESR1_WAKINT_MASK (0x1U)
2345#define CAN_ESR1_WAKINT_SHIFT (0U)
2346#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
2347#define CAN_ESR1_ERRINT_MASK (0x2U)
2348#define CAN_ESR1_ERRINT_SHIFT (1U)
2349#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
2350#define CAN_ESR1_BOFFINT_MASK (0x4U)
2351#define CAN_ESR1_BOFFINT_SHIFT (2U)
2352#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
2353#define CAN_ESR1_RX_MASK (0x8U)
2354#define CAN_ESR1_RX_SHIFT (3U)
2355#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
2356#define CAN_ESR1_FLTCONF_MASK (0x30U)
2357#define CAN_ESR1_FLTCONF_SHIFT (4U)
2358#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
2359#define CAN_ESR1_TX_MASK (0x40U)
2360#define CAN_ESR1_TX_SHIFT (6U)
2361#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
2362#define CAN_ESR1_IDLE_MASK (0x80U)
2363#define CAN_ESR1_IDLE_SHIFT (7U)
2364#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
2365#define CAN_ESR1_RXWRN_MASK (0x100U)
2366#define CAN_ESR1_RXWRN_SHIFT (8U)
2367#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
2368#define CAN_ESR1_TXWRN_MASK (0x200U)
2369#define CAN_ESR1_TXWRN_SHIFT (9U)
2370#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
2371#define CAN_ESR1_STFERR_MASK (0x400U)
2372#define CAN_ESR1_STFERR_SHIFT (10U)
2373#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
2374#define CAN_ESR1_FRMERR_MASK (0x800U)
2375#define CAN_ESR1_FRMERR_SHIFT (11U)
2376#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
2377#define CAN_ESR1_CRCERR_MASK (0x1000U)
2378#define CAN_ESR1_CRCERR_SHIFT (12U)
2379#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
2380#define CAN_ESR1_ACKERR_MASK (0x2000U)
2381#define CAN_ESR1_ACKERR_SHIFT (13U)
2382#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
2383#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
2384#define CAN_ESR1_BIT0ERR_SHIFT (14U)
2385#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
2386#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
2387#define CAN_ESR1_BIT1ERR_SHIFT (15U)
2388#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
2389#define CAN_ESR1_RWRNINT_MASK (0x10000U)
2390#define CAN_ESR1_RWRNINT_SHIFT (16U)
2391#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
2392#define CAN_ESR1_TWRNINT_MASK (0x20000U)
2393#define CAN_ESR1_TWRNINT_SHIFT (17U)
2394#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
2395#define CAN_ESR1_SYNCH_MASK (0x40000U)
2396#define CAN_ESR1_SYNCH_SHIFT (18U)
2397#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
2398
2400#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
2401#define CAN_IMASK1_BUFLM_SHIFT (0U)
2402#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
2403
2405#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
2406#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
2407#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
2408#define CAN_IFLAG1_BUF5I_MASK (0x20U)
2409#define CAN_IFLAG1_BUF5I_SHIFT (5U)
2410#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
2411#define CAN_IFLAG1_BUF6I_MASK (0x40U)
2412#define CAN_IFLAG1_BUF6I_SHIFT (6U)
2413#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
2414#define CAN_IFLAG1_BUF7I_MASK (0x80U)
2415#define CAN_IFLAG1_BUF7I_SHIFT (7U)
2416#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
2417#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
2418#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
2419#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
2420
2422#define CAN_CTRL2_EACEN_MASK (0x10000U)
2423#define CAN_CTRL2_EACEN_SHIFT (16U)
2424#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
2425#define CAN_CTRL2_RRS_MASK (0x20000U)
2426#define CAN_CTRL2_RRS_SHIFT (17U)
2427#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
2428#define CAN_CTRL2_MRP_MASK (0x40000U)
2429#define CAN_CTRL2_MRP_SHIFT (18U)
2430#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
2431#define CAN_CTRL2_TASD_MASK (0xF80000U)
2432#define CAN_CTRL2_TASD_SHIFT (19U)
2433#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
2434#define CAN_CTRL2_RFFN_MASK (0xF000000U)
2435#define CAN_CTRL2_RFFN_SHIFT (24U)
2436#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
2437#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
2438#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
2439#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
2440
2442#define CAN_ESR2_IMB_MASK (0x2000U)
2443#define CAN_ESR2_IMB_SHIFT (13U)
2444#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
2445#define CAN_ESR2_VPS_MASK (0x4000U)
2446#define CAN_ESR2_VPS_SHIFT (14U)
2447#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
2448#define CAN_ESR2_LPTM_MASK (0x7F0000U)
2449#define CAN_ESR2_LPTM_SHIFT (16U)
2450#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
2451
2453#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
2454#define CAN_CRCR_TXCRC_SHIFT (0U)
2455#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
2456#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
2457#define CAN_CRCR_MBCRC_SHIFT (16U)
2458#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
2459
2461#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
2462#define CAN_RXFGMASK_FGM_SHIFT (0U)
2463#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
2464
2466#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
2467#define CAN_RXFIR_IDHIT_SHIFT (0U)
2468#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
2469
2471#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
2472#define CAN_CS_TIME_STAMP_SHIFT (0U)
2473#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
2474#define CAN_CS_DLC_MASK (0xF0000U)
2475#define CAN_CS_DLC_SHIFT (16U)
2476#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
2477#define CAN_CS_RTR_MASK (0x100000U)
2478#define CAN_CS_RTR_SHIFT (20U)
2479#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
2480#define CAN_CS_IDE_MASK (0x200000U)
2481#define CAN_CS_IDE_SHIFT (21U)
2482#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
2483#define CAN_CS_SRR_MASK (0x400000U)
2484#define CAN_CS_SRR_SHIFT (22U)
2485#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
2486#define CAN_CS_CODE_MASK (0xF000000U)
2487#define CAN_CS_CODE_SHIFT (24U)
2488#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
2489
2490/* The count of CAN_CS */
2491#define CAN_CS_COUNT (16U)
2492
2494#define CAN_ID_EXT_MASK (0x3FFFFU)
2495#define CAN_ID_EXT_SHIFT (0U)
2496#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
2497#define CAN_ID_STD_MASK (0x1FFC0000U)
2498#define CAN_ID_STD_SHIFT (18U)
2499#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
2500#define CAN_ID_PRIO_MASK (0xE0000000U)
2501#define CAN_ID_PRIO_SHIFT (29U)
2502#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
2503
2504/* The count of CAN_ID */
2505#define CAN_ID_COUNT (16U)
2506
2508#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
2509#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
2510#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
2511#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
2512#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
2513#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
2514#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
2515#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
2516#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
2517#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
2518#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
2519#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
2520
2521/* The count of CAN_WORD0 */
2522#define CAN_WORD0_COUNT (16U)
2523
2525#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
2526#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
2527#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
2528#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
2529#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
2530#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
2531#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
2532#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
2533#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
2534#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
2535#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
2536#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
2537
2538/* The count of CAN_WORD1 */
2539#define CAN_WORD1_COUNT (16U)
2540
2542#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
2543#define CAN_RXIMR_MI_SHIFT (0U)
2544#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
2545
2546/* The count of CAN_RXIMR */
2547#define CAN_RXIMR_COUNT (16U)
2548
2549
2552 /* end of group CAN_Register_Masks */
2553
2554
2555/* CAN - Peripheral instance base addresses */
2557#define CAN0_BASE (0x40024000u)
2559#define CAN0 ((CAN_Type *)CAN0_BASE)
2561#define CAN1_BASE (0x400A4000u)
2563#define CAN1 ((CAN_Type *)CAN1_BASE)
2565#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2567#define CAN_BASE_PTRS { CAN0, CAN1 }
2569#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
2570#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
2571#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
2572#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
2573#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
2574#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
2575
2578 /* end of group CAN_Peripheral_Access_Layer */
2579
2580
2581/* ----------------------------------------------------------------------------
2582 -- CAU Peripheral Access Layer
2583 ---------------------------------------------------------------------------- */
2584
2591typedef struct {
2592 __O uint32_t DIRECT[16];
2593 uint8_t RESERVED_0[2048];
2594 __O uint32_t LDR_CASR;
2595 __O uint32_t LDR_CAA;
2596 __O uint32_t LDR_CA[9];
2597 uint8_t RESERVED_1[20];
2598 __I uint32_t STR_CASR;
2599 __I uint32_t STR_CAA;
2600 __I uint32_t STR_CA[9];
2601 uint8_t RESERVED_2[20];
2602 __O uint32_t ADR_CASR;
2603 __O uint32_t ADR_CAA;
2604 __O uint32_t ADR_CA[9];
2605 uint8_t RESERVED_3[20];
2606 __O uint32_t RADR_CASR;
2607 __O uint32_t RADR_CAA;
2608 __O uint32_t RADR_CA[9];
2609 uint8_t RESERVED_4[84];
2610 __O uint32_t XOR_CASR;
2611 __O uint32_t XOR_CAA;
2612 __O uint32_t XOR_CA[9];
2613 uint8_t RESERVED_5[20];
2614 __O uint32_t ROTL_CASR;
2615 __O uint32_t ROTL_CAA;
2616 __O uint32_t ROTL_CA[9];
2617 uint8_t RESERVED_6[276];
2618 __O uint32_t AESC_CASR;
2619 __O uint32_t AESC_CAA;
2620 __O uint32_t AESC_CA[9];
2621 uint8_t RESERVED_7[20];
2622 __O uint32_t AESIC_CASR;
2623 __O uint32_t AESIC_CAA;
2624 __O uint32_t AESIC_CA[9];
2625} CAU_Type;
2626
2627/* ----------------------------------------------------------------------------
2628 -- CAU Register Masks
2629 ---------------------------------------------------------------------------- */
2630
2637#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
2638#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
2639#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
2640#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
2641#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
2642#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
2643#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
2644#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
2645#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
2646#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
2647#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
2648#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
2649#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
2650#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
2651#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
2652#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
2653#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
2654#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
2655#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
2656#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
2657#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
2658#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
2659#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
2660#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
2661#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
2662#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
2663#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
2664#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
2665#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
2666#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
2667#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
2668#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
2669#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
2670#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
2671#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
2672#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
2673#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
2674#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
2675#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
2676#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
2677#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
2678#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
2679#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
2680#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
2681#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
2682#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
2683#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
2684#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
2685
2686/* The count of CAU_DIRECT */
2687#define CAU_DIRECT_COUNT (16U)
2688
2690#define CAU_LDR_CASR_IC_MASK (0x1U)
2691#define CAU_LDR_CASR_IC_SHIFT (0U)
2692#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
2693#define CAU_LDR_CASR_DPE_MASK (0x2U)
2694#define CAU_LDR_CASR_DPE_SHIFT (1U)
2695#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
2696#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
2697#define CAU_LDR_CASR_VER_SHIFT (28U)
2698#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
2699
2701#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
2702#define CAU_LDR_CAA_ACC_SHIFT (0U)
2703#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
2704
2706#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
2707#define CAU_LDR_CA_CA0_SHIFT (0U)
2708#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
2709#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
2710#define CAU_LDR_CA_CA1_SHIFT (0U)
2711#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
2712#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
2713#define CAU_LDR_CA_CA2_SHIFT (0U)
2714#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
2715#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
2716#define CAU_LDR_CA_CA3_SHIFT (0U)
2717#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
2718#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
2719#define CAU_LDR_CA_CA4_SHIFT (0U)
2720#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
2721#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
2722#define CAU_LDR_CA_CA5_SHIFT (0U)
2723#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
2724#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
2725#define CAU_LDR_CA_CA6_SHIFT (0U)
2726#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
2727#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
2728#define CAU_LDR_CA_CA7_SHIFT (0U)
2729#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
2730#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
2731#define CAU_LDR_CA_CA8_SHIFT (0U)
2732#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
2733
2734/* The count of CAU_LDR_CA */
2735#define CAU_LDR_CA_COUNT (9U)
2736
2738#define CAU_STR_CASR_IC_MASK (0x1U)
2739#define CAU_STR_CASR_IC_SHIFT (0U)
2740#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
2741#define CAU_STR_CASR_DPE_MASK (0x2U)
2742#define CAU_STR_CASR_DPE_SHIFT (1U)
2743#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
2744#define CAU_STR_CASR_VER_MASK (0xF0000000U)
2745#define CAU_STR_CASR_VER_SHIFT (28U)
2746#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
2747
2749#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
2750#define CAU_STR_CAA_ACC_SHIFT (0U)
2751#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
2752
2754#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
2755#define CAU_STR_CA_CA0_SHIFT (0U)
2756#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
2757#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
2758#define CAU_STR_CA_CA1_SHIFT (0U)
2759#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
2760#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
2761#define CAU_STR_CA_CA2_SHIFT (0U)
2762#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
2763#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
2764#define CAU_STR_CA_CA3_SHIFT (0U)
2765#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
2766#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
2767#define CAU_STR_CA_CA4_SHIFT (0U)
2768#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
2769#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
2770#define CAU_STR_CA_CA5_SHIFT (0U)
2771#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
2772#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
2773#define CAU_STR_CA_CA6_SHIFT (0U)
2774#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
2775#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
2776#define CAU_STR_CA_CA7_SHIFT (0U)
2777#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
2778#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
2779#define CAU_STR_CA_CA8_SHIFT (0U)
2780#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
2781
2782/* The count of CAU_STR_CA */
2783#define CAU_STR_CA_COUNT (9U)
2784
2786#define CAU_ADR_CASR_IC_MASK (0x1U)
2787#define CAU_ADR_CASR_IC_SHIFT (0U)
2788#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
2789#define CAU_ADR_CASR_DPE_MASK (0x2U)
2790#define CAU_ADR_CASR_DPE_SHIFT (1U)
2791#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
2792#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
2793#define CAU_ADR_CASR_VER_SHIFT (28U)
2794#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
2795
2797#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
2798#define CAU_ADR_CAA_ACC_SHIFT (0U)
2799#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
2800
2802#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
2803#define CAU_ADR_CA_CA0_SHIFT (0U)
2804#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
2805#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
2806#define CAU_ADR_CA_CA1_SHIFT (0U)
2807#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
2808#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
2809#define CAU_ADR_CA_CA2_SHIFT (0U)
2810#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
2811#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
2812#define CAU_ADR_CA_CA3_SHIFT (0U)
2813#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
2814#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
2815#define CAU_ADR_CA_CA4_SHIFT (0U)
2816#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
2817#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
2818#define CAU_ADR_CA_CA5_SHIFT (0U)
2819#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
2820#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
2821#define CAU_ADR_CA_CA6_SHIFT (0U)
2822#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
2823#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
2824#define CAU_ADR_CA_CA7_SHIFT (0U)
2825#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
2826#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
2827#define CAU_ADR_CA_CA8_SHIFT (0U)
2828#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
2829
2830/* The count of CAU_ADR_CA */
2831#define CAU_ADR_CA_COUNT (9U)
2832
2834#define CAU_RADR_CASR_IC_MASK (0x1U)
2835#define CAU_RADR_CASR_IC_SHIFT (0U)
2836#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
2837#define CAU_RADR_CASR_DPE_MASK (0x2U)
2838#define CAU_RADR_CASR_DPE_SHIFT (1U)
2839#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
2840#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
2841#define CAU_RADR_CASR_VER_SHIFT (28U)
2842#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
2843
2845#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
2846#define CAU_RADR_CAA_ACC_SHIFT (0U)
2847#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
2848
2850#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
2851#define CAU_RADR_CA_CA0_SHIFT (0U)
2852#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
2853#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
2854#define CAU_RADR_CA_CA1_SHIFT (0U)
2855#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
2856#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
2857#define CAU_RADR_CA_CA2_SHIFT (0U)
2858#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
2859#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
2860#define CAU_RADR_CA_CA3_SHIFT (0U)
2861#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
2862#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
2863#define CAU_RADR_CA_CA4_SHIFT (0U)
2864#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
2865#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
2866#define CAU_RADR_CA_CA5_SHIFT (0U)
2867#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
2868#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
2869#define CAU_RADR_CA_CA6_SHIFT (0U)
2870#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
2871#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
2872#define CAU_RADR_CA_CA7_SHIFT (0U)
2873#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
2874#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
2875#define CAU_RADR_CA_CA8_SHIFT (0U)
2876#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
2877
2878/* The count of CAU_RADR_CA */
2879#define CAU_RADR_CA_COUNT (9U)
2880
2882#define CAU_XOR_CASR_IC_MASK (0x1U)
2883#define CAU_XOR_CASR_IC_SHIFT (0U)
2884#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
2885#define CAU_XOR_CASR_DPE_MASK (0x2U)
2886#define CAU_XOR_CASR_DPE_SHIFT (1U)
2887#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
2888#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
2889#define CAU_XOR_CASR_VER_SHIFT (28U)
2890#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
2891
2893#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
2894#define CAU_XOR_CAA_ACC_SHIFT (0U)
2895#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
2896
2898#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
2899#define CAU_XOR_CA_CA0_SHIFT (0U)
2900#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
2901#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
2902#define CAU_XOR_CA_CA1_SHIFT (0U)
2903#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
2904#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
2905#define CAU_XOR_CA_CA2_SHIFT (0U)
2906#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
2907#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
2908#define CAU_XOR_CA_CA3_SHIFT (0U)
2909#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
2910#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
2911#define CAU_XOR_CA_CA4_SHIFT (0U)
2912#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
2913#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
2914#define CAU_XOR_CA_CA5_SHIFT (0U)
2915#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
2916#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
2917#define CAU_XOR_CA_CA6_SHIFT (0U)
2918#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
2919#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
2920#define CAU_XOR_CA_CA7_SHIFT (0U)
2921#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
2922#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
2923#define CAU_XOR_CA_CA8_SHIFT (0U)
2924#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
2925
2926/* The count of CAU_XOR_CA */
2927#define CAU_XOR_CA_COUNT (9U)
2928
2930#define CAU_ROTL_CASR_IC_MASK (0x1U)
2931#define CAU_ROTL_CASR_IC_SHIFT (0U)
2932#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
2933#define CAU_ROTL_CASR_DPE_MASK (0x2U)
2934#define CAU_ROTL_CASR_DPE_SHIFT (1U)
2935#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
2936#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
2937#define CAU_ROTL_CASR_VER_SHIFT (28U)
2938#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
2939
2941#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
2942#define CAU_ROTL_CAA_ACC_SHIFT (0U)
2943#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
2944
2946#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
2947#define CAU_ROTL_CA_CA0_SHIFT (0U)
2948#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
2949#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
2950#define CAU_ROTL_CA_CA1_SHIFT (0U)
2951#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
2952#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
2953#define CAU_ROTL_CA_CA2_SHIFT (0U)
2954#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
2955#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
2956#define CAU_ROTL_CA_CA3_SHIFT (0U)
2957#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
2958#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
2959#define CAU_ROTL_CA_CA4_SHIFT (0U)
2960#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
2961#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
2962#define CAU_ROTL_CA_CA5_SHIFT (0U)
2963#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
2964#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
2965#define CAU_ROTL_CA_CA6_SHIFT (0U)
2966#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
2967#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
2968#define CAU_ROTL_CA_CA7_SHIFT (0U)
2969#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
2970#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
2971#define CAU_ROTL_CA_CA8_SHIFT (0U)
2972#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
2973
2974/* The count of CAU_ROTL_CA */
2975#define CAU_ROTL_CA_COUNT (9U)
2976
2978#define CAU_AESC_CASR_IC_MASK (0x1U)
2979#define CAU_AESC_CASR_IC_SHIFT (0U)
2980#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
2981#define CAU_AESC_CASR_DPE_MASK (0x2U)
2982#define CAU_AESC_CASR_DPE_SHIFT (1U)
2983#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
2984#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
2985#define CAU_AESC_CASR_VER_SHIFT (28U)
2986#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
2987
2989#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
2990#define CAU_AESC_CAA_ACC_SHIFT (0U)
2991#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
2992
2994#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
2995#define CAU_AESC_CA_CA0_SHIFT (0U)
2996#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
2997#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
2998#define CAU_AESC_CA_CA1_SHIFT (0U)
2999#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
3000#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
3001#define CAU_AESC_CA_CA2_SHIFT (0U)
3002#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
3003#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
3004#define CAU_AESC_CA_CA3_SHIFT (0U)
3005#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
3006#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
3007#define CAU_AESC_CA_CA4_SHIFT (0U)
3008#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
3009#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
3010#define CAU_AESC_CA_CA5_SHIFT (0U)
3011#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
3012#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
3013#define CAU_AESC_CA_CA6_SHIFT (0U)
3014#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
3015#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
3016#define CAU_AESC_CA_CA7_SHIFT (0U)
3017#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
3018#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
3019#define CAU_AESC_CA_CA8_SHIFT (0U)
3020#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
3021
3022/* The count of CAU_AESC_CA */
3023#define CAU_AESC_CA_COUNT (9U)
3024
3026#define CAU_AESIC_CASR_IC_MASK (0x1U)
3027#define CAU_AESIC_CASR_IC_SHIFT (0U)
3028#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
3029#define CAU_AESIC_CASR_DPE_MASK (0x2U)
3030#define CAU_AESIC_CASR_DPE_SHIFT (1U)
3031#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
3032#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
3033#define CAU_AESIC_CASR_VER_SHIFT (28U)
3034#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
3035
3037#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
3038#define CAU_AESIC_CAA_ACC_SHIFT (0U)
3039#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
3040
3042#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
3043#define CAU_AESIC_CA_CA0_SHIFT (0U)
3044#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
3045#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
3046#define CAU_AESIC_CA_CA1_SHIFT (0U)
3047#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
3048#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
3049#define CAU_AESIC_CA_CA2_SHIFT (0U)
3050#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
3051#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
3052#define CAU_AESIC_CA_CA3_SHIFT (0U)
3053#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
3054#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
3055#define CAU_AESIC_CA_CA4_SHIFT (0U)
3056#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
3057#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
3058#define CAU_AESIC_CA_CA5_SHIFT (0U)
3059#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
3060#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
3061#define CAU_AESIC_CA_CA6_SHIFT (0U)
3062#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
3063#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
3064#define CAU_AESIC_CA_CA7_SHIFT (0U)
3065#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
3066#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
3067#define CAU_AESIC_CA_CA8_SHIFT (0U)
3068#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
3069
3070/* The count of CAU_AESIC_CA */
3071#define CAU_AESIC_CA_COUNT (9U)
3072
3073
3076 /* end of group CAU_Register_Masks */
3077
3078
3079/* CAU - Peripheral instance base addresses */
3081#define CAU_BASE (0xE0081000u)
3083#define CAU ((CAU_Type *)CAU_BASE)
3085#define CAU_BASE_ADDRS { CAU_BASE }
3087#define CAU_BASE_PTRS { CAU }
3088
3091 /* end of group CAU_Peripheral_Access_Layer */
3092
3093
3094/* ----------------------------------------------------------------------------
3095 -- CMP Peripheral Access Layer
3096 ---------------------------------------------------------------------------- */
3097
3104typedef struct {
3105 __IO uint8_t CR0;
3106 __IO uint8_t CR1;
3107 __IO uint8_t FPR;
3108 __IO uint8_t SCR;
3109 __IO uint8_t DACCR;
3110 __IO uint8_t MUXCR;
3111} CMP_Type;
3112
3113/* ----------------------------------------------------------------------------
3114 -- CMP Register Masks
3115 ---------------------------------------------------------------------------- */
3116
3123#define CMP_CR0_HYSTCTR_MASK (0x3U)
3124#define CMP_CR0_HYSTCTR_SHIFT (0U)
3125#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
3126#define CMP_CR0_FILTER_CNT_MASK (0x70U)
3127#define CMP_CR0_FILTER_CNT_SHIFT (4U)
3128#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
3129
3131#define CMP_CR1_EN_MASK (0x1U)
3132#define CMP_CR1_EN_SHIFT (0U)
3133#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
3134#define CMP_CR1_OPE_MASK (0x2U)
3135#define CMP_CR1_OPE_SHIFT (1U)
3136#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
3137#define CMP_CR1_COS_MASK (0x4U)
3138#define CMP_CR1_COS_SHIFT (2U)
3139#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
3140#define CMP_CR1_INV_MASK (0x8U)
3141#define CMP_CR1_INV_SHIFT (3U)
3142#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
3143#define CMP_CR1_PMODE_MASK (0x10U)
3144#define CMP_CR1_PMODE_SHIFT (4U)
3145#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
3146#define CMP_CR1_WE_MASK (0x40U)
3147#define CMP_CR1_WE_SHIFT (6U)
3148#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
3149#define CMP_CR1_SE_MASK (0x80U)
3150#define CMP_CR1_SE_SHIFT (7U)
3151#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
3152
3154#define CMP_FPR_FILT_PER_MASK (0xFFU)
3155#define CMP_FPR_FILT_PER_SHIFT (0U)
3156#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
3157
3159#define CMP_SCR_COUT_MASK (0x1U)
3160#define CMP_SCR_COUT_SHIFT (0U)
3161#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
3162#define CMP_SCR_CFF_MASK (0x2U)
3163#define CMP_SCR_CFF_SHIFT (1U)
3164#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
3165#define CMP_SCR_CFR_MASK (0x4U)
3166#define CMP_SCR_CFR_SHIFT (2U)
3167#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
3168#define CMP_SCR_IEF_MASK (0x8U)
3169#define CMP_SCR_IEF_SHIFT (3U)
3170#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
3171#define CMP_SCR_IER_MASK (0x10U)
3172#define CMP_SCR_IER_SHIFT (4U)
3173#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
3174#define CMP_SCR_DMAEN_MASK (0x40U)
3175#define CMP_SCR_DMAEN_SHIFT (6U)
3176#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
3177
3179#define CMP_DACCR_VOSEL_MASK (0x3FU)
3180#define CMP_DACCR_VOSEL_SHIFT (0U)
3181#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
3182#define CMP_DACCR_VRSEL_MASK (0x40U)
3183#define CMP_DACCR_VRSEL_SHIFT (6U)
3184#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
3185#define CMP_DACCR_DACEN_MASK (0x80U)
3186#define CMP_DACCR_DACEN_SHIFT (7U)
3187#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
3188
3190#define CMP_MUXCR_MSEL_MASK (0x7U)
3191#define CMP_MUXCR_MSEL_SHIFT (0U)
3192#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
3193#define CMP_MUXCR_PSEL_MASK (0x38U)
3194#define CMP_MUXCR_PSEL_SHIFT (3U)
3195#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
3196#define CMP_MUXCR_PSTM_MASK (0x40U)
3197#define CMP_MUXCR_PSTM_SHIFT (6U)
3198#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
3199
3200
3203 /* end of group CMP_Register_Masks */
3204
3205
3206/* CMP - Peripheral instance base addresses */
3208#define CMP0_BASE (0x40073000u)
3210#define CMP0 ((CMP_Type *)CMP0_BASE)
3212#define CMP1_BASE (0x40073008u)
3214#define CMP1 ((CMP_Type *)CMP1_BASE)
3216#define CMP2_BASE (0x40073010u)
3218#define CMP2 ((CMP_Type *)CMP2_BASE)
3220#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
3222#define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
3224#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
3225
3228 /* end of group CMP_Peripheral_Access_Layer */
3229
3230
3231/* ----------------------------------------------------------------------------
3232 -- CMT Peripheral Access Layer
3233 ---------------------------------------------------------------------------- */
3234
3241typedef struct {
3242 __IO uint8_t CGH1;
3243 __IO uint8_t CGL1;
3244 __IO uint8_t CGH2;
3245 __IO uint8_t CGL2;
3246 __IO uint8_t OC;
3247 __IO uint8_t MSC;
3248 __IO uint8_t CMD1;
3249 __IO uint8_t CMD2;
3250 __IO uint8_t CMD3;
3251 __IO uint8_t CMD4;
3252 __IO uint8_t PPS;
3253 __IO uint8_t DMA;
3254} CMT_Type;
3255
3256/* ----------------------------------------------------------------------------
3257 -- CMT Register Masks
3258 ---------------------------------------------------------------------------- */
3259
3266#define CMT_CGH1_PH_MASK (0xFFU)
3267#define CMT_CGH1_PH_SHIFT (0U)
3268#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
3269
3271#define CMT_CGL1_PL_MASK (0xFFU)
3272#define CMT_CGL1_PL_SHIFT (0U)
3273#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
3274
3276#define CMT_CGH2_SH_MASK (0xFFU)
3277#define CMT_CGH2_SH_SHIFT (0U)
3278#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
3279
3281#define CMT_CGL2_SL_MASK (0xFFU)
3282#define CMT_CGL2_SL_SHIFT (0U)
3283#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
3284
3286#define CMT_OC_IROPEN_MASK (0x20U)
3287#define CMT_OC_IROPEN_SHIFT (5U)
3288#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
3289#define CMT_OC_CMTPOL_MASK (0x40U)
3290#define CMT_OC_CMTPOL_SHIFT (6U)
3291#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
3292#define CMT_OC_IROL_MASK (0x80U)
3293#define CMT_OC_IROL_SHIFT (7U)
3294#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
3295
3297#define CMT_MSC_MCGEN_MASK (0x1U)
3298#define CMT_MSC_MCGEN_SHIFT (0U)
3299#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
3300#define CMT_MSC_EOCIE_MASK (0x2U)
3301#define CMT_MSC_EOCIE_SHIFT (1U)
3302#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
3303#define CMT_MSC_FSK_MASK (0x4U)
3304#define CMT_MSC_FSK_SHIFT (2U)
3305#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
3306#define CMT_MSC_BASE_MASK (0x8U)
3307#define CMT_MSC_BASE_SHIFT (3U)
3308#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
3309#define CMT_MSC_EXSPC_MASK (0x10U)
3310#define CMT_MSC_EXSPC_SHIFT (4U)
3311#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
3312#define CMT_MSC_CMTDIV_MASK (0x60U)
3313#define CMT_MSC_CMTDIV_SHIFT (5U)
3314#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
3315#define CMT_MSC_EOCF_MASK (0x80U)
3316#define CMT_MSC_EOCF_SHIFT (7U)
3317#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
3318
3320#define CMT_CMD1_MB_MASK (0xFFU)
3321#define CMT_CMD1_MB_SHIFT (0U)
3322#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
3323
3325#define CMT_CMD2_MB_MASK (0xFFU)
3326#define CMT_CMD2_MB_SHIFT (0U)
3327#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
3328
3330#define CMT_CMD3_SB_MASK (0xFFU)
3331#define CMT_CMD3_SB_SHIFT (0U)
3332#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
3333
3335#define CMT_CMD4_SB_MASK (0xFFU)
3336#define CMT_CMD4_SB_SHIFT (0U)
3337#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
3338
3340#define CMT_PPS_PPSDIV_MASK (0xFU)
3341#define CMT_PPS_PPSDIV_SHIFT (0U)
3342#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
3343
3345#define CMT_DMA_DMA_MASK (0x1U)
3346#define CMT_DMA_DMA_SHIFT (0U)
3347#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
3348
3349
3352 /* end of group CMT_Register_Masks */
3353
3354
3355/* CMT - Peripheral instance base addresses */
3357#define CMT_BASE (0x40062000u)
3359#define CMT ((CMT_Type *)CMT_BASE)
3361#define CMT_BASE_ADDRS { CMT_BASE }
3363#define CMT_BASE_PTRS { CMT }
3365#define CMT_IRQS { CMT_IRQn }
3366
3369 /* end of group CMT_Peripheral_Access_Layer */
3370
3371
3372/* ----------------------------------------------------------------------------
3373 -- CRC Peripheral Access Layer
3374 ---------------------------------------------------------------------------- */
3375
3382typedef struct {
3383 union { /* offset: 0x0 */
3384 struct { /* offset: 0x0 */
3385 __IO uint16_t CRCL;
3386 __IO uint16_t CRCH;
3387 } ACCESS16BIT;
3388 __IO uint32_t CRC;
3389 struct { /* offset: 0x0 */
3390 __IO uint8_t CRCLL;
3391 __IO uint8_t CRCLU;
3392 __IO uint8_t CRCHL;
3393 __IO uint8_t CRCHU;
3394 } ACCESS8BIT;
3395 };
3396 union { /* offset: 0x4 */
3397 struct { /* offset: 0x4 */
3398 __IO uint16_t GPOLYL;
3399 __IO uint16_t GPOLYH;
3400 } GPOLY_ACCESS16BIT;
3401 __IO uint32_t GPOLY;
3402 struct { /* offset: 0x4 */
3403 __IO uint8_t GPOLYLL;
3404 __IO uint8_t GPOLYLU;
3405 __IO uint8_t GPOLYHL;
3406 __IO uint8_t GPOLYHU;
3407 } GPOLY_ACCESS8BIT;
3408 };
3409 union { /* offset: 0x8 */
3410 __IO uint32_t CTRL;
3411 struct { /* offset: 0x8 */
3412 uint8_t RESERVED_0[3];
3413 __IO uint8_t CTRLHU;
3414 } CTRL_ACCESS8BIT;
3415 };
3416} CRC_Type;
3417
3418/* ----------------------------------------------------------------------------
3419 -- CRC Register Masks
3420 ---------------------------------------------------------------------------- */
3421
3428#define CRC_CRCL_CRCL_MASK (0xFFFFU)
3429#define CRC_CRCL_CRCL_SHIFT (0U)
3430#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK)
3431
3433#define CRC_CRCH_CRCH_MASK (0xFFFFU)
3434#define CRC_CRCH_CRCH_SHIFT (0U)
3435#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK)
3436
3438#define CRC_CRC_LL_MASK (0xFFU)
3439#define CRC_CRC_LL_SHIFT (0U)
3440#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK)
3441#define CRC_CRC_LU_MASK (0xFF00U)
3442#define CRC_CRC_LU_SHIFT (8U)
3443#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK)
3444#define CRC_CRC_HL_MASK (0xFF0000U)
3445#define CRC_CRC_HL_SHIFT (16U)
3446#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK)
3447#define CRC_CRC_HU_MASK (0xFF000000U)
3448#define CRC_CRC_HU_SHIFT (24U)
3449#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK)
3450
3452#define CRC_CRCLL_CRCLL_MASK (0xFFU)
3453#define CRC_CRCLL_CRCLL_SHIFT (0U)
3454#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK)
3455
3457#define CRC_CRCLU_CRCLU_MASK (0xFFU)
3458#define CRC_CRCLU_CRCLU_SHIFT (0U)
3459#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK)
3460
3462#define CRC_CRCHL_CRCHL_MASK (0xFFU)
3463#define CRC_CRCHL_CRCHL_SHIFT (0U)
3464#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK)
3465
3467#define CRC_CRCHU_CRCHU_MASK (0xFFU)
3468#define CRC_CRCHU_CRCHU_SHIFT (0U)
3469#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK)
3470
3472#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
3473#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
3474#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
3475
3477#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
3478#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
3479#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
3480
3482#define CRC_GPOLY_LOW_MASK (0xFFFFU)
3483#define CRC_GPOLY_LOW_SHIFT (0U)
3484#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
3485#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
3486#define CRC_GPOLY_HIGH_SHIFT (16U)
3487#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
3488
3490#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
3491#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
3492#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
3493
3495#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
3496#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
3497#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
3498
3500#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
3501#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
3502#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
3503
3505#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
3506#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
3507#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
3508
3510#define CRC_CTRL_TCRC_MASK (0x1000000U)
3511#define CRC_CTRL_TCRC_SHIFT (24U)
3512#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
3513#define CRC_CTRL_WAS_MASK (0x2000000U)
3514#define CRC_CTRL_WAS_SHIFT (25U)
3515#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
3516#define CRC_CTRL_FXOR_MASK (0x4000000U)
3517#define CRC_CTRL_FXOR_SHIFT (26U)
3518#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
3519#define CRC_CTRL_TOTR_MASK (0x30000000U)
3520#define CRC_CTRL_TOTR_SHIFT (28U)
3521#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
3522#define CRC_CTRL_TOT_MASK (0xC0000000U)
3523#define CRC_CTRL_TOT_SHIFT (30U)
3524#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
3525
3527#define CRC_CTRLHU_TCRC_MASK (0x1U)
3528#define CRC_CTRLHU_TCRC_SHIFT (0U)
3529#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
3530#define CRC_CTRLHU_WAS_MASK (0x2U)
3531#define CRC_CTRLHU_WAS_SHIFT (1U)
3532#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
3533#define CRC_CTRLHU_FXOR_MASK (0x4U)
3534#define CRC_CTRLHU_FXOR_SHIFT (2U)
3535#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
3536#define CRC_CTRLHU_TOTR_MASK (0x30U)
3537#define CRC_CTRLHU_TOTR_SHIFT (4U)
3538#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
3539#define CRC_CTRLHU_TOT_MASK (0xC0U)
3540#define CRC_CTRLHU_TOT_SHIFT (6U)
3541#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
3542
3543
3546 /* end of group CRC_Register_Masks */
3547
3548
3549/* CRC - Peripheral instance base addresses */
3551#define CRC_BASE (0x40032000u)
3553#define CRC0 ((CRC_Type *)CRC_BASE)
3555#define CRC_BASE_ADDRS { CRC_BASE }
3557#define CRC_BASE_PTRS { CRC0 }
3558
3561 /* end of group CRC_Peripheral_Access_Layer */
3562
3563
3564/* ----------------------------------------------------------------------------
3565 -- DAC Peripheral Access Layer
3566 ---------------------------------------------------------------------------- */
3567
3574typedef struct {
3575 struct { /* offset: 0x0, array step: 0x2 */
3576 __IO uint8_t DATL;
3577 __IO uint8_t DATH;
3578 } DAT[16];
3579 __IO uint8_t SR;
3580 __IO uint8_t C0;
3581 __IO uint8_t C1;
3582 __IO uint8_t C2;
3583} DAC_Type;
3584
3585/* ----------------------------------------------------------------------------
3586 -- DAC Register Masks
3587 ---------------------------------------------------------------------------- */
3588
3595#define DAC_DATL_DATA0_MASK (0xFFU)
3596#define DAC_DATL_DATA0_SHIFT (0U)
3597#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
3598
3599/* The count of DAC_DATL */
3600#define DAC_DATL_COUNT (16U)
3601
3603#define DAC_DATH_DATA1_MASK (0xFU)
3604#define DAC_DATH_DATA1_SHIFT (0U)
3605#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
3606
3607/* The count of DAC_DATH */
3608#define DAC_DATH_COUNT (16U)
3609
3611#define DAC_SR_DACBFRPBF_MASK (0x1U)
3612#define DAC_SR_DACBFRPBF_SHIFT (0U)
3613#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
3614#define DAC_SR_DACBFRPTF_MASK (0x2U)
3615#define DAC_SR_DACBFRPTF_SHIFT (1U)
3616#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
3617#define DAC_SR_DACBFWMF_MASK (0x4U)
3618#define DAC_SR_DACBFWMF_SHIFT (2U)
3619#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
3620
3622#define DAC_C0_DACBBIEN_MASK (0x1U)
3623#define DAC_C0_DACBBIEN_SHIFT (0U)
3624#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
3625#define DAC_C0_DACBTIEN_MASK (0x2U)
3626#define DAC_C0_DACBTIEN_SHIFT (1U)
3627#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
3628#define DAC_C0_DACBWIEN_MASK (0x4U)
3629#define DAC_C0_DACBWIEN_SHIFT (2U)
3630#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
3631#define DAC_C0_LPEN_MASK (0x8U)
3632#define DAC_C0_LPEN_SHIFT (3U)
3633#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
3634#define DAC_C0_DACSWTRG_MASK (0x10U)
3635#define DAC_C0_DACSWTRG_SHIFT (4U)
3636#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
3637#define DAC_C0_DACTRGSEL_MASK (0x20U)
3638#define DAC_C0_DACTRGSEL_SHIFT (5U)
3639#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
3640#define DAC_C0_DACRFS_MASK (0x40U)
3641#define DAC_C0_DACRFS_SHIFT (6U)
3642#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
3643#define DAC_C0_DACEN_MASK (0x80U)
3644#define DAC_C0_DACEN_SHIFT (7U)
3645#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
3646
3648#define DAC_C1_DACBFEN_MASK (0x1U)
3649#define DAC_C1_DACBFEN_SHIFT (0U)
3650#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
3651#define DAC_C1_DACBFMD_MASK (0x6U)
3652#define DAC_C1_DACBFMD_SHIFT (1U)
3653#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
3654#define DAC_C1_DACBFWM_MASK (0x18U)
3655#define DAC_C1_DACBFWM_SHIFT (3U)
3656#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
3657#define DAC_C1_DMAEN_MASK (0x80U)
3658#define DAC_C1_DMAEN_SHIFT (7U)
3659#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
3660
3662#define DAC_C2_DACBFUP_MASK (0xFU)
3663#define DAC_C2_DACBFUP_SHIFT (0U)
3664#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
3665#define DAC_C2_DACBFRP_MASK (0xF0U)
3666#define DAC_C2_DACBFRP_SHIFT (4U)
3667#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
3668
3669
3672 /* end of group DAC_Register_Masks */
3673
3674
3675/* DAC - Peripheral instance base addresses */
3677#define DAC0_BASE (0x400CC000u)
3679#define DAC0 ((DAC_Type *)DAC0_BASE)
3681#define DAC1_BASE (0x400CD000u)
3683#define DAC1 ((DAC_Type *)DAC1_BASE)
3685#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
3687#define DAC_BASE_PTRS { DAC0, DAC1 }
3689#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
3690
3693 /* end of group DAC_Peripheral_Access_Layer */
3694
3695
3696/* ----------------------------------------------------------------------------
3697 -- DMA Peripheral Access Layer
3698 ---------------------------------------------------------------------------- */
3699
3706typedef struct {
3707 __IO uint32_t CR;
3708 __I uint32_t ES;
3709 uint8_t RESERVED_0[4];
3710 __IO uint32_t ERQ;
3711 uint8_t RESERVED_1[4];
3712 __IO uint32_t EEI;
3713 __O uint8_t CEEI;
3714 __O uint8_t SEEI;
3715 __O uint8_t CERQ;
3716 __O uint8_t SERQ;
3717 __O uint8_t CDNE;
3718 __O uint8_t SSRT;
3719 __O uint8_t CERR;
3720 __O uint8_t CINT;
3721 uint8_t RESERVED_2[4];
3722 __IO uint32_t INT;
3723 uint8_t RESERVED_3[4];
3724 __IO uint32_t ERR;
3725 uint8_t RESERVED_4[4];
3726 __IO uint32_t HRS;
3727 uint8_t RESERVED_5[200];
3728 __IO uint8_t DCHPRI3;
3729 __IO uint8_t DCHPRI2;
3730 __IO uint8_t DCHPRI1;
3731 __IO uint8_t DCHPRI0;
3732 __IO uint8_t DCHPRI7;
3733 __IO uint8_t DCHPRI6;
3734 __IO uint8_t DCHPRI5;
3735 __IO uint8_t DCHPRI4;
3736 __IO uint8_t DCHPRI11;
3737 __IO uint8_t DCHPRI10;
3738 __IO uint8_t DCHPRI9;
3739 __IO uint8_t DCHPRI8;
3740 __IO uint8_t DCHPRI15;
3741 __IO uint8_t DCHPRI14;
3742 __IO uint8_t DCHPRI13;
3743 __IO uint8_t DCHPRI12;
3744 uint8_t RESERVED_6[3824];
3745 struct { /* offset: 0x1000, array step: 0x20 */
3746 __IO uint32_t SADDR;
3747 __IO uint16_t SOFF;
3748 __IO uint16_t ATTR;
3749 union { /* offset: 0x1008, array step: 0x20 */
3750 __IO uint32_t NBYTES_MLNO;
3751 __IO uint32_t NBYTES_MLOFFNO;
3752 __IO uint32_t NBYTES_MLOFFYES;
3753 };
3754 __IO uint32_t SLAST;
3755 __IO uint32_t DADDR;
3756 __IO uint16_t DOFF;
3757 union { /* offset: 0x1016, array step: 0x20 */
3758 __IO uint16_t CITER_ELINKNO;
3759 __IO uint16_t CITER_ELINKYES;
3760 };
3761 __IO uint32_t DLAST_SGA;
3762 __IO uint16_t CSR;
3763 union { /* offset: 0x101E, array step: 0x20 */
3764 __IO uint16_t BITER_ELINKNO;
3765 __IO uint16_t BITER_ELINKYES;
3766 };
3767 } TCD[16];
3768} DMA_Type;
3769
3770/* ----------------------------------------------------------------------------
3771 -- DMA Register Masks
3772 ---------------------------------------------------------------------------- */
3773
3780#define DMA_CR_EDBG_MASK (0x2U)
3781#define DMA_CR_EDBG_SHIFT (1U)
3782#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
3783#define DMA_CR_ERCA_MASK (0x4U)
3784#define DMA_CR_ERCA_SHIFT (2U)
3785#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
3786#define DMA_CR_HOE_MASK (0x10U)
3787#define DMA_CR_HOE_SHIFT (4U)
3788#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
3789#define DMA_CR_HALT_MASK (0x20U)
3790#define DMA_CR_HALT_SHIFT (5U)
3791#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
3792#define DMA_CR_CLM_MASK (0x40U)
3793#define DMA_CR_CLM_SHIFT (6U)
3794#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
3795#define DMA_CR_EMLM_MASK (0x80U)
3796#define DMA_CR_EMLM_SHIFT (7U)
3797#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
3798#define DMA_CR_ECX_MASK (0x10000U)
3799#define DMA_CR_ECX_SHIFT (16U)
3800#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
3801#define DMA_CR_CX_MASK (0x20000U)
3802#define DMA_CR_CX_SHIFT (17U)
3803#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
3804
3806#define DMA_ES_DBE_MASK (0x1U)
3807#define DMA_ES_DBE_SHIFT (0U)
3808#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
3809#define DMA_ES_SBE_MASK (0x2U)
3810#define DMA_ES_SBE_SHIFT (1U)
3811#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
3812#define DMA_ES_SGE_MASK (0x4U)
3813#define DMA_ES_SGE_SHIFT (2U)
3814#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
3815#define DMA_ES_NCE_MASK (0x8U)
3816#define DMA_ES_NCE_SHIFT (3U)
3817#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
3818#define DMA_ES_DOE_MASK (0x10U)
3819#define DMA_ES_DOE_SHIFT (4U)
3820#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
3821#define DMA_ES_DAE_MASK (0x20U)
3822#define DMA_ES_DAE_SHIFT (5U)
3823#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
3824#define DMA_ES_SOE_MASK (0x40U)
3825#define DMA_ES_SOE_SHIFT (6U)
3826#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
3827#define DMA_ES_SAE_MASK (0x80U)
3828#define DMA_ES_SAE_SHIFT (7U)
3829#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
3830#define DMA_ES_ERRCHN_MASK (0xF00U)
3831#define DMA_ES_ERRCHN_SHIFT (8U)
3832#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
3833#define DMA_ES_CPE_MASK (0x4000U)
3834#define DMA_ES_CPE_SHIFT (14U)
3835#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
3836#define DMA_ES_ECX_MASK (0x10000U)
3837#define DMA_ES_ECX_SHIFT (16U)
3838#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
3839#define DMA_ES_VLD_MASK (0x80000000U)
3840#define DMA_ES_VLD_SHIFT (31U)
3841#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
3842
3844#define DMA_ERQ_ERQ0_MASK (0x1U)
3845#define DMA_ERQ_ERQ0_SHIFT (0U)
3846#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
3847#define DMA_ERQ_ERQ1_MASK (0x2U)
3848#define DMA_ERQ_ERQ1_SHIFT (1U)
3849#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
3850#define DMA_ERQ_ERQ2_MASK (0x4U)
3851#define DMA_ERQ_ERQ2_SHIFT (2U)
3852#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
3853#define DMA_ERQ_ERQ3_MASK (0x8U)
3854#define DMA_ERQ_ERQ3_SHIFT (3U)
3855#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
3856#define DMA_ERQ_ERQ4_MASK (0x10U)
3857#define DMA_ERQ_ERQ4_SHIFT (4U)
3858#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
3859#define DMA_ERQ_ERQ5_MASK (0x20U)
3860#define DMA_ERQ_ERQ5_SHIFT (5U)
3861#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
3862#define DMA_ERQ_ERQ6_MASK (0x40U)
3863#define DMA_ERQ_ERQ6_SHIFT (6U)
3864#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
3865#define DMA_ERQ_ERQ7_MASK (0x80U)
3866#define DMA_ERQ_ERQ7_SHIFT (7U)
3867#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
3868#define DMA_ERQ_ERQ8_MASK (0x100U)
3869#define DMA_ERQ_ERQ8_SHIFT (8U)
3870#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
3871#define DMA_ERQ_ERQ9_MASK (0x200U)
3872#define DMA_ERQ_ERQ9_SHIFT (9U)
3873#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
3874#define DMA_ERQ_ERQ10_MASK (0x400U)
3875#define DMA_ERQ_ERQ10_SHIFT (10U)
3876#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
3877#define DMA_ERQ_ERQ11_MASK (0x800U)
3878#define DMA_ERQ_ERQ11_SHIFT (11U)
3879#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
3880#define DMA_ERQ_ERQ12_MASK (0x1000U)
3881#define DMA_ERQ_ERQ12_SHIFT (12U)
3882#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
3883#define DMA_ERQ_ERQ13_MASK (0x2000U)
3884#define DMA_ERQ_ERQ13_SHIFT (13U)
3885#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
3886#define DMA_ERQ_ERQ14_MASK (0x4000U)
3887#define DMA_ERQ_ERQ14_SHIFT (14U)
3888#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
3889#define DMA_ERQ_ERQ15_MASK (0x8000U)
3890#define DMA_ERQ_ERQ15_SHIFT (15U)
3891#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
3892
3894#define DMA_EEI_EEI0_MASK (0x1U)
3895#define DMA_EEI_EEI0_SHIFT (0U)
3896#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
3897#define DMA_EEI_EEI1_MASK (0x2U)
3898#define DMA_EEI_EEI1_SHIFT (1U)
3899#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
3900#define DMA_EEI_EEI2_MASK (0x4U)
3901#define DMA_EEI_EEI2_SHIFT (2U)
3902#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
3903#define DMA_EEI_EEI3_MASK (0x8U)
3904#define DMA_EEI_EEI3_SHIFT (3U)
3905#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
3906#define DMA_EEI_EEI4_MASK (0x10U)
3907#define DMA_EEI_EEI4_SHIFT (4U)
3908#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
3909#define DMA_EEI_EEI5_MASK (0x20U)
3910#define DMA_EEI_EEI5_SHIFT (5U)
3911#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
3912#define DMA_EEI_EEI6_MASK (0x40U)
3913#define DMA_EEI_EEI6_SHIFT (6U)
3914#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
3915#define DMA_EEI_EEI7_MASK (0x80U)
3916#define DMA_EEI_EEI7_SHIFT (7U)
3917#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
3918#define DMA_EEI_EEI8_MASK (0x100U)
3919#define DMA_EEI_EEI8_SHIFT (8U)
3920#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
3921#define DMA_EEI_EEI9_MASK (0x200U)
3922#define DMA_EEI_EEI9_SHIFT (9U)
3923#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
3924#define DMA_EEI_EEI10_MASK (0x400U)
3925#define DMA_EEI_EEI10_SHIFT (10U)
3926#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
3927#define DMA_EEI_EEI11_MASK (0x800U)
3928#define DMA_EEI_EEI11_SHIFT (11U)
3929#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
3930#define DMA_EEI_EEI12_MASK (0x1000U)
3931#define DMA_EEI_EEI12_SHIFT (12U)
3932#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
3933#define DMA_EEI_EEI13_MASK (0x2000U)
3934#define DMA_EEI_EEI13_SHIFT (13U)
3935#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
3936#define DMA_EEI_EEI14_MASK (0x4000U)
3937#define DMA_EEI_EEI14_SHIFT (14U)
3938#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
3939#define DMA_EEI_EEI15_MASK (0x8000U)
3940#define DMA_EEI_EEI15_SHIFT (15U)
3941#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
3942
3944#define DMA_CEEI_CEEI_MASK (0xFU)
3945#define DMA_CEEI_CEEI_SHIFT (0U)
3946#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
3947#define DMA_CEEI_CAEE_MASK (0x40U)
3948#define DMA_CEEI_CAEE_SHIFT (6U)
3949#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
3950#define DMA_CEEI_NOP_MASK (0x80U)
3951#define DMA_CEEI_NOP_SHIFT (7U)
3952#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
3953
3955#define DMA_SEEI_SEEI_MASK (0xFU)
3956#define DMA_SEEI_SEEI_SHIFT (0U)
3957#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
3958#define DMA_SEEI_SAEE_MASK (0x40U)
3959#define DMA_SEEI_SAEE_SHIFT (6U)
3960#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
3961#define DMA_SEEI_NOP_MASK (0x80U)
3962#define DMA_SEEI_NOP_SHIFT (7U)
3963#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
3964
3966#define DMA_CERQ_CERQ_MASK (0xFU)
3967#define DMA_CERQ_CERQ_SHIFT (0U)
3968#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
3969#define DMA_CERQ_CAER_MASK (0x40U)
3970#define DMA_CERQ_CAER_SHIFT (6U)
3971#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
3972#define DMA_CERQ_NOP_MASK (0x80U)
3973#define DMA_CERQ_NOP_SHIFT (7U)
3974#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
3975
3977#define DMA_SERQ_SERQ_MASK (0xFU)
3978#define DMA_SERQ_SERQ_SHIFT (0U)
3979#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
3980#define DMA_SERQ_SAER_MASK (0x40U)
3981#define DMA_SERQ_SAER_SHIFT (6U)
3982#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
3983#define DMA_SERQ_NOP_MASK (0x80U)
3984#define DMA_SERQ_NOP_SHIFT (7U)
3985#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
3986
3988#define DMA_CDNE_CDNE_MASK (0xFU)
3989#define DMA_CDNE_CDNE_SHIFT (0U)
3990#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
3991#define DMA_CDNE_CADN_MASK (0x40U)
3992#define DMA_CDNE_CADN_SHIFT (6U)
3993#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
3994#define DMA_CDNE_NOP_MASK (0x80U)
3995#define DMA_CDNE_NOP_SHIFT (7U)
3996#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
3997
3999#define DMA_SSRT_SSRT_MASK (0xFU)
4000#define DMA_SSRT_SSRT_SHIFT (0U)
4001#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
4002#define DMA_SSRT_SAST_MASK (0x40U)
4003#define DMA_SSRT_SAST_SHIFT (6U)
4004#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
4005#define DMA_SSRT_NOP_MASK (0x80U)
4006#define DMA_SSRT_NOP_SHIFT (7U)
4007#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
4008
4010#define DMA_CERR_CERR_MASK (0xFU)
4011#define DMA_CERR_CERR_SHIFT (0U)
4012#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
4013#define DMA_CERR_CAEI_MASK (0x40U)
4014#define DMA_CERR_CAEI_SHIFT (6U)
4015#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
4016#define DMA_CERR_NOP_MASK (0x80U)
4017#define DMA_CERR_NOP_SHIFT (7U)
4018#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
4019
4021#define DMA_CINT_CINT_MASK (0xFU)
4022#define DMA_CINT_CINT_SHIFT (0U)
4023#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
4024#define DMA_CINT_CAIR_MASK (0x40U)
4025#define DMA_CINT_CAIR_SHIFT (6U)
4026#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
4027#define DMA_CINT_NOP_MASK (0x80U)
4028#define DMA_CINT_NOP_SHIFT (7U)
4029#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
4030
4032#define DMA_INT_INT0_MASK (0x1U)
4033#define DMA_INT_INT0_SHIFT (0U)
4034#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
4035#define DMA_INT_INT1_MASK (0x2U)
4036#define DMA_INT_INT1_SHIFT (1U)
4037#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
4038#define DMA_INT_INT2_MASK (0x4U)
4039#define DMA_INT_INT2_SHIFT (2U)
4040#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
4041#define DMA_INT_INT3_MASK (0x8U)
4042#define DMA_INT_INT3_SHIFT (3U)
4043#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
4044#define DMA_INT_INT4_MASK (0x10U)
4045#define DMA_INT_INT4_SHIFT (4U)
4046#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
4047#define DMA_INT_INT5_MASK (0x20U)
4048#define DMA_INT_INT5_SHIFT (5U)
4049#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
4050#define DMA_INT_INT6_MASK (0x40U)
4051#define DMA_INT_INT6_SHIFT (6U)
4052#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
4053#define DMA_INT_INT7_MASK (0x80U)
4054#define DMA_INT_INT7_SHIFT (7U)
4055#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
4056#define DMA_INT_INT8_MASK (0x100U)
4057#define DMA_INT_INT8_SHIFT (8U)
4058#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
4059#define DMA_INT_INT9_MASK (0x200U)
4060#define DMA_INT_INT9_SHIFT (9U)
4061#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
4062#define DMA_INT_INT10_MASK (0x400U)
4063#define DMA_INT_INT10_SHIFT (10U)
4064#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
4065#define DMA_INT_INT11_MASK (0x800U)
4066#define DMA_INT_INT11_SHIFT (11U)
4067#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
4068#define DMA_INT_INT12_MASK (0x1000U)
4069#define DMA_INT_INT12_SHIFT (12U)
4070#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
4071#define DMA_INT_INT13_MASK (0x2000U)
4072#define DMA_INT_INT13_SHIFT (13U)
4073#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
4074#define DMA_INT_INT14_MASK (0x4000U)
4075#define DMA_INT_INT14_SHIFT (14U)
4076#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
4077#define DMA_INT_INT15_MASK (0x8000U)
4078#define DMA_INT_INT15_SHIFT (15U)
4079#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
4080
4082#define DMA_ERR_ERR0_MASK (0x1U)
4083#define DMA_ERR_ERR0_SHIFT (0U)
4084#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
4085#define DMA_ERR_ERR1_MASK (0x2U)
4086#define DMA_ERR_ERR1_SHIFT (1U)
4087#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
4088#define DMA_ERR_ERR2_MASK (0x4U)
4089#define DMA_ERR_ERR2_SHIFT (2U)
4090#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
4091#define DMA_ERR_ERR3_MASK (0x8U)
4092#define DMA_ERR_ERR3_SHIFT (3U)
4093#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
4094#define DMA_ERR_ERR4_MASK (0x10U)
4095#define DMA_ERR_ERR4_SHIFT (4U)
4096#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
4097#define DMA_ERR_ERR5_MASK (0x20U)
4098#define DMA_ERR_ERR5_SHIFT (5U)
4099#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
4100#define DMA_ERR_ERR6_MASK (0x40U)
4101#define DMA_ERR_ERR6_SHIFT (6U)
4102#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
4103#define DMA_ERR_ERR7_MASK (0x80U)
4104#define DMA_ERR_ERR7_SHIFT (7U)
4105#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
4106#define DMA_ERR_ERR8_MASK (0x100U)
4107#define DMA_ERR_ERR8_SHIFT (8U)
4108#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
4109#define DMA_ERR_ERR9_MASK (0x200U)
4110#define DMA_ERR_ERR9_SHIFT (9U)
4111#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
4112#define DMA_ERR_ERR10_MASK (0x400U)
4113#define DMA_ERR_ERR10_SHIFT (10U)
4114#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
4115#define DMA_ERR_ERR11_MASK (0x800U)
4116#define DMA_ERR_ERR11_SHIFT (11U)
4117#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
4118#define DMA_ERR_ERR12_MASK (0x1000U)
4119#define DMA_ERR_ERR12_SHIFT (12U)
4120#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
4121#define DMA_ERR_ERR13_MASK (0x2000U)
4122#define DMA_ERR_ERR13_SHIFT (13U)
4123#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
4124#define DMA_ERR_ERR14_MASK (0x4000U)
4125#define DMA_ERR_ERR14_SHIFT (14U)
4126#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
4127#define DMA_ERR_ERR15_MASK (0x8000U)
4128#define DMA_ERR_ERR15_SHIFT (15U)
4129#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
4130
4132#define DMA_HRS_HRS0_MASK (0x1U)
4133#define DMA_HRS_HRS0_SHIFT (0U)
4134#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
4135#define DMA_HRS_HRS1_MASK (0x2U)
4136#define DMA_HRS_HRS1_SHIFT (1U)
4137#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
4138#define DMA_HRS_HRS2_MASK (0x4U)
4139#define DMA_HRS_HRS2_SHIFT (2U)
4140#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
4141#define DMA_HRS_HRS3_MASK (0x8U)
4142#define DMA_HRS_HRS3_SHIFT (3U)
4143#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
4144#define DMA_HRS_HRS4_MASK (0x10U)
4145#define DMA_HRS_HRS4_SHIFT (4U)
4146#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
4147#define DMA_HRS_HRS5_MASK (0x20U)
4148#define DMA_HRS_HRS5_SHIFT (5U)
4149#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
4150#define DMA_HRS_HRS6_MASK (0x40U)
4151#define DMA_HRS_HRS6_SHIFT (6U)
4152#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
4153#define DMA_HRS_HRS7_MASK (0x80U)
4154#define DMA_HRS_HRS7_SHIFT (7U)
4155#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
4156#define DMA_HRS_HRS8_MASK (0x100U)
4157#define DMA_HRS_HRS8_SHIFT (8U)
4158#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
4159#define DMA_HRS_HRS9_MASK (0x200U)
4160#define DMA_HRS_HRS9_SHIFT (9U)
4161#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
4162#define DMA_HRS_HRS10_MASK (0x400U)
4163#define DMA_HRS_HRS10_SHIFT (10U)
4164#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
4165#define DMA_HRS_HRS11_MASK (0x800U)
4166#define DMA_HRS_HRS11_SHIFT (11U)
4167#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
4168#define DMA_HRS_HRS12_MASK (0x1000U)
4169#define DMA_HRS_HRS12_SHIFT (12U)
4170#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
4171#define DMA_HRS_HRS13_MASK (0x2000U)
4172#define DMA_HRS_HRS13_SHIFT (13U)
4173#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
4174#define DMA_HRS_HRS14_MASK (0x4000U)
4175#define DMA_HRS_HRS14_SHIFT (14U)
4176#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
4177#define DMA_HRS_HRS15_MASK (0x8000U)
4178#define DMA_HRS_HRS15_SHIFT (15U)
4179#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
4180
4182#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
4183#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
4184#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
4185#define DMA_DCHPRI3_DPA_MASK (0x40U)
4186#define DMA_DCHPRI3_DPA_SHIFT (6U)
4187#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
4188#define DMA_DCHPRI3_ECP_MASK (0x80U)
4189#define DMA_DCHPRI3_ECP_SHIFT (7U)
4190#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
4191
4193#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
4194#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
4195#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
4196#define DMA_DCHPRI2_DPA_MASK (0x40U)
4197#define DMA_DCHPRI2_DPA_SHIFT (6U)
4198#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
4199#define DMA_DCHPRI2_ECP_MASK (0x80U)
4200#define DMA_DCHPRI2_ECP_SHIFT (7U)
4201#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
4202
4204#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
4205#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
4206#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
4207#define DMA_DCHPRI1_DPA_MASK (0x40U)
4208#define DMA_DCHPRI1_DPA_SHIFT (6U)
4209#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
4210#define DMA_DCHPRI1_ECP_MASK (0x80U)
4211#define DMA_DCHPRI1_ECP_SHIFT (7U)
4212#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
4213
4215#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
4216#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
4217#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
4218#define DMA_DCHPRI0_DPA_MASK (0x40U)
4219#define DMA_DCHPRI0_DPA_SHIFT (6U)
4220#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
4221#define DMA_DCHPRI0_ECP_MASK (0x80U)
4222#define DMA_DCHPRI0_ECP_SHIFT (7U)
4223#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
4224
4226#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
4227#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
4228#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
4229#define DMA_DCHPRI7_DPA_MASK (0x40U)
4230#define DMA_DCHPRI7_DPA_SHIFT (6U)
4231#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
4232#define DMA_DCHPRI7_ECP_MASK (0x80U)
4233#define DMA_DCHPRI7_ECP_SHIFT (7U)
4234#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
4235
4237#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
4238#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
4239#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
4240#define DMA_DCHPRI6_DPA_MASK (0x40U)
4241#define DMA_DCHPRI6_DPA_SHIFT (6U)
4242#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
4243#define DMA_DCHPRI6_ECP_MASK (0x80U)
4244#define DMA_DCHPRI6_ECP_SHIFT (7U)
4245#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
4246
4248#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
4249#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
4250#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
4251#define DMA_DCHPRI5_DPA_MASK (0x40U)
4252#define DMA_DCHPRI5_DPA_SHIFT (6U)
4253#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
4254#define DMA_DCHPRI5_ECP_MASK (0x80U)
4255#define DMA_DCHPRI5_ECP_SHIFT (7U)
4256#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
4257
4259#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
4260#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
4261#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
4262#define DMA_DCHPRI4_DPA_MASK (0x40U)
4263#define DMA_DCHPRI4_DPA_SHIFT (6U)
4264#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
4265#define DMA_DCHPRI4_ECP_MASK (0x80U)
4266#define DMA_DCHPRI4_ECP_SHIFT (7U)
4267#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
4268
4270#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
4271#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
4272#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
4273#define DMA_DCHPRI11_DPA_MASK (0x40U)
4274#define DMA_DCHPRI11_DPA_SHIFT (6U)
4275#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
4276#define DMA_DCHPRI11_ECP_MASK (0x80U)
4277#define DMA_DCHPRI11_ECP_SHIFT (7U)
4278#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
4279
4281#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
4282#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
4283#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
4284#define DMA_DCHPRI10_DPA_MASK (0x40U)
4285#define DMA_DCHPRI10_DPA_SHIFT (6U)
4286#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
4287#define DMA_DCHPRI10_ECP_MASK (0x80U)
4288#define DMA_DCHPRI10_ECP_SHIFT (7U)
4289#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
4290
4292#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
4293#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
4294#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
4295#define DMA_DCHPRI9_DPA_MASK (0x40U)
4296#define DMA_DCHPRI9_DPA_SHIFT (6U)
4297#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
4298#define DMA_DCHPRI9_ECP_MASK (0x80U)
4299#define DMA_DCHPRI9_ECP_SHIFT (7U)
4300#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
4301
4303#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
4304#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
4305#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
4306#define DMA_DCHPRI8_DPA_MASK (0x40U)
4307#define DMA_DCHPRI8_DPA_SHIFT (6U)
4308#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
4309#define DMA_DCHPRI8_ECP_MASK (0x80U)
4310#define DMA_DCHPRI8_ECP_SHIFT (7U)
4311#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
4312
4314#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
4315#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
4316#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
4317#define DMA_DCHPRI15_DPA_MASK (0x40U)
4318#define DMA_DCHPRI15_DPA_SHIFT (6U)
4319#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
4320#define DMA_DCHPRI15_ECP_MASK (0x80U)
4321#define DMA_DCHPRI15_ECP_SHIFT (7U)
4322#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
4323
4325#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
4326#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
4327#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
4328#define DMA_DCHPRI14_DPA_MASK (0x40U)
4329#define DMA_DCHPRI14_DPA_SHIFT (6U)
4330#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
4331#define DMA_DCHPRI14_ECP_MASK (0x80U)
4332#define DMA_DCHPRI14_ECP_SHIFT (7U)
4333#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
4334
4336#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
4337#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
4338#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
4339#define DMA_DCHPRI13_DPA_MASK (0x40U)
4340#define DMA_DCHPRI13_DPA_SHIFT (6U)
4341#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
4342#define DMA_DCHPRI13_ECP_MASK (0x80U)
4343#define DMA_DCHPRI13_ECP_SHIFT (7U)
4344#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
4345
4347#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
4348#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
4349#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
4350#define DMA_DCHPRI12_DPA_MASK (0x40U)
4351#define DMA_DCHPRI12_DPA_SHIFT (6U)
4352#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
4353#define DMA_DCHPRI12_ECP_MASK (0x80U)
4354#define DMA_DCHPRI12_ECP_SHIFT (7U)
4355#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
4356
4358#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
4359#define DMA_SADDR_SADDR_SHIFT (0U)
4360#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
4361
4362/* The count of DMA_SADDR */
4363#define DMA_SADDR_COUNT (16U)
4364
4366#define DMA_SOFF_SOFF_MASK (0xFFFFU)
4367#define DMA_SOFF_SOFF_SHIFT (0U)
4368#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
4369
4370/* The count of DMA_SOFF */
4371#define DMA_SOFF_COUNT (16U)
4372
4374#define DMA_ATTR_DSIZE_MASK (0x7U)
4375#define DMA_ATTR_DSIZE_SHIFT (0U)
4376#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
4377#define DMA_ATTR_DMOD_MASK (0xF8U)
4378#define DMA_ATTR_DMOD_SHIFT (3U)
4379#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
4380#define DMA_ATTR_SSIZE_MASK (0x700U)
4381#define DMA_ATTR_SSIZE_SHIFT (8U)
4382#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
4383#define DMA_ATTR_SMOD_MASK (0xF800U)
4384#define DMA_ATTR_SMOD_SHIFT (11U)
4385#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
4386
4387/* The count of DMA_ATTR */
4388#define DMA_ATTR_COUNT (16U)
4389
4391#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
4392#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
4393#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
4394
4395/* The count of DMA_NBYTES_MLNO */
4396#define DMA_NBYTES_MLNO_COUNT (16U)
4397
4399#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
4400#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
4401#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
4402#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
4403#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
4404#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
4405#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
4406#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
4407#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
4408
4409/* The count of DMA_NBYTES_MLOFFNO */
4410#define DMA_NBYTES_MLOFFNO_COUNT (16U)
4411
4413#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
4414#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
4415#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
4416#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
4417#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
4418#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
4419#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
4420#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
4421#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
4422#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
4423#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
4424#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
4425
4426/* The count of DMA_NBYTES_MLOFFYES */
4427#define DMA_NBYTES_MLOFFYES_COUNT (16U)
4428
4430#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
4431#define DMA_SLAST_SLAST_SHIFT (0U)
4432#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
4433
4434/* The count of DMA_SLAST */
4435#define DMA_SLAST_COUNT (16U)
4436
4438#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
4439#define DMA_DADDR_DADDR_SHIFT (0U)
4440#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
4441
4442/* The count of DMA_DADDR */
4443#define DMA_DADDR_COUNT (16U)
4444
4446#define DMA_DOFF_DOFF_MASK (0xFFFFU)
4447#define DMA_DOFF_DOFF_SHIFT (0U)
4448#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
4449
4450/* The count of DMA_DOFF */
4451#define DMA_DOFF_COUNT (16U)
4452
4454#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
4455#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
4456#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
4457#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
4458#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
4459#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
4460
4461/* The count of DMA_CITER_ELINKNO */
4462#define DMA_CITER_ELINKNO_COUNT (16U)
4463
4465#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
4466#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
4467#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
4468#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
4469#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
4470#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
4471#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
4472#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
4473#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
4474
4475/* The count of DMA_CITER_ELINKYES */
4476#define DMA_CITER_ELINKYES_COUNT (16U)
4477
4479#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
4480#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
4481#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
4482
4483/* The count of DMA_DLAST_SGA */
4484#define DMA_DLAST_SGA_COUNT (16U)
4485
4487#define DMA_CSR_START_MASK (0x1U)
4488#define DMA_CSR_START_SHIFT (0U)
4489#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
4490#define DMA_CSR_INTMAJOR_MASK (0x2U)
4491#define DMA_CSR_INTMAJOR_SHIFT (1U)
4492#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
4493#define DMA_CSR_INTHALF_MASK (0x4U)
4494#define DMA_CSR_INTHALF_SHIFT (2U)
4495#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
4496#define DMA_CSR_DREQ_MASK (0x8U)
4497#define DMA_CSR_DREQ_SHIFT (3U)
4498#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
4499#define DMA_CSR_ESG_MASK (0x10U)
4500#define DMA_CSR_ESG_SHIFT (4U)
4501#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
4502#define DMA_CSR_MAJORELINK_MASK (0x20U)
4503#define DMA_CSR_MAJORELINK_SHIFT (5U)
4504#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
4505#define DMA_CSR_ACTIVE_MASK (0x40U)
4506#define DMA_CSR_ACTIVE_SHIFT (6U)
4507#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
4508#define DMA_CSR_DONE_MASK (0x80U)
4509#define DMA_CSR_DONE_SHIFT (7U)
4510#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
4511#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
4512#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
4513#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
4514#define DMA_CSR_BWC_MASK (0xC000U)
4515#define DMA_CSR_BWC_SHIFT (14U)
4516#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
4517
4518/* The count of DMA_CSR */
4519#define DMA_CSR_COUNT (16U)
4520
4522#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
4523#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
4524#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
4525#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
4526#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
4527#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
4528
4529/* The count of DMA_BITER_ELINKNO */
4530#define DMA_BITER_ELINKNO_COUNT (16U)
4531
4533#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
4534#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
4535#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
4536#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
4537#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
4538#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
4539#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
4540#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
4541#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
4542
4543/* The count of DMA_BITER_ELINKYES */
4544#define DMA_BITER_ELINKYES_COUNT (16U)
4545
4546
4549 /* end of group DMA_Register_Masks */
4550
4551
4552/* DMA - Peripheral instance base addresses */
4554#define DMA_BASE (0x40008000u)
4556#define DMA0 ((DMA_Type *)DMA_BASE)
4558#define DMA_BASE_ADDRS { DMA_BASE }
4560#define DMA_BASE_PTRS { DMA0 }
4562#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
4563#define DMA_ERROR_IRQS { DMA_Error_IRQn }
4564
4567 /* end of group DMA_Peripheral_Access_Layer */
4568
4569
4570/* ----------------------------------------------------------------------------
4571 -- DMAMUX Peripheral Access Layer
4572 ---------------------------------------------------------------------------- */
4573
4580typedef struct {
4581 __IO uint8_t CHCFG[16];
4582} DMAMUX_Type;
4583
4584/* ----------------------------------------------------------------------------
4585 -- DMAMUX Register Masks
4586 ---------------------------------------------------------------------------- */
4587
4594#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
4595#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
4596#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
4597#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
4598#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
4599#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
4600#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
4601#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
4602#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
4603
4604/* The count of DMAMUX_CHCFG */
4605#define DMAMUX_CHCFG_COUNT (16U)
4606
4607
4610 /* end of group DMAMUX_Register_Masks */
4611
4612
4613/* DMAMUX - Peripheral instance base addresses */
4615#define DMAMUX_BASE (0x40021000u)
4617#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
4619#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
4621#define DMAMUX_BASE_PTRS { DMAMUX }
4622
4625 /* end of group DMAMUX_Peripheral_Access_Layer */
4626
4627
4628/* ----------------------------------------------------------------------------
4629 -- ENET Peripheral Access Layer
4630 ---------------------------------------------------------------------------- */
4631
4638typedef struct {
4639 uint8_t RESERVED_0[4];
4640 __IO uint32_t EIR;
4641 __IO uint32_t EIMR;
4642 uint8_t RESERVED_1[4];
4643 __IO uint32_t RDAR;
4644 __IO uint32_t TDAR;
4645 uint8_t RESERVED_2[12];
4646 __IO uint32_t ECR;
4647 uint8_t RESERVED_3[24];
4648 __IO uint32_t MMFR;
4649 __IO uint32_t MSCR;
4650 uint8_t RESERVED_4[28];
4651 __IO uint32_t MIBC;
4652 uint8_t RESERVED_5[28];
4653 __IO uint32_t RCR;
4654 uint8_t RESERVED_6[60];
4655 __IO uint32_t TCR;
4656 uint8_t RESERVED_7[28];
4657 __IO uint32_t PALR;
4658 __IO uint32_t PAUR;
4659 __IO uint32_t OPD;
4660 uint8_t RESERVED_8[40];
4661 __IO uint32_t IAUR;
4662 __IO uint32_t IALR;
4663 __IO uint32_t GAUR;
4664 __IO uint32_t GALR;
4665 uint8_t RESERVED_9[28];
4666 __IO uint32_t TFWR;
4667 uint8_t RESERVED_10[56];
4668 __IO uint32_t RDSR;
4669 __IO uint32_t TDSR;
4670 __IO uint32_t MRBR;
4671 uint8_t RESERVED_11[4];
4672 __IO uint32_t RSFL;
4673 __IO uint32_t RSEM;
4674 __IO uint32_t RAEM;
4675 __IO uint32_t RAFL;
4676 __IO uint32_t TSEM;
4677 __IO uint32_t TAEM;
4678 __IO uint32_t TAFL;
4679 __IO uint32_t TIPG;
4680 __IO uint32_t FTRL;
4681 uint8_t RESERVED_12[12];
4682 __IO uint32_t TACC;
4683 __IO uint32_t RACC;
4684 uint8_t RESERVED_13[56];
4685 __IO uint32_t RMON_T_DROP;
4686 __IO uint32_t RMON_T_PACKETS;
4687 __IO uint32_t RMON_T_BC_PKT;
4688 __IO uint32_t RMON_T_MC_PKT;
4689 __IO uint32_t RMON_T_CRC_ALIGN;
4690 __IO uint32_t RMON_T_UNDERSIZE;
4691 __IO uint32_t RMON_T_OVERSIZE;
4692 __IO uint32_t RMON_T_FRAG;
4693 __IO uint32_t RMON_T_JAB;
4694 __IO uint32_t RMON_T_COL;
4695 __IO uint32_t RMON_T_P64;
4696 __IO uint32_t RMON_T_P65TO127;
4697 __IO uint32_t RMON_T_P128TO255;
4698 __IO uint32_t RMON_T_P256TO511;
4699 __IO uint32_t RMON_T_P512TO1023;
4700 __IO uint32_t RMON_T_P1024TO2047;
4701 __IO uint32_t RMON_T_P_GTE2048;
4702 __I uint32_t RMON_T_OCTETS;
4703 __IO uint32_t IEEE_T_DROP;
4704 __IO uint32_t IEEE_T_FRAME_OK;
4705 __IO uint32_t IEEE_T_1COL;
4706 __IO uint32_t IEEE_T_MCOL;
4707 __IO uint32_t IEEE_T_DEF;
4708 __IO uint32_t IEEE_T_LCOL;
4709 __IO uint32_t IEEE_T_EXCOL;
4710 __IO uint32_t IEEE_T_MACERR;
4711 __IO uint32_t IEEE_T_CSERR;
4712 __IO uint32_t IEEE_T_SQE;
4713 __IO uint32_t IEEE_T_FDXFC;
4714 __I uint32_t IEEE_T_OCTETS_OK;
4715 uint8_t RESERVED_14[12];
4716 __IO uint32_t RMON_R_PACKETS;
4717 __IO uint32_t RMON_R_BC_PKT;
4718 __IO uint32_t RMON_R_MC_PKT;
4719 __IO uint32_t RMON_R_CRC_ALIGN;
4720 __IO uint32_t RMON_R_UNDERSIZE;
4721 __IO uint32_t RMON_R_OVERSIZE;
4722 __IO uint32_t RMON_R_FRAG;
4723 __IO uint32_t RMON_R_JAB;
4724 __IO uint32_t RMON_R_RESVD_0;
4725 __IO uint32_t RMON_R_P64;
4726 __IO uint32_t RMON_R_P65TO127;
4727 __IO uint32_t RMON_R_P128TO255;
4728 __IO uint32_t RMON_R_P256TO511;
4729 __IO uint32_t RMON_R_P512TO1023;
4730 __IO uint32_t RMON_R_P1024TO2047;
4731 __IO uint32_t RMON_R_P_GTE2048;
4732 __I uint32_t RMON_R_OCTETS;
4733 __IO uint32_t IEEE_R_DROP;
4734 __IO uint32_t IEEE_R_FRAME_OK;
4735 __IO uint32_t IEEE_R_CRC;
4736 __IO uint32_t IEEE_R_ALIGN;
4737 __IO uint32_t IEEE_R_MACERR;
4738 __IO uint32_t IEEE_R_FDXFC;
4739 __I uint32_t IEEE_R_OCTETS_OK;
4740 uint8_t RESERVED_15[284];
4741 __IO uint32_t ATCR;
4742 __IO uint32_t ATVR;
4743 __IO uint32_t ATOFF;
4744 __IO uint32_t ATPER;
4745 __IO uint32_t ATCOR;
4746 __IO uint32_t ATINC;
4747 __IO uint32_t ATSTMP;
4748 uint8_t RESERVED_16[488];
4749 __IO uint32_t TGSR;
4750 struct { /* offset: 0x608, array step: 0x8 */
4751 __IO uint32_t TCSR;
4752 __IO uint32_t TCCR;
4753 } CHANNEL[4];
4754} ENET_Type;
4755
4756/* ----------------------------------------------------------------------------
4757 -- ENET Register Masks
4758 ---------------------------------------------------------------------------- */
4759
4766#define ENET_EIR_TS_TIMER_MASK (0x8000U)
4767#define ENET_EIR_TS_TIMER_SHIFT (15U)
4768#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
4769#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
4770#define ENET_EIR_TS_AVAIL_SHIFT (16U)
4771#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
4772#define ENET_EIR_WAKEUP_MASK (0x20000U)
4773#define ENET_EIR_WAKEUP_SHIFT (17U)
4774#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
4775#define ENET_EIR_PLR_MASK (0x40000U)
4776#define ENET_EIR_PLR_SHIFT (18U)
4777#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
4778#define ENET_EIR_UN_MASK (0x80000U)
4779#define ENET_EIR_UN_SHIFT (19U)
4780#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
4781#define ENET_EIR_RL_MASK (0x100000U)
4782#define ENET_EIR_RL_SHIFT (20U)
4783#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
4784#define ENET_EIR_LC_MASK (0x200000U)
4785#define ENET_EIR_LC_SHIFT (21U)
4786#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
4787#define ENET_EIR_EBERR_MASK (0x400000U)
4788#define ENET_EIR_EBERR_SHIFT (22U)
4789#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
4790#define ENET_EIR_MII_MASK (0x800000U)
4791#define ENET_EIR_MII_SHIFT (23U)
4792#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
4793#define ENET_EIR_RXB_MASK (0x1000000U)
4794#define ENET_EIR_RXB_SHIFT (24U)
4795#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
4796#define ENET_EIR_RXF_MASK (0x2000000U)
4797#define ENET_EIR_RXF_SHIFT (25U)
4798#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
4799#define ENET_EIR_TXB_MASK (0x4000000U)
4800#define ENET_EIR_TXB_SHIFT (26U)
4801#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
4802#define ENET_EIR_TXF_MASK (0x8000000U)
4803#define ENET_EIR_TXF_SHIFT (27U)
4804#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
4805#define ENET_EIR_GRA_MASK (0x10000000U)
4806#define ENET_EIR_GRA_SHIFT (28U)
4807#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
4808#define ENET_EIR_BABT_MASK (0x20000000U)
4809#define ENET_EIR_BABT_SHIFT (29U)
4810#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
4811#define ENET_EIR_BABR_MASK (0x40000000U)
4812#define ENET_EIR_BABR_SHIFT (30U)
4813#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
4814
4816#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
4817#define ENET_EIMR_TS_TIMER_SHIFT (15U)
4818#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
4819#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
4820#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
4821#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
4822#define ENET_EIMR_WAKEUP_MASK (0x20000U)
4823#define ENET_EIMR_WAKEUP_SHIFT (17U)
4824#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
4825#define ENET_EIMR_PLR_MASK (0x40000U)
4826#define ENET_EIMR_PLR_SHIFT (18U)
4827#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
4828#define ENET_EIMR_UN_MASK (0x80000U)
4829#define ENET_EIMR_UN_SHIFT (19U)
4830#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
4831#define ENET_EIMR_RL_MASK (0x100000U)
4832#define ENET_EIMR_RL_SHIFT (20U)
4833#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
4834#define ENET_EIMR_LC_MASK (0x200000U)
4835#define ENET_EIMR_LC_SHIFT (21U)
4836#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
4837#define ENET_EIMR_EBERR_MASK (0x400000U)
4838#define ENET_EIMR_EBERR_SHIFT (22U)
4839#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
4840#define ENET_EIMR_MII_MASK (0x800000U)
4841#define ENET_EIMR_MII_SHIFT (23U)
4842#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
4843#define ENET_EIMR_RXB_MASK (0x1000000U)
4844#define ENET_EIMR_RXB_SHIFT (24U)
4845#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
4846#define ENET_EIMR_RXF_MASK (0x2000000U)
4847#define ENET_EIMR_RXF_SHIFT (25U)
4848#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
4849#define ENET_EIMR_TXB_MASK (0x4000000U)
4850#define ENET_EIMR_TXB_SHIFT (26U)
4851#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
4852#define ENET_EIMR_TXF_MASK (0x8000000U)
4853#define ENET_EIMR_TXF_SHIFT (27U)
4854#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
4855#define ENET_EIMR_GRA_MASK (0x10000000U)
4856#define ENET_EIMR_GRA_SHIFT (28U)
4857#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
4858#define ENET_EIMR_BABT_MASK (0x20000000U)
4859#define ENET_EIMR_BABT_SHIFT (29U)
4860#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
4861#define ENET_EIMR_BABR_MASK (0x40000000U)
4862#define ENET_EIMR_BABR_SHIFT (30U)
4863#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
4864
4866#define ENET_RDAR_RDAR_MASK (0x1000000U)
4867#define ENET_RDAR_RDAR_SHIFT (24U)
4868#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
4869
4871#define ENET_TDAR_TDAR_MASK (0x1000000U)
4872#define ENET_TDAR_TDAR_SHIFT (24U)
4873#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
4874
4876#define ENET_ECR_RESET_MASK (0x1U)
4877#define ENET_ECR_RESET_SHIFT (0U)
4878#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
4879#define ENET_ECR_ETHEREN_MASK (0x2U)
4880#define ENET_ECR_ETHEREN_SHIFT (1U)
4881#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
4882#define ENET_ECR_MAGICEN_MASK (0x4U)
4883#define ENET_ECR_MAGICEN_SHIFT (2U)
4884#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
4885#define ENET_ECR_SLEEP_MASK (0x8U)
4886#define ENET_ECR_SLEEP_SHIFT (3U)
4887#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
4888#define ENET_ECR_EN1588_MASK (0x10U)
4889#define ENET_ECR_EN1588_SHIFT (4U)
4890#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
4891#define ENET_ECR_DBGEN_MASK (0x40U)
4892#define ENET_ECR_DBGEN_SHIFT (6U)
4893#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
4894#define ENET_ECR_STOPEN_MASK (0x80U)
4895#define ENET_ECR_STOPEN_SHIFT (7U)
4896#define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
4897#define ENET_ECR_DBSWP_MASK (0x100U)
4898#define ENET_ECR_DBSWP_SHIFT (8U)
4899#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
4900
4902#define ENET_MMFR_DATA_MASK (0xFFFFU)
4903#define ENET_MMFR_DATA_SHIFT (0U)
4904#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
4905#define ENET_MMFR_TA_MASK (0x30000U)
4906#define ENET_MMFR_TA_SHIFT (16U)
4907#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
4908#define ENET_MMFR_RA_MASK (0x7C0000U)
4909#define ENET_MMFR_RA_SHIFT (18U)
4910#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
4911#define ENET_MMFR_PA_MASK (0xF800000U)
4912#define ENET_MMFR_PA_SHIFT (23U)
4913#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
4914#define ENET_MMFR_OP_MASK (0x30000000U)
4915#define ENET_MMFR_OP_SHIFT (28U)
4916#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
4917#define ENET_MMFR_ST_MASK (0xC0000000U)
4918#define ENET_MMFR_ST_SHIFT (30U)
4919#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
4920
4922#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
4923#define ENET_MSCR_MII_SPEED_SHIFT (1U)
4924#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
4925#define ENET_MSCR_DIS_PRE_MASK (0x80U)
4926#define ENET_MSCR_DIS_PRE_SHIFT (7U)
4927#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
4928#define ENET_MSCR_HOLDTIME_MASK (0x700U)
4929#define ENET_MSCR_HOLDTIME_SHIFT (8U)
4930#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
4931
4933#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
4934#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
4935#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
4936#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
4937#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
4938#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
4939#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
4940#define ENET_MIBC_MIB_DIS_SHIFT (31U)
4941#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
4942
4944#define ENET_RCR_LOOP_MASK (0x1U)
4945#define ENET_RCR_LOOP_SHIFT (0U)
4946#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
4947#define ENET_RCR_DRT_MASK (0x2U)
4948#define ENET_RCR_DRT_SHIFT (1U)
4949#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
4950#define ENET_RCR_MII_MODE_MASK (0x4U)
4951#define ENET_RCR_MII_MODE_SHIFT (2U)
4952#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
4953#define ENET_RCR_PROM_MASK (0x8U)
4954#define ENET_RCR_PROM_SHIFT (3U)
4955#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
4956#define ENET_RCR_BC_REJ_MASK (0x10U)
4957#define ENET_RCR_BC_REJ_SHIFT (4U)
4958#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
4959#define ENET_RCR_FCE_MASK (0x20U)
4960#define ENET_RCR_FCE_SHIFT (5U)
4961#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
4962#define ENET_RCR_RMII_MODE_MASK (0x100U)
4963#define ENET_RCR_RMII_MODE_SHIFT (8U)
4964#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
4965#define ENET_RCR_RMII_10T_MASK (0x200U)
4966#define ENET_RCR_RMII_10T_SHIFT (9U)
4967#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
4968#define ENET_RCR_PADEN_MASK (0x1000U)
4969#define ENET_RCR_PADEN_SHIFT (12U)
4970#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
4971#define ENET_RCR_PAUFWD_MASK (0x2000U)
4972#define ENET_RCR_PAUFWD_SHIFT (13U)
4973#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
4974#define ENET_RCR_CRCFWD_MASK (0x4000U)
4975#define ENET_RCR_CRCFWD_SHIFT (14U)
4976#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
4977#define ENET_RCR_CFEN_MASK (0x8000U)
4978#define ENET_RCR_CFEN_SHIFT (15U)
4979#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
4980#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
4981#define ENET_RCR_MAX_FL_SHIFT (16U)
4982#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
4983#define ENET_RCR_NLC_MASK (0x40000000U)
4984#define ENET_RCR_NLC_SHIFT (30U)
4985#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
4986#define ENET_RCR_GRS_MASK (0x80000000U)
4987#define ENET_RCR_GRS_SHIFT (31U)
4988#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
4989
4991#define ENET_TCR_GTS_MASK (0x1U)
4992#define ENET_TCR_GTS_SHIFT (0U)
4993#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
4994#define ENET_TCR_FDEN_MASK (0x4U)
4995#define ENET_TCR_FDEN_SHIFT (2U)
4996#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
4997#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
4998#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
4999#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
5000#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
5001#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
5002#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
5003#define ENET_TCR_ADDSEL_MASK (0xE0U)
5004#define ENET_TCR_ADDSEL_SHIFT (5U)
5005#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
5006#define ENET_TCR_ADDINS_MASK (0x100U)
5007#define ENET_TCR_ADDINS_SHIFT (8U)
5008#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
5009#define ENET_TCR_CRCFWD_MASK (0x200U)
5010#define ENET_TCR_CRCFWD_SHIFT (9U)
5011#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
5012
5014#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
5015#define ENET_PALR_PADDR1_SHIFT (0U)
5016#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
5017
5019#define ENET_PAUR_TYPE_MASK (0xFFFFU)
5020#define ENET_PAUR_TYPE_SHIFT (0U)
5021#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
5022#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
5023#define ENET_PAUR_PADDR2_SHIFT (16U)
5024#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
5025
5027#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
5028#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
5029#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
5030#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
5031#define ENET_OPD_OPCODE_SHIFT (16U)
5032#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
5033
5035#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
5036#define ENET_IAUR_IADDR1_SHIFT (0U)
5037#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
5038
5040#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
5041#define ENET_IALR_IADDR2_SHIFT (0U)
5042#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
5043
5045#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
5046#define ENET_GAUR_GADDR1_SHIFT (0U)
5047#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
5048
5050#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
5051#define ENET_GALR_GADDR2_SHIFT (0U)
5052#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
5053
5055#define ENET_TFWR_TFWR_MASK (0x3FU)
5056#define ENET_TFWR_TFWR_SHIFT (0U)
5057#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
5058#define ENET_TFWR_STRFWD_MASK (0x100U)
5059#define ENET_TFWR_STRFWD_SHIFT (8U)
5060#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
5061
5063#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
5064#define ENET_RDSR_R_DES_START_SHIFT (3U)
5065#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
5066
5068#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
5069#define ENET_TDSR_X_DES_START_SHIFT (3U)
5070#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
5071
5073#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
5074#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
5075#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
5076
5078#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
5079#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
5080#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
5081
5083#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
5084#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
5085#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
5086
5088#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
5089#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
5090#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
5091
5093#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
5094#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
5095#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
5096
5098#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
5099#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
5100#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
5101
5103#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
5104#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
5105#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
5106
5108#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
5109#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
5110#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
5111
5113#define ENET_TIPG_IPG_MASK (0x1FU)
5114#define ENET_TIPG_IPG_SHIFT (0U)
5115#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
5116
5118#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
5119#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
5120#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
5121
5123#define ENET_TACC_SHIFT16_MASK (0x1U)
5124#define ENET_TACC_SHIFT16_SHIFT (0U)
5125#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
5126#define ENET_TACC_IPCHK_MASK (0x8U)
5127#define ENET_TACC_IPCHK_SHIFT (3U)
5128#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
5129#define ENET_TACC_PROCHK_MASK (0x10U)
5130#define ENET_TACC_PROCHK_SHIFT (4U)
5131#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
5132
5134#define ENET_RACC_PADREM_MASK (0x1U)
5135#define ENET_RACC_PADREM_SHIFT (0U)
5136#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
5137#define ENET_RACC_IPDIS_MASK (0x2U)
5138#define ENET_RACC_IPDIS_SHIFT (1U)
5139#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
5140#define ENET_RACC_PRODIS_MASK (0x4U)
5141#define ENET_RACC_PRODIS_SHIFT (2U)
5142#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
5143#define ENET_RACC_LINEDIS_MASK (0x40U)
5144#define ENET_RACC_LINEDIS_SHIFT (6U)
5145#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
5146#define ENET_RACC_SHIFT16_MASK (0x80U)
5147#define ENET_RACC_SHIFT16_SHIFT (7U)
5148#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
5149
5151#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
5152#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
5153#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
5154
5156#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
5157#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
5158#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
5159
5161#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
5162#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
5163#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
5164
5166#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
5167#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
5168#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
5169
5171#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
5172#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
5173#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
5174
5176#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
5177#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
5178#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
5179
5181#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
5182#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
5183#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
5184
5186#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
5187#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
5188#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
5189
5191#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
5192#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
5193#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
5194
5196#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
5197#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
5198#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
5199
5201#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
5202#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
5203#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
5204
5206#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
5207#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
5208#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
5209
5211#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
5212#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
5213#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
5214
5216#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
5217#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
5218#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
5219
5221#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
5222#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
5223#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
5224
5226#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
5227#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
5228#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
5229
5231#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
5232#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
5233#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
5234
5236#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
5237#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
5238#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
5239
5241#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
5242#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
5243#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
5244
5246#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
5247#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
5248#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
5249
5251#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
5252#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
5253#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
5254
5256#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
5257#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
5258#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
5259
5261#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
5262#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
5263#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
5264
5266#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
5267#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
5268#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
5269
5271#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
5272#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
5273#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
5274
5276#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
5277#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
5278#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
5279
5281#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
5282#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
5283#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
5284
5286#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
5287#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
5288#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
5289
5291#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
5292#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
5293#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
5294
5296#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
5297#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
5298#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
5299
5301#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
5302#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
5303#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
5304
5306#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
5307#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
5308#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
5309
5311#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
5312#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
5313#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
5314
5316#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
5317#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
5318#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
5319
5321#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
5322#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
5323#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
5324
5326#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
5327#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
5328#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
5329
5331#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
5332#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
5333#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
5334
5336#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
5337#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
5338#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
5339
5341#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
5342#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
5343#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
5344
5346#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
5347#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
5348#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
5349
5351#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
5352#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
5353#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
5354
5356#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
5357#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
5358#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
5359
5361#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
5362#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
5363#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
5364
5366#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
5367#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
5368#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
5369
5371#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
5372#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
5373#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
5374
5376#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
5377#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
5378#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
5379
5381#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
5382#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
5383#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
5384
5386#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
5387#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
5388#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
5389
5391#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
5392#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
5393#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
5394
5396#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
5397#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
5398#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
5399
5401#define ENET_ATCR_EN_MASK (0x1U)
5402#define ENET_ATCR_EN_SHIFT (0U)
5403#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
5404#define ENET_ATCR_OFFEN_MASK (0x4U)
5405#define ENET_ATCR_OFFEN_SHIFT (2U)
5406#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
5407#define ENET_ATCR_OFFRST_MASK (0x8U)
5408#define ENET_ATCR_OFFRST_SHIFT (3U)
5409#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
5410#define ENET_ATCR_PEREN_MASK (0x10U)
5411#define ENET_ATCR_PEREN_SHIFT (4U)
5412#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
5413#define ENET_ATCR_PINPER_MASK (0x80U)
5414#define ENET_ATCR_PINPER_SHIFT (7U)
5415#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
5416#define ENET_ATCR_RESTART_MASK (0x200U)
5417#define ENET_ATCR_RESTART_SHIFT (9U)
5418#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
5419#define ENET_ATCR_CAPTURE_MASK (0x800U)
5420#define ENET_ATCR_CAPTURE_SHIFT (11U)
5421#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
5422#define ENET_ATCR_SLAVE_MASK (0x2000U)
5423#define ENET_ATCR_SLAVE_SHIFT (13U)
5424#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
5425
5427#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
5428#define ENET_ATVR_ATIME_SHIFT (0U)
5429#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
5430
5432#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
5433#define ENET_ATOFF_OFFSET_SHIFT (0U)
5434#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
5435
5437#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
5438#define ENET_ATPER_PERIOD_SHIFT (0U)
5439#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
5440
5442#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
5443#define ENET_ATCOR_COR_SHIFT (0U)
5444#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
5445
5447#define ENET_ATINC_INC_MASK (0x7FU)
5448#define ENET_ATINC_INC_SHIFT (0U)
5449#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
5450#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
5451#define ENET_ATINC_INC_CORR_SHIFT (8U)
5452#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
5453
5455#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
5456#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
5457#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
5458
5460#define ENET_TGSR_TF0_MASK (0x1U)
5461#define ENET_TGSR_TF0_SHIFT (0U)
5462#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
5463#define ENET_TGSR_TF1_MASK (0x2U)
5464#define ENET_TGSR_TF1_SHIFT (1U)
5465#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
5466#define ENET_TGSR_TF2_MASK (0x4U)
5467#define ENET_TGSR_TF2_SHIFT (2U)
5468#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
5469#define ENET_TGSR_TF3_MASK (0x8U)
5470#define ENET_TGSR_TF3_SHIFT (3U)
5471#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
5472
5474#define ENET_TCSR_TDRE_MASK (0x1U)
5475#define ENET_TCSR_TDRE_SHIFT (0U)
5476#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
5477#define ENET_TCSR_TMODE_MASK (0x3CU)
5478#define ENET_TCSR_TMODE_SHIFT (2U)
5479#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
5480#define ENET_TCSR_TIE_MASK (0x40U)
5481#define ENET_TCSR_TIE_SHIFT (6U)
5482#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
5483#define ENET_TCSR_TF_MASK (0x80U)
5484#define ENET_TCSR_TF_SHIFT (7U)
5485#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
5486
5487/* The count of ENET_TCSR */
5488#define ENET_TCSR_COUNT (4U)
5489
5491#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
5492#define ENET_TCCR_TCC_SHIFT (0U)
5493#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
5494
5495/* The count of ENET_TCCR */
5496#define ENET_TCCR_COUNT (4U)
5497
5498
5501 /* end of group ENET_Register_Masks */
5502
5503
5504/* ENET - Peripheral instance base addresses */
5506#define ENET_BASE (0x400C0000u)
5508#define ENET ((ENET_Type *)ENET_BASE)
5510#define ENET_BASE_ADDRS { ENET_BASE }
5512#define ENET_BASE_PTRS { ENET }
5514#define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
5515#define ENET_Receive_IRQS { ENET_Receive_IRQn }
5516#define ENET_Error_IRQS { ENET_Error_IRQn }
5517#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
5518/* ENET Buffer Descriptor and Buffer Address Alignment. */
5519#define ENET_BUFF_ALIGNMENT (16U)
5520
5521
5524 /* end of group ENET_Peripheral_Access_Layer */
5525
5526
5527/* ----------------------------------------------------------------------------
5528 -- EWM Peripheral Access Layer
5529 ---------------------------------------------------------------------------- */
5530
5537typedef struct {
5538 __IO uint8_t CTRL;
5539 __O uint8_t SERV;
5540 __IO uint8_t CMPL;
5541 __IO uint8_t CMPH;
5542 uint8_t RESERVED_0[1];
5543 __IO uint8_t CLKPRESCALER;
5544} EWM_Type;
5545
5546/* ----------------------------------------------------------------------------
5547 -- EWM Register Masks
5548 ---------------------------------------------------------------------------- */
5549
5556#define EWM_CTRL_EWMEN_MASK (0x1U)
5557#define EWM_CTRL_EWMEN_SHIFT (0U)
5558#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
5559#define EWM_CTRL_ASSIN_MASK (0x2U)
5560#define EWM_CTRL_ASSIN_SHIFT (1U)
5561#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
5562#define EWM_CTRL_INEN_MASK (0x4U)
5563#define EWM_CTRL_INEN_SHIFT (2U)
5564#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
5565#define EWM_CTRL_INTEN_MASK (0x8U)
5566#define EWM_CTRL_INTEN_SHIFT (3U)
5567#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
5568
5570#define EWM_SERV_SERVICE_MASK (0xFFU)
5571#define EWM_SERV_SERVICE_SHIFT (0U)
5572#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
5573
5575#define EWM_CMPL_COMPAREL_MASK (0xFFU)
5576#define EWM_CMPL_COMPAREL_SHIFT (0U)
5577#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
5578
5580#define EWM_CMPH_COMPAREH_MASK (0xFFU)
5581#define EWM_CMPH_COMPAREH_SHIFT (0U)
5582#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
5583
5585#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
5586#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
5587#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
5588
5589
5592 /* end of group EWM_Register_Masks */
5593
5594
5595/* EWM - Peripheral instance base addresses */
5597#define EWM_BASE (0x40061000u)
5599#define EWM ((EWM_Type *)EWM_BASE)
5601#define EWM_BASE_ADDRS { EWM_BASE }
5603#define EWM_BASE_PTRS { EWM }
5605#define EWM_IRQS { WDOG_EWM_IRQn }
5606
5609 /* end of group EWM_Peripheral_Access_Layer */
5610
5611
5612/* ----------------------------------------------------------------------------
5613 -- FB Peripheral Access Layer
5614 ---------------------------------------------------------------------------- */
5615
5622typedef struct {
5623 struct { /* offset: 0x0, array step: 0xC */
5624 __IO uint32_t CSAR;
5625 __IO uint32_t CSMR;
5626 __IO uint32_t CSCR;
5627 } CS[6];
5628 uint8_t RESERVED_0[24];
5629 __IO uint32_t CSPMCR;
5630} FB_Type;
5631
5632/* ----------------------------------------------------------------------------
5633 -- FB Register Masks
5634 ---------------------------------------------------------------------------- */
5635
5642#define FB_CSAR_BA_MASK (0xFFFF0000U)
5643#define FB_CSAR_BA_SHIFT (16U)
5644#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
5645
5646/* The count of FB_CSAR */
5647#define FB_CSAR_COUNT (6U)
5648
5650#define FB_CSMR_V_MASK (0x1U)
5651#define FB_CSMR_V_SHIFT (0U)
5652#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
5653#define FB_CSMR_WP_MASK (0x100U)
5654#define FB_CSMR_WP_SHIFT (8U)
5655#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
5656#define FB_CSMR_BAM_MASK (0xFFFF0000U)
5657#define FB_CSMR_BAM_SHIFT (16U)
5658#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
5659
5660/* The count of FB_CSMR */
5661#define FB_CSMR_COUNT (6U)
5662
5664#define FB_CSCR_BSTW_MASK (0x8U)
5665#define FB_CSCR_BSTW_SHIFT (3U)
5666#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
5667#define FB_CSCR_BSTR_MASK (0x10U)
5668#define FB_CSCR_BSTR_SHIFT (4U)
5669#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
5670#define FB_CSCR_BEM_MASK (0x20U)
5671#define FB_CSCR_BEM_SHIFT (5U)
5672#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
5673#define FB_CSCR_PS_MASK (0xC0U)
5674#define FB_CSCR_PS_SHIFT (6U)
5675#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
5676#define FB_CSCR_AA_MASK (0x100U)
5677#define FB_CSCR_AA_SHIFT (8U)
5678#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
5679#define FB_CSCR_BLS_MASK (0x200U)
5680#define FB_CSCR_BLS_SHIFT (9U)
5681#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
5682#define FB_CSCR_WS_MASK (0xFC00U)
5683#define FB_CSCR_WS_SHIFT (10U)
5684#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
5685#define FB_CSCR_WRAH_MASK (0x30000U)
5686#define FB_CSCR_WRAH_SHIFT (16U)
5687#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
5688#define FB_CSCR_RDAH_MASK (0xC0000U)
5689#define FB_CSCR_RDAH_SHIFT (18U)
5690#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
5691#define FB_CSCR_ASET_MASK (0x300000U)
5692#define FB_CSCR_ASET_SHIFT (20U)
5693#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
5694#define FB_CSCR_EXTS_MASK (0x400000U)
5695#define FB_CSCR_EXTS_SHIFT (22U)
5696#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
5697#define FB_CSCR_SWSEN_MASK (0x800000U)
5698#define FB_CSCR_SWSEN_SHIFT (23U)
5699#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
5700#define FB_CSCR_SWS_MASK (0xFC000000U)
5701#define FB_CSCR_SWS_SHIFT (26U)
5702#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
5703
5704/* The count of FB_CSCR */
5705#define FB_CSCR_COUNT (6U)
5706
5708#define FB_CSPMCR_GROUP5_MASK (0xF000U)
5709#define FB_CSPMCR_GROUP5_SHIFT (12U)
5710#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
5711#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
5712#define FB_CSPMCR_GROUP4_SHIFT (16U)
5713#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
5714#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
5715#define FB_CSPMCR_GROUP3_SHIFT (20U)
5716#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
5717#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
5718#define FB_CSPMCR_GROUP2_SHIFT (24U)
5719#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
5720#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
5721#define FB_CSPMCR_GROUP1_SHIFT (28U)
5722#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
5723
5724
5727 /* end of group FB_Register_Masks */
5728
5729
5730/* FB - Peripheral instance base addresses */
5732#define FB_BASE (0x4000C000u)
5734#define FB ((FB_Type *)FB_BASE)
5736#define FB_BASE_ADDRS { FB_BASE }
5738#define FB_BASE_PTRS { FB }
5739
5742 /* end of group FB_Peripheral_Access_Layer */
5743
5744
5745/* ----------------------------------------------------------------------------
5746 -- FMC Peripheral Access Layer
5747 ---------------------------------------------------------------------------- */
5748
5755typedef struct {
5756 __IO uint32_t PFAPR;
5757 __IO uint32_t PFB0CR;
5758 __IO uint32_t PFB1CR;
5759 uint8_t RESERVED_0[244];
5760 __IO uint32_t TAGVD[4][8];
5761 uint8_t RESERVED_1[128];
5762 struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
5763 __IO uint32_t DATA_U;
5764 __IO uint32_t DATA_L;
5765 } SET[4][8];
5766} FMC_Type;
5767
5768/* ----------------------------------------------------------------------------
5769 -- FMC Register Masks
5770 ---------------------------------------------------------------------------- */
5771
5778#define FMC_PFAPR_M0AP_MASK (0x3U)
5779#define FMC_PFAPR_M0AP_SHIFT (0U)
5780#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
5781#define FMC_PFAPR_M1AP_MASK (0xCU)
5782#define FMC_PFAPR_M1AP_SHIFT (2U)
5783#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
5784#define FMC_PFAPR_M2AP_MASK (0x30U)
5785#define FMC_PFAPR_M2AP_SHIFT (4U)
5786#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
5787#define FMC_PFAPR_M3AP_MASK (0xC0U)
5788#define FMC_PFAPR_M3AP_SHIFT (6U)
5789#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
5790#define FMC_PFAPR_M4AP_MASK (0x300U)
5791#define FMC_PFAPR_M4AP_SHIFT (8U)
5792#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
5793#define FMC_PFAPR_M5AP_MASK (0xC00U)
5794#define FMC_PFAPR_M5AP_SHIFT (10U)
5795#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
5796#define FMC_PFAPR_M6AP_MASK (0x3000U)
5797#define FMC_PFAPR_M6AP_SHIFT (12U)
5798#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
5799#define FMC_PFAPR_M7AP_MASK (0xC000U)
5800#define FMC_PFAPR_M7AP_SHIFT (14U)
5801#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
5802#define FMC_PFAPR_M0PFD_MASK (0x10000U)
5803#define FMC_PFAPR_M0PFD_SHIFT (16U)
5804#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
5805#define FMC_PFAPR_M1PFD_MASK (0x20000U)
5806#define FMC_PFAPR_M1PFD_SHIFT (17U)
5807#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
5808#define FMC_PFAPR_M2PFD_MASK (0x40000U)
5809#define FMC_PFAPR_M2PFD_SHIFT (18U)
5810#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
5811#define FMC_PFAPR_M3PFD_MASK (0x80000U)
5812#define FMC_PFAPR_M3PFD_SHIFT (19U)
5813#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
5814#define FMC_PFAPR_M4PFD_MASK (0x100000U)
5815#define FMC_PFAPR_M4PFD_SHIFT (20U)
5816#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
5817#define FMC_PFAPR_M5PFD_MASK (0x200000U)
5818#define FMC_PFAPR_M5PFD_SHIFT (21U)
5819#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
5820#define FMC_PFAPR_M6PFD_MASK (0x400000U)
5821#define FMC_PFAPR_M6PFD_SHIFT (22U)
5822#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
5823#define FMC_PFAPR_M7PFD_MASK (0x800000U)
5824#define FMC_PFAPR_M7PFD_SHIFT (23U)
5825#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
5826
5828#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
5829#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
5830#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
5831#define FMC_PFB0CR_B0IPE_MASK (0x2U)
5832#define FMC_PFB0CR_B0IPE_SHIFT (1U)
5833#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
5834#define FMC_PFB0CR_B0DPE_MASK (0x4U)
5835#define FMC_PFB0CR_B0DPE_SHIFT (2U)
5836#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
5837#define FMC_PFB0CR_B0ICE_MASK (0x8U)
5838#define FMC_PFB0CR_B0ICE_SHIFT (3U)
5839#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
5840#define FMC_PFB0CR_B0DCE_MASK (0x10U)
5841#define FMC_PFB0CR_B0DCE_SHIFT (4U)
5842#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
5843#define FMC_PFB0CR_CRC_MASK (0xE0U)
5844#define FMC_PFB0CR_CRC_SHIFT (5U)
5845#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
5846#define FMC_PFB0CR_B0MW_MASK (0x60000U)
5847#define FMC_PFB0CR_B0MW_SHIFT (17U)
5848#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
5849#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
5850#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
5851#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
5852#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
5853#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
5854#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
5855#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
5856#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
5857#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
5858#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
5859#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
5860#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
5861
5863#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
5864#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
5865#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
5866#define FMC_PFB1CR_B1IPE_MASK (0x2U)
5867#define FMC_PFB1CR_B1IPE_SHIFT (1U)
5868#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
5869#define FMC_PFB1CR_B1DPE_MASK (0x4U)
5870#define FMC_PFB1CR_B1DPE_SHIFT (2U)
5871#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
5872#define FMC_PFB1CR_B1ICE_MASK (0x8U)
5873#define FMC_PFB1CR_B1ICE_SHIFT (3U)
5874#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
5875#define FMC_PFB1CR_B1DCE_MASK (0x10U)
5876#define FMC_PFB1CR_B1DCE_SHIFT (4U)
5877#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
5878#define FMC_PFB1CR_B1MW_MASK (0x60000U)
5879#define FMC_PFB1CR_B1MW_SHIFT (17U)
5880#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
5881#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
5882#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
5883#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
5884
5886#define FMC_TAGVD_valid_MASK (0x1U)
5887#define FMC_TAGVD_valid_SHIFT (0U)
5888#define FMC_TAGVD_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK)
5889#define FMC_TAGVD_tag_MASK (0x7FFC0U)
5890#define FMC_TAGVD_tag_SHIFT (6U)
5891#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK)
5892
5893/* The count of FMC_TAGVD */
5894#define FMC_TAGVD_COUNT (4U)
5895
5896/* The count of FMC_TAGVD */
5897#define FMC_TAGVD_COUNT2 (8U)
5898
5900#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
5901#define FMC_DATA_U_data_SHIFT (0U)
5902#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
5903
5904/* The count of FMC_DATA_U */
5905#define FMC_DATA_U_COUNT (4U)
5906
5907/* The count of FMC_DATA_U */
5908#define FMC_DATA_U_COUNT2 (8U)
5909
5911#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
5912#define FMC_DATA_L_data_SHIFT (0U)
5913#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
5914
5915/* The count of FMC_DATA_L */
5916#define FMC_DATA_L_COUNT (4U)
5917
5918/* The count of FMC_DATA_L */
5919#define FMC_DATA_L_COUNT2 (8U)
5920
5921
5924 /* end of group FMC_Register_Masks */
5925
5926
5927/* FMC - Peripheral instance base addresses */
5929#define FMC_BASE (0x4001F000u)
5931#define FMC ((FMC_Type *)FMC_BASE)
5933#define FMC_BASE_ADDRS { FMC_BASE }
5935#define FMC_BASE_PTRS { FMC }
5936
5939 /* end of group FMC_Peripheral_Access_Layer */
5940
5941
5942/* ----------------------------------------------------------------------------
5943 -- FTFL Peripheral Access Layer
5944 ---------------------------------------------------------------------------- */
5945
5952typedef struct {
5953 __IO uint8_t FSTAT;
5954 __IO uint8_t FCNFG;
5955 __I uint8_t FSEC;
5956 __I uint8_t FOPT;
5957 __IO uint8_t FCCOB3;
5958 __IO uint8_t FCCOB2;
5959 __IO uint8_t FCCOB1;
5960 __IO uint8_t FCCOB0;
5961 __IO uint8_t FCCOB7;
5962 __IO uint8_t FCCOB6;
5963 __IO uint8_t FCCOB5;
5964 __IO uint8_t FCCOB4;
5965 __IO uint8_t FCCOBB;
5966 __IO uint8_t FCCOBA;
5967 __IO uint8_t FCCOB9;
5968 __IO uint8_t FCCOB8;
5969 __IO uint8_t FPROT3;
5970 __IO uint8_t FPROT2;
5971 __IO uint8_t FPROT1;
5972 __IO uint8_t FPROT0;
5973 uint8_t RESERVED_0[2];
5974 __IO uint8_t FEPROT;
5975 __IO uint8_t FDPROT;
5976} FTFL_Type;
5977
5978/* ----------------------------------------------------------------------------
5979 -- FTFL Register Masks
5980 ---------------------------------------------------------------------------- */
5981
5988#define FTFL_FSTAT_MGSTAT0_MASK (0x1U)
5989#define FTFL_FSTAT_MGSTAT0_SHIFT (0U)
5990#define FTFL_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK)
5991#define FTFL_FSTAT_FPVIOL_MASK (0x10U)
5992#define FTFL_FSTAT_FPVIOL_SHIFT (4U)
5993#define FTFL_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK)
5994#define FTFL_FSTAT_ACCERR_MASK (0x20U)
5995#define FTFL_FSTAT_ACCERR_SHIFT (5U)
5996#define FTFL_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK)
5997#define FTFL_FSTAT_RDCOLERR_MASK (0x40U)
5998#define FTFL_FSTAT_RDCOLERR_SHIFT (6U)
5999#define FTFL_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK)
6000#define FTFL_FSTAT_CCIF_MASK (0x80U)
6001#define FTFL_FSTAT_CCIF_SHIFT (7U)
6002#define FTFL_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK)
6003
6005#define FTFL_FCNFG_EEERDY_MASK (0x1U)
6006#define FTFL_FCNFG_EEERDY_SHIFT (0U)
6007#define FTFL_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK)
6008#define FTFL_FCNFG_RAMRDY_MASK (0x2U)
6009#define FTFL_FCNFG_RAMRDY_SHIFT (1U)
6010#define FTFL_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK)
6011#define FTFL_FCNFG_PFLSH_MASK (0x4U)
6012#define FTFL_FCNFG_PFLSH_SHIFT (2U)
6013#define FTFL_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK)
6014#define FTFL_FCNFG_SWAP_MASK (0x8U)
6015#define FTFL_FCNFG_SWAP_SHIFT (3U)
6016#define FTFL_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_SWAP_SHIFT)) & FTFL_FCNFG_SWAP_MASK)
6017#define FTFL_FCNFG_ERSSUSP_MASK (0x10U)
6018#define FTFL_FCNFG_ERSSUSP_SHIFT (4U)
6019#define FTFL_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK)
6020#define FTFL_FCNFG_ERSAREQ_MASK (0x20U)
6021#define FTFL_FCNFG_ERSAREQ_SHIFT (5U)
6022#define FTFL_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK)
6023#define FTFL_FCNFG_RDCOLLIE_MASK (0x40U)
6024#define FTFL_FCNFG_RDCOLLIE_SHIFT (6U)
6025#define FTFL_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK)
6026#define FTFL_FCNFG_CCIE_MASK (0x80U)
6027#define FTFL_FCNFG_CCIE_SHIFT (7U)
6028#define FTFL_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK)
6029
6031#define FTFL_FSEC_SEC_MASK (0x3U)
6032#define FTFL_FSEC_SEC_SHIFT (0U)
6033#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK)
6034#define FTFL_FSEC_FSLACC_MASK (0xCU)
6035#define FTFL_FSEC_FSLACC_SHIFT (2U)
6036#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK)
6037#define FTFL_FSEC_MEEN_MASK (0x30U)
6038#define FTFL_FSEC_MEEN_SHIFT (4U)
6039#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK)
6040#define FTFL_FSEC_KEYEN_MASK (0xC0U)
6041#define FTFL_FSEC_KEYEN_SHIFT (6U)
6042#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK)
6043
6045#define FTFL_FOPT_OPT_MASK (0xFFU)
6046#define FTFL_FOPT_OPT_SHIFT (0U)
6047#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK)
6048
6050#define FTFL_FCCOB3_CCOBn_MASK (0xFFU)
6051#define FTFL_FCCOB3_CCOBn_SHIFT (0U)
6052#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK)
6053
6055#define FTFL_FCCOB2_CCOBn_MASK (0xFFU)
6056#define FTFL_FCCOB2_CCOBn_SHIFT (0U)
6057#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK)
6058
6060#define FTFL_FCCOB1_CCOBn_MASK (0xFFU)
6061#define FTFL_FCCOB1_CCOBn_SHIFT (0U)
6062#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK)
6063
6065#define FTFL_FCCOB0_CCOBn_MASK (0xFFU)
6066#define FTFL_FCCOB0_CCOBn_SHIFT (0U)
6067#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK)
6068
6070#define FTFL_FCCOB7_CCOBn_MASK (0xFFU)
6071#define FTFL_FCCOB7_CCOBn_SHIFT (0U)
6072#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK)
6073
6075#define FTFL_FCCOB6_CCOBn_MASK (0xFFU)
6076#define FTFL_FCCOB6_CCOBn_SHIFT (0U)
6077#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK)
6078
6080#define FTFL_FCCOB5_CCOBn_MASK (0xFFU)
6081#define FTFL_FCCOB5_CCOBn_SHIFT (0U)
6082#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK)
6083
6085#define FTFL_FCCOB4_CCOBn_MASK (0xFFU)
6086#define FTFL_FCCOB4_CCOBn_SHIFT (0U)
6087#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK)
6088
6090#define FTFL_FCCOBB_CCOBn_MASK (0xFFU)
6091#define FTFL_FCCOBB_CCOBn_SHIFT (0U)
6092#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK)
6093
6095#define FTFL_FCCOBA_CCOBn_MASK (0xFFU)
6096#define FTFL_FCCOBA_CCOBn_SHIFT (0U)
6097#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK)
6098
6100#define FTFL_FCCOB9_CCOBn_MASK (0xFFU)
6101#define FTFL_FCCOB9_CCOBn_SHIFT (0U)
6102#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK)
6103
6105#define FTFL_FCCOB8_CCOBn_MASK (0xFFU)
6106#define FTFL_FCCOB8_CCOBn_SHIFT (0U)
6107#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK)
6108
6110#define FTFL_FPROT3_PROT_MASK (0xFFU)
6111#define FTFL_FPROT3_PROT_SHIFT (0U)
6112#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK)
6113
6115#define FTFL_FPROT2_PROT_MASK (0xFFU)
6116#define FTFL_FPROT2_PROT_SHIFT (0U)
6117#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK)
6118
6120#define FTFL_FPROT1_PROT_MASK (0xFFU)
6121#define FTFL_FPROT1_PROT_SHIFT (0U)
6122#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK)
6123
6125#define FTFL_FPROT0_PROT_MASK (0xFFU)
6126#define FTFL_FPROT0_PROT_SHIFT (0U)
6127#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK)
6128
6130#define FTFL_FEPROT_EPROT_MASK (0xFFU)
6131#define FTFL_FEPROT_EPROT_SHIFT (0U)
6132#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK)
6133
6135#define FTFL_FDPROT_DPROT_MASK (0xFFU)
6136#define FTFL_FDPROT_DPROT_SHIFT (0U)
6137#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK)
6138
6139
6142 /* end of group FTFL_Register_Masks */
6143
6144
6145/* FTFL - Peripheral instance base addresses */
6147#define FTFL_BASE (0x40020000u)
6149#define FTFL ((FTFL_Type *)FTFL_BASE)
6151#define FTFL_BASE_ADDRS { FTFL_BASE }
6153#define FTFL_BASE_PTRS { FTFL }
6155#define FTFL_COMMAND_COMPLETE_IRQS { FTFL_IRQn }
6156#define FTFL_READ_COLLISION_IRQS { Read_Collision_IRQn }
6157
6160 /* end of group FTFL_Peripheral_Access_Layer */
6161
6162
6163/* ----------------------------------------------------------------------------
6164 -- FTM Peripheral Access Layer
6165 ---------------------------------------------------------------------------- */
6166
6173typedef struct {
6174 __IO uint32_t SC;
6175 __IO uint32_t CNT;
6176 __IO uint32_t MOD;
6177 struct { /* offset: 0xC, array step: 0x8 */
6178 __IO uint32_t CnSC;
6179 __IO uint32_t CnV;
6180 } CONTROLS[8];
6181 __IO uint32_t CNTIN;
6182 __IO uint32_t STATUS;
6183 __IO uint32_t MODE;
6184 __IO uint32_t SYNC;
6185 __IO uint32_t OUTINIT;
6186 __IO uint32_t OUTMASK;
6187 __IO uint32_t COMBINE;
6188 __IO uint32_t DEADTIME;
6189 __IO uint32_t EXTTRIG;
6190 __IO uint32_t POL;
6191 __IO uint32_t FMS;
6192 __IO uint32_t FILTER;
6193 __IO uint32_t FLTCTRL;
6194 __IO uint32_t QDCTRL;
6195 __IO uint32_t CONF;
6196 __IO uint32_t FLTPOL;
6197 __IO uint32_t SYNCONF;
6198 __IO uint32_t INVCTRL;
6199 __IO uint32_t SWOCTRL;
6200 __IO uint32_t PWMLOAD;
6201} FTM_Type;
6202
6203/* ----------------------------------------------------------------------------
6204 -- FTM Register Masks
6205 ---------------------------------------------------------------------------- */
6206
6213#define FTM_SC_PS_MASK (0x7U)
6214#define FTM_SC_PS_SHIFT (0U)
6215#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
6216#define FTM_SC_CLKS_MASK (0x18U)
6217#define FTM_SC_CLKS_SHIFT (3U)
6218#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
6219#define FTM_SC_CPWMS_MASK (0x20U)
6220#define FTM_SC_CPWMS_SHIFT (5U)
6221#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
6222#define FTM_SC_TOIE_MASK (0x40U)
6223#define FTM_SC_TOIE_SHIFT (6U)
6224#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
6225#define FTM_SC_TOF_MASK (0x80U)
6226#define FTM_SC_TOF_SHIFT (7U)
6227#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
6228
6230#define FTM_CNT_COUNT_MASK (0xFFFFU)
6231#define FTM_CNT_COUNT_SHIFT (0U)
6232#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
6233
6235#define FTM_MOD_MOD_MASK (0xFFFFU)
6236#define FTM_MOD_MOD_SHIFT (0U)
6237#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
6238
6240#define FTM_CnSC_DMA_MASK (0x1U)
6241#define FTM_CnSC_DMA_SHIFT (0U)
6242#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
6243#define FTM_CnSC_ELSA_MASK (0x4U)
6244#define FTM_CnSC_ELSA_SHIFT (2U)
6245#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
6246#define FTM_CnSC_ELSB_MASK (0x8U)
6247#define FTM_CnSC_ELSB_SHIFT (3U)
6248#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
6249#define FTM_CnSC_MSA_MASK (0x10U)
6250#define FTM_CnSC_MSA_SHIFT (4U)
6251#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
6252#define FTM_CnSC_MSB_MASK (0x20U)
6253#define FTM_CnSC_MSB_SHIFT (5U)
6254#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
6255#define FTM_CnSC_CHIE_MASK (0x40U)
6256#define FTM_CnSC_CHIE_SHIFT (6U)
6257#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
6258#define FTM_CnSC_CHF_MASK (0x80U)
6259#define FTM_CnSC_CHF_SHIFT (7U)
6260#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
6261
6262/* The count of FTM_CnSC */
6263#define FTM_CnSC_COUNT (8U)
6264
6266#define FTM_CnV_VAL_MASK (0xFFFFU)
6267#define FTM_CnV_VAL_SHIFT (0U)
6268#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
6269
6270/* The count of FTM_CnV */
6271#define FTM_CnV_COUNT (8U)
6272
6274#define FTM_CNTIN_INIT_MASK (0xFFFFU)
6275#define FTM_CNTIN_INIT_SHIFT (0U)
6276#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
6277
6279#define FTM_STATUS_CH0F_MASK (0x1U)
6280#define FTM_STATUS_CH0F_SHIFT (0U)
6281#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
6282#define FTM_STATUS_CH1F_MASK (0x2U)
6283#define FTM_STATUS_CH1F_SHIFT (1U)
6284#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
6285#define FTM_STATUS_CH2F_MASK (0x4U)
6286#define FTM_STATUS_CH2F_SHIFT (2U)
6287#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
6288#define FTM_STATUS_CH3F_MASK (0x8U)
6289#define FTM_STATUS_CH3F_SHIFT (3U)
6290#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
6291#define FTM_STATUS_CH4F_MASK (0x10U)
6292#define FTM_STATUS_CH4F_SHIFT (4U)
6293#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
6294#define FTM_STATUS_CH5F_MASK (0x20U)
6295#define FTM_STATUS_CH5F_SHIFT (5U)
6296#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
6297#define FTM_STATUS_CH6F_MASK (0x40U)
6298#define FTM_STATUS_CH6F_SHIFT (6U)
6299#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
6300#define FTM_STATUS_CH7F_MASK (0x80U)
6301#define FTM_STATUS_CH7F_SHIFT (7U)
6302#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
6303
6305#define FTM_MODE_FTMEN_MASK (0x1U)
6306#define FTM_MODE_FTMEN_SHIFT (0U)
6307#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
6308#define FTM_MODE_INIT_MASK (0x2U)
6309#define FTM_MODE_INIT_SHIFT (1U)
6310#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
6311#define FTM_MODE_WPDIS_MASK (0x4U)
6312#define FTM_MODE_WPDIS_SHIFT (2U)
6313#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
6314#define FTM_MODE_PWMSYNC_MASK (0x8U)
6315#define FTM_MODE_PWMSYNC_SHIFT (3U)
6316#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
6317#define FTM_MODE_CAPTEST_MASK (0x10U)
6318#define FTM_MODE_CAPTEST_SHIFT (4U)
6319#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
6320#define FTM_MODE_FAULTM_MASK (0x60U)
6321#define FTM_MODE_FAULTM_SHIFT (5U)
6322#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
6323#define FTM_MODE_FAULTIE_MASK (0x80U)
6324#define FTM_MODE_FAULTIE_SHIFT (7U)
6325#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
6326
6328#define FTM_SYNC_CNTMIN_MASK (0x1U)
6329#define FTM_SYNC_CNTMIN_SHIFT (0U)
6330#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
6331#define FTM_SYNC_CNTMAX_MASK (0x2U)
6332#define FTM_SYNC_CNTMAX_SHIFT (1U)
6333#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
6334#define FTM_SYNC_REINIT_MASK (0x4U)
6335#define FTM_SYNC_REINIT_SHIFT (2U)
6336#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
6337#define FTM_SYNC_SYNCHOM_MASK (0x8U)
6338#define FTM_SYNC_SYNCHOM_SHIFT (3U)
6339#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
6340#define FTM_SYNC_TRIG0_MASK (0x10U)
6341#define FTM_SYNC_TRIG0_SHIFT (4U)
6342#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
6343#define FTM_SYNC_TRIG1_MASK (0x20U)
6344#define FTM_SYNC_TRIG1_SHIFT (5U)
6345#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
6346#define FTM_SYNC_TRIG2_MASK (0x40U)
6347#define FTM_SYNC_TRIG2_SHIFT (6U)
6348#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
6349#define FTM_SYNC_SWSYNC_MASK (0x80U)
6350#define FTM_SYNC_SWSYNC_SHIFT (7U)
6351#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
6352
6354#define FTM_OUTINIT_CH0OI_MASK (0x1U)
6355#define FTM_OUTINIT_CH0OI_SHIFT (0U)
6356#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
6357#define FTM_OUTINIT_CH1OI_MASK (0x2U)
6358#define FTM_OUTINIT_CH1OI_SHIFT (1U)
6359#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
6360#define FTM_OUTINIT_CH2OI_MASK (0x4U)
6361#define FTM_OUTINIT_CH2OI_SHIFT (2U)
6362#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
6363#define FTM_OUTINIT_CH3OI_MASK (0x8U)
6364#define FTM_OUTINIT_CH3OI_SHIFT (3U)
6365#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
6366#define FTM_OUTINIT_CH4OI_MASK (0x10U)
6367#define FTM_OUTINIT_CH4OI_SHIFT (4U)
6368#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
6369#define FTM_OUTINIT_CH5OI_MASK (0x20U)
6370#define FTM_OUTINIT_CH5OI_SHIFT (5U)
6371#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
6372#define FTM_OUTINIT_CH6OI_MASK (0x40U)
6373#define FTM_OUTINIT_CH6OI_SHIFT (6U)
6374#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
6375#define FTM_OUTINIT_CH7OI_MASK (0x80U)
6376#define FTM_OUTINIT_CH7OI_SHIFT (7U)
6377#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
6378
6380#define FTM_OUTMASK_CH0OM_MASK (0x1U)
6381#define FTM_OUTMASK_CH0OM_SHIFT (0U)
6382#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
6383#define FTM_OUTMASK_CH1OM_MASK (0x2U)
6384#define FTM_OUTMASK_CH1OM_SHIFT (1U)
6385#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
6386#define FTM_OUTMASK_CH2OM_MASK (0x4U)
6387#define FTM_OUTMASK_CH2OM_SHIFT (2U)
6388#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
6389#define FTM_OUTMASK_CH3OM_MASK (0x8U)
6390#define FTM_OUTMASK_CH3OM_SHIFT (3U)
6391#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
6392#define FTM_OUTMASK_CH4OM_MASK (0x10U)
6393#define FTM_OUTMASK_CH4OM_SHIFT (4U)
6394#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
6395#define FTM_OUTMASK_CH5OM_MASK (0x20U)
6396#define FTM_OUTMASK_CH5OM_SHIFT (5U)
6397#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
6398#define FTM_OUTMASK_CH6OM_MASK (0x40U)
6399#define FTM_OUTMASK_CH6OM_SHIFT (6U)
6400#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
6401#define FTM_OUTMASK_CH7OM_MASK (0x80U)
6402#define FTM_OUTMASK_CH7OM_SHIFT (7U)
6403#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
6404
6406#define FTM_COMBINE_COMBINE0_MASK (0x1U)
6407#define FTM_COMBINE_COMBINE0_SHIFT (0U)
6408#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
6409#define FTM_COMBINE_COMP0_MASK (0x2U)
6410#define FTM_COMBINE_COMP0_SHIFT (1U)
6411#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
6412#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
6413#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
6414#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
6415#define FTM_COMBINE_DECAP0_MASK (0x8U)
6416#define FTM_COMBINE_DECAP0_SHIFT (3U)
6417#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
6418#define FTM_COMBINE_DTEN0_MASK (0x10U)
6419#define FTM_COMBINE_DTEN0_SHIFT (4U)
6420#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
6421#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
6422#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
6423#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
6424#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
6425#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
6426#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
6427#define FTM_COMBINE_COMBINE1_MASK (0x100U)
6428#define FTM_COMBINE_COMBINE1_SHIFT (8U)
6429#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
6430#define FTM_COMBINE_COMP1_MASK (0x200U)
6431#define FTM_COMBINE_COMP1_SHIFT (9U)
6432#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
6433#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
6434#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
6435#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
6436#define FTM_COMBINE_DECAP1_MASK (0x800U)
6437#define FTM_COMBINE_DECAP1_SHIFT (11U)
6438#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
6439#define FTM_COMBINE_DTEN1_MASK (0x1000U)
6440#define FTM_COMBINE_DTEN1_SHIFT (12U)
6441#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
6442#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
6443#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
6444#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
6445#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
6446#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
6447#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
6448#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
6449#define FTM_COMBINE_COMBINE2_SHIFT (16U)
6450#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
6451#define FTM_COMBINE_COMP2_MASK (0x20000U)
6452#define FTM_COMBINE_COMP2_SHIFT (17U)
6453#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
6454#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
6455#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
6456#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
6457#define FTM_COMBINE_DECAP2_MASK (0x80000U)
6458#define FTM_COMBINE_DECAP2_SHIFT (19U)
6459#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
6460#define FTM_COMBINE_DTEN2_MASK (0x100000U)
6461#define FTM_COMBINE_DTEN2_SHIFT (20U)
6462#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
6463#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
6464#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
6465#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
6466#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
6467#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
6468#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
6469#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
6470#define FTM_COMBINE_COMBINE3_SHIFT (24U)
6471#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
6472#define FTM_COMBINE_COMP3_MASK (0x2000000U)
6473#define FTM_COMBINE_COMP3_SHIFT (25U)
6474#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
6475#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
6476#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
6477#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
6478#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
6479#define FTM_COMBINE_DECAP3_SHIFT (27U)
6480#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
6481#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
6482#define FTM_COMBINE_DTEN3_SHIFT (28U)
6483#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
6484#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
6485#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
6486#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
6487#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
6488#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
6489#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
6490
6492#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
6493#define FTM_DEADTIME_DTVAL_SHIFT (0U)
6494#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
6495#define FTM_DEADTIME_DTPS_MASK (0xC0U)
6496#define FTM_DEADTIME_DTPS_SHIFT (6U)
6497#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
6498
6500#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
6501#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
6502#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
6503#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
6504#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
6505#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
6506#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
6507#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
6508#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
6509#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
6510#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
6511#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
6512#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
6513#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
6514#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
6515#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
6516#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
6517#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
6518#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
6519#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
6520#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
6521#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
6522#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
6523#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
6524
6526#define FTM_POL_POL0_MASK (0x1U)
6527#define FTM_POL_POL0_SHIFT (0U)
6528#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
6529#define FTM_POL_POL1_MASK (0x2U)
6530#define FTM_POL_POL1_SHIFT (1U)
6531#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
6532#define FTM_POL_POL2_MASK (0x4U)
6533#define FTM_POL_POL2_SHIFT (2U)
6534#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
6535#define FTM_POL_POL3_MASK (0x8U)
6536#define FTM_POL_POL3_SHIFT (3U)
6537#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
6538#define FTM_POL_POL4_MASK (0x10U)
6539#define FTM_POL_POL4_SHIFT (4U)
6540#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
6541#define FTM_POL_POL5_MASK (0x20U)
6542#define FTM_POL_POL5_SHIFT (5U)
6543#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
6544#define FTM_POL_POL6_MASK (0x40U)
6545#define FTM_POL_POL6_SHIFT (6U)
6546#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
6547#define FTM_POL_POL7_MASK (0x80U)
6548#define FTM_POL_POL7_SHIFT (7U)
6549#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
6550
6552#define FTM_FMS_FAULTF0_MASK (0x1U)
6553#define FTM_FMS_FAULTF0_SHIFT (0U)
6554#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
6555#define FTM_FMS_FAULTF1_MASK (0x2U)
6556#define FTM_FMS_FAULTF1_SHIFT (1U)
6557#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
6558#define FTM_FMS_FAULTF2_MASK (0x4U)
6559#define FTM_FMS_FAULTF2_SHIFT (2U)
6560#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
6561#define FTM_FMS_FAULTF3_MASK (0x8U)
6562#define FTM_FMS_FAULTF3_SHIFT (3U)
6563#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
6564#define FTM_FMS_FAULTIN_MASK (0x20U)
6565#define FTM_FMS_FAULTIN_SHIFT (5U)
6566#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
6567#define FTM_FMS_WPEN_MASK (0x40U)
6568#define FTM_FMS_WPEN_SHIFT (6U)
6569#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
6570#define FTM_FMS_FAULTF_MASK (0x80U)
6571#define FTM_FMS_FAULTF_SHIFT (7U)
6572#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
6573
6575#define FTM_FILTER_CH0FVAL_MASK (0xFU)
6576#define FTM_FILTER_CH0FVAL_SHIFT (0U)
6577#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
6578#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
6579#define FTM_FILTER_CH1FVAL_SHIFT (4U)
6580#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
6581#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
6582#define FTM_FILTER_CH2FVAL_SHIFT (8U)
6583#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
6584#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
6585#define FTM_FILTER_CH3FVAL_SHIFT (12U)
6586#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
6587
6589#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
6590#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
6591#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
6592#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
6593#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
6594#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
6595#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
6596#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
6597#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
6598#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
6599#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
6600#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
6601#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
6602#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
6603#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
6604#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
6605#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
6606#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
6607#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
6608#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
6609#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
6610#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
6611#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
6612#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
6613#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
6614#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
6615#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
6616
6618#define FTM_QDCTRL_QUADEN_MASK (0x1U)
6619#define FTM_QDCTRL_QUADEN_SHIFT (0U)
6620#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
6621#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
6622#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
6623#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
6624#define FTM_QDCTRL_QUADIR_MASK (0x4U)
6625#define FTM_QDCTRL_QUADIR_SHIFT (2U)
6626#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
6627#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
6628#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
6629#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
6630#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
6631#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
6632#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
6633#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
6634#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
6635#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
6636#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
6637#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
6638#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
6639#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
6640#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
6641#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
6642
6644#define FTM_CONF_NUMTOF_MASK (0x1FU)
6645#define FTM_CONF_NUMTOF_SHIFT (0U)
6646#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
6647#define FTM_CONF_BDMMODE_MASK (0xC0U)
6648#define FTM_CONF_BDMMODE_SHIFT (6U)
6649#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
6650#define FTM_CONF_GTBEEN_MASK (0x200U)
6651#define FTM_CONF_GTBEEN_SHIFT (9U)
6652#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
6653#define FTM_CONF_GTBEOUT_MASK (0x400U)
6654#define FTM_CONF_GTBEOUT_SHIFT (10U)
6655#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
6656
6658#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
6659#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
6660#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
6661#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
6662#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
6663#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
6664#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
6665#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
6666#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
6667#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
6668#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
6669#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
6670
6672#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
6673#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
6674#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
6675#define FTM_SYNCONF_CNTINC_MASK (0x4U)
6676#define FTM_SYNCONF_CNTINC_SHIFT (2U)
6677#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
6678#define FTM_SYNCONF_INVC_MASK (0x10U)
6679#define FTM_SYNCONF_INVC_SHIFT (4U)
6680#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
6681#define FTM_SYNCONF_SWOC_MASK (0x20U)
6682#define FTM_SYNCONF_SWOC_SHIFT (5U)
6683#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
6684#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
6685#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
6686#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
6687#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
6688#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
6689#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
6690#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
6691#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
6692#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
6693#define FTM_SYNCONF_SWOM_MASK (0x400U)
6694#define FTM_SYNCONF_SWOM_SHIFT (10U)
6695#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
6696#define FTM_SYNCONF_SWINVC_MASK (0x800U)
6697#define FTM_SYNCONF_SWINVC_SHIFT (11U)
6698#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
6699#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
6700#define FTM_SYNCONF_SWSOC_SHIFT (12U)
6701#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
6702#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
6703#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
6704#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
6705#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
6706#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
6707#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
6708#define FTM_SYNCONF_HWOM_MASK (0x40000U)
6709#define FTM_SYNCONF_HWOM_SHIFT (18U)
6710#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
6711#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
6712#define FTM_SYNCONF_HWINVC_SHIFT (19U)
6713#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
6714#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
6715#define FTM_SYNCONF_HWSOC_SHIFT (20U)
6716#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
6717
6719#define FTM_INVCTRL_INV0EN_MASK (0x1U)
6720#define FTM_INVCTRL_INV0EN_SHIFT (0U)
6721#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
6722#define FTM_INVCTRL_INV1EN_MASK (0x2U)
6723#define FTM_INVCTRL_INV1EN_SHIFT (1U)
6724#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
6725#define FTM_INVCTRL_INV2EN_MASK (0x4U)
6726#define FTM_INVCTRL_INV2EN_SHIFT (2U)
6727#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
6728#define FTM_INVCTRL_INV3EN_MASK (0x8U)
6729#define FTM_INVCTRL_INV3EN_SHIFT (3U)
6730#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
6731
6733#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
6734#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
6735#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
6736#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
6737#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
6738#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
6739#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
6740#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
6741#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
6742#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
6743#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
6744#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
6745#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
6746#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
6747#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
6748#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
6749#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
6750#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
6751#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
6752#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
6753#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
6754#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
6755#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
6756#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
6757#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
6758#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
6759#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
6760#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
6761#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
6762#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
6763#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
6764#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
6765#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
6766#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
6767#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
6768#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
6769#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
6770#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
6771#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
6772#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
6773#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
6774#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
6775#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
6776#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
6777#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
6778#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
6779#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
6780#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
6781
6783#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
6784#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
6785#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
6786#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
6787#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
6788#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
6789#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
6790#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
6791#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
6792#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
6793#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
6794#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
6795#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
6796#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
6797#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
6798#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
6799#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
6800#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
6801#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
6802#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
6803#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
6804#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
6805#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
6806#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
6807#define FTM_PWMLOAD_LDOK_MASK (0x200U)
6808#define FTM_PWMLOAD_LDOK_SHIFT (9U)
6809#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
6810
6811
6814 /* end of group FTM_Register_Masks */
6815
6816
6817/* FTM - Peripheral instance base addresses */
6819#define FTM0_BASE (0x40038000u)
6821#define FTM0 ((FTM_Type *)FTM0_BASE)
6823#define FTM1_BASE (0x40039000u)
6825#define FTM1 ((FTM_Type *)FTM1_BASE)
6827#define FTM2_BASE (0x400B8000u)
6829#define FTM2 ((FTM_Type *)FTM2_BASE)
6831#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
6833#define FTM_BASE_PTRS { FTM0, FTM1, FTM2 }
6835#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
6836
6839 /* end of group FTM_Peripheral_Access_Layer */
6840
6841
6842/* ----------------------------------------------------------------------------
6843 -- GPIO Peripheral Access Layer
6844 ---------------------------------------------------------------------------- */
6845
6852typedef struct {
6853 __IO uint32_t PDOR;
6854 __O uint32_t PSOR;
6855 __O uint32_t PCOR;
6856 __O uint32_t PTOR;
6857 __I uint32_t PDIR;
6858 __IO uint32_t PDDR;
6859} GPIO_Type;
6860
6861/* ----------------------------------------------------------------------------
6862 -- GPIO Register Masks
6863 ---------------------------------------------------------------------------- */
6864
6871#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
6872#define GPIO_PDOR_PDO_SHIFT (0U)
6873#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
6874
6876#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
6877#define GPIO_PSOR_PTSO_SHIFT (0U)
6878#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
6879
6881#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
6882#define GPIO_PCOR_PTCO_SHIFT (0U)
6883#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
6884
6886#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
6887#define GPIO_PTOR_PTTO_SHIFT (0U)
6888#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
6889
6891#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
6892#define GPIO_PDIR_PDI_SHIFT (0U)
6893#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
6894
6896#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
6897#define GPIO_PDDR_PDD_SHIFT (0U)
6898#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
6899
6900
6903 /* end of group GPIO_Register_Masks */
6904
6905
6906/* GPIO - Peripheral instance base addresses */
6908#define GPIOA_BASE (0x400FF000u)
6910#define GPIOA ((GPIO_Type *)GPIOA_BASE)
6912#define GPIOB_BASE (0x400FF040u)
6914#define GPIOB ((GPIO_Type *)GPIOB_BASE)
6916#define GPIOC_BASE (0x400FF080u)
6918#define GPIOC ((GPIO_Type *)GPIOC_BASE)
6920#define GPIOD_BASE (0x400FF0C0u)
6922#define GPIOD ((GPIO_Type *)GPIOD_BASE)
6924#define GPIOE_BASE (0x400FF100u)
6926#define GPIOE ((GPIO_Type *)GPIOE_BASE)
6928#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
6930#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
6931
6934 /* end of group GPIO_Peripheral_Access_Layer */
6935
6936
6937/* ----------------------------------------------------------------------------
6938 -- I2C Peripheral Access Layer
6939 ---------------------------------------------------------------------------- */
6940
6947typedef struct {
6948 __IO uint8_t A1;
6949 __IO uint8_t F;
6950 __IO uint8_t C1;
6951 __IO uint8_t S;
6952 __IO uint8_t D;
6953 __IO uint8_t C2;
6954 __IO uint8_t FLT;
6955 __IO uint8_t RA;
6956 __IO uint8_t SMB;
6957 __IO uint8_t A2;
6958 __IO uint8_t SLTH;
6959 __IO uint8_t SLTL;
6960} I2C_Type;
6961
6962/* ----------------------------------------------------------------------------
6963 -- I2C Register Masks
6964 ---------------------------------------------------------------------------- */
6965
6972#define I2C_A1_AD_MASK (0xFEU)
6973#define I2C_A1_AD_SHIFT (1U)
6974#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
6975
6977#define I2C_F_ICR_MASK (0x3FU)
6978#define I2C_F_ICR_SHIFT (0U)
6979#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
6980#define I2C_F_MULT_MASK (0xC0U)
6981#define I2C_F_MULT_SHIFT (6U)
6982#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
6983
6985#define I2C_C1_DMAEN_MASK (0x1U)
6986#define I2C_C1_DMAEN_SHIFT (0U)
6987#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
6988#define I2C_C1_WUEN_MASK (0x2U)
6989#define I2C_C1_WUEN_SHIFT (1U)
6990#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
6991#define I2C_C1_RSTA_MASK (0x4U)
6992#define I2C_C1_RSTA_SHIFT (2U)
6993#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
6994#define I2C_C1_TXAK_MASK (0x8U)
6995#define I2C_C1_TXAK_SHIFT (3U)
6996#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
6997#define I2C_C1_TX_MASK (0x10U)
6998#define I2C_C1_TX_SHIFT (4U)
6999#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
7000#define I2C_C1_MST_MASK (0x20U)
7001#define I2C_C1_MST_SHIFT (5U)
7002#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
7003#define I2C_C1_IICIE_MASK (0x40U)
7004#define I2C_C1_IICIE_SHIFT (6U)
7005#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
7006#define I2C_C1_IICEN_MASK (0x80U)
7007#define I2C_C1_IICEN_SHIFT (7U)
7008#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
7009
7011#define I2C_S_RXAK_MASK (0x1U)
7012#define I2C_S_RXAK_SHIFT (0U)
7013#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
7014#define I2C_S_IICIF_MASK (0x2U)
7015#define I2C_S_IICIF_SHIFT (1U)
7016#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
7017#define I2C_S_SRW_MASK (0x4U)
7018#define I2C_S_SRW_SHIFT (2U)
7019#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
7020#define I2C_S_RAM_MASK (0x8U)
7021#define I2C_S_RAM_SHIFT (3U)
7022#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
7023#define I2C_S_ARBL_MASK (0x10U)
7024#define I2C_S_ARBL_SHIFT (4U)
7025#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
7026#define I2C_S_BUSY_MASK (0x20U)
7027#define I2C_S_BUSY_SHIFT (5U)
7028#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
7029#define I2C_S_IAAS_MASK (0x40U)
7030#define I2C_S_IAAS_SHIFT (6U)
7031#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
7032#define I2C_S_TCF_MASK (0x80U)
7033#define I2C_S_TCF_SHIFT (7U)
7034#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
7035
7037#define I2C_D_DATA_MASK (0xFFU)
7038#define I2C_D_DATA_SHIFT (0U)
7039#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
7040
7042#define I2C_C2_AD_MASK (0x7U)
7043#define I2C_C2_AD_SHIFT (0U)
7044#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
7045#define I2C_C2_RMEN_MASK (0x8U)
7046#define I2C_C2_RMEN_SHIFT (3U)
7047#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
7048#define I2C_C2_SBRC_MASK (0x10U)
7049#define I2C_C2_SBRC_SHIFT (4U)
7050#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
7051#define I2C_C2_HDRS_MASK (0x20U)
7052#define I2C_C2_HDRS_SHIFT (5U)
7053#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
7054#define I2C_C2_ADEXT_MASK (0x40U)
7055#define I2C_C2_ADEXT_SHIFT (6U)
7056#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
7057#define I2C_C2_GCAEN_MASK (0x80U)
7058#define I2C_C2_GCAEN_SHIFT (7U)
7059#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
7060
7062#define I2C_FLT_FLT_MASK (0x1FU)
7063#define I2C_FLT_FLT_SHIFT (0U)
7064#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
7065
7067#define I2C_RA_RAD_MASK (0xFEU)
7068#define I2C_RA_RAD_SHIFT (1U)
7069#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
7070
7072#define I2C_SMB_SHTF2IE_MASK (0x1U)
7073#define I2C_SMB_SHTF2IE_SHIFT (0U)
7074#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
7075#define I2C_SMB_SHTF2_MASK (0x2U)
7076#define I2C_SMB_SHTF2_SHIFT (1U)
7077#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
7078#define I2C_SMB_SHTF1_MASK (0x4U)
7079#define I2C_SMB_SHTF1_SHIFT (2U)
7080#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
7081#define I2C_SMB_SLTF_MASK (0x8U)
7082#define I2C_SMB_SLTF_SHIFT (3U)
7083#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
7084#define I2C_SMB_TCKSEL_MASK (0x10U)
7085#define I2C_SMB_TCKSEL_SHIFT (4U)
7086#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
7087#define I2C_SMB_SIICAEN_MASK (0x20U)
7088#define I2C_SMB_SIICAEN_SHIFT (5U)
7089#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
7090#define I2C_SMB_ALERTEN_MASK (0x40U)
7091#define I2C_SMB_ALERTEN_SHIFT (6U)
7092#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
7093#define I2C_SMB_FACK_MASK (0x80U)
7094#define I2C_SMB_FACK_SHIFT (7U)
7095#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
7096
7098#define I2C_A2_SAD_MASK (0xFEU)
7099#define I2C_A2_SAD_SHIFT (1U)
7100#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
7101
7103#define I2C_SLTH_SSLT_MASK (0xFFU)
7104#define I2C_SLTH_SSLT_SHIFT (0U)
7105#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
7106
7108#define I2C_SLTL_SSLT_MASK (0xFFU)
7109#define I2C_SLTL_SSLT_SHIFT (0U)
7110#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
7111
7112
7115 /* end of group I2C_Register_Masks */
7116
7117
7118/* I2C - Peripheral instance base addresses */
7120#define I2C0_BASE (0x40066000u)
7122#define I2C0 ((I2C_Type *)I2C0_BASE)
7124#define I2C1_BASE (0x40067000u)
7126#define I2C1 ((I2C_Type *)I2C1_BASE)
7128#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
7130#define I2C_BASE_PTRS { I2C0, I2C1 }
7132#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
7133
7136 /* end of group I2C_Peripheral_Access_Layer */
7137
7138
7139/* ----------------------------------------------------------------------------
7140 -- I2S Peripheral Access Layer
7141 ---------------------------------------------------------------------------- */
7142
7149typedef struct {
7150 __IO uint32_t TCSR;
7151 __IO uint32_t TCR1;
7152 __IO uint32_t TCR2;
7153 __IO uint32_t TCR3;
7154 __IO uint32_t TCR4;
7155 __IO uint32_t TCR5;
7156 uint8_t RESERVED_0[8];
7157 __O uint32_t TDR[2];
7158 uint8_t RESERVED_1[24];
7159 __I uint32_t TFR[2];
7160 uint8_t RESERVED_2[24];
7161 __IO uint32_t TMR;
7162 uint8_t RESERVED_3[28];
7163 __IO uint32_t RCSR;
7164 __IO uint32_t RCR1;
7165 __IO uint32_t RCR2;
7166 __IO uint32_t RCR3;
7167 __IO uint32_t RCR4;
7168 __IO uint32_t RCR5;
7169 uint8_t RESERVED_4[8];
7170 __I uint32_t RDR[2];
7171 uint8_t RESERVED_5[24];
7172 __I uint32_t RFR[2];
7173 uint8_t RESERVED_6[24];
7174 __IO uint32_t RMR;
7175 uint8_t RESERVED_7[28];
7176 __IO uint32_t MCR;
7177 __IO uint32_t MDR;
7178} I2S_Type;
7179
7180/* ----------------------------------------------------------------------------
7181 -- I2S Register Masks
7182 ---------------------------------------------------------------------------- */
7183
7190#define I2S_TCSR_FRDE_MASK (0x1U)
7191#define I2S_TCSR_FRDE_SHIFT (0U)
7192#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
7193#define I2S_TCSR_FWDE_MASK (0x2U)
7194#define I2S_TCSR_FWDE_SHIFT (1U)
7195#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
7196#define I2S_TCSR_FRIE_MASK (0x100U)
7197#define I2S_TCSR_FRIE_SHIFT (8U)
7198#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
7199#define I2S_TCSR_FWIE_MASK (0x200U)
7200#define I2S_TCSR_FWIE_SHIFT (9U)
7201#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
7202#define I2S_TCSR_FEIE_MASK (0x400U)
7203#define I2S_TCSR_FEIE_SHIFT (10U)
7204#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
7205#define I2S_TCSR_SEIE_MASK (0x800U)
7206#define I2S_TCSR_SEIE_SHIFT (11U)
7207#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
7208#define I2S_TCSR_WSIE_MASK (0x1000U)
7209#define I2S_TCSR_WSIE_SHIFT (12U)
7210#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
7211#define I2S_TCSR_FRF_MASK (0x10000U)
7212#define I2S_TCSR_FRF_SHIFT (16U)
7213#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
7214#define I2S_TCSR_FWF_MASK (0x20000U)
7215#define I2S_TCSR_FWF_SHIFT (17U)
7216#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
7217#define I2S_TCSR_FEF_MASK (0x40000U)
7218#define I2S_TCSR_FEF_SHIFT (18U)
7219#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
7220#define I2S_TCSR_SEF_MASK (0x80000U)
7221#define I2S_TCSR_SEF_SHIFT (19U)
7222#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
7223#define I2S_TCSR_WSF_MASK (0x100000U)
7224#define I2S_TCSR_WSF_SHIFT (20U)
7225#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
7226#define I2S_TCSR_SR_MASK (0x1000000U)
7227#define I2S_TCSR_SR_SHIFT (24U)
7228#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
7229#define I2S_TCSR_FR_MASK (0x2000000U)
7230#define I2S_TCSR_FR_SHIFT (25U)
7231#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
7232#define I2S_TCSR_BCE_MASK (0x10000000U)
7233#define I2S_TCSR_BCE_SHIFT (28U)
7234#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
7235#define I2S_TCSR_DBGE_MASK (0x20000000U)
7236#define I2S_TCSR_DBGE_SHIFT (29U)
7237#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
7238#define I2S_TCSR_STOPE_MASK (0x40000000U)
7239#define I2S_TCSR_STOPE_SHIFT (30U)
7240#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
7241#define I2S_TCSR_TE_MASK (0x80000000U)
7242#define I2S_TCSR_TE_SHIFT (31U)
7243#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
7244
7246#define I2S_TCR1_TFW_MASK (0x7U)
7247#define I2S_TCR1_TFW_SHIFT (0U)
7248#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
7249
7251#define I2S_TCR2_DIV_MASK (0xFFU)
7252#define I2S_TCR2_DIV_SHIFT (0U)
7253#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
7254#define I2S_TCR2_BCD_MASK (0x1000000U)
7255#define I2S_TCR2_BCD_SHIFT (24U)
7256#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
7257#define I2S_TCR2_BCP_MASK (0x2000000U)
7258#define I2S_TCR2_BCP_SHIFT (25U)
7259#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
7260#define I2S_TCR2_MSEL_MASK (0xC000000U)
7261#define I2S_TCR2_MSEL_SHIFT (26U)
7262#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
7263#define I2S_TCR2_BCI_MASK (0x10000000U)
7264#define I2S_TCR2_BCI_SHIFT (28U)
7265#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
7266#define I2S_TCR2_BCS_MASK (0x20000000U)
7267#define I2S_TCR2_BCS_SHIFT (29U)
7268#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
7269#define I2S_TCR2_SYNC_MASK (0xC0000000U)
7270#define I2S_TCR2_SYNC_SHIFT (30U)
7271#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
7272
7274#define I2S_TCR3_WDFL_MASK (0x1FU)
7275#define I2S_TCR3_WDFL_SHIFT (0U)
7276#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
7277#define I2S_TCR3_TCE_MASK (0x30000U)
7278#define I2S_TCR3_TCE_SHIFT (16U)
7279#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
7280
7282#define I2S_TCR4_FSD_MASK (0x1U)
7283#define I2S_TCR4_FSD_SHIFT (0U)
7284#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
7285#define I2S_TCR4_FSP_MASK (0x2U)
7286#define I2S_TCR4_FSP_SHIFT (1U)
7287#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
7288#define I2S_TCR4_FSE_MASK (0x8U)
7289#define I2S_TCR4_FSE_SHIFT (3U)
7290#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
7291#define I2S_TCR4_MF_MASK (0x10U)
7292#define I2S_TCR4_MF_SHIFT (4U)
7293#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
7294#define I2S_TCR4_SYWD_MASK (0x1F00U)
7295#define I2S_TCR4_SYWD_SHIFT (8U)
7296#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
7297#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
7298#define I2S_TCR4_FRSZ_SHIFT (16U)
7299#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
7300
7302#define I2S_TCR5_FBT_MASK (0x1F00U)
7303#define I2S_TCR5_FBT_SHIFT (8U)
7304#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
7305#define I2S_TCR5_W0W_MASK (0x1F0000U)
7306#define I2S_TCR5_W0W_SHIFT (16U)
7307#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
7308#define I2S_TCR5_WNW_MASK (0x1F000000U)
7309#define I2S_TCR5_WNW_SHIFT (24U)
7310#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
7311
7313#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
7314#define I2S_TDR_TDR_SHIFT (0U)
7315#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
7316
7317/* The count of I2S_TDR */
7318#define I2S_TDR_COUNT (2U)
7319
7321#define I2S_TFR_RFP_MASK (0xFU)
7322#define I2S_TFR_RFP_SHIFT (0U)
7323#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
7324#define I2S_TFR_WFP_MASK (0xF0000U)
7325#define I2S_TFR_WFP_SHIFT (16U)
7326#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
7327
7328/* The count of I2S_TFR */
7329#define I2S_TFR_COUNT (2U)
7330
7332#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
7333#define I2S_TMR_TWM_SHIFT (0U)
7334#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
7335
7337#define I2S_RCSR_FRDE_MASK (0x1U)
7338#define I2S_RCSR_FRDE_SHIFT (0U)
7339#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
7340#define I2S_RCSR_FWDE_MASK (0x2U)
7341#define I2S_RCSR_FWDE_SHIFT (1U)
7342#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
7343#define I2S_RCSR_FRIE_MASK (0x100U)
7344#define I2S_RCSR_FRIE_SHIFT (8U)
7345#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
7346#define I2S_RCSR_FWIE_MASK (0x200U)
7347#define I2S_RCSR_FWIE_SHIFT (9U)
7348#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
7349#define I2S_RCSR_FEIE_MASK (0x400U)
7350#define I2S_RCSR_FEIE_SHIFT (10U)
7351#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
7352#define I2S_RCSR_SEIE_MASK (0x800U)
7353#define I2S_RCSR_SEIE_SHIFT (11U)
7354#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
7355#define I2S_RCSR_WSIE_MASK (0x1000U)
7356#define I2S_RCSR_WSIE_SHIFT (12U)
7357#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
7358#define I2S_RCSR_FRF_MASK (0x10000U)
7359#define I2S_RCSR_FRF_SHIFT (16U)
7360#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
7361#define I2S_RCSR_FWF_MASK (0x20000U)
7362#define I2S_RCSR_FWF_SHIFT (17U)
7363#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
7364#define I2S_RCSR_FEF_MASK (0x40000U)
7365#define I2S_RCSR_FEF_SHIFT (18U)
7366#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
7367#define I2S_RCSR_SEF_MASK (0x80000U)
7368#define I2S_RCSR_SEF_SHIFT (19U)
7369#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
7370#define I2S_RCSR_WSF_MASK (0x100000U)
7371#define I2S_RCSR_WSF_SHIFT (20U)
7372#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
7373#define I2S_RCSR_SR_MASK (0x1000000U)
7374#define I2S_RCSR_SR_SHIFT (24U)
7375#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
7376#define I2S_RCSR_FR_MASK (0x2000000U)
7377#define I2S_RCSR_FR_SHIFT (25U)
7378#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
7379#define I2S_RCSR_BCE_MASK (0x10000000U)
7380#define I2S_RCSR_BCE_SHIFT (28U)
7381#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
7382#define I2S_RCSR_DBGE_MASK (0x20000000U)
7383#define I2S_RCSR_DBGE_SHIFT (29U)
7384#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
7385#define I2S_RCSR_STOPE_MASK (0x40000000U)
7386#define I2S_RCSR_STOPE_SHIFT (30U)
7387#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
7388#define I2S_RCSR_RE_MASK (0x80000000U)
7389#define I2S_RCSR_RE_SHIFT (31U)
7390#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
7391
7393#define I2S_RCR1_RFW_MASK (0x7U)
7394#define I2S_RCR1_RFW_SHIFT (0U)
7395#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
7396
7398#define I2S_RCR2_DIV_MASK (0xFFU)
7399#define I2S_RCR2_DIV_SHIFT (0U)
7400#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
7401#define I2S_RCR2_BCD_MASK (0x1000000U)
7402#define I2S_RCR2_BCD_SHIFT (24U)
7403#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
7404#define I2S_RCR2_BCP_MASK (0x2000000U)
7405#define I2S_RCR2_BCP_SHIFT (25U)
7406#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
7407#define I2S_RCR2_MSEL_MASK (0xC000000U)
7408#define I2S_RCR2_MSEL_SHIFT (26U)
7409#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
7410#define I2S_RCR2_BCI_MASK (0x10000000U)
7411#define I2S_RCR2_BCI_SHIFT (28U)
7412#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
7413#define I2S_RCR2_BCS_MASK (0x20000000U)
7414#define I2S_RCR2_BCS_SHIFT (29U)
7415#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
7416#define I2S_RCR2_SYNC_MASK (0xC0000000U)
7417#define I2S_RCR2_SYNC_SHIFT (30U)
7418#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
7419
7421#define I2S_RCR3_WDFL_MASK (0x1FU)
7422#define I2S_RCR3_WDFL_SHIFT (0U)
7423#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
7424#define I2S_RCR3_RCE_MASK (0x30000U)
7425#define I2S_RCR3_RCE_SHIFT (16U)
7426#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
7427
7429#define I2S_RCR4_FSD_MASK (0x1U)
7430#define I2S_RCR4_FSD_SHIFT (0U)
7431#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
7432#define I2S_RCR4_FSP_MASK (0x2U)
7433#define I2S_RCR4_FSP_SHIFT (1U)
7434#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
7435#define I2S_RCR4_FSE_MASK (0x8U)
7436#define I2S_RCR4_FSE_SHIFT (3U)
7437#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
7438#define I2S_RCR4_MF_MASK (0x10U)
7439#define I2S_RCR4_MF_SHIFT (4U)
7440#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
7441#define I2S_RCR4_SYWD_MASK (0x1F00U)
7442#define I2S_RCR4_SYWD_SHIFT (8U)
7443#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
7444#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
7445#define I2S_RCR4_FRSZ_SHIFT (16U)
7446#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
7447
7449#define I2S_RCR5_FBT_MASK (0x1F00U)
7450#define I2S_RCR5_FBT_SHIFT (8U)
7451#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
7452#define I2S_RCR5_W0W_MASK (0x1F0000U)
7453#define I2S_RCR5_W0W_SHIFT (16U)
7454#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
7455#define I2S_RCR5_WNW_MASK (0x1F000000U)
7456#define I2S_RCR5_WNW_SHIFT (24U)
7457#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
7458
7460#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
7461#define I2S_RDR_RDR_SHIFT (0U)
7462#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
7463
7464/* The count of I2S_RDR */
7465#define I2S_RDR_COUNT (2U)
7466
7468#define I2S_RFR_RFP_MASK (0xFU)
7469#define I2S_RFR_RFP_SHIFT (0U)
7470#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
7471#define I2S_RFR_WFP_MASK (0xF0000U)
7472#define I2S_RFR_WFP_SHIFT (16U)
7473#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
7474
7475/* The count of I2S_RFR */
7476#define I2S_RFR_COUNT (2U)
7477
7479#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
7480#define I2S_RMR_RWM_SHIFT (0U)
7481#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
7482
7484#define I2S_MCR_MICS_MASK (0x3000000U)
7485#define I2S_MCR_MICS_SHIFT (24U)
7486#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
7487#define I2S_MCR_MOE_MASK (0x40000000U)
7488#define I2S_MCR_MOE_SHIFT (30U)
7489#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
7490#define I2S_MCR_DUF_MASK (0x80000000U)
7491#define I2S_MCR_DUF_SHIFT (31U)
7492#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
7493
7495#define I2S_MDR_DIVIDE_MASK (0xFFFU)
7496#define I2S_MDR_DIVIDE_SHIFT (0U)
7497#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
7498#define I2S_MDR_FRACT_MASK (0xFF000U)
7499#define I2S_MDR_FRACT_SHIFT (12U)
7500#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
7501
7502
7505 /* end of group I2S_Register_Masks */
7506
7507
7508/* I2S - Peripheral instance base addresses */
7510#define I2S0_BASE (0x4002F000u)
7512#define I2S0 ((I2S_Type *)I2S0_BASE)
7514#define I2S_BASE_ADDRS { I2S0_BASE }
7516#define I2S_BASE_PTRS { I2S0 }
7518#define I2S_RX_IRQS { I2S0_Rx_IRQn }
7519#define I2S_TX_IRQS { I2S0_Tx_IRQn }
7520
7523 /* end of group I2S_Peripheral_Access_Layer */
7524
7525
7526/* ----------------------------------------------------------------------------
7527 -- LLWU Peripheral Access Layer
7528 ---------------------------------------------------------------------------- */
7529
7536typedef struct {
7537 __IO uint8_t PE1;
7538 __IO uint8_t PE2;
7539 __IO uint8_t PE3;
7540 __IO uint8_t PE4;
7541 __IO uint8_t ME;
7542 __IO uint8_t F1;
7543 __IO uint8_t F2;
7544 __I uint8_t F3;
7545 __IO uint8_t FILT1;
7546 __IO uint8_t FILT2;
7547 __IO uint8_t RST;
7548} LLWU_Type;
7549
7550/* ----------------------------------------------------------------------------
7551 -- LLWU Register Masks
7552 ---------------------------------------------------------------------------- */
7553
7560#define LLWU_PE1_WUPE0_MASK (0x3U)
7561#define LLWU_PE1_WUPE0_SHIFT (0U)
7562#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
7563#define LLWU_PE1_WUPE1_MASK (0xCU)
7564#define LLWU_PE1_WUPE1_SHIFT (2U)
7565#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
7566#define LLWU_PE1_WUPE2_MASK (0x30U)
7567#define LLWU_PE1_WUPE2_SHIFT (4U)
7568#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
7569#define LLWU_PE1_WUPE3_MASK (0xC0U)
7570#define LLWU_PE1_WUPE3_SHIFT (6U)
7571#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
7572
7574#define LLWU_PE2_WUPE4_MASK (0x3U)
7575#define LLWU_PE2_WUPE4_SHIFT (0U)
7576#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
7577#define LLWU_PE2_WUPE5_MASK (0xCU)
7578#define LLWU_PE2_WUPE5_SHIFT (2U)
7579#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
7580#define LLWU_PE2_WUPE6_MASK (0x30U)
7581#define LLWU_PE2_WUPE6_SHIFT (4U)
7582#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
7583#define LLWU_PE2_WUPE7_MASK (0xC0U)
7584#define LLWU_PE2_WUPE7_SHIFT (6U)
7585#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
7586
7588#define LLWU_PE3_WUPE8_MASK (0x3U)
7589#define LLWU_PE3_WUPE8_SHIFT (0U)
7590#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
7591#define LLWU_PE3_WUPE9_MASK (0xCU)
7592#define LLWU_PE3_WUPE9_SHIFT (2U)
7593#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
7594#define LLWU_PE3_WUPE10_MASK (0x30U)
7595#define LLWU_PE3_WUPE10_SHIFT (4U)
7596#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
7597#define LLWU_PE3_WUPE11_MASK (0xC0U)
7598#define LLWU_PE3_WUPE11_SHIFT (6U)
7599#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
7600
7602#define LLWU_PE4_WUPE12_MASK (0x3U)
7603#define LLWU_PE4_WUPE12_SHIFT (0U)
7604#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
7605#define LLWU_PE4_WUPE13_MASK (0xCU)
7606#define LLWU_PE4_WUPE13_SHIFT (2U)
7607#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
7608#define LLWU_PE4_WUPE14_MASK (0x30U)
7609#define LLWU_PE4_WUPE14_SHIFT (4U)
7610#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
7611#define LLWU_PE4_WUPE15_MASK (0xC0U)
7612#define LLWU_PE4_WUPE15_SHIFT (6U)
7613#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
7614
7616#define LLWU_ME_WUME0_MASK (0x1U)
7617#define LLWU_ME_WUME0_SHIFT (0U)
7618#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
7619#define LLWU_ME_WUME1_MASK (0x2U)
7620#define LLWU_ME_WUME1_SHIFT (1U)
7621#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
7622#define LLWU_ME_WUME2_MASK (0x4U)
7623#define LLWU_ME_WUME2_SHIFT (2U)
7624#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
7625#define LLWU_ME_WUME3_MASK (0x8U)
7626#define LLWU_ME_WUME3_SHIFT (3U)
7627#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
7628#define LLWU_ME_WUME4_MASK (0x10U)
7629#define LLWU_ME_WUME4_SHIFT (4U)
7630#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
7631#define LLWU_ME_WUME5_MASK (0x20U)
7632#define LLWU_ME_WUME5_SHIFT (5U)
7633#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
7634#define LLWU_ME_WUME6_MASK (0x40U)
7635#define LLWU_ME_WUME6_SHIFT (6U)
7636#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
7637#define LLWU_ME_WUME7_MASK (0x80U)
7638#define LLWU_ME_WUME7_SHIFT (7U)
7639#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
7640
7642#define LLWU_F1_WUF0_MASK (0x1U)
7643#define LLWU_F1_WUF0_SHIFT (0U)
7644#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
7645#define LLWU_F1_WUF1_MASK (0x2U)
7646#define LLWU_F1_WUF1_SHIFT (1U)
7647#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
7648#define LLWU_F1_WUF2_MASK (0x4U)
7649#define LLWU_F1_WUF2_SHIFT (2U)
7650#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
7651#define LLWU_F1_WUF3_MASK (0x8U)
7652#define LLWU_F1_WUF3_SHIFT (3U)
7653#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
7654#define LLWU_F1_WUF4_MASK (0x10U)
7655#define LLWU_F1_WUF4_SHIFT (4U)
7656#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
7657#define LLWU_F1_WUF5_MASK (0x20U)
7658#define LLWU_F1_WUF5_SHIFT (5U)
7659#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
7660#define LLWU_F1_WUF6_MASK (0x40U)
7661#define LLWU_F1_WUF6_SHIFT (6U)
7662#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
7663#define LLWU_F1_WUF7_MASK (0x80U)
7664#define LLWU_F1_WUF7_SHIFT (7U)
7665#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
7666
7668#define LLWU_F2_WUF8_MASK (0x1U)
7669#define LLWU_F2_WUF8_SHIFT (0U)
7670#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
7671#define LLWU_F2_WUF9_MASK (0x2U)
7672#define LLWU_F2_WUF9_SHIFT (1U)
7673#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
7674#define LLWU_F2_WUF10_MASK (0x4U)
7675#define LLWU_F2_WUF10_SHIFT (2U)
7676#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
7677#define LLWU_F2_WUF11_MASK (0x8U)
7678#define LLWU_F2_WUF11_SHIFT (3U)
7679#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
7680#define LLWU_F2_WUF12_MASK (0x10U)
7681#define LLWU_F2_WUF12_SHIFT (4U)
7682#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
7683#define LLWU_F2_WUF13_MASK (0x20U)
7684#define LLWU_F2_WUF13_SHIFT (5U)
7685#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
7686#define LLWU_F2_WUF14_MASK (0x40U)
7687#define LLWU_F2_WUF14_SHIFT (6U)
7688#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
7689#define LLWU_F2_WUF15_MASK (0x80U)
7690#define LLWU_F2_WUF15_SHIFT (7U)
7691#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
7692
7694#define LLWU_F3_MWUF0_MASK (0x1U)
7695#define LLWU_F3_MWUF0_SHIFT (0U)
7696#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
7697#define LLWU_F3_MWUF1_MASK (0x2U)
7698#define LLWU_F3_MWUF1_SHIFT (1U)
7699#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
7700#define LLWU_F3_MWUF2_MASK (0x4U)
7701#define LLWU_F3_MWUF2_SHIFT (2U)
7702#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
7703#define LLWU_F3_MWUF3_MASK (0x8U)
7704#define LLWU_F3_MWUF3_SHIFT (3U)
7705#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
7706#define LLWU_F3_MWUF4_MASK (0x10U)
7707#define LLWU_F3_MWUF4_SHIFT (4U)
7708#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
7709#define LLWU_F3_MWUF5_MASK (0x20U)
7710#define LLWU_F3_MWUF5_SHIFT (5U)
7711#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
7712#define LLWU_F3_MWUF6_MASK (0x40U)
7713#define LLWU_F3_MWUF6_SHIFT (6U)
7714#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
7715#define LLWU_F3_MWUF7_MASK (0x80U)
7716#define LLWU_F3_MWUF7_SHIFT (7U)
7717#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
7718
7720#define LLWU_FILT1_FILTSEL_MASK (0xFU)
7721#define LLWU_FILT1_FILTSEL_SHIFT (0U)
7722#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
7723#define LLWU_FILT1_FILTE_MASK (0x60U)
7724#define LLWU_FILT1_FILTE_SHIFT (5U)
7725#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
7726#define LLWU_FILT1_FILTF_MASK (0x80U)
7727#define LLWU_FILT1_FILTF_SHIFT (7U)
7728#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
7729
7731#define LLWU_FILT2_FILTSEL_MASK (0xFU)
7732#define LLWU_FILT2_FILTSEL_SHIFT (0U)
7733#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
7734#define LLWU_FILT2_FILTE_MASK (0x60U)
7735#define LLWU_FILT2_FILTE_SHIFT (5U)
7736#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
7737#define LLWU_FILT2_FILTF_MASK (0x80U)
7738#define LLWU_FILT2_FILTF_SHIFT (7U)
7739#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
7740
7742#define LLWU_RST_RSTFILT_MASK (0x1U)
7743#define LLWU_RST_RSTFILT_SHIFT (0U)
7744#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
7745#define LLWU_RST_LLRSTE_MASK (0x2U)
7746#define LLWU_RST_LLRSTE_SHIFT (1U)
7747#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
7748
7749
7752 /* end of group LLWU_Register_Masks */
7753
7754
7755/* LLWU - Peripheral instance base addresses */
7757#define LLWU_BASE (0x4007C000u)
7759#define LLWU ((LLWU_Type *)LLWU_BASE)
7761#define LLWU_BASE_ADDRS { LLWU_BASE }
7763#define LLWU_BASE_PTRS { LLWU }
7765#define LLWU_IRQS { LLWU_IRQn }
7766
7769 /* end of group LLWU_Peripheral_Access_Layer */
7770
7771
7772/* ----------------------------------------------------------------------------
7773 -- LPTMR Peripheral Access Layer
7774 ---------------------------------------------------------------------------- */
7775
7782typedef struct {
7783 __IO uint32_t CSR;
7784 __IO uint32_t PSR;
7785 __IO uint32_t CMR;
7786 __IO uint32_t CNR;
7787} LPTMR_Type;
7788
7789/* ----------------------------------------------------------------------------
7790 -- LPTMR Register Masks
7791 ---------------------------------------------------------------------------- */
7792
7799#define LPTMR_CSR_TEN_MASK (0x1U)
7800#define LPTMR_CSR_TEN_SHIFT (0U)
7801#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
7802#define LPTMR_CSR_TMS_MASK (0x2U)
7803#define LPTMR_CSR_TMS_SHIFT (1U)
7804#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
7805#define LPTMR_CSR_TFC_MASK (0x4U)
7806#define LPTMR_CSR_TFC_SHIFT (2U)
7807#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
7808#define LPTMR_CSR_TPP_MASK (0x8U)
7809#define LPTMR_CSR_TPP_SHIFT (3U)
7810#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
7811#define LPTMR_CSR_TPS_MASK (0x30U)
7812#define LPTMR_CSR_TPS_SHIFT (4U)
7813#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
7814#define LPTMR_CSR_TIE_MASK (0x40U)
7815#define LPTMR_CSR_TIE_SHIFT (6U)
7816#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
7817#define LPTMR_CSR_TCF_MASK (0x80U)
7818#define LPTMR_CSR_TCF_SHIFT (7U)
7819#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
7820
7822#define LPTMR_PSR_PCS_MASK (0x3U)
7823#define LPTMR_PSR_PCS_SHIFT (0U)
7824#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
7825#define LPTMR_PSR_PBYP_MASK (0x4U)
7826#define LPTMR_PSR_PBYP_SHIFT (2U)
7827#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
7828#define LPTMR_PSR_PRESCALE_MASK (0x78U)
7829#define LPTMR_PSR_PRESCALE_SHIFT (3U)
7830#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
7831
7833#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
7834#define LPTMR_CMR_COMPARE_SHIFT (0U)
7835#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
7836
7838#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
7839#define LPTMR_CNR_COUNTER_SHIFT (0U)
7840#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
7841
7842
7845 /* end of group LPTMR_Register_Masks */
7846
7847
7848/* LPTMR - Peripheral instance base addresses */
7850#define LPTMR0_BASE (0x40040000u)
7852#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
7854#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
7856#define LPTMR_BASE_PTRS { LPTMR0 }
7858#define LPTMR_IRQS { LPTMR0_IRQn }
7859
7862 /* end of group LPTMR_Peripheral_Access_Layer */
7863
7864
7865/* ----------------------------------------------------------------------------
7866 -- MCG Peripheral Access Layer
7867 ---------------------------------------------------------------------------- */
7868
7875typedef struct {
7876 __IO uint8_t C1;
7877 __IO uint8_t C2;
7878 __IO uint8_t C3;
7879 __IO uint8_t C4;
7880 __IO uint8_t C5;
7881 __IO uint8_t C6;
7882 __IO uint8_t S;
7883 uint8_t RESERVED_0[1];
7884 __IO uint8_t SC;
7885 uint8_t RESERVED_1[1];
7886 __IO uint8_t ATCVH;
7887 __IO uint8_t ATCVL;
7888 __IO uint8_t C7;
7889 __IO uint8_t C8;
7890 __I uint8_t C9;
7891 __I uint8_t C10;
7892} MCG_Type;
7893
7894/* ----------------------------------------------------------------------------
7895 -- MCG Register Masks
7896 ---------------------------------------------------------------------------- */
7897
7904#define MCG_C1_IREFSTEN_MASK (0x1U)
7905#define MCG_C1_IREFSTEN_SHIFT (0U)
7906#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
7907#define MCG_C1_IRCLKEN_MASK (0x2U)
7908#define MCG_C1_IRCLKEN_SHIFT (1U)
7909#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
7910#define MCG_C1_IREFS_MASK (0x4U)
7911#define MCG_C1_IREFS_SHIFT (2U)
7912#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
7913#define MCG_C1_FRDIV_MASK (0x38U)
7914#define MCG_C1_FRDIV_SHIFT (3U)
7915#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
7916#define MCG_C1_CLKS_MASK (0xC0U)
7917#define MCG_C1_CLKS_SHIFT (6U)
7918#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
7919
7921#define MCG_C2_IRCS_MASK (0x1U)
7922#define MCG_C2_IRCS_SHIFT (0U)
7923#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
7924#define MCG_C2_LP_MASK (0x2U)
7925#define MCG_C2_LP_SHIFT (1U)
7926#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
7927#define MCG_C2_EREFS0_MASK (0x4U)
7928#define MCG_C2_EREFS0_SHIFT (2U)
7929#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
7930#define MCG_C2_HGO0_MASK (0x8U)
7931#define MCG_C2_HGO0_SHIFT (3U)
7932#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
7933#define MCG_C2_RANGE0_MASK (0x30U)
7934#define MCG_C2_RANGE0_SHIFT (4U)
7935#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
7936#define MCG_C2_LOCRE0_MASK (0x80U)
7937#define MCG_C2_LOCRE0_SHIFT (7U)
7938#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
7939
7941#define MCG_C3_SCTRIM_MASK (0xFFU)
7942#define MCG_C3_SCTRIM_SHIFT (0U)
7943#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
7944
7946#define MCG_C4_SCFTRIM_MASK (0x1U)
7947#define MCG_C4_SCFTRIM_SHIFT (0U)
7948#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
7949#define MCG_C4_FCTRIM_MASK (0x1EU)
7950#define MCG_C4_FCTRIM_SHIFT (1U)
7951#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
7952#define MCG_C4_DRST_DRS_MASK (0x60U)
7953#define MCG_C4_DRST_DRS_SHIFT (5U)
7954#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
7955#define MCG_C4_DMX32_MASK (0x80U)
7956#define MCG_C4_DMX32_SHIFT (7U)
7957#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
7958
7960#define MCG_C5_PRDIV0_MASK (0x1FU)
7961#define MCG_C5_PRDIV0_SHIFT (0U)
7962#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
7963#define MCG_C5_PLLSTEN0_MASK (0x20U)
7964#define MCG_C5_PLLSTEN0_SHIFT (5U)
7965#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
7966#define MCG_C5_PLLCLKEN0_MASK (0x40U)
7967#define MCG_C5_PLLCLKEN0_SHIFT (6U)
7968#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
7969
7971#define MCG_C6_VDIV0_MASK (0x1FU)
7972#define MCG_C6_VDIV0_SHIFT (0U)
7973#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
7974#define MCG_C6_CME0_MASK (0x20U)
7975#define MCG_C6_CME0_SHIFT (5U)
7976#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
7977#define MCG_C6_PLLS_MASK (0x40U)
7978#define MCG_C6_PLLS_SHIFT (6U)
7979#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
7980#define MCG_C6_LOLIE0_MASK (0x80U)
7981#define MCG_C6_LOLIE0_SHIFT (7U)
7982#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
7983
7985#define MCG_S_IRCST_MASK (0x1U)
7986#define MCG_S_IRCST_SHIFT (0U)
7987#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
7988#define MCG_S_OSCINIT0_MASK (0x2U)
7989#define MCG_S_OSCINIT0_SHIFT (1U)
7990#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
7991#define MCG_S_CLKST_MASK (0xCU)
7992#define MCG_S_CLKST_SHIFT (2U)
7993#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
7994#define MCG_S_IREFST_MASK (0x10U)
7995#define MCG_S_IREFST_SHIFT (4U)
7996#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
7997#define MCG_S_PLLST_MASK (0x20U)
7998#define MCG_S_PLLST_SHIFT (5U)
7999#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
8000#define MCG_S_LOCK0_MASK (0x40U)
8001#define MCG_S_LOCK0_SHIFT (6U)
8002#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
8003#define MCG_S_LOLS_MASK (0x80U)
8004#define MCG_S_LOLS_SHIFT (7U)
8005#define MCG_S_LOLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS_SHIFT)) & MCG_S_LOLS_MASK)
8006
8008#define MCG_SC_LOCS0_MASK (0x1U)
8009#define MCG_SC_LOCS0_SHIFT (0U)
8010#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
8011#define MCG_SC_FCRDIV_MASK (0xEU)
8012#define MCG_SC_FCRDIV_SHIFT (1U)
8013#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
8014#define MCG_SC_FLTPRSRV_MASK (0x10U)
8015#define MCG_SC_FLTPRSRV_SHIFT (4U)
8016#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
8017#define MCG_SC_ATMF_MASK (0x20U)
8018#define MCG_SC_ATMF_SHIFT (5U)
8019#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
8020#define MCG_SC_ATMS_MASK (0x40U)
8021#define MCG_SC_ATMS_SHIFT (6U)
8022#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
8023#define MCG_SC_ATME_MASK (0x80U)
8024#define MCG_SC_ATME_SHIFT (7U)
8025#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
8026
8028#define MCG_ATCVH_ATCVH_MASK (0xFFU)
8029#define MCG_ATCVH_ATCVH_SHIFT (0U)
8030#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
8031
8033#define MCG_ATCVL_ATCVL_MASK (0xFFU)
8034#define MCG_ATCVL_ATCVL_SHIFT (0U)
8035#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
8036
8038#define MCG_C7_OSCSEL_MASK (0x1U)
8039#define MCG_C7_OSCSEL_SHIFT (0U)
8040#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
8041
8043#define MCG_C8_LOCS1_MASK (0x1U)
8044#define MCG_C8_LOCS1_SHIFT (0U)
8045#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
8046#define MCG_C8_CME1_MASK (0x20U)
8047#define MCG_C8_CME1_SHIFT (5U)
8048#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
8049#define MCG_C8_LOLRE_MASK (0x40U)
8050#define MCG_C8_LOLRE_SHIFT (6U)
8051#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
8052#define MCG_C8_LOCRE1_MASK (0x80U)
8053#define MCG_C8_LOCRE1_SHIFT (7U)
8054#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
8055
8056
8059 /* end of group MCG_Register_Masks */
8060
8061
8062/* MCG - Peripheral instance base addresses */
8064#define MCG_BASE (0x40064000u)
8066#define MCG ((MCG_Type *)MCG_BASE)
8068#define MCG_BASE_ADDRS { MCG_BASE }
8070#define MCG_BASE_PTRS { MCG }
8072#define MCG_IRQS { MCG_IRQn }
8073/* MCG C2[EREFS] backward compatibility */
8074#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
8075#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
8076#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
8077#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
8078
8079/* MCG C2[HGO] backward compatibility */
8080#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
8081#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
8082#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
8083#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
8084
8085/* MCG C2[RANGE] backward compatibility */
8086#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
8087#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
8088#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
8089#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
8090
8091/* MCG S[LOLS0] backward compatibility */
8092#define MCG_S_LOLS0_MASK (MCG_S_LOLS_MASK)
8093#define MCG_S_LOLS0_SHIFT (MCG_S_LOLS_SHIFT)
8094#define MCG_S_LOLS0_WIDTH (MCG_S_LOLS_WIDTH)
8095#define MCG_S_LOLS0(x) (MCG_S_LOLS(x))
8096
8097
8100 /* end of group MCG_Peripheral_Access_Layer */
8101
8102
8103/* ----------------------------------------------------------------------------
8104 -- MCM Peripheral Access Layer
8105 ---------------------------------------------------------------------------- */
8106
8113typedef struct {
8114 uint8_t RESERVED_0[8];
8115 __I uint16_t PLASC;
8116 __I uint16_t PLAMC;
8117 __IO uint32_t CR;
8118 __IO uint32_t ISR;
8119 __IO uint32_t ETBCC;
8120 __IO uint32_t ETBRL;
8121 __I uint32_t ETBCNT;
8122 uint8_t RESERVED_1[16];
8123 __IO uint32_t PID;
8124} MCM_Type;
8125
8126/* ----------------------------------------------------------------------------
8127 -- MCM Register Masks
8128 ---------------------------------------------------------------------------- */
8129
8136#define MCM_PLASC_ASC_MASK (0xFFU)
8137#define MCM_PLASC_ASC_SHIFT (0U)
8138#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
8139
8141#define MCM_PLAMC_AMC_MASK (0xFFU)
8142#define MCM_PLAMC_AMC_SHIFT (0U)
8143#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
8144
8146#define MCM_CR_SRAMUAP_MASK (0x3000000U)
8147#define MCM_CR_SRAMUAP_SHIFT (24U)
8148#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
8149#define MCM_CR_SRAMUWP_MASK (0x4000000U)
8150#define MCM_CR_SRAMUWP_SHIFT (26U)
8151#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
8152#define MCM_CR_SRAMLAP_MASK (0x30000000U)
8153#define MCM_CR_SRAMLAP_SHIFT (28U)
8154#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
8155#define MCM_CR_SRAMLWP_MASK (0x40000000U)
8156#define MCM_CR_SRAMLWP_SHIFT (30U)
8157#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
8158
8160#define MCM_ISR_IRQ_MASK (0x2U)
8161#define MCM_ISR_IRQ_SHIFT (1U)
8162#define MCM_ISR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISR_IRQ_SHIFT)) & MCM_ISR_IRQ_MASK)
8163#define MCM_ISR_NMI_MASK (0x4U)
8164#define MCM_ISR_NMI_SHIFT (2U)
8165#define MCM_ISR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISR_NMI_SHIFT)) & MCM_ISR_NMI_MASK)
8166#define MCM_ISR_DHREQ_MASK (0x8U)
8167#define MCM_ISR_DHREQ_SHIFT (3U)
8168#define MCM_ISR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISR_DHREQ_SHIFT)) & MCM_ISR_DHREQ_MASK)
8169
8171#define MCM_ETBCC_CNTEN_MASK (0x1U)
8172#define MCM_ETBCC_CNTEN_SHIFT (0U)
8173#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
8174#define MCM_ETBCC_RSPT_MASK (0x6U)
8175#define MCM_ETBCC_RSPT_SHIFT (1U)
8176#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
8177#define MCM_ETBCC_RLRQ_MASK (0x8U)
8178#define MCM_ETBCC_RLRQ_SHIFT (3U)
8179#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
8180#define MCM_ETBCC_ETDIS_MASK (0x10U)
8181#define MCM_ETBCC_ETDIS_SHIFT (4U)
8182#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
8183#define MCM_ETBCC_ITDIS_MASK (0x20U)
8184#define MCM_ETBCC_ITDIS_SHIFT (5U)
8185#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
8186
8188#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
8189#define MCM_ETBRL_RELOAD_SHIFT (0U)
8190#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
8191
8193#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
8194#define MCM_ETBCNT_COUNTER_SHIFT (0U)
8195#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
8196
8198#define MCM_PID_PID_MASK (0xFFU)
8199#define MCM_PID_PID_SHIFT (0U)
8200#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
8201
8202
8205 /* end of group MCM_Register_Masks */
8206
8207
8208/* MCM - Peripheral instance base addresses */
8210#define MCM_BASE (0xE0080000u)
8212#define MCM ((MCM_Type *)MCM_BASE)
8214#define MCM_BASE_ADDRS { MCM_BASE }
8216#define MCM_BASE_PTRS { MCM }
8218#define MCM_IRQS { MCM_IRQn }
8219
8222 /* end of group MCM_Peripheral_Access_Layer */
8223
8224
8225/* ----------------------------------------------------------------------------
8226 -- NV Peripheral Access Layer
8227 ---------------------------------------------------------------------------- */
8228
8235typedef struct {
8236 __I uint8_t BACKKEY3;
8237 __I uint8_t BACKKEY2;
8238 __I uint8_t BACKKEY1;
8239 __I uint8_t BACKKEY0;
8240 __I uint8_t BACKKEY7;
8241 __I uint8_t BACKKEY6;
8242 __I uint8_t BACKKEY5;
8243 __I uint8_t BACKKEY4;
8244 __I uint8_t FPROT3;
8245 __I uint8_t FPROT2;
8246 __I uint8_t FPROT1;
8247 __I uint8_t FPROT0;
8248 __I uint8_t FSEC;
8249 __I uint8_t FOPT;
8250 __I uint8_t FEPROT;
8251 __I uint8_t FDPROT;
8252} NV_Type;
8253
8254/* ----------------------------------------------------------------------------
8255 -- NV Register Masks
8256 ---------------------------------------------------------------------------- */
8257
8264#define NV_BACKKEY3_KEY_MASK (0xFFU)
8265#define NV_BACKKEY3_KEY_SHIFT (0U)
8266#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
8267
8269#define NV_BACKKEY2_KEY_MASK (0xFFU)
8270#define NV_BACKKEY2_KEY_SHIFT (0U)
8271#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
8272
8274#define NV_BACKKEY1_KEY_MASK (0xFFU)
8275#define NV_BACKKEY1_KEY_SHIFT (0U)
8276#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
8277
8279#define NV_BACKKEY0_KEY_MASK (0xFFU)
8280#define NV_BACKKEY0_KEY_SHIFT (0U)
8281#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
8282
8284#define NV_BACKKEY7_KEY_MASK (0xFFU)
8285#define NV_BACKKEY7_KEY_SHIFT (0U)
8286#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
8287
8289#define NV_BACKKEY6_KEY_MASK (0xFFU)
8290#define NV_BACKKEY6_KEY_SHIFT (0U)
8291#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
8292
8294#define NV_BACKKEY5_KEY_MASK (0xFFU)
8295#define NV_BACKKEY5_KEY_SHIFT (0U)
8296#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
8297
8299#define NV_BACKKEY4_KEY_MASK (0xFFU)
8300#define NV_BACKKEY4_KEY_SHIFT (0U)
8301#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
8302
8304#define NV_FPROT3_PROT_MASK (0xFFU)
8305#define NV_FPROT3_PROT_SHIFT (0U)
8306#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
8307
8309#define NV_FPROT2_PROT_MASK (0xFFU)
8310#define NV_FPROT2_PROT_SHIFT (0U)
8311#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
8312
8314#define NV_FPROT1_PROT_MASK (0xFFU)
8315#define NV_FPROT1_PROT_SHIFT (0U)
8316#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
8317
8319#define NV_FPROT0_PROT_MASK (0xFFU)
8320#define NV_FPROT0_PROT_SHIFT (0U)
8321#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
8322
8324#define NV_FSEC_SEC_MASK (0x3U)
8325#define NV_FSEC_SEC_SHIFT (0U)
8326#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
8327#define NV_FSEC_FSLACC_MASK (0xCU)
8328#define NV_FSEC_FSLACC_SHIFT (2U)
8329#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
8330#define NV_FSEC_MEEN_MASK (0x30U)
8331#define NV_FSEC_MEEN_SHIFT (4U)
8332#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
8333#define NV_FSEC_KEYEN_MASK (0xC0U)
8334#define NV_FSEC_KEYEN_SHIFT (6U)
8335#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
8336
8338#define NV_FOPT_LPBOOT_MASK (0x1U)
8339#define NV_FOPT_LPBOOT_SHIFT (0U)
8340#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
8341#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
8342#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
8343#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
8344#define NV_FOPT_NMI_DIS_MASK (0x4U)
8345#define NV_FOPT_NMI_DIS_SHIFT (2U)
8346#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
8347
8349#define NV_FEPROT_EPROT_MASK (0xFFU)
8350#define NV_FEPROT_EPROT_SHIFT (0U)
8351#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
8352
8354#define NV_FDPROT_DPROT_MASK (0xFFU)
8355#define NV_FDPROT_DPROT_SHIFT (0U)
8356#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
8357
8358
8361 /* end of group NV_Register_Masks */
8362
8363
8364/* NV - Peripheral instance base addresses */
8366#define FTFL_FlashConfig_BASE (0x400u)
8368#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
8370#define NV_BASE_ADDRS { FTFL_FlashConfig_BASE }
8372#define NV_BASE_PTRS { FTFL_FlashConfig }
8373
8376 /* end of group NV_Peripheral_Access_Layer */
8377
8378
8379/* ----------------------------------------------------------------------------
8380 -- OSC Peripheral Access Layer
8381 ---------------------------------------------------------------------------- */
8382
8389typedef struct {
8390 __IO uint8_t CR;
8391} OSC_Type;
8392
8393/* ----------------------------------------------------------------------------
8394 -- OSC Register Masks
8395 ---------------------------------------------------------------------------- */
8396
8403#define OSC_CR_SC16P_MASK (0x1U)
8404#define OSC_CR_SC16P_SHIFT (0U)
8405#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
8406#define OSC_CR_SC8P_MASK (0x2U)
8407#define OSC_CR_SC8P_SHIFT (1U)
8408#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
8409#define OSC_CR_SC4P_MASK (0x4U)
8410#define OSC_CR_SC4P_SHIFT (2U)
8411#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
8412#define OSC_CR_SC2P_MASK (0x8U)
8413#define OSC_CR_SC2P_SHIFT (3U)
8414#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
8415#define OSC_CR_EREFSTEN_MASK (0x20U)
8416#define OSC_CR_EREFSTEN_SHIFT (5U)
8417#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
8418#define OSC_CR_ERCLKEN_MASK (0x80U)
8419#define OSC_CR_ERCLKEN_SHIFT (7U)
8420#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
8421
8422
8425 /* end of group OSC_Register_Masks */
8426
8427
8428/* OSC - Peripheral instance base addresses */
8430#define OSC_BASE (0x40065000u)
8432#define OSC ((OSC_Type *)OSC_BASE)
8434#define OSC_BASE_ADDRS { OSC_BASE }
8436#define OSC_BASE_PTRS { OSC }
8437
8440 /* end of group OSC_Peripheral_Access_Layer */
8441
8442
8443/* ----------------------------------------------------------------------------
8444 -- PDB Peripheral Access Layer
8445 ---------------------------------------------------------------------------- */
8446
8453typedef struct {
8454 __IO uint32_t SC;
8455 __IO uint32_t MOD;
8456 __I uint32_t CNT;
8457 __IO uint32_t IDLY;
8458 struct { /* offset: 0x10, array step: 0x28 */
8459 __IO uint32_t C1;
8460 __IO uint32_t S;
8461 __IO uint32_t DLY[2];
8462 uint8_t RESERVED_0[24];
8463 } CH[2];
8464 uint8_t RESERVED_0[240];
8465 struct { /* offset: 0x150, array step: 0x8 */
8466 __IO uint32_t INTC;
8467 __IO uint32_t INT;
8468 } DAC[2];
8469 uint8_t RESERVED_1[48];
8470 __IO uint32_t POEN;
8471 __IO uint32_t PODLY[3];
8472} PDB_Type;
8473
8474/* ----------------------------------------------------------------------------
8475 -- PDB Register Masks
8476 ---------------------------------------------------------------------------- */
8477
8484#define PDB_SC_LDOK_MASK (0x1U)
8485#define PDB_SC_LDOK_SHIFT (0U)
8486#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
8487#define PDB_SC_CONT_MASK (0x2U)
8488#define PDB_SC_CONT_SHIFT (1U)
8489#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
8490#define PDB_SC_MULT_MASK (0xCU)
8491#define PDB_SC_MULT_SHIFT (2U)
8492#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
8493#define PDB_SC_PDBIE_MASK (0x20U)
8494#define PDB_SC_PDBIE_SHIFT (5U)
8495#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
8496#define PDB_SC_PDBIF_MASK (0x40U)
8497#define PDB_SC_PDBIF_SHIFT (6U)
8498#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
8499#define PDB_SC_PDBEN_MASK (0x80U)
8500#define PDB_SC_PDBEN_SHIFT (7U)
8501#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
8502#define PDB_SC_TRGSEL_MASK (0xF00U)
8503#define PDB_SC_TRGSEL_SHIFT (8U)
8504#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
8505#define PDB_SC_PRESCALER_MASK (0x7000U)
8506#define PDB_SC_PRESCALER_SHIFT (12U)
8507#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
8508#define PDB_SC_DMAEN_MASK (0x8000U)
8509#define PDB_SC_DMAEN_SHIFT (15U)
8510#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
8511#define PDB_SC_SWTRIG_MASK (0x10000U)
8512#define PDB_SC_SWTRIG_SHIFT (16U)
8513#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
8514#define PDB_SC_PDBEIE_MASK (0x20000U)
8515#define PDB_SC_PDBEIE_SHIFT (17U)
8516#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
8517#define PDB_SC_LDMOD_MASK (0xC0000U)
8518#define PDB_SC_LDMOD_SHIFT (18U)
8519#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
8520
8522#define PDB_MOD_MOD_MASK (0xFFFFU)
8523#define PDB_MOD_MOD_SHIFT (0U)
8524#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
8525
8527#define PDB_CNT_CNT_MASK (0xFFFFU)
8528#define PDB_CNT_CNT_SHIFT (0U)
8529#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
8530
8532#define PDB_IDLY_IDLY_MASK (0xFFFFU)
8533#define PDB_IDLY_IDLY_SHIFT (0U)
8534#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
8535
8537#define PDB_C1_EN_MASK (0xFFU)
8538#define PDB_C1_EN_SHIFT (0U)
8539#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
8540#define PDB_C1_TOS_MASK (0xFF00U)
8541#define PDB_C1_TOS_SHIFT (8U)
8542#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
8543#define PDB_C1_BB_MASK (0xFF0000U)
8544#define PDB_C1_BB_SHIFT (16U)
8545#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
8546
8547/* The count of PDB_C1 */
8548#define PDB_C1_COUNT (2U)
8549
8551#define PDB_S_ERR_MASK (0xFFU)
8552#define PDB_S_ERR_SHIFT (0U)
8553#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
8554#define PDB_S_CF_MASK (0xFF0000U)
8555#define PDB_S_CF_SHIFT (16U)
8556#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
8557
8558/* The count of PDB_S */
8559#define PDB_S_COUNT (2U)
8560
8562#define PDB_DLY_DLY_MASK (0xFFFFU)
8563#define PDB_DLY_DLY_SHIFT (0U)
8564#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
8565
8566/* The count of PDB_DLY */
8567#define PDB_DLY_COUNT (2U)
8568
8569/* The count of PDB_DLY */
8570#define PDB_DLY_COUNT2 (2U)
8571
8573#define PDB_INTC_TOE_MASK (0x1U)
8574#define PDB_INTC_TOE_SHIFT (0U)
8575#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
8576#define PDB_INTC_EXT_MASK (0x2U)
8577#define PDB_INTC_EXT_SHIFT (1U)
8578#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
8579
8580/* The count of PDB_INTC */
8581#define PDB_INTC_COUNT (2U)
8582
8584#define PDB_INT_INT_MASK (0xFFFFU)
8585#define PDB_INT_INT_SHIFT (0U)
8586#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
8587
8588/* The count of PDB_INT */
8589#define PDB_INT_COUNT (2U)
8590
8592#define PDB_POEN_POEN_MASK (0xFFU)
8593#define PDB_POEN_POEN_SHIFT (0U)
8594#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
8595
8597#define PDB_PODLY_DLY2_MASK (0xFFFFU)
8598#define PDB_PODLY_DLY2_SHIFT (0U)
8599#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
8600#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
8601#define PDB_PODLY_DLY1_SHIFT (16U)
8602#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
8603
8604/* The count of PDB_PODLY */
8605#define PDB_PODLY_COUNT (3U)
8606
8607
8610 /* end of group PDB_Register_Masks */
8611
8612
8613/* PDB - Peripheral instance base addresses */
8615#define PDB0_BASE (0x40036000u)
8617#define PDB0 ((PDB_Type *)PDB0_BASE)
8619#define PDB_BASE_ADDRS { PDB0_BASE }
8621#define PDB_BASE_PTRS { PDB0 }
8623#define PDB_IRQS { PDB0_IRQn }
8624
8627 /* end of group PDB_Peripheral_Access_Layer */
8628
8629
8630/* ----------------------------------------------------------------------------
8631 -- PIT Peripheral Access Layer
8632 ---------------------------------------------------------------------------- */
8633
8640typedef struct {
8641 __IO uint32_t MCR;
8642 uint8_t RESERVED_0[252];
8643 struct { /* offset: 0x100, array step: 0x10 */
8644 __IO uint32_t LDVAL;
8645 __I uint32_t CVAL;
8646 __IO uint32_t TCTRL;
8647 __IO uint32_t TFLG;
8648 } CHANNEL[4];
8649} PIT_Type;
8650
8651/* ----------------------------------------------------------------------------
8652 -- PIT Register Masks
8653 ---------------------------------------------------------------------------- */
8654
8661#define PIT_MCR_FRZ_MASK (0x1U)
8662#define PIT_MCR_FRZ_SHIFT (0U)
8663#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
8664#define PIT_MCR_MDIS_MASK (0x2U)
8665#define PIT_MCR_MDIS_SHIFT (1U)
8666#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
8667
8669#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
8670#define PIT_LDVAL_TSV_SHIFT (0U)
8671#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
8672
8673/* The count of PIT_LDVAL */
8674#define PIT_LDVAL_COUNT (4U)
8675
8677#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
8678#define PIT_CVAL_TVL_SHIFT (0U)
8679#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
8680
8681/* The count of PIT_CVAL */
8682#define PIT_CVAL_COUNT (4U)
8683
8685#define PIT_TCTRL_TEN_MASK (0x1U)
8686#define PIT_TCTRL_TEN_SHIFT (0U)
8687#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
8688#define PIT_TCTRL_TIE_MASK (0x2U)
8689#define PIT_TCTRL_TIE_SHIFT (1U)
8690#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
8691#define PIT_TCTRL_CHN_MASK (0x4U)
8692#define PIT_TCTRL_CHN_SHIFT (2U)
8693#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
8694
8695/* The count of PIT_TCTRL */
8696#define PIT_TCTRL_COUNT (4U)
8697
8699#define PIT_TFLG_TIF_MASK (0x1U)
8700#define PIT_TFLG_TIF_SHIFT (0U)
8701#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
8702
8703/* The count of PIT_TFLG */
8704#define PIT_TFLG_COUNT (4U)
8705
8706
8709 /* end of group PIT_Register_Masks */
8710
8711
8712/* PIT - Peripheral instance base addresses */
8714#define PIT_BASE (0x40037000u)
8716#define PIT ((PIT_Type *)PIT_BASE)
8718#define PIT_BASE_ADDRS { PIT_BASE }
8720#define PIT_BASE_PTRS { PIT }
8722#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
8723
8726 /* end of group PIT_Peripheral_Access_Layer */
8727
8728
8729/* ----------------------------------------------------------------------------
8730 -- PMC Peripheral Access Layer
8731 ---------------------------------------------------------------------------- */
8732
8739typedef struct {
8740 __IO uint8_t LVDSC1;
8741 __IO uint8_t LVDSC2;
8742 __IO uint8_t REGSC;
8743} PMC_Type;
8744
8745/* ----------------------------------------------------------------------------
8746 -- PMC Register Masks
8747 ---------------------------------------------------------------------------- */
8748
8755#define PMC_LVDSC1_LVDV_MASK (0x3U)
8756#define PMC_LVDSC1_LVDV_SHIFT (0U)
8757#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
8758#define PMC_LVDSC1_LVDRE_MASK (0x10U)
8759#define PMC_LVDSC1_LVDRE_SHIFT (4U)
8760#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
8761#define PMC_LVDSC1_LVDIE_MASK (0x20U)
8762#define PMC_LVDSC1_LVDIE_SHIFT (5U)
8763#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
8764#define PMC_LVDSC1_LVDACK_MASK (0x40U)
8765#define PMC_LVDSC1_LVDACK_SHIFT (6U)
8766#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
8767#define PMC_LVDSC1_LVDF_MASK (0x80U)
8768#define PMC_LVDSC1_LVDF_SHIFT (7U)
8769#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
8770
8772#define PMC_LVDSC2_LVWV_MASK (0x3U)
8773#define PMC_LVDSC2_LVWV_SHIFT (0U)
8774#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
8775#define PMC_LVDSC2_LVWIE_MASK (0x20U)
8776#define PMC_LVDSC2_LVWIE_SHIFT (5U)
8777#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
8778#define PMC_LVDSC2_LVWACK_MASK (0x40U)
8779#define PMC_LVDSC2_LVWACK_SHIFT (6U)
8780#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
8781#define PMC_LVDSC2_LVWF_MASK (0x80U)
8782#define PMC_LVDSC2_LVWF_SHIFT (7U)
8783#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
8784
8786#define PMC_REGSC_BGBE_MASK (0x1U)
8787#define PMC_REGSC_BGBE_SHIFT (0U)
8788#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
8789#define PMC_REGSC_REGONS_MASK (0x4U)
8790#define PMC_REGSC_REGONS_SHIFT (2U)
8791#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
8792#define PMC_REGSC_ACKISO_MASK (0x8U)
8793#define PMC_REGSC_ACKISO_SHIFT (3U)
8794#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
8795#define PMC_REGSC_BGEN_MASK (0x10U)
8796#define PMC_REGSC_BGEN_SHIFT (4U)
8797#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
8798
8799
8802 /* end of group PMC_Register_Masks */
8803
8804
8805/* PMC - Peripheral instance base addresses */
8807#define PMC_BASE (0x4007D000u)
8809#define PMC ((PMC_Type *)PMC_BASE)
8811#define PMC_BASE_ADDRS { PMC_BASE }
8813#define PMC_BASE_PTRS { PMC }
8815#define PMC_IRQS { LVD_LVW_IRQn }
8816
8819 /* end of group PMC_Peripheral_Access_Layer */
8820
8821
8822/* ----------------------------------------------------------------------------
8823 -- PORT Peripheral Access Layer
8824 ---------------------------------------------------------------------------- */
8825
8832typedef struct {
8833 __IO uint32_t PCR[32];
8834 __O uint32_t GPCLR;
8835 __O uint32_t GPCHR;
8836 uint8_t RESERVED_0[24];
8837 __IO uint32_t ISFR;
8838 uint8_t RESERVED_1[28];
8839 __IO uint32_t DFER;
8840 __IO uint32_t DFCR;
8841 __IO uint32_t DFWR;
8842} PORT_Type;
8843
8844/* ----------------------------------------------------------------------------
8845 -- PORT Register Masks
8846 ---------------------------------------------------------------------------- */
8847
8854#define PORT_PCR_PS_MASK (0x1U)
8855#define PORT_PCR_PS_SHIFT (0U)
8856#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
8857#define PORT_PCR_PE_MASK (0x2U)
8858#define PORT_PCR_PE_SHIFT (1U)
8859#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
8860#define PORT_PCR_SRE_MASK (0x4U)
8861#define PORT_PCR_SRE_SHIFT (2U)
8862#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
8863#define PORT_PCR_PFE_MASK (0x10U)
8864#define PORT_PCR_PFE_SHIFT (4U)
8865#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
8866#define PORT_PCR_ODE_MASK (0x20U)
8867#define PORT_PCR_ODE_SHIFT (5U)
8868#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
8869#define PORT_PCR_DSE_MASK (0x40U)
8870#define PORT_PCR_DSE_SHIFT (6U)
8871#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
8872#define PORT_PCR_MUX_MASK (0x700U)
8873#define PORT_PCR_MUX_SHIFT (8U)
8874#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
8875#define PORT_PCR_LK_MASK (0x8000U)
8876#define PORT_PCR_LK_SHIFT (15U)
8877#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
8878#define PORT_PCR_IRQC_MASK (0xF0000U)
8879#define PORT_PCR_IRQC_SHIFT (16U)
8880#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
8881#define PORT_PCR_ISF_MASK (0x1000000U)
8882#define PORT_PCR_ISF_SHIFT (24U)
8883#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
8884
8885/* The count of PORT_PCR */
8886#define PORT_PCR_COUNT (32U)
8887
8889#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
8890#define PORT_GPCLR_GPWD_SHIFT (0U)
8891#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
8892#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
8893#define PORT_GPCLR_GPWE_SHIFT (16U)
8894#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
8895
8897#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
8898#define PORT_GPCHR_GPWD_SHIFT (0U)
8899#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
8900#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
8901#define PORT_GPCHR_GPWE_SHIFT (16U)
8902#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
8903
8905#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
8906#define PORT_ISFR_ISF_SHIFT (0U)
8907#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
8908
8910#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
8911#define PORT_DFER_DFE_SHIFT (0U)
8912#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
8913
8915#define PORT_DFCR_CS_MASK (0x1U)
8916#define PORT_DFCR_CS_SHIFT (0U)
8917#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
8918
8920#define PORT_DFWR_FILT_MASK (0x1FU)
8921#define PORT_DFWR_FILT_SHIFT (0U)
8922#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
8923
8924
8927 /* end of group PORT_Register_Masks */
8928
8929
8930/* PORT - Peripheral instance base addresses */
8932#define PORTA_BASE (0x40049000u)
8934#define PORTA ((PORT_Type *)PORTA_BASE)
8936#define PORTB_BASE (0x4004A000u)
8938#define PORTB ((PORT_Type *)PORTB_BASE)
8940#define PORTC_BASE (0x4004B000u)
8942#define PORTC ((PORT_Type *)PORTC_BASE)
8944#define PORTD_BASE (0x4004C000u)
8946#define PORTD ((PORT_Type *)PORTD_BASE)
8948#define PORTE_BASE (0x4004D000u)
8950#define PORTE ((PORT_Type *)PORTE_BASE)
8952#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
8954#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
8956#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
8957
8960 /* end of group PORT_Peripheral_Access_Layer */
8961
8962
8963/* ----------------------------------------------------------------------------
8964 -- RCM Peripheral Access Layer
8965 ---------------------------------------------------------------------------- */
8966
8973typedef struct {
8974 __I uint8_t SRS0;
8975 __I uint8_t SRS1;
8976 uint8_t RESERVED_0[2];
8977 __IO uint8_t RPFC;
8978 __IO uint8_t RPFW;
8979 uint8_t RESERVED_1[1];
8980 __I uint8_t MR;
8981} RCM_Type;
8982
8983/* ----------------------------------------------------------------------------
8984 -- RCM Register Masks
8985 ---------------------------------------------------------------------------- */
8986
8993#define RCM_SRS0_WAKEUP_MASK (0x1U)
8994#define RCM_SRS0_WAKEUP_SHIFT (0U)
8995#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
8996#define RCM_SRS0_LVD_MASK (0x2U)
8997#define RCM_SRS0_LVD_SHIFT (1U)
8998#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
8999#define RCM_SRS0_LOC_MASK (0x4U)
9000#define RCM_SRS0_LOC_SHIFT (2U)
9001#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
9002#define RCM_SRS0_LOL_MASK (0x8U)
9003#define RCM_SRS0_LOL_SHIFT (3U)
9004#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
9005#define RCM_SRS0_WDOG_MASK (0x20U)
9006#define RCM_SRS0_WDOG_SHIFT (5U)
9007#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
9008#define RCM_SRS0_PIN_MASK (0x40U)
9009#define RCM_SRS0_PIN_SHIFT (6U)
9010#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
9011#define RCM_SRS0_POR_MASK (0x80U)
9012#define RCM_SRS0_POR_SHIFT (7U)
9013#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
9014
9016#define RCM_SRS1_JTAG_MASK (0x1U)
9017#define RCM_SRS1_JTAG_SHIFT (0U)
9018#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
9019#define RCM_SRS1_LOCKUP_MASK (0x2U)
9020#define RCM_SRS1_LOCKUP_SHIFT (1U)
9021#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
9022#define RCM_SRS1_SW_MASK (0x4U)
9023#define RCM_SRS1_SW_SHIFT (2U)
9024#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
9025#define RCM_SRS1_MDM_AP_MASK (0x8U)
9026#define RCM_SRS1_MDM_AP_SHIFT (3U)
9027#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
9028#define RCM_SRS1_EZPT_MASK (0x10U)
9029#define RCM_SRS1_EZPT_SHIFT (4U)
9030#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
9031#define RCM_SRS1_SACKERR_MASK (0x20U)
9032#define RCM_SRS1_SACKERR_SHIFT (5U)
9033#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
9034
9036#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
9037#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
9038#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
9039#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
9040#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
9041#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
9042
9044#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
9045#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
9046#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
9047
9049#define RCM_MR_EZP_MS_MASK (0x2U)
9050#define RCM_MR_EZP_MS_SHIFT (1U)
9051#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
9052
9053
9056 /* end of group RCM_Register_Masks */
9057
9058
9059/* RCM - Peripheral instance base addresses */
9061#define RCM_BASE (0x4007F000u)
9063#define RCM ((RCM_Type *)RCM_BASE)
9065#define RCM_BASE_ADDRS { RCM_BASE }
9067#define RCM_BASE_PTRS { RCM }
9068
9071 /* end of group RCM_Peripheral_Access_Layer */
9072
9073
9074/* ----------------------------------------------------------------------------
9075 -- RFSYS Peripheral Access Layer
9076 ---------------------------------------------------------------------------- */
9077
9084typedef struct {
9085 __IO uint32_t REG[8];
9086} RFSYS_Type;
9087
9088/* ----------------------------------------------------------------------------
9089 -- RFSYS Register Masks
9090 ---------------------------------------------------------------------------- */
9091
9098#define RFSYS_REG_LL_MASK (0xFFU)
9099#define RFSYS_REG_LL_SHIFT (0U)
9100#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
9101#define RFSYS_REG_LH_MASK (0xFF00U)
9102#define RFSYS_REG_LH_SHIFT (8U)
9103#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
9104#define RFSYS_REG_HL_MASK (0xFF0000U)
9105#define RFSYS_REG_HL_SHIFT (16U)
9106#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
9107#define RFSYS_REG_HH_MASK (0xFF000000U)
9108#define RFSYS_REG_HH_SHIFT (24U)
9109#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
9110
9111/* The count of RFSYS_REG */
9112#define RFSYS_REG_COUNT (8U)
9113
9114
9117 /* end of group RFSYS_Register_Masks */
9118
9119
9120/* RFSYS - Peripheral instance base addresses */
9122#define RFSYS_BASE (0x40041000u)
9124#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
9126#define RFSYS_BASE_ADDRS { RFSYS_BASE }
9128#define RFSYS_BASE_PTRS { RFSYS }
9129
9132 /* end of group RFSYS_Peripheral_Access_Layer */
9133
9134
9135/* ----------------------------------------------------------------------------
9136 -- RFVBAT Peripheral Access Layer
9137 ---------------------------------------------------------------------------- */
9138
9145typedef struct {
9146 __IO uint32_t REG[8];
9147} RFVBAT_Type;
9148
9149/* ----------------------------------------------------------------------------
9150 -- RFVBAT Register Masks
9151 ---------------------------------------------------------------------------- */
9152
9159#define RFVBAT_REG_LL_MASK (0xFFU)
9160#define RFVBAT_REG_LL_SHIFT (0U)
9161#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
9162#define RFVBAT_REG_LH_MASK (0xFF00U)
9163#define RFVBAT_REG_LH_SHIFT (8U)
9164#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
9165#define RFVBAT_REG_HL_MASK (0xFF0000U)
9166#define RFVBAT_REG_HL_SHIFT (16U)
9167#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
9168#define RFVBAT_REG_HH_MASK (0xFF000000U)
9169#define RFVBAT_REG_HH_SHIFT (24U)
9170#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
9171
9172/* The count of RFVBAT_REG */
9173#define RFVBAT_REG_COUNT (8U)
9174
9175
9178 /* end of group RFVBAT_Register_Masks */
9179
9180
9181/* RFVBAT - Peripheral instance base addresses */
9183#define RFVBAT_BASE (0x4003E000u)
9185#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
9187#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
9189#define RFVBAT_BASE_PTRS { RFVBAT }
9190
9193 /* end of group RFVBAT_Peripheral_Access_Layer */
9194
9195
9196/* ----------------------------------------------------------------------------
9197 -- RNG Peripheral Access Layer
9198 ---------------------------------------------------------------------------- */
9199
9206typedef struct {
9207 __IO uint32_t CR;
9208 __I uint32_t SR;
9209 __O uint32_t ER;
9210 __I uint32_t OR;
9211} RNG_Type;
9212
9213/* ----------------------------------------------------------------------------
9214 -- RNG Register Masks
9215 ---------------------------------------------------------------------------- */
9216
9223#define RNG_CR_GO_MASK (0x1U)
9224#define RNG_CR_GO_SHIFT (0U)
9225#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
9226#define RNG_CR_HA_MASK (0x2U)
9227#define RNG_CR_HA_SHIFT (1U)
9228#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
9229#define RNG_CR_INTM_MASK (0x4U)
9230#define RNG_CR_INTM_SHIFT (2U)
9231#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
9232#define RNG_CR_CLRI_MASK (0x8U)
9233#define RNG_CR_CLRI_SHIFT (3U)
9234#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
9235#define RNG_CR_SLP_MASK (0x10U)
9236#define RNG_CR_SLP_SHIFT (4U)
9237#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
9238
9240#define RNG_SR_SECV_MASK (0x1U)
9241#define RNG_SR_SECV_SHIFT (0U)
9242#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
9243#define RNG_SR_LRS_MASK (0x2U)
9244#define RNG_SR_LRS_SHIFT (1U)
9245#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
9246#define RNG_SR_ORU_MASK (0x4U)
9247#define RNG_SR_ORU_SHIFT (2U)
9248#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
9249#define RNG_SR_ERRI_MASK (0x8U)
9250#define RNG_SR_ERRI_SHIFT (3U)
9251#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
9252#define RNG_SR_SLP_MASK (0x10U)
9253#define RNG_SR_SLP_SHIFT (4U)
9254#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
9255#define RNG_SR_OREG_LVL_MASK (0xFF00U)
9256#define RNG_SR_OREG_LVL_SHIFT (8U)
9257#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
9258#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
9259#define RNG_SR_OREG_SIZE_SHIFT (16U)
9260#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
9261
9263#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
9264#define RNG_ER_EXT_ENT_SHIFT (0U)
9265#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
9266
9268#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
9269#define RNG_OR_RANDOUT_SHIFT (0U)
9270#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
9271
9272
9275 /* end of group RNG_Register_Masks */
9276
9277
9278/* RNG - Peripheral instance base addresses */
9280#define RNG_BASE (0x400A0000u)
9282#define RNG ((RNG_Type *)RNG_BASE)
9284#define RNG_BASE_ADDRS { RNG_BASE }
9286#define RNG_BASE_PTRS { RNG }
9288#define RNG_IRQS { RNG_IRQn }
9289
9292 /* end of group RNG_Peripheral_Access_Layer */
9293
9294
9295/* ----------------------------------------------------------------------------
9296 -- RTC Peripheral Access Layer
9297 ---------------------------------------------------------------------------- */
9298
9305typedef struct {
9306 __IO uint32_t TSR;
9307 __IO uint32_t TPR;
9308 __IO uint32_t TAR;
9309 __IO uint32_t TCR;
9310 __IO uint32_t CR;
9311 __IO uint32_t SR;
9312 __IO uint32_t LR;
9313 __IO uint32_t IER;
9314 uint8_t RESERVED_0[2016];
9315 __IO uint32_t WAR;
9316 __IO uint32_t RAR;
9317} RTC_Type;
9318
9319/* ----------------------------------------------------------------------------
9320 -- RTC Register Masks
9321 ---------------------------------------------------------------------------- */
9322
9329#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
9330#define RTC_TSR_TSR_SHIFT (0U)
9331#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
9332
9334#define RTC_TPR_TPR_MASK (0xFFFFU)
9335#define RTC_TPR_TPR_SHIFT (0U)
9336#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
9337
9339#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
9340#define RTC_TAR_TAR_SHIFT (0U)
9341#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
9342
9344#define RTC_TCR_TCR_MASK (0xFFU)
9345#define RTC_TCR_TCR_SHIFT (0U)
9346#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
9347#define RTC_TCR_CIR_MASK (0xFF00U)
9348#define RTC_TCR_CIR_SHIFT (8U)
9349#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
9350#define RTC_TCR_TCV_MASK (0xFF0000U)
9351#define RTC_TCR_TCV_SHIFT (16U)
9352#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
9353#define RTC_TCR_CIC_MASK (0xFF000000U)
9354#define RTC_TCR_CIC_SHIFT (24U)
9355#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
9356
9358#define RTC_CR_SWR_MASK (0x1U)
9359#define RTC_CR_SWR_SHIFT (0U)
9360#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
9361#define RTC_CR_WPE_MASK (0x2U)
9362#define RTC_CR_WPE_SHIFT (1U)
9363#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
9364#define RTC_CR_SUP_MASK (0x4U)
9365#define RTC_CR_SUP_SHIFT (2U)
9366#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
9367#define RTC_CR_UM_MASK (0x8U)
9368#define RTC_CR_UM_SHIFT (3U)
9369#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
9370#define RTC_CR_OSCE_MASK (0x100U)
9371#define RTC_CR_OSCE_SHIFT (8U)
9372#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
9373#define RTC_CR_CLKO_MASK (0x200U)
9374#define RTC_CR_CLKO_SHIFT (9U)
9375#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
9376#define RTC_CR_SC16P_MASK (0x400U)
9377#define RTC_CR_SC16P_SHIFT (10U)
9378#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
9379#define RTC_CR_SC8P_MASK (0x800U)
9380#define RTC_CR_SC8P_SHIFT (11U)
9381#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
9382#define RTC_CR_SC4P_MASK (0x1000U)
9383#define RTC_CR_SC4P_SHIFT (12U)
9384#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
9385#define RTC_CR_SC2P_MASK (0x2000U)
9386#define RTC_CR_SC2P_SHIFT (13U)
9387#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
9388
9390#define RTC_SR_TIF_MASK (0x1U)
9391#define RTC_SR_TIF_SHIFT (0U)
9392#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
9393#define RTC_SR_TOF_MASK (0x2U)
9394#define RTC_SR_TOF_SHIFT (1U)
9395#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
9396#define RTC_SR_TAF_MASK (0x4U)
9397#define RTC_SR_TAF_SHIFT (2U)
9398#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
9399#define RTC_SR_TCE_MASK (0x10U)
9400#define RTC_SR_TCE_SHIFT (4U)
9401#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
9402
9404#define RTC_LR_TCL_MASK (0x8U)
9405#define RTC_LR_TCL_SHIFT (3U)
9406#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
9407#define RTC_LR_CRL_MASK (0x10U)
9408#define RTC_LR_CRL_SHIFT (4U)
9409#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
9410#define RTC_LR_SRL_MASK (0x20U)
9411#define RTC_LR_SRL_SHIFT (5U)
9412#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
9413#define RTC_LR_LRL_MASK (0x40U)
9414#define RTC_LR_LRL_SHIFT (6U)
9415#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
9416
9418#define RTC_IER_TIIE_MASK (0x1U)
9419#define RTC_IER_TIIE_SHIFT (0U)
9420#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
9421#define RTC_IER_TOIE_MASK (0x2U)
9422#define RTC_IER_TOIE_SHIFT (1U)
9423#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
9424#define RTC_IER_TAIE_MASK (0x4U)
9425#define RTC_IER_TAIE_SHIFT (2U)
9426#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
9427#define RTC_IER_TSIE_MASK (0x10U)
9428#define RTC_IER_TSIE_SHIFT (4U)
9429#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
9430#define RTC_IER_WPON_MASK (0x80U)
9431#define RTC_IER_WPON_SHIFT (7U)
9432#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
9433
9435#define RTC_WAR_TSRW_MASK (0x1U)
9436#define RTC_WAR_TSRW_SHIFT (0U)
9437#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
9438#define RTC_WAR_TPRW_MASK (0x2U)
9439#define RTC_WAR_TPRW_SHIFT (1U)
9440#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
9441#define RTC_WAR_TARW_MASK (0x4U)
9442#define RTC_WAR_TARW_SHIFT (2U)
9443#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
9444#define RTC_WAR_TCRW_MASK (0x8U)
9445#define RTC_WAR_TCRW_SHIFT (3U)
9446#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
9447#define RTC_WAR_CRW_MASK (0x10U)
9448#define RTC_WAR_CRW_SHIFT (4U)
9449#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
9450#define RTC_WAR_SRW_MASK (0x20U)
9451#define RTC_WAR_SRW_SHIFT (5U)
9452#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
9453#define RTC_WAR_LRW_MASK (0x40U)
9454#define RTC_WAR_LRW_SHIFT (6U)
9455#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
9456#define RTC_WAR_IERW_MASK (0x80U)
9457#define RTC_WAR_IERW_SHIFT (7U)
9458#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
9459
9461#define RTC_RAR_TSRR_MASK (0x1U)
9462#define RTC_RAR_TSRR_SHIFT (0U)
9463#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
9464#define RTC_RAR_TPRR_MASK (0x2U)
9465#define RTC_RAR_TPRR_SHIFT (1U)
9466#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
9467#define RTC_RAR_TARR_MASK (0x4U)
9468#define RTC_RAR_TARR_SHIFT (2U)
9469#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
9470#define RTC_RAR_TCRR_MASK (0x8U)
9471#define RTC_RAR_TCRR_SHIFT (3U)
9472#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
9473#define RTC_RAR_CRR_MASK (0x10U)
9474#define RTC_RAR_CRR_SHIFT (4U)
9475#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
9476#define RTC_RAR_SRR_MASK (0x20U)
9477#define RTC_RAR_SRR_SHIFT (5U)
9478#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
9479#define RTC_RAR_LRR_MASK (0x40U)
9480#define RTC_RAR_LRR_SHIFT (6U)
9481#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
9482#define RTC_RAR_IERR_MASK (0x80U)
9483#define RTC_RAR_IERR_SHIFT (7U)
9484#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
9485
9486
9489 /* end of group RTC_Register_Masks */
9490
9491
9492/* RTC - Peripheral instance base addresses */
9494#define RTC_BASE (0x4003D000u)
9496#define RTC ((RTC_Type *)RTC_BASE)
9498#define RTC_BASE_ADDRS { RTC_BASE }
9500#define RTC_BASE_PTRS { RTC }
9502#define RTC_IRQS { RTC_IRQn }
9503#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
9504
9507 /* end of group RTC_Peripheral_Access_Layer */
9508
9509
9510/* ----------------------------------------------------------------------------
9511 -- SDHC Peripheral Access Layer
9512 ---------------------------------------------------------------------------- */
9513
9520typedef struct {
9521 __IO uint32_t DSADDR;
9522 __IO uint32_t BLKATTR;
9523 __IO uint32_t CMDARG;
9524 __IO uint32_t XFERTYP;
9525 __I uint32_t CMDRSP[4];
9526 __IO uint32_t DATPORT;
9527 __I uint32_t PRSSTAT;
9528 __IO uint32_t PROCTL;
9529 __IO uint32_t SYSCTL;
9530 __IO uint32_t IRQSTAT;
9531 __IO uint32_t IRQSTATEN;
9532 __IO uint32_t IRQSIGEN;
9533 __I uint32_t AC12ERR;
9534 __I uint32_t HTCAPBLT;
9535 __IO uint32_t WML;
9536 uint8_t RESERVED_0[8];
9537 __O uint32_t FEVT;
9538 __I uint32_t ADMAES;
9539 __IO uint32_t ADSADDR;
9540 uint8_t RESERVED_1[100];
9541 __IO uint32_t VENDOR;
9542 __IO uint32_t MMCBOOT;
9543 uint8_t RESERVED_2[52];
9544 __I uint32_t HOSTVER;
9545} SDHC_Type;
9546
9547/* ----------------------------------------------------------------------------
9548 -- SDHC Register Masks
9549 ---------------------------------------------------------------------------- */
9550
9557#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
9558#define SDHC_DSADDR_DSADDR_SHIFT (2U)
9559#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
9560
9562#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
9563#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
9564#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
9565#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
9566#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
9567#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
9568
9570#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
9571#define SDHC_CMDARG_CMDARG_SHIFT (0U)
9572#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
9573
9575#define SDHC_XFERTYP_DMAEN_MASK (0x1U)
9576#define SDHC_XFERTYP_DMAEN_SHIFT (0U)
9577#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
9578#define SDHC_XFERTYP_BCEN_MASK (0x2U)
9579#define SDHC_XFERTYP_BCEN_SHIFT (1U)
9580#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
9581#define SDHC_XFERTYP_AC12EN_MASK (0x4U)
9582#define SDHC_XFERTYP_AC12EN_SHIFT (2U)
9583#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
9584#define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
9585#define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
9586#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
9587#define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
9588#define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
9589#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
9590#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
9591#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
9592#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
9593#define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
9594#define SDHC_XFERTYP_CCCEN_SHIFT (19U)
9595#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
9596#define SDHC_XFERTYP_CICEN_MASK (0x100000U)
9597#define SDHC_XFERTYP_CICEN_SHIFT (20U)
9598#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
9599#define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
9600#define SDHC_XFERTYP_DPSEL_SHIFT (21U)
9601#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
9602#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
9603#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
9604#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
9605#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
9606#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
9607#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
9608
9610#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
9611#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
9612#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
9613#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
9614#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
9615#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
9616#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
9617#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
9618#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
9619#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
9620#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
9621#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
9622
9623/* The count of SDHC_CMDRSP */
9624#define SDHC_CMDRSP_COUNT (4U)
9625
9627#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
9628#define SDHC_DATPORT_DATCONT_SHIFT (0U)
9629#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
9630
9632#define SDHC_PRSSTAT_CIHB_MASK (0x1U)
9633#define SDHC_PRSSTAT_CIHB_SHIFT (0U)
9634#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
9635#define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
9636#define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
9637#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
9638#define SDHC_PRSSTAT_DLA_MASK (0x4U)
9639#define SDHC_PRSSTAT_DLA_SHIFT (2U)
9640#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
9641#define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
9642#define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
9643#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
9644#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
9645#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
9646#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
9647#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
9648#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
9649#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
9650#define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
9651#define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
9652#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
9653#define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
9654#define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
9655#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
9656#define SDHC_PRSSTAT_WTA_MASK (0x100U)
9657#define SDHC_PRSSTAT_WTA_SHIFT (8U)
9658#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
9659#define SDHC_PRSSTAT_RTA_MASK (0x200U)
9660#define SDHC_PRSSTAT_RTA_SHIFT (9U)
9661#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
9662#define SDHC_PRSSTAT_BWEN_MASK (0x400U)
9663#define SDHC_PRSSTAT_BWEN_SHIFT (10U)
9664#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
9665#define SDHC_PRSSTAT_BREN_MASK (0x800U)
9666#define SDHC_PRSSTAT_BREN_SHIFT (11U)
9667#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
9668#define SDHC_PRSSTAT_CINS_MASK (0x10000U)
9669#define SDHC_PRSSTAT_CINS_SHIFT (16U)
9670#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
9671#define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
9672#define SDHC_PRSSTAT_CLSL_SHIFT (23U)
9673#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
9674#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
9675#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
9676#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
9677
9679#define SDHC_PROCTL_LCTL_MASK (0x1U)
9680#define SDHC_PROCTL_LCTL_SHIFT (0U)
9681#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
9682#define SDHC_PROCTL_DTW_MASK (0x6U)
9683#define SDHC_PROCTL_DTW_SHIFT (1U)
9684#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
9685#define SDHC_PROCTL_D3CD_MASK (0x8U)
9686#define SDHC_PROCTL_D3CD_SHIFT (3U)
9687#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
9688#define SDHC_PROCTL_EMODE_MASK (0x30U)
9689#define SDHC_PROCTL_EMODE_SHIFT (4U)
9690#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
9691#define SDHC_PROCTL_CDTL_MASK (0x40U)
9692#define SDHC_PROCTL_CDTL_SHIFT (6U)
9693#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
9694#define SDHC_PROCTL_CDSS_MASK (0x80U)
9695#define SDHC_PROCTL_CDSS_SHIFT (7U)
9696#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
9697#define SDHC_PROCTL_DMAS_MASK (0x300U)
9698#define SDHC_PROCTL_DMAS_SHIFT (8U)
9699#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
9700#define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
9701#define SDHC_PROCTL_SABGREQ_SHIFT (16U)
9702#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
9703#define SDHC_PROCTL_CREQ_MASK (0x20000U)
9704#define SDHC_PROCTL_CREQ_SHIFT (17U)
9705#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
9706#define SDHC_PROCTL_RWCTL_MASK (0x40000U)
9707#define SDHC_PROCTL_RWCTL_SHIFT (18U)
9708#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
9709#define SDHC_PROCTL_IABG_MASK (0x80000U)
9710#define SDHC_PROCTL_IABG_SHIFT (19U)
9711#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
9712#define SDHC_PROCTL_WECINT_MASK (0x1000000U)
9713#define SDHC_PROCTL_WECINT_SHIFT (24U)
9714#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
9715#define SDHC_PROCTL_WECINS_MASK (0x2000000U)
9716#define SDHC_PROCTL_WECINS_SHIFT (25U)
9717#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
9718#define SDHC_PROCTL_WECRM_MASK (0x4000000U)
9719#define SDHC_PROCTL_WECRM_SHIFT (26U)
9720#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
9721
9723#define SDHC_SYSCTL_IPGEN_MASK (0x1U)
9724#define SDHC_SYSCTL_IPGEN_SHIFT (0U)
9725#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
9726#define SDHC_SYSCTL_HCKEN_MASK (0x2U)
9727#define SDHC_SYSCTL_HCKEN_SHIFT (1U)
9728#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
9729#define SDHC_SYSCTL_PEREN_MASK (0x4U)
9730#define SDHC_SYSCTL_PEREN_SHIFT (2U)
9731#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
9732#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
9733#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
9734#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
9735#define SDHC_SYSCTL_DVS_MASK (0xF0U)
9736#define SDHC_SYSCTL_DVS_SHIFT (4U)
9737#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
9738#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
9739#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
9740#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
9741#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
9742#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
9743#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
9744#define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
9745#define SDHC_SYSCTL_RSTA_SHIFT (24U)
9746#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
9747#define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
9748#define SDHC_SYSCTL_RSTC_SHIFT (25U)
9749#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
9750#define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
9751#define SDHC_SYSCTL_RSTD_SHIFT (26U)
9752#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
9753#define SDHC_SYSCTL_INITA_MASK (0x8000000U)
9754#define SDHC_SYSCTL_INITA_SHIFT (27U)
9755#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
9756
9758#define SDHC_IRQSTAT_CC_MASK (0x1U)
9759#define SDHC_IRQSTAT_CC_SHIFT (0U)
9760#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
9761#define SDHC_IRQSTAT_TC_MASK (0x2U)
9762#define SDHC_IRQSTAT_TC_SHIFT (1U)
9763#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
9764#define SDHC_IRQSTAT_BGE_MASK (0x4U)
9765#define SDHC_IRQSTAT_BGE_SHIFT (2U)
9766#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
9767#define SDHC_IRQSTAT_DINT_MASK (0x8U)
9768#define SDHC_IRQSTAT_DINT_SHIFT (3U)
9769#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
9770#define SDHC_IRQSTAT_BWR_MASK (0x10U)
9771#define SDHC_IRQSTAT_BWR_SHIFT (4U)
9772#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
9773#define SDHC_IRQSTAT_BRR_MASK (0x20U)
9774#define SDHC_IRQSTAT_BRR_SHIFT (5U)
9775#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
9776#define SDHC_IRQSTAT_CINS_MASK (0x40U)
9777#define SDHC_IRQSTAT_CINS_SHIFT (6U)
9778#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
9779#define SDHC_IRQSTAT_CRM_MASK (0x80U)
9780#define SDHC_IRQSTAT_CRM_SHIFT (7U)
9781#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
9782#define SDHC_IRQSTAT_CINT_MASK (0x100U)
9783#define SDHC_IRQSTAT_CINT_SHIFT (8U)
9784#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
9785#define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
9786#define SDHC_IRQSTAT_CTOE_SHIFT (16U)
9787#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
9788#define SDHC_IRQSTAT_CCE_MASK (0x20000U)
9789#define SDHC_IRQSTAT_CCE_SHIFT (17U)
9790#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
9791#define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
9792#define SDHC_IRQSTAT_CEBE_SHIFT (18U)
9793#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
9794#define SDHC_IRQSTAT_CIE_MASK (0x80000U)
9795#define SDHC_IRQSTAT_CIE_SHIFT (19U)
9796#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
9797#define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
9798#define SDHC_IRQSTAT_DTOE_SHIFT (20U)
9799#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
9800#define SDHC_IRQSTAT_DCE_MASK (0x200000U)
9801#define SDHC_IRQSTAT_DCE_SHIFT (21U)
9802#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
9803#define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
9804#define SDHC_IRQSTAT_DEBE_SHIFT (22U)
9805#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
9806#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
9807#define SDHC_IRQSTAT_AC12E_SHIFT (24U)
9808#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
9809#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
9810#define SDHC_IRQSTAT_DMAE_SHIFT (28U)
9811#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
9812
9814#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
9815#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
9816#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
9817#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
9818#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
9819#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
9820#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
9821#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
9822#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
9823#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
9824#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
9825#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
9826#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
9827#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
9828#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
9829#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
9830#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
9831#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
9832#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
9833#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
9834#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
9835#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
9836#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
9837#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
9838#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
9839#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
9840#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
9841#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
9842#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
9843#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
9844#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
9845#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
9846#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
9847#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
9848#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
9849#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
9850#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
9851#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
9852#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
9853#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
9854#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
9855#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
9856#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
9857#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
9858#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
9859#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
9860#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
9861#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
9862#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
9863#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
9864#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
9865#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
9866#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
9867#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
9868
9870#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
9871#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
9872#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
9873#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
9874#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
9875#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
9876#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
9877#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
9878#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
9879#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
9880#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
9881#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
9882#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
9883#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
9884#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
9885#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
9886#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
9887#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
9888#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
9889#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
9890#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
9891#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
9892#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
9893#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
9894#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
9895#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
9896#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
9897#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
9898#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
9899#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
9900#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
9901#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
9902#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
9903#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
9904#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
9905#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
9906#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
9907#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
9908#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
9909#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
9910#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
9911#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
9912#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
9913#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
9914#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
9915#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
9916#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
9917#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
9918#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
9919#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
9920#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
9921#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
9922#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
9923#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
9924
9926#define SDHC_AC12ERR_AC12NE_MASK (0x1U)
9927#define SDHC_AC12ERR_AC12NE_SHIFT (0U)
9928#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
9929#define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
9930#define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
9931#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
9932#define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
9933#define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
9934#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
9935#define SDHC_AC12ERR_AC12CE_MASK (0x8U)
9936#define SDHC_AC12ERR_AC12CE_SHIFT (3U)
9937#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
9938#define SDHC_AC12ERR_AC12IE_MASK (0x10U)
9939#define SDHC_AC12ERR_AC12IE_SHIFT (4U)
9940#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
9941#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
9942#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
9943#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
9944
9946#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
9947#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
9948#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
9949#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
9950#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
9951#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
9952#define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
9953#define SDHC_HTCAPBLT_HSS_SHIFT (21U)
9954#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
9955#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
9956#define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
9957#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
9958#define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
9959#define SDHC_HTCAPBLT_SRS_SHIFT (23U)
9960#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
9961#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
9962#define SDHC_HTCAPBLT_VS33_SHIFT (24U)
9963#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
9964#define SDHC_HTCAPBLT_VS30_MASK (0x2000000U)
9965#define SDHC_HTCAPBLT_VS30_SHIFT (25U)
9966#define SDHC_HTCAPBLT_VS30(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS30_SHIFT)) & SDHC_HTCAPBLT_VS30_MASK)
9967#define SDHC_HTCAPBLT_VS18_MASK (0x4000000U)
9968#define SDHC_HTCAPBLT_VS18_SHIFT (26U)
9969#define SDHC_HTCAPBLT_VS18(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS18_SHIFT)) & SDHC_HTCAPBLT_VS18_MASK)
9970
9972#define SDHC_WML_RDWML_MASK (0xFFU)
9973#define SDHC_WML_RDWML_SHIFT (0U)
9974#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
9975#define SDHC_WML_WRWML_MASK (0xFF0000U)
9976#define SDHC_WML_WRWML_SHIFT (16U)
9977#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
9978
9980#define SDHC_FEVT_AC12NE_MASK (0x1U)
9981#define SDHC_FEVT_AC12NE_SHIFT (0U)
9982#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
9983#define SDHC_FEVT_AC12TOE_MASK (0x2U)
9984#define SDHC_FEVT_AC12TOE_SHIFT (1U)
9985#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
9986#define SDHC_FEVT_AC12CE_MASK (0x4U)
9987#define SDHC_FEVT_AC12CE_SHIFT (2U)
9988#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
9989#define SDHC_FEVT_AC12EBE_MASK (0x8U)
9990#define SDHC_FEVT_AC12EBE_SHIFT (3U)
9991#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
9992#define SDHC_FEVT_AC12IE_MASK (0x10U)
9993#define SDHC_FEVT_AC12IE_SHIFT (4U)
9994#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
9995#define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
9996#define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
9997#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
9998#define SDHC_FEVT_CTOE_MASK (0x10000U)
9999#define SDHC_FEVT_CTOE_SHIFT (16U)
10000#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
10001#define SDHC_FEVT_CCE_MASK (0x20000U)
10002#define SDHC_FEVT_CCE_SHIFT (17U)
10003#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
10004#define SDHC_FEVT_CEBE_MASK (0x40000U)
10005#define SDHC_FEVT_CEBE_SHIFT (18U)
10006#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
10007#define SDHC_FEVT_CIE_MASK (0x80000U)
10008#define SDHC_FEVT_CIE_SHIFT (19U)
10009#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
10010#define SDHC_FEVT_DTOE_MASK (0x100000U)
10011#define SDHC_FEVT_DTOE_SHIFT (20U)
10012#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
10013#define SDHC_FEVT_DCE_MASK (0x200000U)
10014#define SDHC_FEVT_DCE_SHIFT (21U)
10015#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
10016#define SDHC_FEVT_DEBE_MASK (0x400000U)
10017#define SDHC_FEVT_DEBE_SHIFT (22U)
10018#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
10019#define SDHC_FEVT_AC12E_MASK (0x1000000U)
10020#define SDHC_FEVT_AC12E_SHIFT (24U)
10021#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
10022#define SDHC_FEVT_DMAE_MASK (0x10000000U)
10023#define SDHC_FEVT_DMAE_SHIFT (28U)
10024#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
10025#define SDHC_FEVT_CINT_MASK (0x80000000U)
10026#define SDHC_FEVT_CINT_SHIFT (31U)
10027#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
10028
10030#define SDHC_ADMAES_ADMAES_MASK (0x3U)
10031#define SDHC_ADMAES_ADMAES_SHIFT (0U)
10032#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
10033#define SDHC_ADMAES_ADMALME_MASK (0x4U)
10034#define SDHC_ADMAES_ADMALME_SHIFT (2U)
10035#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
10036#define SDHC_ADMAES_ADMADCE_MASK (0x8U)
10037#define SDHC_ADMAES_ADMADCE_SHIFT (3U)
10038#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
10039
10041#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
10042#define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
10043#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
10044
10046#define SDHC_VENDOR_EXTDMAEN_MASK (0x1U)
10047#define SDHC_VENDOR_EXTDMAEN_SHIFT (0U)
10048#define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
10049#define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
10050#define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
10051#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
10052#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
10053#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
10054#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
10055
10057#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
10058#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
10059#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
10060#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
10061#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
10062#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
10063#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
10064#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
10065#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
10066#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
10067#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
10068#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
10069#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
10070#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
10071#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
10072#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
10073#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
10074#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
10075
10077#define SDHC_HOSTVER_SVN_MASK (0xFFU)
10078#define SDHC_HOSTVER_SVN_SHIFT (0U)
10079#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
10080#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
10081#define SDHC_HOSTVER_VVN_SHIFT (8U)
10082#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
10083
10084
10087 /* end of group SDHC_Register_Masks */
10088
10089
10090/* SDHC - Peripheral instance base addresses */
10092#define SDHC_BASE (0x400B1000u)
10094#define SDHC ((SDHC_Type *)SDHC_BASE)
10096#define SDHC_BASE_ADDRS { SDHC_BASE }
10098#define SDHC_BASE_PTRS { SDHC }
10100#define SDHC_IRQS { SDHC_IRQn }
10101
10104 /* end of group SDHC_Peripheral_Access_Layer */
10105
10106
10107/* ----------------------------------------------------------------------------
10108 -- SIM Peripheral Access Layer
10109 ---------------------------------------------------------------------------- */
10110
10117typedef struct {
10118 __IO uint32_t SOPT1;
10119 __IO uint32_t SOPT1CFG;
10120 uint8_t RESERVED_0[4092];
10121 __IO uint32_t SOPT2;
10122 uint8_t RESERVED_1[4];
10123 __IO uint32_t SOPT4;
10124 __IO uint32_t SOPT5;
10125 uint8_t RESERVED_2[4];
10126 __IO uint32_t SOPT7;
10127 uint8_t RESERVED_3[8];
10128 __I uint32_t SDID;
10129 __IO uint32_t SCGC1;
10130 __IO uint32_t SCGC2;
10131 __IO uint32_t SCGC3;
10132 __IO uint32_t SCGC4;
10133 __IO uint32_t SCGC5;
10134 __IO uint32_t SCGC6;
10135 __IO uint32_t SCGC7;
10136 __IO uint32_t CLKDIV1;
10137 __IO uint32_t CLKDIV2;
10138 __IO uint32_t FCFG1;
10139 __I uint32_t FCFG2;
10140 __I uint32_t UIDH;
10141 __I uint32_t UIDMH;
10142 __I uint32_t UIDML;
10143 __I uint32_t UIDL;
10144} SIM_Type;
10145
10146/* ----------------------------------------------------------------------------
10147 -- SIM Register Masks
10148 ---------------------------------------------------------------------------- */
10149
10156#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
10157#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
10158#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
10159#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
10160#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
10161#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
10162#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
10163#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
10164#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
10165#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
10166#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
10167#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
10168#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
10169#define SIM_SOPT1_USBREGEN_SHIFT (31U)
10170#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
10171
10173#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
10174#define SIM_SOPT1CFG_URWE_SHIFT (24U)
10175#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
10176#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
10177#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
10178#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
10179#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
10180#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
10181#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
10182
10184#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
10185#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
10186#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
10187#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
10188#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
10189#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
10190#define SIM_SOPT2_FBSL_MASK (0x300U)
10191#define SIM_SOPT2_FBSL_SHIFT (8U)
10192#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
10193#define SIM_SOPT2_PTD7PAD_MASK (0x800U)
10194#define SIM_SOPT2_PTD7PAD_SHIFT (11U)
10195#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
10196#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
10197#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
10198#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
10199#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
10200#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
10201#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
10202#define SIM_SOPT2_USBSRC_MASK (0x40000U)
10203#define SIM_SOPT2_USBSRC_SHIFT (18U)
10204#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
10205#define SIM_SOPT2_RMIISRC_MASK (0x80000U)
10206#define SIM_SOPT2_RMIISRC_SHIFT (19U)
10207#define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
10208#define SIM_SOPT2_TIMESRC_MASK (0x300000U)
10209#define SIM_SOPT2_TIMESRC_SHIFT (20U)
10210#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
10211#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
10212#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
10213#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
10214
10216#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
10217#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
10218#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
10219#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
10220#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
10221#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
10222#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
10223#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
10224#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
10225#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
10226#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
10227#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
10228#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
10229#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
10230#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
10231#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
10232#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
10233#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
10234#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
10235#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
10236#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
10237#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
10238#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
10239#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
10240#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
10241#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
10242#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
10243#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
10244#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
10245#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
10246#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
10247#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
10248#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
10249#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
10250#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
10251#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
10252
10254#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
10255#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
10256#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
10257#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
10258#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
10259#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
10260#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
10261#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
10262#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
10263#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
10264#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
10265#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
10266
10268#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
10269#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
10270#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
10271#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
10272#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
10273#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
10274#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
10275#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
10276#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
10277#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
10278#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
10279#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
10280#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
10281#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
10282#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
10283#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
10284#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
10285#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
10286
10288#define SIM_SDID_PINID_MASK (0xFU)
10289#define SIM_SDID_PINID_SHIFT (0U)
10290#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
10291#define SIM_SDID_FAMID_MASK (0x70U)
10292#define SIM_SDID_FAMID_SHIFT (4U)
10293#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
10294#define SIM_SDID_REVID_MASK (0xF000U)
10295#define SIM_SDID_REVID_SHIFT (12U)
10296#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
10297
10299#define SIM_SCGC1_UART4_MASK (0x400U)
10300#define SIM_SCGC1_UART4_SHIFT (10U)
10301#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
10302#define SIM_SCGC1_UART5_MASK (0x800U)
10303#define SIM_SCGC1_UART5_SHIFT (11U)
10304#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
10305
10307#define SIM_SCGC2_ENET_MASK (0x1U)
10308#define SIM_SCGC2_ENET_SHIFT (0U)
10309#define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
10310#define SIM_SCGC2_DAC0_MASK (0x1000U)
10311#define SIM_SCGC2_DAC0_SHIFT (12U)
10312#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
10313#define SIM_SCGC2_DAC1_MASK (0x2000U)
10314#define SIM_SCGC2_DAC1_SHIFT (13U)
10315#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
10316
10318#define SIM_SCGC3_RNGA_MASK (0x1U)
10319#define SIM_SCGC3_RNGA_SHIFT (0U)
10320#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
10321#define SIM_SCGC3_FLEXCAN1_MASK (0x10U)
10322#define SIM_SCGC3_FLEXCAN1_SHIFT (4U)
10323#define SIM_SCGC3_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
10324#define SIM_SCGC3_SPI2_MASK (0x1000U)
10325#define SIM_SCGC3_SPI2_SHIFT (12U)
10326#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
10327#define SIM_SCGC3_SDHC_MASK (0x20000U)
10328#define SIM_SCGC3_SDHC_SHIFT (17U)
10329#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
10330#define SIM_SCGC3_FTM2_MASK (0x1000000U)
10331#define SIM_SCGC3_FTM2_SHIFT (24U)
10332#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
10333#define SIM_SCGC3_ADC1_MASK (0x8000000U)
10334#define SIM_SCGC3_ADC1_SHIFT (27U)
10335#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
10336
10338#define SIM_SCGC4_EWM_MASK (0x2U)
10339#define SIM_SCGC4_EWM_SHIFT (1U)
10340#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
10341#define SIM_SCGC4_CMT_MASK (0x4U)
10342#define SIM_SCGC4_CMT_SHIFT (2U)
10343#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
10344#define SIM_SCGC4_I2C0_MASK (0x40U)
10345#define SIM_SCGC4_I2C0_SHIFT (6U)
10346#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
10347#define SIM_SCGC4_I2C1_MASK (0x80U)
10348#define SIM_SCGC4_I2C1_SHIFT (7U)
10349#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
10350#define SIM_SCGC4_UART0_MASK (0x400U)
10351#define SIM_SCGC4_UART0_SHIFT (10U)
10352#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
10353#define SIM_SCGC4_UART1_MASK (0x800U)
10354#define SIM_SCGC4_UART1_SHIFT (11U)
10355#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
10356#define SIM_SCGC4_UART2_MASK (0x1000U)
10357#define SIM_SCGC4_UART2_SHIFT (12U)
10358#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
10359#define SIM_SCGC4_UART3_MASK (0x2000U)
10360#define SIM_SCGC4_UART3_SHIFT (13U)
10361#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
10362#define SIM_SCGC4_USBOTG_MASK (0x40000U)
10363#define SIM_SCGC4_USBOTG_SHIFT (18U)
10364#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
10365#define SIM_SCGC4_CMP_MASK (0x80000U)
10366#define SIM_SCGC4_CMP_SHIFT (19U)
10367#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
10368#define SIM_SCGC4_VREF_MASK (0x100000U)
10369#define SIM_SCGC4_VREF_SHIFT (20U)
10370#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
10371#define SIM_SCGC4_LLWU_MASK (0x10000000U)
10372#define SIM_SCGC4_LLWU_SHIFT (28U)
10373#define SIM_SCGC4_LLWU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_LLWU_SHIFT)) & SIM_SCGC4_LLWU_MASK)
10374
10376#define SIM_SCGC5_LPTIMER_MASK (0x1U)
10377#define SIM_SCGC5_LPTIMER_SHIFT (0U)
10378#define SIM_SCGC5_LPTIMER(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTIMER_SHIFT)) & SIM_SCGC5_LPTIMER_MASK)
10379#define SIM_SCGC5_TSI_MASK (0x20U)
10380#define SIM_SCGC5_TSI_SHIFT (5U)
10381#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
10382#define SIM_SCGC5_PORTA_MASK (0x200U)
10383#define SIM_SCGC5_PORTA_SHIFT (9U)
10384#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
10385#define SIM_SCGC5_PORTB_MASK (0x400U)
10386#define SIM_SCGC5_PORTB_SHIFT (10U)
10387#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
10388#define SIM_SCGC5_PORTC_MASK (0x800U)
10389#define SIM_SCGC5_PORTC_SHIFT (11U)
10390#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
10391#define SIM_SCGC5_PORTD_MASK (0x1000U)
10392#define SIM_SCGC5_PORTD_SHIFT (12U)
10393#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
10394#define SIM_SCGC5_PORTE_MASK (0x2000U)
10395#define SIM_SCGC5_PORTE_SHIFT (13U)
10396#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
10397
10399#define SIM_SCGC6_FTFL_MASK (0x1U)
10400#define SIM_SCGC6_FTFL_SHIFT (0U)
10401#define SIM_SCGC6_FTFL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK)
10402#define SIM_SCGC6_DMAMUX_MASK (0x2U)
10403#define SIM_SCGC6_DMAMUX_SHIFT (1U)
10404#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
10405#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
10406#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
10407#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
10408#define SIM_SCGC6_SPI0_MASK (0x1000U)
10409#define SIM_SCGC6_SPI0_SHIFT (12U)
10410#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
10411#define SIM_SCGC6_SPI1_MASK (0x2000U)
10412#define SIM_SCGC6_SPI1_SHIFT (13U)
10413#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
10414#define SIM_SCGC6_I2S_MASK (0x8000U)
10415#define SIM_SCGC6_I2S_SHIFT (15U)
10416#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
10417#define SIM_SCGC6_CRC_MASK (0x40000U)
10418#define SIM_SCGC6_CRC_SHIFT (18U)
10419#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
10420#define SIM_SCGC6_USBDCD_MASK (0x200000U)
10421#define SIM_SCGC6_USBDCD_SHIFT (21U)
10422#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
10423#define SIM_SCGC6_PDB_MASK (0x400000U)
10424#define SIM_SCGC6_PDB_SHIFT (22U)
10425#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
10426#define SIM_SCGC6_PIT_MASK (0x800000U)
10427#define SIM_SCGC6_PIT_SHIFT (23U)
10428#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
10429#define SIM_SCGC6_FTM0_MASK (0x1000000U)
10430#define SIM_SCGC6_FTM0_SHIFT (24U)
10431#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
10432#define SIM_SCGC6_FTM1_MASK (0x2000000U)
10433#define SIM_SCGC6_FTM1_SHIFT (25U)
10434#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
10435#define SIM_SCGC6_ADC0_MASK (0x8000000U)
10436#define SIM_SCGC6_ADC0_SHIFT (27U)
10437#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
10438#define SIM_SCGC6_RTC_MASK (0x20000000U)
10439#define SIM_SCGC6_RTC_SHIFT (29U)
10440#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
10441
10443#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
10444#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
10445#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
10446#define SIM_SCGC7_DMA_MASK (0x2U)
10447#define SIM_SCGC7_DMA_SHIFT (1U)
10448#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
10449#define SIM_SCGC7_MPU_MASK (0x4U)
10450#define SIM_SCGC7_MPU_SHIFT (2U)
10451#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
10452
10454#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
10455#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
10456#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
10457#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
10458#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
10459#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
10460#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
10461#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
10462#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
10463#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
10464#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
10465#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
10466
10468#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
10469#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
10470#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
10471#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
10472#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
10473#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
10474
10476#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
10477#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
10478#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
10479#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
10480#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
10481#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
10482#define SIM_FCFG1_DEPART_MASK (0xF00U)
10483#define SIM_FCFG1_DEPART_SHIFT (8U)
10484#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
10485#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
10486#define SIM_FCFG1_EESIZE_SHIFT (16U)
10487#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
10488#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
10489#define SIM_FCFG1_PFSIZE_SHIFT (24U)
10490#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
10491#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
10492#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
10493#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
10494
10496#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
10497#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
10498#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
10499#define SIM_FCFG2_PFLSH_MASK (0x800000U)
10500#define SIM_FCFG2_PFLSH_SHIFT (23U)
10501#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
10502#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
10503#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
10504#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
10505#define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
10506#define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
10507#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
10508
10510#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
10511#define SIM_UIDH_UID_SHIFT (0U)
10512#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
10513
10515#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
10516#define SIM_UIDMH_UID_SHIFT (0U)
10517#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
10518
10520#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
10521#define SIM_UIDML_UID_SHIFT (0U)
10522#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
10523
10525#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
10526#define SIM_UIDL_UID_SHIFT (0U)
10527#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
10528
10529
10532 /* end of group SIM_Register_Masks */
10533
10534
10535/* SIM - Peripheral instance base addresses */
10537#define SIM_BASE (0x40047000u)
10539#define SIM ((SIM_Type *)SIM_BASE)
10541#define SIM_BASE_ADDRS { SIM_BASE }
10543#define SIM_BASE_PTRS { SIM }
10544
10547 /* end of group SIM_Peripheral_Access_Layer */
10548
10549
10550/* ----------------------------------------------------------------------------
10551 -- SMC Peripheral Access Layer
10552 ---------------------------------------------------------------------------- */
10553
10560typedef struct {
10561 __IO uint8_t PMPROT;
10562 __IO uint8_t PMCTRL;
10563 __IO uint8_t VLLSCTRL;
10564 __I uint8_t PMSTAT;
10565} SMC_Type;
10566
10567/* ----------------------------------------------------------------------------
10568 -- SMC Register Masks
10569 ---------------------------------------------------------------------------- */
10570
10577#define SMC_PMPROT_AVLLS_MASK (0x2U)
10578#define SMC_PMPROT_AVLLS_SHIFT (1U)
10579#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
10580#define SMC_PMPROT_ALLS_MASK (0x8U)
10581#define SMC_PMPROT_ALLS_SHIFT (3U)
10582#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
10583#define SMC_PMPROT_AVLP_MASK (0x20U)
10584#define SMC_PMPROT_AVLP_SHIFT (5U)
10585#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
10586
10588#define SMC_PMCTRL_STOPM_MASK (0x7U)
10589#define SMC_PMCTRL_STOPM_SHIFT (0U)
10590#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
10591#define SMC_PMCTRL_STOPA_MASK (0x8U)
10592#define SMC_PMCTRL_STOPA_SHIFT (3U)
10593#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
10594#define SMC_PMCTRL_RUNM_MASK (0x60U)
10595#define SMC_PMCTRL_RUNM_SHIFT (5U)
10596#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
10597#define SMC_PMCTRL_LPWUI_MASK (0x80U)
10598#define SMC_PMCTRL_LPWUI_SHIFT (7U)
10599#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
10600
10602#define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
10603#define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
10604#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
10605#define SMC_VLLSCTRL_RAM2PO_MASK (0x10U)
10606#define SMC_VLLSCTRL_RAM2PO_SHIFT (4U)
10607#define SMC_VLLSCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_RAM2PO_SHIFT)) & SMC_VLLSCTRL_RAM2PO_MASK)
10608
10610#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
10611#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
10612#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
10613
10614
10617 /* end of group SMC_Register_Masks */
10618
10619
10620/* SMC - Peripheral instance base addresses */
10622#define SMC_BASE (0x4007E000u)
10624#define SMC ((SMC_Type *)SMC_BASE)
10626#define SMC_BASE_ADDRS { SMC_BASE }
10628#define SMC_BASE_PTRS { SMC }
10629
10632 /* end of group SMC_Peripheral_Access_Layer */
10633
10634
10635/* ----------------------------------------------------------------------------
10636 -- SPI Peripheral Access Layer
10637 ---------------------------------------------------------------------------- */
10638
10645typedef struct {
10646 __IO uint32_t MCR;
10647 uint8_t RESERVED_0[4];
10648 __IO uint32_t TCR;
10649 union { /* offset: 0xC */
10650 __IO uint32_t CTAR[2];
10651 __IO uint32_t CTAR_SLAVE[1];
10652 };
10653 uint8_t RESERVED_1[24];
10654 __IO uint32_t SR;
10655 __IO uint32_t RSER;
10656 union { /* offset: 0x34 */
10657 __IO uint32_t PUSHR;
10658 __IO uint32_t PUSHR_SLAVE;
10659 };
10660 __I uint32_t POPR;
10661 __I uint32_t TXFR0;
10662 __I uint32_t TXFR1;
10663 __I uint32_t TXFR2;
10664 __I uint32_t TXFR3;
10665 uint8_t RESERVED_2[48];
10666 __I uint32_t RXFR0;
10667 __I uint32_t RXFR1;
10668 __I uint32_t RXFR2;
10669 __I uint32_t RXFR3;
10670} SPI_Type;
10671
10672/* ----------------------------------------------------------------------------
10673 -- SPI Register Masks
10674 ---------------------------------------------------------------------------- */
10675
10682#define SPI_MCR_HALT_MASK (0x1U)
10683#define SPI_MCR_HALT_SHIFT (0U)
10684#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
10685#define SPI_MCR_SMPL_PT_MASK (0x300U)
10686#define SPI_MCR_SMPL_PT_SHIFT (8U)
10687#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
10688#define SPI_MCR_CLR_RXF_MASK (0x400U)
10689#define SPI_MCR_CLR_RXF_SHIFT (10U)
10690#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
10691#define SPI_MCR_CLR_TXF_MASK (0x800U)
10692#define SPI_MCR_CLR_TXF_SHIFT (11U)
10693#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
10694#define SPI_MCR_DIS_RXF_MASK (0x1000U)
10695#define SPI_MCR_DIS_RXF_SHIFT (12U)
10696#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
10697#define SPI_MCR_DIS_TXF_MASK (0x2000U)
10698#define SPI_MCR_DIS_TXF_SHIFT (13U)
10699#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
10700#define SPI_MCR_MDIS_MASK (0x4000U)
10701#define SPI_MCR_MDIS_SHIFT (14U)
10702#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
10703#define SPI_MCR_DOZE_MASK (0x8000U)
10704#define SPI_MCR_DOZE_SHIFT (15U)
10705#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
10706#define SPI_MCR_PCSIS_MASK (0x3F0000U)
10707#define SPI_MCR_PCSIS_SHIFT (16U)
10708#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
10709#define SPI_MCR_ROOE_MASK (0x1000000U)
10710#define SPI_MCR_ROOE_SHIFT (24U)
10711#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
10712#define SPI_MCR_PCSSE_MASK (0x2000000U)
10713#define SPI_MCR_PCSSE_SHIFT (25U)
10714#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
10715#define SPI_MCR_MTFE_MASK (0x4000000U)
10716#define SPI_MCR_MTFE_SHIFT (26U)
10717#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
10718#define SPI_MCR_FRZ_MASK (0x8000000U)
10719#define SPI_MCR_FRZ_SHIFT (27U)
10720#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
10721#define SPI_MCR_DCONF_MASK (0x30000000U)
10722#define SPI_MCR_DCONF_SHIFT (28U)
10723#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
10724#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
10725#define SPI_MCR_CONT_SCKE_SHIFT (30U)
10726#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
10727#define SPI_MCR_MSTR_MASK (0x80000000U)
10728#define SPI_MCR_MSTR_SHIFT (31U)
10729#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
10730
10732#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
10733#define SPI_TCR_SPI_TCNT_SHIFT (16U)
10734#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
10735
10737#define SPI_CTAR_BR_MASK (0xFU)
10738#define SPI_CTAR_BR_SHIFT (0U)
10739#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
10740#define SPI_CTAR_DT_MASK (0xF0U)
10741#define SPI_CTAR_DT_SHIFT (4U)
10742#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
10743#define SPI_CTAR_ASC_MASK (0xF00U)
10744#define SPI_CTAR_ASC_SHIFT (8U)
10745#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
10746#define SPI_CTAR_CSSCK_MASK (0xF000U)
10747#define SPI_CTAR_CSSCK_SHIFT (12U)
10748#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
10749#define SPI_CTAR_PBR_MASK (0x30000U)
10750#define SPI_CTAR_PBR_SHIFT (16U)
10751#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
10752#define SPI_CTAR_PDT_MASK (0xC0000U)
10753#define SPI_CTAR_PDT_SHIFT (18U)
10754#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
10755#define SPI_CTAR_PASC_MASK (0x300000U)
10756#define SPI_CTAR_PASC_SHIFT (20U)
10757#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
10758#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
10759#define SPI_CTAR_PCSSCK_SHIFT (22U)
10760#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
10761#define SPI_CTAR_LSBFE_MASK (0x1000000U)
10762#define SPI_CTAR_LSBFE_SHIFT (24U)
10763#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
10764#define SPI_CTAR_CPHA_MASK (0x2000000U)
10765#define SPI_CTAR_CPHA_SHIFT (25U)
10766#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
10767#define SPI_CTAR_CPOL_MASK (0x4000000U)
10768#define SPI_CTAR_CPOL_SHIFT (26U)
10769#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
10770#define SPI_CTAR_FMSZ_MASK (0x78000000U)
10771#define SPI_CTAR_FMSZ_SHIFT (27U)
10772#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
10773#define SPI_CTAR_DBR_MASK (0x80000000U)
10774#define SPI_CTAR_DBR_SHIFT (31U)
10775#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
10776
10777/* The count of SPI_CTAR */
10778#define SPI_CTAR_COUNT (2U)
10779
10781#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
10782#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
10783#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
10784#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
10785#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
10786#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
10787#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
10788#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
10789#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
10790
10791/* The count of SPI_CTAR_SLAVE */
10792#define SPI_CTAR_SLAVE_COUNT (1U)
10793
10795#define SPI_SR_POPNXTPTR_MASK (0xFU)
10796#define SPI_SR_POPNXTPTR_SHIFT (0U)
10797#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
10798#define SPI_SR_RXCTR_MASK (0xF0U)
10799#define SPI_SR_RXCTR_SHIFT (4U)
10800#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
10801#define SPI_SR_TXNXTPTR_MASK (0xF00U)
10802#define SPI_SR_TXNXTPTR_SHIFT (8U)
10803#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
10804#define SPI_SR_TXCTR_MASK (0xF000U)
10805#define SPI_SR_TXCTR_SHIFT (12U)
10806#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
10807#define SPI_SR_RFDF_MASK (0x20000U)
10808#define SPI_SR_RFDF_SHIFT (17U)
10809#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
10810#define SPI_SR_RFOF_MASK (0x80000U)
10811#define SPI_SR_RFOF_SHIFT (19U)
10812#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
10813#define SPI_SR_TFFF_MASK (0x2000000U)
10814#define SPI_SR_TFFF_SHIFT (25U)
10815#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
10816#define SPI_SR_TFUF_MASK (0x8000000U)
10817#define SPI_SR_TFUF_SHIFT (27U)
10818#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
10819#define SPI_SR_EOQF_MASK (0x10000000U)
10820#define SPI_SR_EOQF_SHIFT (28U)
10821#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
10822#define SPI_SR_TXRXS_MASK (0x40000000U)
10823#define SPI_SR_TXRXS_SHIFT (30U)
10824#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
10825#define SPI_SR_TCF_MASK (0x80000000U)
10826#define SPI_SR_TCF_SHIFT (31U)
10827#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
10828
10830#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
10831#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
10832#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
10833#define SPI_RSER_RFDF_RE_MASK (0x20000U)
10834#define SPI_RSER_RFDF_RE_SHIFT (17U)
10835#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
10836#define SPI_RSER_RFOF_RE_MASK (0x80000U)
10837#define SPI_RSER_RFOF_RE_SHIFT (19U)
10838#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
10839#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
10840#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
10841#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
10842#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
10843#define SPI_RSER_TFFF_RE_SHIFT (25U)
10844#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
10845#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
10846#define SPI_RSER_TFUF_RE_SHIFT (27U)
10847#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
10848#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
10849#define SPI_RSER_EOQF_RE_SHIFT (28U)
10850#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
10851#define SPI_RSER_TCF_RE_MASK (0x80000000U)
10852#define SPI_RSER_TCF_RE_SHIFT (31U)
10853#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
10854
10856#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
10857#define SPI_PUSHR_TXDATA_SHIFT (0U)
10858#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
10859#define SPI_PUSHR_PCS_MASK (0x3F0000U)
10860#define SPI_PUSHR_PCS_SHIFT (16U)
10861#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
10862#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
10863#define SPI_PUSHR_CTCNT_SHIFT (26U)
10864#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
10865#define SPI_PUSHR_EOQ_MASK (0x8000000U)
10866#define SPI_PUSHR_EOQ_SHIFT (27U)
10867#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
10868#define SPI_PUSHR_CTAS_MASK (0x70000000U)
10869#define SPI_PUSHR_CTAS_SHIFT (28U)
10870#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
10871#define SPI_PUSHR_CONT_MASK (0x80000000U)
10872#define SPI_PUSHR_CONT_SHIFT (31U)
10873#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
10874
10876#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU)
10877#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
10878#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
10879
10881#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
10882#define SPI_POPR_RXDATA_SHIFT (0U)
10883#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
10884
10886#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
10887#define SPI_TXFR0_TXDATA_SHIFT (0U)
10888#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
10889#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
10890#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
10891#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
10892
10894#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
10895#define SPI_TXFR1_TXDATA_SHIFT (0U)
10896#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
10897#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
10898#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
10899#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
10900
10902#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
10903#define SPI_TXFR2_TXDATA_SHIFT (0U)
10904#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
10905#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
10906#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
10907#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
10908
10910#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
10911#define SPI_TXFR3_TXDATA_SHIFT (0U)
10912#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
10913#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
10914#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
10915#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
10916
10918#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
10919#define SPI_RXFR0_RXDATA_SHIFT (0U)
10920#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
10921
10923#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
10924#define SPI_RXFR1_RXDATA_SHIFT (0U)
10925#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
10926
10928#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
10929#define SPI_RXFR2_RXDATA_SHIFT (0U)
10930#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
10931
10933#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
10934#define SPI_RXFR3_RXDATA_SHIFT (0U)
10935#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
10936
10937
10940 /* end of group SPI_Register_Masks */
10941
10942
10943/* SPI - Peripheral instance base addresses */
10945#define SPI0_BASE (0x4002C000u)
10947#define SPI0 ((SPI_Type *)SPI0_BASE)
10949#define SPI1_BASE (0x4002D000u)
10951#define SPI1 ((SPI_Type *)SPI1_BASE)
10953#define SPI2_BASE (0x400AC000u)
10955#define SPI2 ((SPI_Type *)SPI2_BASE)
10957#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
10959#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
10961#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
10962
10965 /* end of group SPI_Peripheral_Access_Layer */
10966
10967
10968/* ----------------------------------------------------------------------------
10969 -- SYSMPU Peripheral Access Layer
10970 ---------------------------------------------------------------------------- */
10971
10978typedef struct {
10979 __IO uint32_t CESR;
10980 uint8_t RESERVED_0[12];
10981 struct { /* offset: 0x10, array step: 0x8 */
10982 __I uint32_t EAR;
10983 __I uint32_t EDR;
10984 } SP[5];
10985 uint8_t RESERVED_1[968];
10986 __IO uint32_t WORD[12][4];
10987 uint8_t RESERVED_2[832];
10988 __IO uint32_t RGDAAC[12];
10989} SYSMPU_Type;
10990
10991/* ----------------------------------------------------------------------------
10992 -- SYSMPU Register Masks
10993 ---------------------------------------------------------------------------- */
10994
11001#define SYSMPU_CESR_VLD_MASK (0x1U)
11002#define SYSMPU_CESR_VLD_SHIFT (0U)
11003#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
11004#define SYSMPU_CESR_NRGD_MASK (0xF00U)
11005#define SYSMPU_CESR_NRGD_SHIFT (8U)
11006#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
11007#define SYSMPU_CESR_NSP_MASK (0xF000U)
11008#define SYSMPU_CESR_NSP_SHIFT (12U)
11009#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
11010#define SYSMPU_CESR_HRL_MASK (0xF0000U)
11011#define SYSMPU_CESR_HRL_SHIFT (16U)
11012#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
11013#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
11014#define SYSMPU_CESR_SPERR_SHIFT (27U)
11015#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
11016
11018#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
11019#define SYSMPU_EAR_EADDR_SHIFT (0U)
11020#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
11021
11022/* The count of SYSMPU_EAR */
11023#define SYSMPU_EAR_COUNT (5U)
11024
11026#define SYSMPU_EDR_ERW_MASK (0x1U)
11027#define SYSMPU_EDR_ERW_SHIFT (0U)
11028#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
11029#define SYSMPU_EDR_EATTR_MASK (0xEU)
11030#define SYSMPU_EDR_EATTR_SHIFT (1U)
11031#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
11032#define SYSMPU_EDR_EMN_MASK (0xF0U)
11033#define SYSMPU_EDR_EMN_SHIFT (4U)
11034#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
11035#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
11036#define SYSMPU_EDR_EACD_SHIFT (16U)
11037#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
11038
11039/* The count of SYSMPU_EDR */
11040#define SYSMPU_EDR_COUNT (5U)
11041
11043#define SYSMPU_WORD_M0UM_MASK (0x7U)
11044#define SYSMPU_WORD_M0UM_SHIFT (0U)
11045#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
11046#define SYSMPU_WORD_VLD_MASK (0x1U)
11047#define SYSMPU_WORD_VLD_SHIFT (0U)
11048#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
11049#define SYSMPU_WORD_M0SM_MASK (0x18U)
11050#define SYSMPU_WORD_M0SM_SHIFT (3U)
11051#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
11052#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
11053#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
11054#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
11055#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
11056#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
11057#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
11058#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
11059#define SYSMPU_WORD_M1UM_SHIFT (6U)
11060#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
11061#define SYSMPU_WORD_M1SM_MASK (0x600U)
11062#define SYSMPU_WORD_M1SM_SHIFT (9U)
11063#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
11064#define SYSMPU_WORD_M2UM_MASK (0x7000U)
11065#define SYSMPU_WORD_M2UM_SHIFT (12U)
11066#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
11067#define SYSMPU_WORD_M2SM_MASK (0x18000U)
11068#define SYSMPU_WORD_M2SM_SHIFT (15U)
11069#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
11070#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
11071#define SYSMPU_WORD_M3UM_SHIFT (18U)
11072#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
11073#define SYSMPU_WORD_M3SM_MASK (0x600000U)
11074#define SYSMPU_WORD_M3SM_SHIFT (21U)
11075#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
11076#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
11077#define SYSMPU_WORD_M4WE_SHIFT (24U)
11078#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
11079#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
11080#define SYSMPU_WORD_M4RE_SHIFT (25U)
11081#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
11082#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
11083#define SYSMPU_WORD_M5WE_SHIFT (26U)
11084#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
11085#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
11086#define SYSMPU_WORD_M5RE_SHIFT (27U)
11087#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
11088#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
11089#define SYSMPU_WORD_M6WE_SHIFT (28U)
11090#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
11091#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
11092#define SYSMPU_WORD_M6RE_SHIFT (29U)
11093#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
11094#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
11095#define SYSMPU_WORD_M7WE_SHIFT (30U)
11096#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
11097#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
11098#define SYSMPU_WORD_M7RE_SHIFT (31U)
11099#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
11100
11101/* The count of SYSMPU_WORD */
11102#define SYSMPU_WORD_COUNT (12U)
11103
11104/* The count of SYSMPU_WORD */
11105#define SYSMPU_WORD_COUNT2 (4U)
11106
11108#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
11109#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
11110#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
11111#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
11112#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
11113#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
11114#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
11115#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
11116#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
11117#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
11118#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
11119#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
11120#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
11121#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
11122#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
11123#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
11124#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
11125#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
11126#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
11127#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
11128#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
11129#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
11130#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
11131#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
11132#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
11133#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
11134#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
11135#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
11136#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
11137#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
11138#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
11139#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
11140#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
11141#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
11142#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
11143#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
11144#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
11145#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
11146#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
11147#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
11148#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
11149#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
11150#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
11151#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
11152#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
11153#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
11154#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
11155#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
11156
11157/* The count of SYSMPU_RGDAAC */
11158#define SYSMPU_RGDAAC_COUNT (12U)
11159
11160
11163 /* end of group SYSMPU_Register_Masks */
11164
11165
11166/* SYSMPU - Peripheral instance base addresses */
11168#define SYSMPU_BASE (0x4000D000u)
11170#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
11172#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
11174#define SYSMPU_BASE_PTRS { SYSMPU }
11175
11178 /* end of group SYSMPU_Peripheral_Access_Layer */
11179
11180
11181/* ----------------------------------------------------------------------------
11182 -- TSI Peripheral Access Layer
11183 ---------------------------------------------------------------------------- */
11184
11191typedef struct {
11192 __IO uint32_t GENCS;
11193 __IO uint32_t SCANC;
11194 __IO uint32_t PEN;
11195 __I uint32_t WUCNTR;
11196 uint8_t RESERVED_0[240];
11197 __I uint32_t CNTR1;
11198 __I uint32_t CNTR3;
11199 __I uint32_t CNTR5;
11200 __I uint32_t CNTR7;
11201 __I uint32_t CNTR9;
11202 __I uint32_t CNTR11;
11203 __I uint32_t CNTR13;
11204 __I uint32_t CNTR15;
11205 __IO uint32_t THRESHOLD;
11206} TSI_Type;
11207
11208/* ----------------------------------------------------------------------------
11209 -- TSI Register Masks
11210 ---------------------------------------------------------------------------- */
11211
11218#define TSI_GENCS_STPE_MASK (0x1U)
11219#define TSI_GENCS_STPE_SHIFT (0U)
11220#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
11221#define TSI_GENCS_STM_MASK (0x2U)
11222#define TSI_GENCS_STM_SHIFT (1U)
11223#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
11224#define TSI_GENCS_ESOR_MASK (0x10U)
11225#define TSI_GENCS_ESOR_SHIFT (4U)
11226#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
11227#define TSI_GENCS_ERIE_MASK (0x20U)
11228#define TSI_GENCS_ERIE_SHIFT (5U)
11229#define TSI_GENCS_ERIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ERIE_SHIFT)) & TSI_GENCS_ERIE_MASK)
11230#define TSI_GENCS_TSIIE_MASK (0x40U)
11231#define TSI_GENCS_TSIIE_SHIFT (6U)
11232#define TSI_GENCS_TSIIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIE_SHIFT)) & TSI_GENCS_TSIIE_MASK)
11233#define TSI_GENCS_TSIEN_MASK (0x80U)
11234#define TSI_GENCS_TSIEN_SHIFT (7U)
11235#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
11236#define TSI_GENCS_SWTS_MASK (0x100U)
11237#define TSI_GENCS_SWTS_SHIFT (8U)
11238#define TSI_GENCS_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK)
11239#define TSI_GENCS_SCNIP_MASK (0x200U)
11240#define TSI_GENCS_SCNIP_SHIFT (9U)
11241#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
11242#define TSI_GENCS_OVRF_MASK (0x1000U)
11243#define TSI_GENCS_OVRF_SHIFT (12U)
11244#define TSI_GENCS_OVRF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OVRF_SHIFT)) & TSI_GENCS_OVRF_MASK)
11245#define TSI_GENCS_EXTERF_MASK (0x2000U)
11246#define TSI_GENCS_EXTERF_SHIFT (13U)
11247#define TSI_GENCS_EXTERF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTERF_SHIFT)) & TSI_GENCS_EXTERF_MASK)
11248#define TSI_GENCS_OUTRGF_MASK (0x4000U)
11249#define TSI_GENCS_OUTRGF_SHIFT (14U)
11250#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
11251#define TSI_GENCS_EOSF_MASK (0x8000U)
11252#define TSI_GENCS_EOSF_SHIFT (15U)
11253#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
11254#define TSI_GENCS_PS_MASK (0x70000U)
11255#define TSI_GENCS_PS_SHIFT (16U)
11256#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
11257#define TSI_GENCS_NSCN_MASK (0xF80000U)
11258#define TSI_GENCS_NSCN_SHIFT (19U)
11259#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
11260#define TSI_GENCS_LPSCNITV_MASK (0xF000000U)
11261#define TSI_GENCS_LPSCNITV_SHIFT (24U)
11262#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPSCNITV_SHIFT)) & TSI_GENCS_LPSCNITV_MASK)
11263#define TSI_GENCS_LPCLKS_MASK (0x10000000U)
11264#define TSI_GENCS_LPCLKS_SHIFT (28U)
11265#define TSI_GENCS_LPCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPCLKS_SHIFT)) & TSI_GENCS_LPCLKS_MASK)
11266
11268#define TSI_SCANC_AMPSC_MASK (0x7U)
11269#define TSI_SCANC_AMPSC_SHIFT (0U)
11270#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMPSC_SHIFT)) & TSI_SCANC_AMPSC_MASK)
11271#define TSI_SCANC_AMCLKS_MASK (0x18U)
11272#define TSI_SCANC_AMCLKS_SHIFT (3U)
11273#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMCLKS_SHIFT)) & TSI_SCANC_AMCLKS_MASK)
11274#define TSI_SCANC_SMOD_MASK (0xFF00U)
11275#define TSI_SCANC_SMOD_SHIFT (8U)
11276#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_SMOD_SHIFT)) & TSI_SCANC_SMOD_MASK)
11277#define TSI_SCANC_EXTCHRG_MASK (0xF0000U)
11278#define TSI_SCANC_EXTCHRG_SHIFT (16U)
11279#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_EXTCHRG_SHIFT)) & TSI_SCANC_EXTCHRG_MASK)
11280#define TSI_SCANC_REFCHRG_MASK (0xF000000U)
11281#define TSI_SCANC_REFCHRG_SHIFT (24U)
11282#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_REFCHRG_SHIFT)) & TSI_SCANC_REFCHRG_MASK)
11283
11285#define TSI_PEN_PEN0_MASK (0x1U)
11286#define TSI_PEN_PEN0_SHIFT (0U)
11287#define TSI_PEN_PEN0(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN0_SHIFT)) & TSI_PEN_PEN0_MASK)
11288#define TSI_PEN_PEN1_MASK (0x2U)
11289#define TSI_PEN_PEN1_SHIFT (1U)
11290#define TSI_PEN_PEN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN1_SHIFT)) & TSI_PEN_PEN1_MASK)
11291#define TSI_PEN_PEN2_MASK (0x4U)
11292#define TSI_PEN_PEN2_SHIFT (2U)
11293#define TSI_PEN_PEN2(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN2_SHIFT)) & TSI_PEN_PEN2_MASK)
11294#define TSI_PEN_PEN3_MASK (0x8U)
11295#define TSI_PEN_PEN3_SHIFT (3U)
11296#define TSI_PEN_PEN3(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN3_SHIFT)) & TSI_PEN_PEN3_MASK)
11297#define TSI_PEN_PEN4_MASK (0x10U)
11298#define TSI_PEN_PEN4_SHIFT (4U)
11299#define TSI_PEN_PEN4(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN4_SHIFT)) & TSI_PEN_PEN4_MASK)
11300#define TSI_PEN_PEN5_MASK (0x20U)
11301#define TSI_PEN_PEN5_SHIFT (5U)
11302#define TSI_PEN_PEN5(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN5_SHIFT)) & TSI_PEN_PEN5_MASK)
11303#define TSI_PEN_PEN6_MASK (0x40U)
11304#define TSI_PEN_PEN6_SHIFT (6U)
11305#define TSI_PEN_PEN6(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN6_SHIFT)) & TSI_PEN_PEN6_MASK)
11306#define TSI_PEN_PEN7_MASK (0x80U)
11307#define TSI_PEN_PEN7_SHIFT (7U)
11308#define TSI_PEN_PEN7(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN7_SHIFT)) & TSI_PEN_PEN7_MASK)
11309#define TSI_PEN_PEN8_MASK (0x100U)
11310#define TSI_PEN_PEN8_SHIFT (8U)
11311#define TSI_PEN_PEN8(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN8_SHIFT)) & TSI_PEN_PEN8_MASK)
11312#define TSI_PEN_PEN9_MASK (0x200U)
11313#define TSI_PEN_PEN9_SHIFT (9U)
11314#define TSI_PEN_PEN9(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN9_SHIFT)) & TSI_PEN_PEN9_MASK)
11315#define TSI_PEN_PEN10_MASK (0x400U)
11316#define TSI_PEN_PEN10_SHIFT (10U)
11317#define TSI_PEN_PEN10(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN10_SHIFT)) & TSI_PEN_PEN10_MASK)
11318#define TSI_PEN_PEN11_MASK (0x800U)
11319#define TSI_PEN_PEN11_SHIFT (11U)
11320#define TSI_PEN_PEN11(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN11_SHIFT)) & TSI_PEN_PEN11_MASK)
11321#define TSI_PEN_PEN12_MASK (0x1000U)
11322#define TSI_PEN_PEN12_SHIFT (12U)
11323#define TSI_PEN_PEN12(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN12_SHIFT)) & TSI_PEN_PEN12_MASK)
11324#define TSI_PEN_PEN13_MASK (0x2000U)
11325#define TSI_PEN_PEN13_SHIFT (13U)
11326#define TSI_PEN_PEN13(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN13_SHIFT)) & TSI_PEN_PEN13_MASK)
11327#define TSI_PEN_PEN14_MASK (0x4000U)
11328#define TSI_PEN_PEN14_SHIFT (14U)
11329#define TSI_PEN_PEN14(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN14_SHIFT)) & TSI_PEN_PEN14_MASK)
11330#define TSI_PEN_PEN15_MASK (0x8000U)
11331#define TSI_PEN_PEN15_SHIFT (15U)
11332#define TSI_PEN_PEN15(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN15_SHIFT)) & TSI_PEN_PEN15_MASK)
11333#define TSI_PEN_LPSP_MASK (0xF0000U)
11334#define TSI_PEN_LPSP_SHIFT (16U)
11335#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_LPSP_SHIFT)) & TSI_PEN_LPSP_MASK)
11336
11338#define TSI_WUCNTR_WUCNT_MASK (0xFFFFU)
11339#define TSI_WUCNTR_WUCNT_SHIFT (0U)
11340#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_WUCNTR_WUCNT_SHIFT)) & TSI_WUCNTR_WUCNT_MASK)
11341
11343#define TSI_CNTR1_CTN1_MASK (0xFFFFU)
11344#define TSI_CNTR1_CTN1_SHIFT (0U)
11345#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN1_SHIFT)) & TSI_CNTR1_CTN1_MASK)
11346#define TSI_CNTR1_CTN_MASK (0xFFFF0000U)
11347#define TSI_CNTR1_CTN_SHIFT (16U)
11348#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN_SHIFT)) & TSI_CNTR1_CTN_MASK)
11349
11351#define TSI_CNTR3_CTN1_MASK (0xFFFFU)
11352#define TSI_CNTR3_CTN1_SHIFT (0U)
11353#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN1_SHIFT)) & TSI_CNTR3_CTN1_MASK)
11354#define TSI_CNTR3_CTN_MASK (0xFFFF0000U)
11355#define TSI_CNTR3_CTN_SHIFT (16U)
11356#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN_SHIFT)) & TSI_CNTR3_CTN_MASK)
11357
11359#define TSI_CNTR5_CTN1_MASK (0xFFFFU)
11360#define TSI_CNTR5_CTN1_SHIFT (0U)
11361#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN1_SHIFT)) & TSI_CNTR5_CTN1_MASK)
11362#define TSI_CNTR5_CTN_MASK (0xFFFF0000U)
11363#define TSI_CNTR5_CTN_SHIFT (16U)
11364#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN_SHIFT)) & TSI_CNTR5_CTN_MASK)
11365
11367#define TSI_CNTR7_CTN1_MASK (0xFFFFU)
11368#define TSI_CNTR7_CTN1_SHIFT (0U)
11369#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN1_SHIFT)) & TSI_CNTR7_CTN1_MASK)
11370#define TSI_CNTR7_CTN_MASK (0xFFFF0000U)
11371#define TSI_CNTR7_CTN_SHIFT (16U)
11372#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN_SHIFT)) & TSI_CNTR7_CTN_MASK)
11373
11375#define TSI_CNTR9_CTN1_MASK (0xFFFFU)
11376#define TSI_CNTR9_CTN1_SHIFT (0U)
11377#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN1_SHIFT)) & TSI_CNTR9_CTN1_MASK)
11378#define TSI_CNTR9_CTN_MASK (0xFFFF0000U)
11379#define TSI_CNTR9_CTN_SHIFT (16U)
11380#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN_SHIFT)) & TSI_CNTR9_CTN_MASK)
11381
11383#define TSI_CNTR11_CTN1_MASK (0xFFFFU)
11384#define TSI_CNTR11_CTN1_SHIFT (0U)
11385#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN1_SHIFT)) & TSI_CNTR11_CTN1_MASK)
11386#define TSI_CNTR11_CTN_MASK (0xFFFF0000U)
11387#define TSI_CNTR11_CTN_SHIFT (16U)
11388#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN_SHIFT)) & TSI_CNTR11_CTN_MASK)
11389
11391#define TSI_CNTR13_CTN1_MASK (0xFFFFU)
11392#define TSI_CNTR13_CTN1_SHIFT (0U)
11393#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN1_SHIFT)) & TSI_CNTR13_CTN1_MASK)
11394#define TSI_CNTR13_CTN_MASK (0xFFFF0000U)
11395#define TSI_CNTR13_CTN_SHIFT (16U)
11396#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN_SHIFT)) & TSI_CNTR13_CTN_MASK)
11397
11399#define TSI_CNTR15_CTN1_MASK (0xFFFFU)
11400#define TSI_CNTR15_CTN1_SHIFT (0U)
11401#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN1_SHIFT)) & TSI_CNTR15_CTN1_MASK)
11402#define TSI_CNTR15_CTN_MASK (0xFFFF0000U)
11403#define TSI_CNTR15_CTN_SHIFT (16U)
11404#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN_SHIFT)) & TSI_CNTR15_CTN_MASK)
11405
11407#define TSI_THRESHOLD_HTHH_MASK (0xFFFFU)
11408#define TSI_THRESHOLD_HTHH_SHIFT (0U)
11409#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_HTHH_SHIFT)) & TSI_THRESHOLD_HTHH_MASK)
11410#define TSI_THRESHOLD_LTHH_MASK (0xFFFF0000U)
11411#define TSI_THRESHOLD_LTHH_SHIFT (16U)
11412#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_LTHH_SHIFT)) & TSI_THRESHOLD_LTHH_MASK)
11413
11414
11417 /* end of group TSI_Register_Masks */
11418
11419
11420/* TSI - Peripheral instance base addresses */
11422#define TSI0_BASE (0x40045000u)
11424#define TSI0 ((TSI_Type *)TSI0_BASE)
11426#define TSI_BASE_ADDRS { TSI0_BASE }
11428#define TSI_BASE_PTRS { TSI0 }
11430#define TSI_IRQS { TSI0_IRQn }
11431
11434 /* end of group TSI_Peripheral_Access_Layer */
11435
11436
11437/* ----------------------------------------------------------------------------
11438 -- UART Peripheral Access Layer
11439 ---------------------------------------------------------------------------- */
11440
11447typedef struct {
11448 __IO uint8_t BDH;
11449 __IO uint8_t BDL;
11450 __IO uint8_t C1;
11451 __IO uint8_t C2;
11452 __I uint8_t S1;
11453 __IO uint8_t S2;
11454 __IO uint8_t C3;
11455 __IO uint8_t D;
11456 __IO uint8_t MA1;
11457 __IO uint8_t MA2;
11458 __IO uint8_t C4;
11459 __IO uint8_t C5;
11460 __I uint8_t ED;
11461 __IO uint8_t MODEM;
11462 __IO uint8_t IR;
11463 uint8_t RESERVED_0[1];
11464 __IO uint8_t PFIFO;
11465 __IO uint8_t CFIFO;
11466 __IO uint8_t SFIFO;
11467 __IO uint8_t TWFIFO;
11468 __I uint8_t TCFIFO;
11469 __IO uint8_t RWFIFO;
11470 __I uint8_t RCFIFO;
11471 uint8_t RESERVED_1[1];
11472 __IO uint8_t C7816;
11473 __IO uint8_t IE7816;
11474 __IO uint8_t IS7816;
11475 union { /* offset: 0x1B */
11476 __IO uint8_t WP7816T0;
11477 __IO uint8_t WP7816T1;
11478 };
11479 __IO uint8_t WN7816;
11480 __IO uint8_t WF7816;
11481 __IO uint8_t ET7816;
11482 __IO uint8_t TL7816;
11483 uint8_t RESERVED_2[1];
11484 __IO uint8_t C6;
11485 __IO uint8_t PCTH;
11486 __IO uint8_t PCTL;
11487 __IO uint8_t B1T;
11488 __IO uint8_t SDTH;
11489 __IO uint8_t SDTL;
11490 __IO uint8_t PRE;
11491 __IO uint8_t TPL;
11492 __IO uint8_t IE;
11493 __IO uint8_t WB;
11494 __IO uint8_t S3;
11495 __IO uint8_t S4;
11496 __I uint8_t RPL;
11497 __I uint8_t RPREL;
11498 __IO uint8_t CPW;
11499 __IO uint8_t RIDT;
11500 __IO uint8_t TIDT;
11501} UART_Type;
11502
11503/* ----------------------------------------------------------------------------
11504 -- UART Register Masks
11505 ---------------------------------------------------------------------------- */
11506
11513#define UART_BDH_SBR_MASK (0x1FU)
11514#define UART_BDH_SBR_SHIFT (0U)
11515#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
11516#define UART_BDH_RXEDGIE_MASK (0x40U)
11517#define UART_BDH_RXEDGIE_SHIFT (6U)
11518#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
11519#define UART_BDH_LBKDIE_MASK (0x80U)
11520#define UART_BDH_LBKDIE_SHIFT (7U)
11521#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
11522
11524#define UART_BDL_SBR_MASK (0xFFU)
11525#define UART_BDL_SBR_SHIFT (0U)
11526#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
11527
11529#define UART_C1_PT_MASK (0x1U)
11530#define UART_C1_PT_SHIFT (0U)
11531#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
11532#define UART_C1_PE_MASK (0x2U)
11533#define UART_C1_PE_SHIFT (1U)
11534#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
11535#define UART_C1_ILT_MASK (0x4U)
11536#define UART_C1_ILT_SHIFT (2U)
11537#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
11538#define UART_C1_WAKE_MASK (0x8U)
11539#define UART_C1_WAKE_SHIFT (3U)
11540#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
11541#define UART_C1_M_MASK (0x10U)
11542#define UART_C1_M_SHIFT (4U)
11543#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
11544#define UART_C1_RSRC_MASK (0x20U)
11545#define UART_C1_RSRC_SHIFT (5U)
11546#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
11547#define UART_C1_UARTSWAI_MASK (0x40U)
11548#define UART_C1_UARTSWAI_SHIFT (6U)
11549#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
11550#define UART_C1_LOOPS_MASK (0x80U)
11551#define UART_C1_LOOPS_SHIFT (7U)
11552#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
11553
11555#define UART_C2_SBK_MASK (0x1U)
11556#define UART_C2_SBK_SHIFT (0U)
11557#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
11558#define UART_C2_RWU_MASK (0x2U)
11559#define UART_C2_RWU_SHIFT (1U)
11560#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
11561#define UART_C2_RE_MASK (0x4U)
11562#define UART_C2_RE_SHIFT (2U)
11563#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
11564#define UART_C2_TE_MASK (0x8U)
11565#define UART_C2_TE_SHIFT (3U)
11566#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
11567#define UART_C2_ILIE_MASK (0x10U)
11568#define UART_C2_ILIE_SHIFT (4U)
11569#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
11570#define UART_C2_RIE_MASK (0x20U)
11571#define UART_C2_RIE_SHIFT (5U)
11572#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
11573#define UART_C2_TCIE_MASK (0x40U)
11574#define UART_C2_TCIE_SHIFT (6U)
11575#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
11576#define UART_C2_TIE_MASK (0x80U)
11577#define UART_C2_TIE_SHIFT (7U)
11578#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
11579
11581#define UART_S1_PF_MASK (0x1U)
11582#define UART_S1_PF_SHIFT (0U)
11583#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
11584#define UART_S1_FE_MASK (0x2U)
11585#define UART_S1_FE_SHIFT (1U)
11586#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
11587#define UART_S1_NF_MASK (0x4U)
11588#define UART_S1_NF_SHIFT (2U)
11589#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
11590#define UART_S1_OR_MASK (0x8U)
11591#define UART_S1_OR_SHIFT (3U)
11592#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
11593#define UART_S1_IDLE_MASK (0x10U)
11594#define UART_S1_IDLE_SHIFT (4U)
11595#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
11596#define UART_S1_RDRF_MASK (0x20U)
11597#define UART_S1_RDRF_SHIFT (5U)
11598#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
11599#define UART_S1_TC_MASK (0x40U)
11600#define UART_S1_TC_SHIFT (6U)
11601#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
11602#define UART_S1_TDRE_MASK (0x80U)
11603#define UART_S1_TDRE_SHIFT (7U)
11604#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
11605
11607#define UART_S2_RAF_MASK (0x1U)
11608#define UART_S2_RAF_SHIFT (0U)
11609#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
11610#define UART_S2_LBKDE_MASK (0x2U)
11611#define UART_S2_LBKDE_SHIFT (1U)
11612#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
11613#define UART_S2_BRK13_MASK (0x4U)
11614#define UART_S2_BRK13_SHIFT (2U)
11615#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
11616#define UART_S2_RWUID_MASK (0x8U)
11617#define UART_S2_RWUID_SHIFT (3U)
11618#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
11619#define UART_S2_RXINV_MASK (0x10U)
11620#define UART_S2_RXINV_SHIFT (4U)
11621#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
11622#define UART_S2_MSBF_MASK (0x20U)
11623#define UART_S2_MSBF_SHIFT (5U)
11624#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
11625#define UART_S2_RXEDGIF_MASK (0x40U)
11626#define UART_S2_RXEDGIF_SHIFT (6U)
11627#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
11628#define UART_S2_LBKDIF_MASK (0x80U)
11629#define UART_S2_LBKDIF_SHIFT (7U)
11630#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
11631
11633#define UART_C3_PEIE_MASK (0x1U)
11634#define UART_C3_PEIE_SHIFT (0U)
11635#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
11636#define UART_C3_FEIE_MASK (0x2U)
11637#define UART_C3_FEIE_SHIFT (1U)
11638#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
11639#define UART_C3_NEIE_MASK (0x4U)
11640#define UART_C3_NEIE_SHIFT (2U)
11641#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
11642#define UART_C3_ORIE_MASK (0x8U)
11643#define UART_C3_ORIE_SHIFT (3U)
11644#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
11645#define UART_C3_TXINV_MASK (0x10U)
11646#define UART_C3_TXINV_SHIFT (4U)
11647#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
11648#define UART_C3_TXDIR_MASK (0x20U)
11649#define UART_C3_TXDIR_SHIFT (5U)
11650#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
11651#define UART_C3_T8_MASK (0x40U)
11652#define UART_C3_T8_SHIFT (6U)
11653#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
11654#define UART_C3_R8_MASK (0x80U)
11655#define UART_C3_R8_SHIFT (7U)
11656#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
11657
11659#define UART_D_RT_MASK (0xFFU)
11660#define UART_D_RT_SHIFT (0U)
11661#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
11662
11664#define UART_MA1_MA_MASK (0xFFU)
11665#define UART_MA1_MA_SHIFT (0U)
11666#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
11667
11669#define UART_MA2_MA_MASK (0xFFU)
11670#define UART_MA2_MA_SHIFT (0U)
11671#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
11672
11674#define UART_C4_BRFA_MASK (0x1FU)
11675#define UART_C4_BRFA_SHIFT (0U)
11676#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
11677#define UART_C4_M10_MASK (0x20U)
11678#define UART_C4_M10_SHIFT (5U)
11679#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
11680#define UART_C4_MAEN2_MASK (0x40U)
11681#define UART_C4_MAEN2_SHIFT (6U)
11682#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
11683#define UART_C4_MAEN1_MASK (0x80U)
11684#define UART_C4_MAEN1_SHIFT (7U)
11685#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
11686
11688#define UART_C5_RDMAS_MASK (0x20U)
11689#define UART_C5_RDMAS_SHIFT (5U)
11690#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
11691#define UART_C5_TDMAS_MASK (0x80U)
11692#define UART_C5_TDMAS_SHIFT (7U)
11693#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
11694
11696#define UART_ED_PARITYE_MASK (0x40U)
11697#define UART_ED_PARITYE_SHIFT (6U)
11698#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
11699#define UART_ED_NOISY_MASK (0x80U)
11700#define UART_ED_NOISY_SHIFT (7U)
11701#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
11702
11704#define UART_MODEM_TXCTSE_MASK (0x1U)
11705#define UART_MODEM_TXCTSE_SHIFT (0U)
11706#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
11707#define UART_MODEM_TXRTSE_MASK (0x2U)
11708#define UART_MODEM_TXRTSE_SHIFT (1U)
11709#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
11710#define UART_MODEM_TXRTSPOL_MASK (0x4U)
11711#define UART_MODEM_TXRTSPOL_SHIFT (2U)
11712#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
11713#define UART_MODEM_RXRTSE_MASK (0x8U)
11714#define UART_MODEM_RXRTSE_SHIFT (3U)
11715#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
11716
11718#define UART_IR_TNP_MASK (0x3U)
11719#define UART_IR_TNP_SHIFT (0U)
11720#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
11721#define UART_IR_IREN_MASK (0x4U)
11722#define UART_IR_IREN_SHIFT (2U)
11723#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
11724
11726#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
11727#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
11728#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
11729#define UART_PFIFO_RXFE_MASK (0x8U)
11730#define UART_PFIFO_RXFE_SHIFT (3U)
11731#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
11732#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
11733#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
11734#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
11735#define UART_PFIFO_TXFE_MASK (0x80U)
11736#define UART_PFIFO_TXFE_SHIFT (7U)
11737#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
11738
11740#define UART_CFIFO_RXUFE_MASK (0x1U)
11741#define UART_CFIFO_RXUFE_SHIFT (0U)
11742#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
11743#define UART_CFIFO_TXOFE_MASK (0x2U)
11744#define UART_CFIFO_TXOFE_SHIFT (1U)
11745#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
11746#define UART_CFIFO_RXOFE_MASK (0x4U)
11747#define UART_CFIFO_RXOFE_SHIFT (2U)
11748#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
11749#define UART_CFIFO_RXFLUSH_MASK (0x40U)
11750#define UART_CFIFO_RXFLUSH_SHIFT (6U)
11751#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
11752#define UART_CFIFO_TXFLUSH_MASK (0x80U)
11753#define UART_CFIFO_TXFLUSH_SHIFT (7U)
11754#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
11755
11757#define UART_SFIFO_RXUF_MASK (0x1U)
11758#define UART_SFIFO_RXUF_SHIFT (0U)
11759#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
11760#define UART_SFIFO_TXOF_MASK (0x2U)
11761#define UART_SFIFO_TXOF_SHIFT (1U)
11762#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
11763#define UART_SFIFO_RXOF_MASK (0x4U)
11764#define UART_SFIFO_RXOF_SHIFT (2U)
11765#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
11766#define UART_SFIFO_RXEMPT_MASK (0x40U)
11767#define UART_SFIFO_RXEMPT_SHIFT (6U)
11768#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
11769#define UART_SFIFO_TXEMPT_MASK (0x80U)
11770#define UART_SFIFO_TXEMPT_SHIFT (7U)
11771#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
11772
11774#define UART_TWFIFO_TXWATER_MASK (0xFFU)
11775#define UART_TWFIFO_TXWATER_SHIFT (0U)
11776#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
11777
11779#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
11780#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
11781#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
11782
11784#define UART_RWFIFO_RXWATER_MASK (0xFFU)
11785#define UART_RWFIFO_RXWATER_SHIFT (0U)
11786#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
11787
11789#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
11790#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
11791#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
11792
11794#define UART_C7816_ISO_7816E_MASK (0x1U)
11795#define UART_C7816_ISO_7816E_SHIFT (0U)
11796#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
11797#define UART_C7816_TTYPE_MASK (0x2U)
11798#define UART_C7816_TTYPE_SHIFT (1U)
11799#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
11800#define UART_C7816_INIT_MASK (0x4U)
11801#define UART_C7816_INIT_SHIFT (2U)
11802#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
11803#define UART_C7816_ANACK_MASK (0x8U)
11804#define UART_C7816_ANACK_SHIFT (3U)
11805#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
11806#define UART_C7816_ONACK_MASK (0x10U)
11807#define UART_C7816_ONACK_SHIFT (4U)
11808#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
11809
11811#define UART_IE7816_RXTE_MASK (0x1U)
11812#define UART_IE7816_RXTE_SHIFT (0U)
11813#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
11814#define UART_IE7816_TXTE_MASK (0x2U)
11815#define UART_IE7816_TXTE_SHIFT (1U)
11816#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
11817#define UART_IE7816_GTVE_MASK (0x4U)
11818#define UART_IE7816_GTVE_SHIFT (2U)
11819#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
11820#define UART_IE7816_INITDE_MASK (0x10U)
11821#define UART_IE7816_INITDE_SHIFT (4U)
11822#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
11823#define UART_IE7816_BWTE_MASK (0x20U)
11824#define UART_IE7816_BWTE_SHIFT (5U)
11825#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
11826#define UART_IE7816_CWTE_MASK (0x40U)
11827#define UART_IE7816_CWTE_SHIFT (6U)
11828#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
11829#define UART_IE7816_WTE_MASK (0x80U)
11830#define UART_IE7816_WTE_SHIFT (7U)
11831#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
11832
11834#define UART_IS7816_RXT_MASK (0x1U)
11835#define UART_IS7816_RXT_SHIFT (0U)
11836#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
11837#define UART_IS7816_TXT_MASK (0x2U)
11838#define UART_IS7816_TXT_SHIFT (1U)
11839#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
11840#define UART_IS7816_GTV_MASK (0x4U)
11841#define UART_IS7816_GTV_SHIFT (2U)
11842#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
11843#define UART_IS7816_INITD_MASK (0x10U)
11844#define UART_IS7816_INITD_SHIFT (4U)
11845#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
11846#define UART_IS7816_BWT_MASK (0x20U)
11847#define UART_IS7816_BWT_SHIFT (5U)
11848#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
11849#define UART_IS7816_CWT_MASK (0x40U)
11850#define UART_IS7816_CWT_SHIFT (6U)
11851#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
11852#define UART_IS7816_WT_MASK (0x80U)
11853#define UART_IS7816_WT_SHIFT (7U)
11854#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
11855
11857#define UART_WP7816T0_WI_MASK (0xFFU)
11858#define UART_WP7816T0_WI_SHIFT (0U)
11859#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
11860
11862#define UART_WP7816T1_BWI_MASK (0xFU)
11863#define UART_WP7816T1_BWI_SHIFT (0U)
11864#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
11865#define UART_WP7816T1_CWI_MASK (0xF0U)
11866#define UART_WP7816T1_CWI_SHIFT (4U)
11867#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
11868
11870#define UART_WN7816_GTN_MASK (0xFFU)
11871#define UART_WN7816_GTN_SHIFT (0U)
11872#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
11873
11875#define UART_WF7816_GTFD_MASK (0xFFU)
11876#define UART_WF7816_GTFD_SHIFT (0U)
11877#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
11878
11880#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
11881#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
11882#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
11883#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
11884#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
11885#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
11886
11888#define UART_TL7816_TLEN_MASK (0xFFU)
11889#define UART_TL7816_TLEN_SHIFT (0U)
11890#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
11891
11893#define UART_C6_CP_MASK (0x10U)
11894#define UART_C6_CP_SHIFT (4U)
11895#define UART_C6_CP(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CP_SHIFT)) & UART_C6_CP_MASK)
11896#define UART_C6_CE_MASK (0x20U)
11897#define UART_C6_CE_SHIFT (5U)
11898#define UART_C6_CE(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CE_SHIFT)) & UART_C6_CE_MASK)
11899#define UART_C6_TX709_MASK (0x40U)
11900#define UART_C6_TX709_SHIFT (6U)
11901#define UART_C6_TX709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_TX709_SHIFT)) & UART_C6_TX709_MASK)
11902#define UART_C6_EN709_MASK (0x80U)
11903#define UART_C6_EN709_SHIFT (7U)
11904#define UART_C6_EN709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_EN709_SHIFT)) & UART_C6_EN709_MASK)
11905
11907#define UART_PCTH_PCTH_MASK (0xFFU)
11908#define UART_PCTH_PCTH_SHIFT (0U)
11909#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTH_PCTH_SHIFT)) & UART_PCTH_PCTH_MASK)
11910
11912#define UART_PCTL_PCTL_MASK (0xFFU)
11913#define UART_PCTL_PCTL_SHIFT (0U)
11914#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTL_PCTL_SHIFT)) & UART_PCTL_PCTL_MASK)
11915
11917#define UART_B1T_B1T_MASK (0xFFU)
11918#define UART_B1T_B1T_SHIFT (0U)
11919#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x)) << UART_B1T_B1T_SHIFT)) & UART_B1T_B1T_MASK)
11920
11922#define UART_SDTH_SDTH_MASK (0xFFU)
11923#define UART_SDTH_SDTH_SHIFT (0U)
11924#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTH_SDTH_SHIFT)) & UART_SDTH_SDTH_MASK)
11925
11927#define UART_SDTL_SDTL_MASK (0xFFU)
11928#define UART_SDTL_SDTL_SHIFT (0U)
11929#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTL_SDTL_SHIFT)) & UART_SDTL_SDTL_MASK)
11930
11932#define UART_PRE_PREAMBLE_MASK (0xFFU)
11933#define UART_PRE_PREAMBLE_SHIFT (0U)
11934#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x)) << UART_PRE_PREAMBLE_SHIFT)) & UART_PRE_PREAMBLE_MASK)
11935
11937#define UART_TPL_TPL_MASK (0xFFU)
11938#define UART_TPL_TPL_SHIFT (0U)
11939#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x)) << UART_TPL_TPL_SHIFT)) & UART_TPL_TPL_MASK)
11940
11942#define UART_IE_TXFIE_MASK (0x1U)
11943#define UART_IE_TXFIE_SHIFT (0U)
11944#define UART_IE_TXFIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_TXFIE_SHIFT)) & UART_IE_TXFIE_MASK)
11945#define UART_IE_PSIE_MASK (0x2U)
11946#define UART_IE_PSIE_SHIFT (1U)
11947#define UART_IE_PSIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PSIE_SHIFT)) & UART_IE_PSIE_MASK)
11948#define UART_IE_PCTEIE_MASK (0x4U)
11949#define UART_IE_PCTEIE_SHIFT (2U)
11950#define UART_IE_PCTEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PCTEIE_SHIFT)) & UART_IE_PCTEIE_MASK)
11951#define UART_IE_PTXIE_MASK (0x8U)
11952#define UART_IE_PTXIE_SHIFT (3U)
11953#define UART_IE_PTXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PTXIE_SHIFT)) & UART_IE_PTXIE_MASK)
11954#define UART_IE_PRXIE_MASK (0x10U)
11955#define UART_IE_PRXIE_SHIFT (4U)
11956#define UART_IE_PRXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PRXIE_SHIFT)) & UART_IE_PRXIE_MASK)
11957#define UART_IE_ISDIE_MASK (0x20U)
11958#define UART_IE_ISDIE_SHIFT (5U)
11959#define UART_IE_ISDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_ISDIE_SHIFT)) & UART_IE_ISDIE_MASK)
11960#define UART_IE_WBEIE_MASK (0x40U)
11961#define UART_IE_WBEIE_SHIFT (6U)
11962#define UART_IE_WBEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_WBEIE_SHIFT)) & UART_IE_WBEIE_MASK)
11963
11965#define UART_WB_WBASE_MASK (0xFFU)
11966#define UART_WB_WBASE_SHIFT (0U)
11967#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x)) << UART_WB_WBASE_SHIFT)) & UART_WB_WBASE_MASK)
11968
11970#define UART_S3_TXFF_MASK (0x1U)
11971#define UART_S3_TXFF_SHIFT (0U)
11972#define UART_S3_TXFF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_TXFF_SHIFT)) & UART_S3_TXFF_MASK)
11973#define UART_S3_PSF_MASK (0x2U)
11974#define UART_S3_PSF_SHIFT (1U)
11975#define UART_S3_PSF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PSF_SHIFT)) & UART_S3_PSF_MASK)
11976#define UART_S3_PCTEF_MASK (0x4U)
11977#define UART_S3_PCTEF_SHIFT (2U)
11978#define UART_S3_PCTEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PCTEF_SHIFT)) & UART_S3_PCTEF_MASK)
11979#define UART_S3_PTXF_MASK (0x8U)
11980#define UART_S3_PTXF_SHIFT (3U)
11981#define UART_S3_PTXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PTXF_SHIFT)) & UART_S3_PTXF_MASK)
11982#define UART_S3_PRXF_MASK (0x10U)
11983#define UART_S3_PRXF_SHIFT (4U)
11984#define UART_S3_PRXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PRXF_SHIFT)) & UART_S3_PRXF_MASK)
11985#define UART_S3_ISD_MASK (0x20U)
11986#define UART_S3_ISD_SHIFT (5U)
11987#define UART_S3_ISD(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_ISD_SHIFT)) & UART_S3_ISD_MASK)
11988#define UART_S3_WBEF_MASK (0x40U)
11989#define UART_S3_WBEF_SHIFT (6U)
11990#define UART_S3_WBEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_WBEF_SHIFT)) & UART_S3_WBEF_MASK)
11991#define UART_S3_PEF_MASK (0x80U)
11992#define UART_S3_PEF_SHIFT (7U)
11993#define UART_S3_PEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PEF_SHIFT)) & UART_S3_PEF_MASK)
11994
11996#define UART_S4_FE_MASK (0x1U)
11997#define UART_S4_FE_SHIFT (0U)
11998#define UART_S4_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_FE_SHIFT)) & UART_S4_FE_MASK)
11999#define UART_S4_ILCV_MASK (0x2U)
12000#define UART_S4_ILCV_SHIFT (1U)
12001#define UART_S4_ILCV(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_ILCV_SHIFT)) & UART_S4_ILCV_MASK)
12002#define UART_S4_CDET_MASK (0xCU)
12003#define UART_S4_CDET_SHIFT (2U)
12004#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_CDET_SHIFT)) & UART_S4_CDET_MASK)
12005#define UART_S4_INITF_MASK (0x10U)
12006#define UART_S4_INITF_SHIFT (4U)
12007#define UART_S4_INITF(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_INITF_SHIFT)) & UART_S4_INITF_MASK)
12008
12010#define UART_RPL_RPL_MASK (0xFFU)
12011#define UART_RPL_RPL_SHIFT (0U)
12012#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPL_RPL_SHIFT)) & UART_RPL_RPL_MASK)
12013
12015#define UART_RPREL_RPREL_MASK (0xFFU)
12016#define UART_RPREL_RPREL_SHIFT (0U)
12017#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPREL_RPREL_SHIFT)) & UART_RPREL_RPREL_MASK)
12018
12020#define UART_CPW_CPW_MASK (0xFFU)
12021#define UART_CPW_CPW_SHIFT (0U)
12022#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x)) << UART_CPW_CPW_SHIFT)) & UART_CPW_CPW_MASK)
12023
12025#define UART_RIDT_RIDT_MASK (0xFFU)
12026#define UART_RIDT_RIDT_SHIFT (0U)
12027#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_RIDT_RIDT_SHIFT)) & UART_RIDT_RIDT_MASK)
12028
12030#define UART_TIDT_TIDT_MASK (0xFFU)
12031#define UART_TIDT_TIDT_SHIFT (0U)
12032#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_TIDT_TIDT_SHIFT)) & UART_TIDT_TIDT_MASK)
12033
12034
12037 /* end of group UART_Register_Masks */
12038
12039
12040/* UART - Peripheral instance base addresses */
12042#define UART0_BASE (0x4006A000u)
12044#define UART0 ((UART_Type *)UART0_BASE)
12046#define UART1_BASE (0x4006B000u)
12048#define UART1 ((UART_Type *)UART1_BASE)
12050#define UART2_BASE (0x4006C000u)
12052#define UART2 ((UART_Type *)UART2_BASE)
12054#define UART3_BASE (0x4006D000u)
12056#define UART3 ((UART_Type *)UART3_BASE)
12058#define UART4_BASE (0x400EA000u)
12060#define UART4 ((UART_Type *)UART4_BASE)
12062#define UART5_BASE (0x400EB000u)
12064#define UART5 ((UART_Type *)UART5_BASE)
12066#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
12068#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
12070#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
12071#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
12072#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
12073
12076 /* end of group UART_Peripheral_Access_Layer */
12077
12078
12079/* ----------------------------------------------------------------------------
12080 -- USB Peripheral Access Layer
12081 ---------------------------------------------------------------------------- */
12082
12089typedef struct {
12090 __I uint8_t PERID;
12091 uint8_t RESERVED_0[3];
12092 __I uint8_t IDCOMP;
12093 uint8_t RESERVED_1[3];
12094 __I uint8_t REV;
12095 uint8_t RESERVED_2[3];
12096 __I uint8_t ADDINFO;
12097 uint8_t RESERVED_3[3];
12098 __IO uint8_t OTGISTAT;
12099 uint8_t RESERVED_4[3];
12100 __IO uint8_t OTGICR;
12101 uint8_t RESERVED_5[3];
12102 __IO uint8_t OTGSTAT;
12103 uint8_t RESERVED_6[3];
12104 __IO uint8_t OTGCTL;
12105 uint8_t RESERVED_7[99];
12106 __IO uint8_t ISTAT;
12107 uint8_t RESERVED_8[3];
12108 __IO uint8_t INTEN;
12109 uint8_t RESERVED_9[3];
12110 __IO uint8_t ERRSTAT;
12111 uint8_t RESERVED_10[3];
12112 __IO uint8_t ERREN;
12113 uint8_t RESERVED_11[3];
12114 __I uint8_t STAT;
12115 uint8_t RESERVED_12[3];
12116 __IO uint8_t CTL;
12117 uint8_t RESERVED_13[3];
12118 __IO uint8_t ADDR;
12119 uint8_t RESERVED_14[3];
12120 __IO uint8_t BDTPAGE1;
12121 uint8_t RESERVED_15[3];
12122 __IO uint8_t FRMNUML;
12123 uint8_t RESERVED_16[3];
12124 __IO uint8_t FRMNUMH;
12125 uint8_t RESERVED_17[3];
12126 __IO uint8_t TOKEN;
12127 uint8_t RESERVED_18[3];
12128 __IO uint8_t SOFTHLD;
12129 uint8_t RESERVED_19[3];
12130 __IO uint8_t BDTPAGE2;
12131 uint8_t RESERVED_20[3];
12132 __IO uint8_t BDTPAGE3;
12133 uint8_t RESERVED_21[11];
12134 struct { /* offset: 0xC0, array step: 0x4 */
12135 __IO uint8_t ENDPT;
12136 uint8_t RESERVED_0[3];
12137 } ENDPOINT[16];
12138 __IO uint8_t USBCTRL;
12139 uint8_t RESERVED_22[3];
12140 __I uint8_t OBSERVE;
12141 uint8_t RESERVED_23[3];
12142 __IO uint8_t CONTROL;
12143 uint8_t RESERVED_24[3];
12144 __IO uint8_t USBTRC0;
12145 uint8_t RESERVED_25[7];
12146 __IO uint8_t USBFRMADJUST;
12147} USB_Type;
12148
12149/* ----------------------------------------------------------------------------
12150 -- USB Register Masks
12151 ---------------------------------------------------------------------------- */
12152
12159#define USB_PERID_ID_MASK (0x3FU)
12160#define USB_PERID_ID_SHIFT (0U)
12161#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
12162
12164#define USB_IDCOMP_NID_MASK (0x3FU)
12165#define USB_IDCOMP_NID_SHIFT (0U)
12166#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
12167
12169#define USB_REV_REV_MASK (0xFFU)
12170#define USB_REV_REV_SHIFT (0U)
12171#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
12172
12174#define USB_ADDINFO_IEHOST_MASK (0x1U)
12175#define USB_ADDINFO_IEHOST_SHIFT (0U)
12176#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
12177#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
12178#define USB_ADDINFO_IRQNUM_SHIFT (3U)
12179#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
12180
12182#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
12183#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
12184#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
12185#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
12186#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
12187#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
12188#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
12189#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
12190#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
12191#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
12192#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
12193#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
12194#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
12195#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
12196#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
12197#define USB_OTGISTAT_IDCHG_MASK (0x80U)
12198#define USB_OTGISTAT_IDCHG_SHIFT (7U)
12199#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
12200
12202#define USB_OTGICR_AVBUSEN_MASK (0x1U)
12203#define USB_OTGICR_AVBUSEN_SHIFT (0U)
12204#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
12205#define USB_OTGICR_BSESSEN_MASK (0x4U)
12206#define USB_OTGICR_BSESSEN_SHIFT (2U)
12207#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
12208#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
12209#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
12210#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
12211#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
12212#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
12213#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
12214#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
12215#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
12216#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
12217#define USB_OTGICR_IDEN_MASK (0x80U)
12218#define USB_OTGICR_IDEN_SHIFT (7U)
12219#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
12220
12222#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
12223#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
12224#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
12225#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
12226#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
12227#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
12228#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
12229#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
12230#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
12231#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
12232#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
12233#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
12234#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
12235#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
12236#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
12237#define USB_OTGSTAT_ID_MASK (0x80U)
12238#define USB_OTGSTAT_ID_SHIFT (7U)
12239#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
12240
12242#define USB_OTGCTL_OTGEN_MASK (0x4U)
12243#define USB_OTGCTL_OTGEN_SHIFT (2U)
12244#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
12245#define USB_OTGCTL_DMLOW_MASK (0x10U)
12246#define USB_OTGCTL_DMLOW_SHIFT (4U)
12247#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
12248#define USB_OTGCTL_DPLOW_MASK (0x20U)
12249#define USB_OTGCTL_DPLOW_SHIFT (5U)
12250#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
12251#define USB_OTGCTL_DPHIGH_MASK (0x80U)
12252#define USB_OTGCTL_DPHIGH_SHIFT (7U)
12253#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
12254
12256#define USB_ISTAT_USBRST_MASK (0x1U)
12257#define USB_ISTAT_USBRST_SHIFT (0U)
12258#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
12259#define USB_ISTAT_ERROR_MASK (0x2U)
12260#define USB_ISTAT_ERROR_SHIFT (1U)
12261#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
12262#define USB_ISTAT_SOFTOK_MASK (0x4U)
12263#define USB_ISTAT_SOFTOK_SHIFT (2U)
12264#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
12265#define USB_ISTAT_TOKDNE_MASK (0x8U)
12266#define USB_ISTAT_TOKDNE_SHIFT (3U)
12267#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
12268#define USB_ISTAT_SLEEP_MASK (0x10U)
12269#define USB_ISTAT_SLEEP_SHIFT (4U)
12270#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
12271#define USB_ISTAT_RESUME_MASK (0x20U)
12272#define USB_ISTAT_RESUME_SHIFT (5U)
12273#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
12274#define USB_ISTAT_ATTACH_MASK (0x40U)
12275#define USB_ISTAT_ATTACH_SHIFT (6U)
12276#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
12277#define USB_ISTAT_STALL_MASK (0x80U)
12278#define USB_ISTAT_STALL_SHIFT (7U)
12279#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
12280
12282#define USB_INTEN_USBRSTEN_MASK (0x1U)
12283#define USB_INTEN_USBRSTEN_SHIFT (0U)
12284#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
12285#define USB_INTEN_ERROREN_MASK (0x2U)
12286#define USB_INTEN_ERROREN_SHIFT (1U)
12287#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
12288#define USB_INTEN_SOFTOKEN_MASK (0x4U)
12289#define USB_INTEN_SOFTOKEN_SHIFT (2U)
12290#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
12291#define USB_INTEN_TOKDNEEN_MASK (0x8U)
12292#define USB_INTEN_TOKDNEEN_SHIFT (3U)
12293#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
12294#define USB_INTEN_SLEEPEN_MASK (0x10U)
12295#define USB_INTEN_SLEEPEN_SHIFT (4U)
12296#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
12297#define USB_INTEN_RESUMEEN_MASK (0x20U)
12298#define USB_INTEN_RESUMEEN_SHIFT (5U)
12299#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
12300#define USB_INTEN_ATTACHEN_MASK (0x40U)
12301#define USB_INTEN_ATTACHEN_SHIFT (6U)
12302#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
12303#define USB_INTEN_STALLEN_MASK (0x80U)
12304#define USB_INTEN_STALLEN_SHIFT (7U)
12305#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
12306
12308#define USB_ERRSTAT_PIDERR_MASK (0x1U)
12309#define USB_ERRSTAT_PIDERR_SHIFT (0U)
12310#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
12311#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
12312#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
12313#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
12314#define USB_ERRSTAT_CRC16_MASK (0x4U)
12315#define USB_ERRSTAT_CRC16_SHIFT (2U)
12316#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
12317#define USB_ERRSTAT_DFN8_MASK (0x8U)
12318#define USB_ERRSTAT_DFN8_SHIFT (3U)
12319#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
12320#define USB_ERRSTAT_BTOERR_MASK (0x10U)
12321#define USB_ERRSTAT_BTOERR_SHIFT (4U)
12322#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
12323#define USB_ERRSTAT_DMAERR_MASK (0x20U)
12324#define USB_ERRSTAT_DMAERR_SHIFT (5U)
12325#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
12326#define USB_ERRSTAT_BTSERR_MASK (0x80U)
12327#define USB_ERRSTAT_BTSERR_SHIFT (7U)
12328#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
12329
12331#define USB_ERREN_PIDERREN_MASK (0x1U)
12332#define USB_ERREN_PIDERREN_SHIFT (0U)
12333#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
12334#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
12335#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
12336#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
12337#define USB_ERREN_CRC16EN_MASK (0x4U)
12338#define USB_ERREN_CRC16EN_SHIFT (2U)
12339#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
12340#define USB_ERREN_DFN8EN_MASK (0x8U)
12341#define USB_ERREN_DFN8EN_SHIFT (3U)
12342#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
12343#define USB_ERREN_BTOERREN_MASK (0x10U)
12344#define USB_ERREN_BTOERREN_SHIFT (4U)
12345#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
12346#define USB_ERREN_DMAERREN_MASK (0x20U)
12347#define USB_ERREN_DMAERREN_SHIFT (5U)
12348#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
12349#define USB_ERREN_BTSERREN_MASK (0x80U)
12350#define USB_ERREN_BTSERREN_SHIFT (7U)
12351#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
12352
12354#define USB_STAT_ODD_MASK (0x4U)
12355#define USB_STAT_ODD_SHIFT (2U)
12356#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
12357#define USB_STAT_TX_MASK (0x8U)
12358#define USB_STAT_TX_SHIFT (3U)
12359#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
12360#define USB_STAT_ENDP_MASK (0xF0U)
12361#define USB_STAT_ENDP_SHIFT (4U)
12362#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
12363
12365#define USB_CTL_USBENSOFEN_MASK (0x1U)
12366#define USB_CTL_USBENSOFEN_SHIFT (0U)
12367#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
12368#define USB_CTL_ODDRST_MASK (0x2U)
12369#define USB_CTL_ODDRST_SHIFT (1U)
12370#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
12371#define USB_CTL_RESUME_MASK (0x4U)
12372#define USB_CTL_RESUME_SHIFT (2U)
12373#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
12374#define USB_CTL_HOSTMODEEN_MASK (0x8U)
12375#define USB_CTL_HOSTMODEEN_SHIFT (3U)
12376#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
12377#define USB_CTL_RESET_MASK (0x10U)
12378#define USB_CTL_RESET_SHIFT (4U)
12379#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
12380#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
12381#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
12382#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
12383#define USB_CTL_SE0_MASK (0x40U)
12384#define USB_CTL_SE0_SHIFT (6U)
12385#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
12386#define USB_CTL_JSTATE_MASK (0x80U)
12387#define USB_CTL_JSTATE_SHIFT (7U)
12388#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
12389
12391#define USB_ADDR_ADDR_MASK (0x7FU)
12392#define USB_ADDR_ADDR_SHIFT (0U)
12393#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
12394#define USB_ADDR_LSEN_MASK (0x80U)
12395#define USB_ADDR_LSEN_SHIFT (7U)
12396#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
12397
12399#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
12400#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
12401#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
12402
12404#define USB_FRMNUML_FRM_MASK (0xFFU)
12405#define USB_FRMNUML_FRM_SHIFT (0U)
12406#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
12407
12409#define USB_FRMNUMH_FRM_MASK (0x7U)
12410#define USB_FRMNUMH_FRM_SHIFT (0U)
12411#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
12412
12414#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
12415#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
12416#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
12417#define USB_TOKEN_TOKENPID_MASK (0xF0U)
12418#define USB_TOKEN_TOKENPID_SHIFT (4U)
12419#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
12420
12422#define USB_SOFTHLD_CNT_MASK (0xFFU)
12423#define USB_SOFTHLD_CNT_SHIFT (0U)
12424#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
12425
12427#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
12428#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
12429#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
12430
12432#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
12433#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
12434#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
12435
12437#define USB_ENDPT_EPHSHK_MASK (0x1U)
12438#define USB_ENDPT_EPHSHK_SHIFT (0U)
12439#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
12440#define USB_ENDPT_EPSTALL_MASK (0x2U)
12441#define USB_ENDPT_EPSTALL_SHIFT (1U)
12442#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
12443#define USB_ENDPT_EPTXEN_MASK (0x4U)
12444#define USB_ENDPT_EPTXEN_SHIFT (2U)
12445#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
12446#define USB_ENDPT_EPRXEN_MASK (0x8U)
12447#define USB_ENDPT_EPRXEN_SHIFT (3U)
12448#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
12449#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
12450#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
12451#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
12452#define USB_ENDPT_RETRYDIS_MASK (0x40U)
12453#define USB_ENDPT_RETRYDIS_SHIFT (6U)
12454#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
12455#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
12456#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
12457#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
12458
12459/* The count of USB_ENDPT */
12460#define USB_ENDPT_COUNT (16U)
12461
12463#define USB_USBCTRL_PDE_MASK (0x40U)
12464#define USB_USBCTRL_PDE_SHIFT (6U)
12465#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
12466#define USB_USBCTRL_SUSP_MASK (0x80U)
12467#define USB_USBCTRL_SUSP_SHIFT (7U)
12468#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
12469
12471#define USB_OBSERVE_DMPD_MASK (0x10U)
12472#define USB_OBSERVE_DMPD_SHIFT (4U)
12473#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
12474#define USB_OBSERVE_DPPD_MASK (0x40U)
12475#define USB_OBSERVE_DPPD_SHIFT (6U)
12476#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
12477#define USB_OBSERVE_DPPU_MASK (0x80U)
12478#define USB_OBSERVE_DPPU_SHIFT (7U)
12479#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
12480
12482#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
12483#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
12484#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
12485
12487#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
12488#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
12489#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
12490#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
12491#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
12492#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
12493#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
12494#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
12495#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
12496#define USB_USBTRC0_USBRESET_MASK (0x80U)
12497#define USB_USBTRC0_USBRESET_SHIFT (7U)
12498#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
12499
12501#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
12502#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
12503#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
12504
12505
12508 /* end of group USB_Register_Masks */
12509
12510
12511/* USB - Peripheral instance base addresses */
12513#define USB0_BASE (0x40072000u)
12515#define USB0 ((USB_Type *)USB0_BASE)
12517#define USB_BASE_ADDRS { USB0_BASE }
12519#define USB_BASE_PTRS { USB0 }
12521#define USB_IRQS { USB0_IRQn }
12522
12525 /* end of group USB_Peripheral_Access_Layer */
12526
12527
12528/* ----------------------------------------------------------------------------
12529 -- USBDCD Peripheral Access Layer
12530 ---------------------------------------------------------------------------- */
12531
12538typedef struct {
12539 __IO uint32_t CONTROL;
12540 __IO uint32_t CLOCK;
12541 __I uint32_t STATUS;
12542 uint8_t RESERVED_0[4];
12543 __IO uint32_t TIMER0;
12544 __IO uint32_t TIMER1;
12545 __IO uint32_t TIMER2;
12546} USBDCD_Type;
12547
12548/* ----------------------------------------------------------------------------
12549 -- USBDCD Register Masks
12550 ---------------------------------------------------------------------------- */
12551
12558#define USBDCD_CONTROL_IACK_MASK (0x1U)
12559#define USBDCD_CONTROL_IACK_SHIFT (0U)
12560#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
12561#define USBDCD_CONTROL_IF_MASK (0x100U)
12562#define USBDCD_CONTROL_IF_SHIFT (8U)
12563#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
12564#define USBDCD_CONTROL_IE_MASK (0x10000U)
12565#define USBDCD_CONTROL_IE_SHIFT (16U)
12566#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
12567#define USBDCD_CONTROL_START_MASK (0x1000000U)
12568#define USBDCD_CONTROL_START_SHIFT (24U)
12569#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
12570#define USBDCD_CONTROL_SR_MASK (0x2000000U)
12571#define USBDCD_CONTROL_SR_SHIFT (25U)
12572#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
12573
12575#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
12576#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
12577#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
12578#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
12579#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
12580#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
12581
12583#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
12584#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
12585#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
12586#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
12587#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
12588#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
12589#define USBDCD_STATUS_ERR_MASK (0x100000U)
12590#define USBDCD_STATUS_ERR_SHIFT (20U)
12591#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
12592#define USBDCD_STATUS_TO_MASK (0x200000U)
12593#define USBDCD_STATUS_TO_SHIFT (21U)
12594#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
12595#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
12596#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
12597#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
12598
12600#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
12601#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
12602#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
12603#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
12604#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
12605#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
12606
12608#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
12609#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
12610#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
12611#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
12612#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
12613#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
12614
12616#define USBDCD_TIMER2_CHECK_DM_MASK (0xFU)
12617#define USBDCD_TIMER2_CHECK_DM_SHIFT (0U)
12618#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK)
12619#define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3FF0000U)
12620#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16U)
12621#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK)
12622
12623
12626 /* end of group USBDCD_Register_Masks */
12627
12628
12629/* USBDCD - Peripheral instance base addresses */
12631#define USBDCD_BASE (0x40035000u)
12633#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
12635#define USBDCD_BASE_ADDRS { USBDCD_BASE }
12637#define USBDCD_BASE_PTRS { USBDCD }
12639#define USBDCD_IRQS { USBDCD_IRQn }
12640
12643 /* end of group USBDCD_Peripheral_Access_Layer */
12644
12645
12646/* ----------------------------------------------------------------------------
12647 -- VREF Peripheral Access Layer
12648 ---------------------------------------------------------------------------- */
12649
12656typedef struct {
12657 __IO uint8_t TRM;
12658 __IO uint8_t SC;
12659} VREF_Type;
12660
12661/* ----------------------------------------------------------------------------
12662 -- VREF Register Masks
12663 ---------------------------------------------------------------------------- */
12664
12671#define VREF_TRM_TRIM_MASK (0x3FU)
12672#define VREF_TRM_TRIM_SHIFT (0U)
12673#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
12674#define VREF_TRM_CHOPEN_MASK (0x40U)
12675#define VREF_TRM_CHOPEN_SHIFT (6U)
12676#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
12677
12679#define VREF_SC_MODE_LV_MASK (0x3U)
12680#define VREF_SC_MODE_LV_SHIFT (0U)
12681#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
12682#define VREF_SC_VREFST_MASK (0x4U)
12683#define VREF_SC_VREFST_SHIFT (2U)
12684#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
12685#define VREF_SC_ICOMPEN_MASK (0x20U)
12686#define VREF_SC_ICOMPEN_SHIFT (5U)
12687#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
12688#define VREF_SC_REGEN_MASK (0x40U)
12689#define VREF_SC_REGEN_SHIFT (6U)
12690#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
12691#define VREF_SC_VREFEN_MASK (0x80U)
12692#define VREF_SC_VREFEN_SHIFT (7U)
12693#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
12694
12695
12698 /* end of group VREF_Register_Masks */
12699
12700
12701/* VREF - Peripheral instance base addresses */
12703#define VREF_BASE (0x40074000u)
12705#define VREF ((VREF_Type *)VREF_BASE)
12707#define VREF_BASE_ADDRS { VREF_BASE }
12709#define VREF_BASE_PTRS { VREF }
12710
12713 /* end of group VREF_Peripheral_Access_Layer */
12714
12715
12716/* ----------------------------------------------------------------------------
12717 -- WDOG Peripheral Access Layer
12718 ---------------------------------------------------------------------------- */
12719
12726typedef struct {
12727 __IO uint16_t STCTRLH;
12728 __IO uint16_t STCTRLL;
12729 __IO uint16_t TOVALH;
12730 __IO uint16_t TOVALL;
12731 __IO uint16_t WINH;
12732 __IO uint16_t WINL;
12733 __IO uint16_t REFRESH;
12734 __IO uint16_t UNLOCK;
12735 __IO uint16_t TMROUTH;
12736 __IO uint16_t TMROUTL;
12737 __IO uint16_t RSTCNT;
12738 __IO uint16_t PRESC;
12739} WDOG_Type;
12740
12741/* ----------------------------------------------------------------------------
12742 -- WDOG Register Masks
12743 ---------------------------------------------------------------------------- */
12744
12751#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
12752#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
12753#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
12754#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
12755#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
12756#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
12757#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
12758#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
12759#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
12760#define WDOG_STCTRLH_WINEN_MASK (0x8U)
12761#define WDOG_STCTRLH_WINEN_SHIFT (3U)
12762#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
12763#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
12764#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
12765#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
12766#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
12767#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
12768#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
12769#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
12770#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
12771#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
12772#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
12773#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
12774#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
12775#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
12776#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
12777#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
12778#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
12779#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
12780#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
12781#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
12782#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
12783#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
12784#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
12785#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
12786#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
12787
12789#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
12790#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
12791#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
12792
12794#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
12795#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
12796#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
12797
12799#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
12800#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
12801#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
12802
12804#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
12805#define WDOG_WINH_WINHIGH_SHIFT (0U)
12806#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
12807
12809#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
12810#define WDOG_WINL_WINLOW_SHIFT (0U)
12811#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
12812
12814#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
12815#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
12816#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
12817
12819#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
12820#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
12821#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
12822
12824#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
12825#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
12826#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
12827
12829#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
12830#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
12831#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
12832
12834#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
12835#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
12836#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
12837
12839#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
12840#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
12841#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
12842
12843
12846 /* end of group WDOG_Register_Masks */
12847
12848
12849/* WDOG - Peripheral instance base addresses */
12851#define WDOG_BASE (0x40052000u)
12853#define WDOG ((WDOG_Type *)WDOG_BASE)
12855#define WDOG_BASE_ADDRS { WDOG_BASE }
12857#define WDOG_BASE_PTRS { WDOG }
12859#define WDOG_IRQS { WDOG_EWM_IRQn }
12860
12863 /* end of group WDOG_Peripheral_Access_Layer */
12864
12865
12866/*
12867** End of section using anonymous unions
12868*/
12869
12870#if defined(__ARMCC_VERSION)
12871 #pragma pop
12872#elif defined(__CWCC__)
12873 #pragma pop
12874#elif defined(__GNUC__)
12875 /* leave anonymous unions enabled */
12876#elif defined(__IAR_SYSTEMS_ICC__)
12877 #pragma language=default
12878#else
12879 #error Not supported compiler type
12880#endif
12881
12884 /* end of group Peripheral_access_layer */
12885
12886
12887/* ----------------------------------------------------------------------------
12888 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
12889 ---------------------------------------------------------------------------- */
12890
12896#if defined(__ARMCC_VERSION)
12897 #if (__ARMCC_VERSION >= 6010050)
12898 #pragma clang system_header
12899 #endif
12900#elif defined(__IAR_SYSTEMS_ICC__)
12901 #pragma system_include
12902#endif
12903
12910#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
12917#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
12918
12921 /* end of group Bit_Field_Generic_Macros */
12922
12923
12924/* ----------------------------------------------------------------------------
12925 -- SDK Compatibility
12926 ---------------------------------------------------------------------------- */
12927
12933#define DSPI0 SPI0
12934#define DSPI1 SPI1
12935#define DSPI2 SPI2
12936#define FLEXCAN0 CAN0
12937#define FLEXCAN1 CAN1
12938#define PTA_BASE GPIOA_BASE
12939#define PTA GPIOA
12940#define PTB_BASE GPIOB_BASE
12941#define PTB GPIOB
12942#define PTC_BASE GPIOC_BASE
12943#define PTC GPIOC
12944#define PTD_BASE GPIOD_BASE
12945#define PTD GPIOD
12946#define PTE_BASE GPIOE_BASE
12947#define PTE GPIOE
12948#define DMAMUX0 DMAMUX
12949#define WP7816_T_TYPE0 WP7816T0
12950#define WP7816_T_TYPE1 WP7816T1
12951#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
12952#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
12953#define UART_WP7816_T_TYPE0_WI(X) UART_WP7816T0_WI(X)
12954#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
12955#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
12956#define UART_WP7816_T_TYPE1_BWI(X) UART_WP7816T1_BWI(X)
12957#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
12958#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
12959#define UART_WP7816_T_TYPE1_CWI(X) UART_WP7816T1_CWI(X)
12960#define SDHC_WML_WRBRSTLEN_MASK This_symbol_has_been_deprecated
12961#define SDHC_WML_WRBRSTLEN_SHIFT This_symbol_has_been_deprecated
12962#define SDHC_WML_WRBRSTLEN(x) This_symbol_has_been_deprecated
12963#define CAN_IMASK2_BUFHM_MASK This_symbol_has_been_deprecated
12964#define CAN_IMASK2_BUFHM_SHIFT This_symbol_has_been_deprecated
12965#define CAN_IMASK2_BUFHM(x) This_symbol_has_been_deprecated
12966#define CAN_IFLAG2_BUFHI_MASK This_symbol_has_been_deprecated
12967#define CAN_IFLAG2_BUFHI_SHIFT This_symbol_has_been_deprecated
12968#define CAN_IFLAG2_BUFHI(x) This_symbol_has_been_deprecated
12969#define DAC_DATL_DATA_MASK DAC_DATL_DATA0_MASK
12970#define DAC_DATL_DATA_SHIFT DAC_DATL_DATA0_SHIFT
12971#define DAC_DATL_DATA(x) DAC_DATL_DATA0(x)
12972#define DAC_DATH_DATA_MASK DAC_DATH_DATA1_MASK
12973#define DAC_DATH_DATA_SHIFT DAC_DATH_DATA1_SHIFT
12974#define DAC_DATH_DATA(x) DAC_DATH_DATA1(x)
12975#define SIM_SCGC6_RNGA_MASK This_symbol_has_been_deprecated
12976#define SIM_SCGC6_RNGA_SHIFT This_symbol_has_been_deprecated
12977#define Watchdog_IRQn WDOG_EWM_IRQn
12978#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
12979#define LPTimer_IRQn LPTMR0_IRQn
12980#define LPTimer_IRQHandler LPTMR0_IRQHandler
12981#define LLW_IRQn LLWU_IRQn
12982#define LLW_IRQHandler LLWU_IRQHandler
12983
12986 /* end of group SDK_Compatibility_Symbols */
12987
12988
12989#endif /* _MK60D10_H_ */
12990
__O
#define __O
Definition core_cm3.h:169
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn
IRQn
Definition MK60D10.h:157
MCM_IRQn
@ MCM_IRQn
Definition MK60D10.h:190
PendSV_IRQn
@ PendSV_IRQn
Definition MK60D10.h:169
DMA7_IRQn
@ DMA7_IRQn
Definition MK60D10.h:180
CAN1_ORed_Message_buffer_IRQn
@ CAN1_ORed_Message_buffer_IRQn
Definition MK60D10.h:210
FTM0_IRQn
@ FTM0_IRQn
Definition MK60D10.h:235
ADC0_IRQn
@ ADC0_IRQn
Definition MK60D10.h:230
WDOG_EWM_IRQn
@ WDOG_EWM_IRQn
Definition MK60D10.h:195
PORTE_IRQn
@ PORTE_IRQn
Definition MK60D10.h:264
I2C0_IRQn
@ I2C0_IRQn
Definition MK60D10.h:197
MCG_IRQn
@ MCG_IRQn
Definition MK60D10.h:257
DMA11_IRQn
@ DMA11_IRQn
Definition MK60D10.h:184
CAN1_Bus_Off_IRQn
@ CAN1_Bus_Off_IRQn
Definition MK60D10.h:211
NotAvail_IRQn
@ NotAvail_IRQn
Definition MK60D10.h:159
DMA2_IRQn
@ DMA2_IRQn
Definition MK60D10.h:175
RTC_Seconds_IRQn
@ RTC_Seconds_IRQn
Definition MK60D10.h:240
UART4_RX_TX_IRQn
@ UART4_RX_TX_IRQn
Definition MK60D10.h:226
Reserved116_IRQn
@ Reserved116_IRQn
Definition MK60D10.h:273
DMA13_IRQn
@ DMA13_IRQn
Definition MK60D10.h:186
CAN1_Error_IRQn
@ CAN1_Error_IRQn
Definition MK60D10.h:212
PORTD_IRQn
@ PORTD_IRQn
Definition MK60D10.h:263
UART0_LON_IRQn
@ UART0_LON_IRQn
Definition MK60D10.h:217
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition MK60D10.h:164
DMA3_IRQn
@ DMA3_IRQn
Definition MK60D10.h:176
ADC1_IRQn
@ ADC1_IRQn
Definition MK60D10.h:231
Reserved102_IRQn
@ Reserved102_IRQn
Definition MK60D10.h:259
CAN0_ORed_Message_buffer_IRQn
@ CAN0_ORed_Message_buffer_IRQn
Definition MK60D10.h:202
DMA12_IRQn
@ DMA12_IRQn
Definition MK60D10.h:185
UART5_ERR_IRQn
@ UART5_ERR_IRQn
Definition MK60D10.h:229
TSI0_IRQn
@ TSI0_IRQn
Definition MK60D10.h:256
Reserved119_IRQn
@ Reserved119_IRQn
Definition MK60D10.h:276
SDHC_IRQn
@ SDHC_IRQn
Definition MK60D10.h:253
FTM1_IRQn
@ FTM1_IRQn
Definition MK60D10.h:236
I2S0_Tx_IRQn
@ I2S0_Tx_IRQn
Definition MK60D10.h:208
CAN0_Wake_Up_IRQn
@ CAN0_Wake_Up_IRQn
Definition MK60D10.h:207
SWI_IRQn
@ SWI_IRQn
Definition MK60D10.h:267
I2S0_Rx_IRQn
@ I2S0_Rx_IRQn
Definition MK60D10.h:209
SVCall_IRQn
@ SVCall_IRQn
Definition MK60D10.h:167
CAN0_Tx_Warning_IRQn
@ CAN0_Tx_Warning_IRQn
Definition MK60D10.h:205
SPI2_IRQn
@ SPI2_IRQn
Definition MK60D10.h:201
DMA_Error_IRQn
@ DMA_Error_IRQn
Definition MK60D10.h:189
DMA0_IRQn
@ DMA0_IRQn
Definition MK60D10.h:173
DMA1_IRQn
@ DMA1_IRQn
Definition MK60D10.h:174
UART0_RX_TX_IRQn
@ UART0_RX_TX_IRQn
Definition MK60D10.h:218
Reserved109_IRQn
@ Reserved109_IRQn
Definition MK60D10.h:266
DAC0_IRQn
@ DAC0_IRQn
Definition MK60D10.h:254
FTM2_IRQn
@ FTM2_IRQn
Definition MK60D10.h:237
CMT_IRQn
@ CMT_IRQn
Definition MK60D10.h:238
UsageFault_IRQn
@ UsageFault_IRQn
Definition MK60D10.h:166
UART4_ERR_IRQn
@ UART4_ERR_IRQn
Definition MK60D10.h:227
Reserved115_IRQn
@ Reserved115_IRQn
Definition MK60D10.h:272
SysTick_IRQn
@ SysTick_IRQn
Definition MK60D10.h:170
DMA4_IRQn
@ DMA4_IRQn
Definition MK60D10.h:177
CAN0_Error_IRQn
@ CAN0_Error_IRQn
Definition MK60D10.h:204
UART5_RX_TX_IRQn
@ UART5_RX_TX_IRQn
Definition MK60D10.h:228
UART0_ERR_IRQn
@ UART0_ERR_IRQn
Definition MK60D10.h:219
CAN1_Rx_Warning_IRQn
@ CAN1_Rx_Warning_IRQn
Definition MK60D10.h:214
CMP2_IRQn
@ CMP2_IRQn
Definition MK60D10.h:234
DMA5_IRQn
@ DMA5_IRQn
Definition MK60D10.h:178
Reserved117_IRQn
@ Reserved117_IRQn
Definition MK60D10.h:274
Reserved95_IRQn
@ Reserved95_IRQn
Definition MK60D10.h:252
DMA15_IRQn
@ DMA15_IRQn
Definition MK60D10.h:188
CAN1_Wake_Up_IRQn
@ CAN1_Wake_Up_IRQn
Definition MK60D10.h:215
DMA10_IRQn
@ DMA10_IRQn
Definition MK60D10.h:183
BusFault_IRQn
@ BusFault_IRQn
Definition MK60D10.h:165
CMP0_IRQn
@ CMP0_IRQn
Definition MK60D10.h:232
ENET_Receive_IRQn
@ ENET_Receive_IRQn
Definition MK60D10.h:250
PDB0_IRQn
@ PDB0_IRQn
Definition MK60D10.h:245
UART2_RX_TX_IRQn
@ UART2_RX_TX_IRQn
Definition MK60D10.h:222
LLWU_IRQn
@ LLWU_IRQn
Definition MK60D10.h:194
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition MK60D10.h:168
RNG_IRQn
@ RNG_IRQn
Definition MK60D10.h:196
UART1_ERR_IRQn
@ UART1_ERR_IRQn
Definition MK60D10.h:221
USBDCD_IRQn
@ USBDCD_IRQn
Definition MK60D10.h:247
LPTMR0_IRQn
@ LPTMR0_IRQn
Definition MK60D10.h:258
Reserved59_IRQn
@ Reserved59_IRQn
Definition MK60D10.h:216
Read_Collision_IRQn
@ Read_Collision_IRQn
Definition MK60D10.h:192
DMA6_IRQn
@ DMA6_IRQn
Definition MK60D10.h:179
LVD_LVW_IRQn
@ LVD_LVW_IRQn
Definition MK60D10.h:193
PIT3_IRQn
@ PIT3_IRQn
Definition MK60D10.h:244
FTFL_IRQn
@ FTFL_IRQn
Definition MK60D10.h:191
UART2_ERR_IRQn
@ UART2_ERR_IRQn
Definition MK60D10.h:223
SPI1_IRQn
@ SPI1_IRQn
Definition MK60D10.h:200
HardFault_IRQn
@ HardFault_IRQn
Definition MK60D10.h:163
CAN0_Rx_Warning_IRQn
@ CAN0_Rx_Warning_IRQn
Definition MK60D10.h:206
PIT0_IRQn
@ PIT0_IRQn
Definition MK60D10.h:241
UART3_RX_TX_IRQn
@ UART3_RX_TX_IRQn
Definition MK60D10.h:224
ENET_Error_IRQn
@ ENET_Error_IRQn
Definition MK60D10.h:251
PORTA_IRQn
@ PORTA_IRQn
Definition MK60D10.h:260
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition MK60D10.h:248
CMP1_IRQn
@ CMP1_IRQn
Definition MK60D10.h:233
PORTC_IRQn
@ PORTC_IRQn
Definition MK60D10.h:262
Reserved113_IRQn
@ Reserved113_IRQn
Definition MK60D10.h:270
ENET_Transmit_IRQn
@ ENET_Transmit_IRQn
Definition MK60D10.h:249
PORTB_IRQn
@ PORTB_IRQn
Definition MK60D10.h:261
Reserved108_IRQn
@ Reserved108_IRQn
Definition MK60D10.h:265
Reserved111_IRQn
@ Reserved111_IRQn
Definition MK60D10.h:268
UART3_ERR_IRQn
@ UART3_ERR_IRQn
Definition MK60D10.h:225
DMA14_IRQn
@ DMA14_IRQn
Definition MK60D10.h:187
UART1_RX_TX_IRQn
@ UART1_RX_TX_IRQn
Definition MK60D10.h:220
USB0_IRQn
@ USB0_IRQn
Definition MK60D10.h:246
CAN0_Bus_Off_IRQn
@ CAN0_Bus_Off_IRQn
Definition MK60D10.h:203
CAN1_Tx_Warning_IRQn
@ CAN1_Tx_Warning_IRQn
Definition MK60D10.h:213
RTC_IRQn
@ RTC_IRQn
Definition MK60D10.h:239
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition MK60D10.h:162
PIT1_IRQn
@ PIT1_IRQn
Definition MK60D10.h:242
Reserved114_IRQn
@ Reserved114_IRQn
Definition MK60D10.h:271
Reserved112_IRQn
@ Reserved112_IRQn
Definition MK60D10.h:269
DAC1_IRQn
@ DAC1_IRQn
Definition MK60D10.h:255
I2C1_IRQn
@ I2C1_IRQn
Definition MK60D10.h:198
DMA8_IRQn
@ DMA8_IRQn
Definition MK60D10.h:181
Reserved118_IRQn
@ Reserved118_IRQn
Definition MK60D10.h:275
SPI0_IRQn
@ SPI0_IRQn
Definition MK60D10.h:199
DMA9_IRQn
@ DMA9_IRQn
Definition MK60D10.h:182
PIT2_IRQn
@ PIT2_IRQn
Definition MK60D10.h:243
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70
ENET_Type::IEEE_R_OCTETS_OK
__I uint32_t IEEE_R_OCTETS_OK
Definition MK60D10.h:4739
ENET_Type::IEEE_T_DEF
__IO uint32_t IEEE_T_DEF
Definition MK60D10.h:4707
MCG_Type::C10
__I uint8_t C10
Definition MK60D10.h:7891
ENET_Type::TCCR
__IO uint32_t TCCR
Definition MK60D10.h:4752
ENET_Type::ECR
__IO uint32_t ECR
Definition MK60D10.h:4646
USB_Type::USBTRC0
__IO uint8_t USBTRC0
Definition MK60D10.h:12144
DMA_Type::DCHPRI10
__IO uint8_t DCHPRI10
Definition MK60D10.h:3737
SPI_Type::POPR
__I uint32_t POPR
Definition MK60D10.h:10660
CAU_Type::ROTL_CAA
__O uint32_t ROTL_CAA
Definition MK60D10.h:2615
AIPS_Type::PACRG
__IO uint32_t PACRG
Definition MK60D10.h:736
UART_Type::TPL
__IO uint8_t TPL
Definition MK60D10.h:11491
ENET_Type::IEEE_R_CRC
__IO uint32_t IEEE_R_CRC
Definition MK60D10.h:4735
ADC_Type::CFG2
__IO uint32_t CFG2
Definition MK60D10.h:452
PDB_Type::C1
__IO uint32_t C1
Definition MK60D10.h:8459
USB_Type::CONTROL
__IO uint8_t CONTROL
Definition MK60D10.h:12142
AIPS_Type::PACRB
__IO uint32_t PACRB
Definition MK60D10.h:730
AIPS_Type::PACRI
__IO uint32_t PACRI
Definition MK60D10.h:738
FTM_Type::QDCTRL
__IO uint32_t QDCTRL
Definition MK60D10.h:6194
NV_Type::FPROT0
__I uint8_t FPROT0
Definition MK60D10.h:8247
CRC_Type::CRCLU
__IO uint8_t CRCLU
Definition MK60D10.h:3391
NV_Type::BACKKEY4
__I uint8_t BACKKEY4
Definition MK60D10.h:8243
CAN_Type::RXMGMASK
__IO uint32_t RXMGMASK
Definition MK60D10.h:2171
MCG_Type::C3
__IO uint8_t C3
Definition MK60D10.h:7878
PDB_Type::IDLY
__IO uint32_t IDLY
Definition MK60D10.h:8457
ENET_Type::RAFL
__IO uint32_t RAFL
Definition MK60D10.h:4675
FTFL_Type::FSTAT
__IO uint8_t FSTAT
Definition MK60D10.h:5953
ENET_Type::RMON_R_JAB
__IO uint32_t RMON_R_JAB
Definition MK60D10.h:4723
CAN_Type::RX15MASK
__IO uint32_t RX15MASK
Definition MK60D10.h:2173
AIPS_Type::PACRC
__IO uint32_t PACRC
Definition MK60D10.h:731
SPI_Type::TXFR2
__I uint32_t TXFR2
Definition MK60D10.h:10663
DAC_Type::DATL
__IO uint8_t DATL
Definition MK60D10.h:3576
ENET_Type::TAEM
__IO uint32_t TAEM
Definition MK60D10.h:4677
SPI_Type::RSER
__IO uint32_t RSER
Definition MK60D10.h:10655
ADC_Type::OFS
__IO uint32_t OFS
Definition MK60D10.h:458
I2S_Type::MCR
__IO uint32_t MCR
Definition MK60D10.h:7176
WDOG_Type::STCTRLH
__IO uint16_t STCTRLH
Definition MK60D10.h:12727
MCM_Type::ETBCNT
__I uint32_t ETBCNT
Definition MK60D10.h:8121
FTFL_Type::FCCOB5
__IO uint8_t FCCOB5
Definition MK60D10.h:5963
SIM_Type::SCGC5
__IO uint32_t SCGC5
Definition MK60D10.h:10133
DMA_Type::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition MK60D10.h:3759
CMP_Type::DACCR
__IO uint8_t DACCR
Definition MK60D10.h:3109
ADC_Type::PGA
__IO uint32_t PGA
Definition MK60D10.h:468
ADC_Type::CLP3
__IO uint32_t CLP3
Definition MK60D10.h:464
CRC_Type::CTRL
__IO uint32_t CTRL
Definition MK60D10.h:3410
I2C_Type::SMB
__IO uint8_t SMB
Definition MK60D10.h:6956
SDHC_Type::HTCAPBLT
__I uint32_t HTCAPBLT
Definition MK60D10.h:9534
FTM_Type::FILTER
__IO uint32_t FILTER
Definition MK60D10.h:6192
I2C_Type::S
__IO uint8_t S
Definition MK60D10.h:6951
UART_Type::WP7816T1
__IO uint8_t WP7816T1
Definition MK60D10.h:11477
AIPS_Type::PACRJ
__IO uint32_t PACRJ
Definition MK60D10.h:739
UART_Type::CFIFO
__IO uint8_t CFIFO
Definition MK60D10.h:11465
ENET_Type::RMON_T_P256TO511
__IO uint32_t RMON_T_P256TO511
Definition MK60D10.h:4698
ADC_Type::CLP0
__IO uint32_t CLP0
Definition MK60D10.h:467
SDHC_Type::DATPORT
__IO uint32_t DATPORT
Definition MK60D10.h:9526
FTM_Type::MODE
__IO uint32_t MODE
Definition MK60D10.h:6183
SIM_Type::UIDH
__I uint32_t UIDH
Definition MK60D10.h:10140
SIM_Type::UIDML
__I uint32_t UIDML
Definition MK60D10.h:10142
CRC_Type::GPOLYH
__IO uint16_t GPOLYH
Definition MK60D10.h:3399
FTM_Type::POL
__IO uint32_t POL
Definition MK60D10.h:6190
ENET_Type::RMON_R_P65TO127
__IO uint32_t RMON_R_P65TO127
Definition MK60D10.h:4726
CMT_Type::CMD3
__IO uint8_t CMD3
Definition MK60D10.h:3250
CMT_Type::PPS
__IO uint8_t PPS
Definition MK60D10.h:3252
ENET_Type::IEEE_R_ALIGN
__IO uint32_t IEEE_R_ALIGN
Definition MK60D10.h:4736
ENET_Type::RMON_T_FRAG
__IO uint32_t RMON_T_FRAG
Definition MK60D10.h:4692
UART_Type::RPREL
__I uint8_t RPREL
Definition MK60D10.h:11497
CAN_Type::RXFIR
__I uint32_t RXFIR
Definition MK60D10.h:2185
I2C_Type::C2
__IO uint8_t C2
Definition MK60D10.h:6953
UART_Type::WB
__IO uint8_t WB
Definition MK60D10.h:11493
ENET_Type::RCR
__IO uint32_t RCR
Definition MK60D10.h:4653
TSI_Type::THRESHOLD
__IO uint32_t THRESHOLD
Definition MK60D10.h:11205
PIT_Type::TCTRL
__IO uint32_t TCTRL
Definition MK60D10.h:8646
FTM_Type::CnSC
__IO uint32_t CnSC
Definition MK60D10.h:6178
SDHC_Type::IRQSTATEN
__IO uint32_t IRQSTATEN
Definition MK60D10.h:9531
PORT_Type::ISFR
__IO uint32_t ISFR
Definition MK60D10.h:8837
TSI_Type::SCANC
__IO uint32_t SCANC
Definition MK60D10.h:11193
UART_Type::RIDT
__IO uint8_t RIDT
Definition MK60D10.h:11499
MCM_Type::PLAMC
__I uint16_t PLAMC
Definition MK60D10.h:8116
UART_Type::C3
__IO uint8_t C3
Definition MK60D10.h:11454
DMA_Type::ERQ
__IO uint32_t ERQ
Definition MK60D10.h:3710
PMC_Type::REGSC
__IO uint8_t REGSC
Definition MK60D10.h:8742
ADC_Type::MG
__IO uint32_t MG
Definition MK60D10.h:460
SPI_Type::TXFR0
__I uint32_t TXFR0
Definition MK60D10.h:10661
ENET_Type::RMON_T_JAB
__IO uint32_t RMON_T_JAB
Definition MK60D10.h:4693
I2C_Type::A2
__IO uint8_t A2
Definition MK60D10.h:6957
GPIO_Type::PDIR
__I uint32_t PDIR
Definition MK60D10.h:6857
ENET_Type::TGSR
__IO uint32_t TGSR
Definition MK60D10.h:4749
FTFL_Type::FPROT2
__IO uint8_t FPROT2
Definition MK60D10.h:5970
PDB_Type::SC
__IO uint32_t SC
Definition MK60D10.h:8454
FTM_Type::PWMLOAD
__IO uint32_t PWMLOAD
Definition MK60D10.h:6200
UART_Type::SFIFO
__IO uint8_t SFIFO
Definition MK60D10.h:11466
UART_Type::C7816
__IO uint8_t C7816
Definition MK60D10.h:11472
SIM_Type::SOPT5
__IO uint32_t SOPT5
Definition MK60D10.h:10124
USB_Type::ERREN
__IO uint8_t ERREN
Definition MK60D10.h:12112
I2S_Type::RCR4
__IO uint32_t RCR4
Definition MK60D10.h:7167
USB_Type::OTGCTL
__IO uint8_t OTGCTL
Definition MK60D10.h:12104
MCG_Type::C2
__IO uint8_t C2
Definition MK60D10.h:7877
PMC_Type::LVDSC1
__IO uint8_t LVDSC1
Definition MK60D10.h:8740
ENET_Type::IEEE_R_FDXFC
__IO uint32_t IEEE_R_FDXFC
Definition MK60D10.h:4738
AXBS_Type::MGPCR5
__IO uint32_t MGPCR5
Definition MK60D10.h:2050
AIPS_Type::PACRA
__IO uint32_t PACRA
Definition MK60D10.h:729
WDOG_Type::STCTRLL
__IO uint16_t STCTRLL
Definition MK60D10.h:12728
ADC_Type::CLM2
__IO uint32_t CLM2
Definition MK60D10.h:473
UART_Type::RWFIFO
__IO uint8_t RWFIFO
Definition MK60D10.h:11469
I2S_Type::TMR
__IO uint32_t TMR
Definition MK60D10.h:7161
LLWU_Type::F2
__IO uint8_t F2
Definition MK60D10.h:7543
USB_Type::PERID
__I uint8_t PERID
Definition MK60D10.h:12090
ENET_Type::RACC
__IO uint32_t RACC
Definition MK60D10.h:4683
ENET_Type::EIR
__IO uint32_t EIR
Definition MK60D10.h:4640
DMA_Type::CERR
__O uint8_t CERR
Definition MK60D10.h:3719
AIPS_Type::PACRK
__IO uint32_t PACRK
Definition MK60D10.h:740
USB_Type::USBFRMADJUST
__IO uint8_t USBFRMADJUST
Definition MK60D10.h:12146
UART_Type::MA2
__IO uint8_t MA2
Definition MK60D10.h:11457
SPI_Type::PUSHR_SLAVE
__IO uint32_t PUSHR_SLAVE
Definition MK60D10.h:10658
UART_Type::PCTH
__IO uint8_t PCTH
Definition MK60D10.h:11485
USB_Type::OTGISTAT
__IO uint8_t OTGISTAT
Definition MK60D10.h:12098
SIM_Type::CLKDIV1
__IO uint32_t CLKDIV1
Definition MK60D10.h:10136
ENET_Type::TCSR
__IO uint32_t TCSR
Definition MK60D10.h:4751
ENET_Type::IEEE_T_EXCOL
__IO uint32_t IEEE_T_EXCOL
Definition MK60D10.h:4709
EWM_Type::CTRL
__IO uint8_t CTRL
Definition MK60D10.h:5538
DMA_Type::ATTR
__IO uint16_t ATTR
Definition MK60D10.h:3748
ENET_Type::MMFR
__IO uint32_t MMFR
Definition MK60D10.h:4648
GPIO_Type::PDOR
__IO uint32_t PDOR
Definition MK60D10.h:6853
ENET_Type::RMON_T_OVERSIZE
__IO uint32_t RMON_T_OVERSIZE
Definition MK60D10.h:4691
SIM_Type::UIDMH
__I uint32_t UIDMH
Definition MK60D10.h:10141
MCG_Type::C6
__IO uint8_t C6
Definition MK60D10.h:7881
VREF_Type::TRM
__IO uint8_t TRM
Definition MK60D10.h:12657
USB_Type::BDTPAGE3
__IO uint8_t BDTPAGE3
Definition MK60D10.h:12132
CRC_Type::CRCHL
__IO uint8_t CRCHL
Definition MK60D10.h:3392
CAU_Type::ROTL_CASR
__O uint32_t ROTL_CASR
Definition MK60D10.h:2614
NV_Type::BACKKEY6
__I uint8_t BACKKEY6
Definition MK60D10.h:8241
USBDCD_Type::CONTROL
__IO uint32_t CONTROL
Definition MK60D10.h:12539
DMA_Type::SOFF
__IO uint16_t SOFF
Definition MK60D10.h:3747
I2S_Type::TCR3
__IO uint32_t TCR3
Definition MK60D10.h:7153
UART_Type::IS7816
__IO uint8_t IS7816
Definition MK60D10.h:11474
ENET_Type::GAUR
__IO uint32_t GAUR
Definition MK60D10.h:4663
ADC_Type::CLP4
__IO uint32_t CLP4
Definition MK60D10.h:463
LLWU_Type::F3
__I uint8_t F3
Definition MK60D10.h:7544
ADC_Type::PG
__IO uint32_t PG
Definition MK60D10.h:459
UART_Type::WN7816
__IO uint8_t WN7816
Definition MK60D10.h:11479
CAN_Type::RX14MASK
__IO uint32_t RX14MASK
Definition MK60D10.h:2172
NV_Type::FDPROT
__I uint8_t FDPROT
Definition MK60D10.h:8251
LLWU_Type::PE4
__IO uint8_t PE4
Definition MK60D10.h:7540
ENET_Type::ATVR
__IO uint32_t ATVR
Definition MK60D10.h:4742
I2S_Type::RCSR
__IO uint32_t RCSR
Definition MK60D10.h:7163
CAN_Type::CRCR
__I uint32_t CRCR
Definition MK60D10.h:2183
WDOG_Type::TOVALL
__IO uint16_t TOVALL
Definition MK60D10.h:12730
ENET_Type::PAUR
__IO uint32_t PAUR
Definition MK60D10.h:4658
I2S_Type::TCR1
__IO uint32_t TCR1
Definition MK60D10.h:7151
UART_Type::C2
__IO uint8_t C2
Definition MK60D10.h:11451
RNG_Type::ER
__O uint32_t ER
Definition MK60D10.h:9209
DAC_Type::C2
__IO uint8_t C2
Definition MK60D10.h:3582
I2S_Type::TCR2
__IO uint32_t TCR2
Definition MK60D10.h:7152
DMA_Type::SLAST
__IO uint32_t SLAST
Definition MK60D10.h:3754
UART_Type::SDTH
__IO uint8_t SDTH
Definition MK60D10.h:11488
FTFL_Type::FOPT
__I uint8_t FOPT
Definition MK60D10.h:5956
SIM_Type::SOPT2
__IO uint32_t SOPT2
Definition MK60D10.h:10121
I2C_Type::SLTH
__IO uint8_t SLTH
Definition MK60D10.h:6958
LPTMR_Type::CSR
__IO uint32_t CSR
Definition MK60D10.h:7783
ADC_Type::CFG1
__IO uint32_t CFG1
Definition MK60D10.h:451
ENET_Type::TCR
__IO uint32_t TCR
Definition MK60D10.h:4655
RCM_Type::SRS1
__I uint8_t SRS1
Definition MK60D10.h:8975
RCM_Type::RPFW
__IO uint8_t RPFW
Definition MK60D10.h:8978
SIM_Type::SOPT4
__IO uint32_t SOPT4
Definition MK60D10.h:10123
SDHC_Type::HOSTVER
__I uint32_t HOSTVER
Definition MK60D10.h:9544
GPIO_Type::PDDR
__IO uint32_t PDDR
Definition MK60D10.h:6858
WDOG_Type::WINH
__IO uint16_t WINH
Definition MK60D10.h:12731
ENET_Type::RMON_T_P_GTE2048
__IO uint32_t RMON_T_P_GTE2048
Definition MK60D10.h:4701
DMA_Type::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition MK60D10.h:3765
TSI_Type::CNTR5
__I uint32_t CNTR5
Definition MK60D10.h:11199
CAU_Type::STR_CASR
__I uint32_t STR_CASR
Definition MK60D10.h:2598
CMP_Type::CR1
__IO uint8_t CR1
Definition MK60D10.h:3106
USBDCD_Type::STATUS
__I uint32_t STATUS
Definition MK60D10.h:12541
CMP_Type::FPR
__IO uint8_t FPR
Definition MK60D10.h:3107
ENET_Type::MRBR
__IO uint32_t MRBR
Definition MK60D10.h:4670
ENET_Type::RAEM
__IO uint32_t RAEM
Definition MK60D10.h:4674
FTFL_Type::FPROT3
__IO uint8_t FPROT3
Definition MK60D10.h:5969
ENET_Type::RSEM
__IO uint32_t RSEM
Definition MK60D10.h:4673
DAC_Type::C0
__IO uint8_t C0
Definition MK60D10.h:3580
FTM_Type::CnV
__IO uint32_t CnV
Definition MK60D10.h:6179
DMA_Type::DCHPRI2
__IO uint8_t DCHPRI2
Definition MK60D10.h:3729
I2C_Type::F
__IO uint8_t F
Definition MK60D10.h:6949
SDHC_Type::ADSADDR
__IO uint32_t ADSADDR
Definition MK60D10.h:9539
CAN_Type::WORD1
__IO uint32_t WORD1
Definition MK60D10.h:2191
FTFL_Type::FPROT1
__IO uint8_t FPROT1
Definition MK60D10.h:5971
UART_Type::SDTL
__IO uint8_t SDTL
Definition MK60D10.h:11489
ADC_Type::CLP1
__IO uint32_t CLP1
Definition MK60D10.h:466
I2S_Type::RCR3
__IO uint32_t RCR3
Definition MK60D10.h:7166
RNG_Type::SR
__I uint32_t SR
Definition MK60D10.h:9208
NV_Type::FPROT2
__I uint8_t FPROT2
Definition MK60D10.h:8245
DMA_Type::DCHPRI12
__IO uint8_t DCHPRI12
Definition MK60D10.h:3743
NV_Type::FPROT1
__I uint8_t FPROT1
Definition MK60D10.h:8246
CAU_Type::LDR_CAA
__O uint32_t LDR_CAA
Definition MK60D10.h:2595
ENET_Type::IEEE_T_FRAME_OK
__IO uint32_t IEEE_T_FRAME_OK
Definition MK60D10.h:4704
FTFL_Type::FCCOB0
__IO uint8_t FCCOB0
Definition MK60D10.h:5960
CRC_Type::CTRLHU
__IO uint8_t CTRLHU
Definition MK60D10.h:3413
ENET_Type::RMON_R_P64
__IO uint32_t RMON_R_P64
Definition MK60D10.h:4725
DMA_Type::DCHPRI5
__IO uint8_t DCHPRI5
Definition MK60D10.h:3734
ENET_Type::RMON_R_FRAG
__IO uint32_t RMON_R_FRAG
Definition MK60D10.h:4722
MCG_Type::C7
__IO uint8_t C7
Definition MK60D10.h:7888
ENET_Type::RMON_T_DROP
__IO uint32_t RMON_T_DROP
Definition MK60D10.h:4685
FTM_Type::SC
__IO uint32_t SC
Definition MK60D10.h:6174
SIM_Type::SCGC7
__IO uint32_t SCGC7
Definition MK60D10.h:10135
CAN_Type::IFLAG1
__IO uint32_t IFLAG1
Definition MK60D10.h:2179
USB_Type::STAT
__I uint8_t STAT
Definition MK60D10.h:12114
CAU_Type::RADR_CAA
__O uint32_t RADR_CAA
Definition MK60D10.h:2607
I2C_Type::D
__IO uint8_t D
Definition MK60D10.h:6952
RCM_Type::MR
__I uint8_t MR
Definition MK60D10.h:8980
USB_Type::SOFTHLD
__IO uint8_t SOFTHLD
Definition MK60D10.h:12128
ENET_Type::RMON_T_UNDERSIZE
__IO uint32_t RMON_T_UNDERSIZE
Definition MK60D10.h:4690
CAN_Type::ECR
__IO uint32_t ECR
Definition MK60D10.h:2174
CRC_Type::GPOLYLL
__IO uint8_t GPOLYLL
Definition MK60D10.h:3403
LLWU_Type::FILT2
__IO uint8_t FILT2
Definition MK60D10.h:7546
RTC_Type::TCR
__IO uint32_t TCR
Definition MK60D10.h:9309
ADC_Type::CLP2
__IO uint32_t CLP2
Definition MK60D10.h:465
MCG_Type::ATCVH
__IO uint8_t ATCVH
Definition MK60D10.h:7886
USB_Type::TOKEN
__IO uint8_t TOKEN
Definition MK60D10.h:12126
UART_Type::IE
__IO uint8_t IE
Definition MK60D10.h:11492
DMA_Type::HRS
__IO uint32_t HRS
Definition MK60D10.h:3726
UART_Type::RPL
__I uint8_t RPL
Definition MK60D10.h:11496
CMP_Type::SCR
__IO uint8_t SCR
Definition MK60D10.h:3108
ENET_Type::RMON_R_OCTETS
__I uint32_t RMON_R_OCTETS
Definition MK60D10.h:4732
SIM_Type::SCGC3
__IO uint32_t SCGC3
Definition MK60D10.h:10131
RTC_Type::TSR
__IO uint32_t TSR
Definition MK60D10.h:9306
PDB_Type::POEN
__IO uint32_t POEN
Definition MK60D10.h:8470
FTM_Type::INVCTRL
__IO uint32_t INVCTRL
Definition MK60D10.h:6198
USB_Type::FRMNUMH
__IO uint8_t FRMNUMH
Definition MK60D10.h:12124
ENET_Type::ATSTMP
__IO uint32_t ATSTMP
Definition MK60D10.h:4747
SIM_Type::SOPT1CFG
__IO uint32_t SOPT1CFG
Definition MK60D10.h:10119
FTM_Type::CNTIN
__IO uint32_t CNTIN
Definition MK60D10.h:6181
DMA_Type::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition MK60D10.h:3752
I2C_Type::A1
__IO uint8_t A1
Definition MK60D10.h:6948
UART_Type::WF7816
__IO uint8_t WF7816
Definition MK60D10.h:11480
AXBS_Type::PRS
__IO uint32_t PRS
Definition MK60D10.h:2034
PORT_Type::DFER
__IO uint32_t DFER
Definition MK60D10.h:8839
DMA_Type::CSR
__IO uint16_t CSR
Definition MK60D10.h:3762
FB_Type::CSCR
__IO uint32_t CSCR
Definition MK60D10.h:5626
SDHC_Type::WML
__IO uint32_t WML
Definition MK60D10.h:9535
AIPS_Type::PACRE
__IO uint32_t PACRE
Definition MK60D10.h:734
FTM_Type::OUTMASK
__IO uint32_t OUTMASK
Definition MK60D10.h:6186
AXBS_Type::MGPCR0
__IO uint32_t MGPCR0
Definition MK60D10.h:2040
UART_Type::BDH
__IO uint8_t BDH
Definition MK60D10.h:11448
EWM_Type::CLKPRESCALER
__IO uint8_t CLKPRESCALER
Definition MK60D10.h:5543
FTFL_Type::FCCOB3
__IO uint8_t FCCOB3
Definition MK60D10.h:5957
SPI_Type::MCR
__IO uint32_t MCR
Definition MK60D10.h:10646
ENET_Type::ATCOR
__IO uint32_t ATCOR
Definition MK60D10.h:4745
SDHC_Type::ADMAES
__I uint32_t ADMAES
Definition MK60D10.h:9538
DMA_Type::DCHPRI14
__IO uint8_t DCHPRI14
Definition MK60D10.h:3741
DMA_Type::CR
__IO uint32_t CR
Definition MK60D10.h:3707
DMA_Type::DCHPRI8
__IO uint8_t DCHPRI8
Definition MK60D10.h:3739
GPIO_Type::PSOR
__O uint32_t PSOR
Definition MK60D10.h:6854
CMT_Type::CMD4
__IO uint8_t CMD4
Definition MK60D10.h:3251
MCM_Type::ETBRL
__IO uint32_t ETBRL
Definition MK60D10.h:8120
SPI_Type::TXFR3
__I uint32_t TXFR3
Definition MK60D10.h:10664
ENET_Type::RMON_T_BC_PKT
__IO uint32_t RMON_T_BC_PKT
Definition MK60D10.h:4687
NV_Type::FPROT3
__I uint8_t FPROT3
Definition MK60D10.h:8244
ENET_Type::IEEE_T_OCTETS_OK
__I uint32_t IEEE_T_OCTETS_OK
Definition MK60D10.h:4714
PIT_Type::LDVAL
__IO uint32_t LDVAL
Definition MK60D10.h:8644
CMT_Type::DMA
__IO uint8_t DMA
Definition MK60D10.h:3253
ENET_Type::RMON_T_P128TO255
__IO uint32_t RMON_T_P128TO255
Definition MK60D10.h:4697
SIM_Type::FCFG2
__I uint32_t FCFG2
Definition MK60D10.h:10139
ENET_Type::RMON_R_CRC_ALIGN
__IO uint32_t RMON_R_CRC_ALIGN
Definition MK60D10.h:4719
FMC_Type::DATA_U
__IO uint32_t DATA_U
Definition MK60D10.h:5763
DMA_Type::DCHPRI7
__IO uint8_t DCHPRI7
Definition MK60D10.h:3732
DMA_Type::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition MK60D10.h:3751
GPIO_Type::PCOR
__O uint32_t PCOR
Definition MK60D10.h:6855
SPI_Type::PUSHR
__IO uint32_t PUSHR
Definition MK60D10.h:10657
CMT_Type::OC
__IO uint8_t OC
Definition MK60D10.h:3246
CMP_Type::MUXCR
__IO uint8_t MUXCR
Definition MK60D10.h:3110
I2C_Type::RA
__IO uint8_t RA
Definition MK60D10.h:6955
USBDCD_Type::TIMER0
__IO uint32_t TIMER0
Definition MK60D10.h:12543
USBDCD_Type::TIMER1
__IO uint32_t TIMER1
Definition MK60D10.h:12544
DMA_Type::CINT
__O uint8_t CINT
Definition MK60D10.h:3720
ENET_Type::RMON_T_P65TO127
__IO uint32_t RMON_T_P65TO127
Definition MK60D10.h:4696
RTC_Type::WAR
__IO uint32_t WAR
Definition MK60D10.h:9315
ENET_Type::IEEE_T_DROP
__IO uint32_t IEEE_T_DROP
Definition MK60D10.h:4703
TSI_Type::CNTR9
__I uint32_t CNTR9
Definition MK60D10.h:11201
USBDCD_Type::TIMER2
__IO uint32_t TIMER2
Definition MK60D10.h:12545
SIM_Type::SOPT1
__IO uint32_t SOPT1
Definition MK60D10.h:10118
CAU_Type::STR_CAA
__I uint32_t STR_CAA
Definition MK60D10.h:2599
PDB_Type::INTC
__IO uint32_t INTC
Definition MK60D10.h:8466
USB_Type::ADDINFO
__I uint8_t ADDINFO
Definition MK60D10.h:12096
MCG_Type::C1
__IO uint8_t C1
Definition MK60D10.h:7876
ADC_Type::CLMD
__IO uint32_t CLMD
Definition MK60D10.h:469
SIM_Type::SCGC1
__IO uint32_t SCGC1
Definition MK60D10.h:10129
ADC_Type::SC2
__IO uint32_t SC2
Definition MK60D10.h:456
UART_Type::MA1
__IO uint8_t MA1
Definition MK60D10.h:11456
SIM_Type::SCGC2
__IO uint32_t SCGC2
Definition MK60D10.h:10130
FTFL_Type::FCCOB6
__IO uint8_t FCCOB6
Definition MK60D10.h:5962
ENET_Type::MIBC
__IO uint32_t MIBC
Definition MK60D10.h:4651
ENET_Type::IEEE_T_CSERR
__IO uint32_t IEEE_T_CSERR
Definition MK60D10.h:4711
LPTMR_Type::PSR
__IO uint32_t PSR
Definition MK60D10.h:7784
SYSMPU_Type::CESR
__IO uint32_t CESR
Definition MK60D10.h:10979
I2S_Type::RCR1
__IO uint32_t RCR1
Definition MK60D10.h:7164
UART_Type::TIDT
__IO uint8_t TIDT
Definition MK60D10.h:11500
ENET_Type::RSFL
__IO uint32_t RSFL
Definition MK60D10.h:4672
ENET_Type::TACC
__IO uint32_t TACC
Definition MK60D10.h:4682
CAN_Type::ESR2
__I uint32_t ESR2
Definition MK60D10.h:2181
LLWU_Type::F1
__IO uint8_t F1
Definition MK60D10.h:7542
ENET_Type::OPD
__IO uint32_t OPD
Definition MK60D10.h:4659
UART_Type::TWFIFO
__IO uint8_t TWFIFO
Definition MK60D10.h:11467
CAN_Type::CTRL1
__IO uint32_t CTRL1
Definition MK60D10.h:2168
ADC_Type::CLPS
__IO uint32_t CLPS
Definition MK60D10.h:462
ENET_Type::IEEE_R_DROP
__IO uint32_t IEEE_R_DROP
Definition MK60D10.h:4733
USB_Type::USBCTRL
__IO uint8_t USBCTRL
Definition MK60D10.h:12138
UART_Type::C1
__IO uint8_t C1
Definition MK60D10.h:11450
UART_Type::ED
__I uint8_t ED
Definition MK60D10.h:11460
SDHC_Type::MMCBOOT
__IO uint32_t MMCBOOT
Definition MK60D10.h:9542
ENET_Type::ATOFF
__IO uint32_t ATOFF
Definition MK60D10.h:4743
MCM_Type::ISR
__IO uint32_t ISR
Definition MK60D10.h:8118
SIM_Type::UIDL
__I uint32_t UIDL
Definition MK60D10.h:10143
MCM_Type::ETBCC
__IO uint32_t ETBCC
Definition MK60D10.h:8119
I2C_Type::SLTL
__IO uint8_t SLTL
Definition MK60D10.h:6959
MCM_Type::PLASC
__I uint16_t PLASC
Definition MK60D10.h:8115
FTM_Type::DEADTIME
__IO uint32_t DEADTIME
Definition MK60D10.h:6188
CAN_Type::CTRL2
__IO uint32_t CTRL2
Definition MK60D10.h:2180
MCG_Type::SC
__IO uint8_t SC
Definition MK60D10.h:7884
TSI_Type::GENCS
__IO uint32_t GENCS
Definition MK60D10.h:11192
RTC_Type::IER
__IO uint32_t IER
Definition MK60D10.h:9313
SDHC_Type::CMDARG
__IO uint32_t CMDARG
Definition MK60D10.h:9523
UART_Type::BDL
__IO uint8_t BDL
Definition MK60D10.h:11449
ENET_Type::PALR
__IO uint32_t PALR
Definition MK60D10.h:4657
ENET_Type::TSEM
__IO uint32_t TSEM
Definition MK60D10.h:4676
FTFL_Type::FCCOB9
__IO uint8_t FCCOB9
Definition MK60D10.h:5967
FTM_Type::SYNCONF
__IO uint32_t SYNCONF
Definition MK60D10.h:6197
UART_Type::TCFIFO
__I uint8_t TCFIFO
Definition MK60D10.h:11468
NV_Type::BACKKEY0
__I uint8_t BACKKEY0
Definition MK60D10.h:8239
DMA_Type::DCHPRI0
__IO uint8_t DCHPRI0
Definition MK60D10.h:3731
TSI_Type::CNTR7
__I uint32_t CNTR7
Definition MK60D10.h:11200
FTFL_Type::FCCOB2
__IO uint8_t FCCOB2
Definition MK60D10.h:5958
CRC_Type::GPOLYHL
__IO uint8_t GPOLYHL
Definition MK60D10.h:3405
ADC_Type::CLM0
__IO uint32_t CLM0
Definition MK60D10.h:475
USB_Type::ADDR
__IO uint8_t ADDR
Definition MK60D10.h:12118
ADC_Type::CLM1
__IO uint32_t CLM1
Definition MK60D10.h:474
TSI_Type::CNTR13
__I uint32_t CNTR13
Definition MK60D10.h:11203
FB_Type::CSMR
__IO uint32_t CSMR
Definition MK60D10.h:5625
USBDCD_Type::CLOCK
__IO uint32_t CLOCK
Definition MK60D10.h:12540
SDHC_Type::IRQSIGEN
__IO uint32_t IRQSIGEN
Definition MK60D10.h:9532
EWM_Type::SERV
__O uint8_t SERV
Definition MK60D10.h:5539
ADC_Type::CLM3
__IO uint32_t CLM3
Definition MK60D10.h:472
SPI_Type::RXFR1
__I uint32_t RXFR1
Definition MK60D10.h:10667
CAU_Type::AESC_CASR
__O uint32_t AESC_CASR
Definition MK60D10.h:2618
ENET_Type::RMON_R_P_GTE2048
__IO uint32_t RMON_R_P_GTE2048
Definition MK60D10.h:4731
PORT_Type::DFCR
__IO uint32_t DFCR
Definition MK60D10.h:8840
I2C_Type::C1
__IO uint8_t C1
Definition MK60D10.h:6950
TSI_Type::CNTR15
__I uint32_t CNTR15
Definition MK60D10.h:11204
ENET_Type::IEEE_T_FDXFC
__IO uint32_t IEEE_T_FDXFC
Definition MK60D10.h:4713
AIPS_Type::PACRN
__IO uint32_t PACRN
Definition MK60D10.h:743
ENET_Type::RMON_T_COL
__IO uint32_t RMON_T_COL
Definition MK60D10.h:4694
AXBS_Type::CRS
__IO uint32_t CRS
Definition MK60D10.h:2036
WDOG_Type::WINL
__IO uint16_t WINL
Definition MK60D10.h:12732
I2S_Type::TCR5
__IO uint32_t TCR5
Definition MK60D10.h:7155
SDHC_Type::AC12ERR
__I uint32_t AC12ERR
Definition MK60D10.h:9533
FTFL_Type::FCCOBA
__IO uint8_t FCCOBA
Definition MK60D10.h:5966
AIPS_Type::PACRH
__IO uint32_t PACRH
Definition MK60D10.h:737
VREF_Type::SC
__IO uint8_t SC
Definition MK60D10.h:12658
ENET_Type::RMON_R_OVERSIZE
__IO uint32_t RMON_R_OVERSIZE
Definition MK60D10.h:4721
WDOG_Type::RSTCNT
__IO uint16_t RSTCNT
Definition MK60D10.h:12737
EWM_Type::CMPH
__IO uint8_t CMPH
Definition MK60D10.h:5541
CRC_Type::CRCHU
__IO uint8_t CRCHU
Definition MK60D10.h:3393
ENET_Type::RMON_T_P1024TO2047
__IO uint32_t RMON_T_P1024TO2047
Definition MK60D10.h:4700
LLWU_Type::PE2
__IO uint8_t PE2
Definition MK60D10.h:7538
ENET_Type::ATPER
__IO uint32_t ATPER
Definition MK60D10.h:4744
DMA_Type::CDNE
__O uint8_t CDNE
Definition MK60D10.h:3717
DMA_Type::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition MK60D10.h:3758
UART_Type::IE7816
__IO uint8_t IE7816
Definition MK60D10.h:11473
NV_Type::BACKKEY3
__I uint8_t BACKKEY3
Definition MK60D10.h:8236
EWM_Type::CMPL
__IO uint8_t CMPL
Definition MK60D10.h:5540
DMA_Type::SSRT
__O uint8_t SSRT
Definition MK60D10.h:3718
CAN_Type::WORD0
__IO uint32_t WORD0
Definition MK60D10.h:2190
DMA_Type::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition MK60D10.h:3750
ENET_Type::IEEE_T_MACERR
__IO uint32_t IEEE_T_MACERR
Definition MK60D10.h:4710
LPTMR_Type::CNR
__IO uint32_t CNR
Definition MK60D10.h:7786
WDOG_Type::REFRESH
__IO uint16_t REFRESH
Definition MK60D10.h:12733
CAN_Type::ESR1
__IO uint32_t ESR1
Definition MK60D10.h:2175
RCM_Type::SRS0
__I uint8_t SRS0
Definition MK60D10.h:8974
SPI_Type::RXFR2
__I uint32_t RXFR2
Definition MK60D10.h:10668
AIPS_Type::PACRO
__IO uint32_t PACRO
Definition MK60D10.h:744
CAU_Type::AESIC_CASR
__O uint32_t AESIC_CASR
Definition MK60D10.h:2622
FTFL_Type::FCCOB7
__IO uint8_t FCCOB7
Definition MK60D10.h:5961
FMC_Type::DATA_L
__IO uint32_t DATA_L
Definition MK60D10.h:5764
CAN_Type::ID
__IO uint32_t ID
Definition MK60D10.h:2189
DMA_Type::SADDR
__IO uint32_t SADDR
Definition MK60D10.h:3746
MCG_Type::S
__IO uint8_t S
Definition MK60D10.h:7882
AIPS_Type::PACRP
__IO uint32_t PACRP
Definition MK60D10.h:745
CMT_Type::CGH2
__IO uint8_t CGH2
Definition MK60D10.h:3244
RNG_Type::CR
__IO uint32_t CR
Definition MK60D10.h:9207
NV_Type::FEPROT
__I uint8_t FEPROT
Definition MK60D10.h:8250
TSI_Type::WUCNTR
__I uint32_t WUCNTR
Definition MK60D10.h:11195
DMA_Type::SEEI
__O uint8_t SEEI
Definition MK60D10.h:3714
ENET_Type::TDAR
__IO uint32_t TDAR
Definition MK60D10.h:4644
FTFL_Type::FCCOB1
__IO uint8_t FCCOB1
Definition MK60D10.h:5959
FB_Type::CSPMCR
__IO uint32_t CSPMCR
Definition MK60D10.h:5629
SYSMPU_Type::EAR
__I uint32_t EAR
Definition MK60D10.h:10982
LPTMR_Type::CMR
__IO uint32_t CMR
Definition MK60D10.h:7785
TSI_Type::CNTR1
__I uint32_t CNTR1
Definition MK60D10.h:11197
DMA_Type::SERQ
__O uint8_t SERQ
Definition MK60D10.h:3716
FTM_Type::STATUS
__IO uint32_t STATUS
Definition MK60D10.h:6182
USB_Type::OBSERVE
__I uint8_t OBSERVE
Definition MK60D10.h:12140
LLWU_Type::FILT1
__IO uint8_t FILT1
Definition MK60D10.h:7545
ENET_Type::TDSR
__IO uint32_t TDSR
Definition MK60D10.h:4669
AXBS_Type::MGPCR4
__IO uint32_t MGPCR4
Definition MK60D10.h:2048
DMA_Type::CERQ
__O uint8_t CERQ
Definition MK60D10.h:3715
NV_Type::FOPT
__I uint8_t FOPT
Definition MK60D10.h:8249
FTFL_Type::FEPROT
__IO uint8_t FEPROT
Definition MK60D10.h:5974
FTFL_Type::FPROT0
__IO uint8_t FPROT0
Definition MK60D10.h:5972
CMT_Type::CMD2
__IO uint8_t CMD2
Definition MK60D10.h:3249
ENET_Type::IEEE_T_1COL
__IO uint32_t IEEE_T_1COL
Definition MK60D10.h:4705
AIPS_Type::PACRD
__IO uint32_t PACRD
Definition MK60D10.h:732
UART_Type::S4
__IO uint8_t S4
Definition MK60D10.h:11495
ENET_Type::IAUR
__IO uint32_t IAUR
Definition MK60D10.h:4661
AXBS_Type::MGPCR2
__IO uint32_t MGPCR2
Definition MK60D10.h:2044
CRC_Type::GPOLYL
__IO uint16_t GPOLYL
Definition MK60D10.h:3398
ENET_Type::RMON_R_BC_PKT
__IO uint32_t RMON_R_BC_PKT
Definition MK60D10.h:4717
USB_Type::ISTAT
__IO uint8_t ISTAT
Definition MK60D10.h:12106
UART_Type::C4
__IO uint8_t C4
Definition MK60D10.h:11458
SDHC_Type::XFERTYP
__IO uint32_t XFERTYP
Definition MK60D10.h:9524
ENET_Type::RMON_T_MC_PKT
__IO uint32_t RMON_T_MC_PKT
Definition MK60D10.h:4688
ENET_Type::RMON_R_P512TO1023
__IO uint32_t RMON_R_P512TO1023
Definition MK60D10.h:4729
ADC_Type::CLMS
__IO uint32_t CLMS
Definition MK60D10.h:470
TSI_Type::CNTR11
__I uint32_t CNTR11
Definition MK60D10.h:11202
ENET_Type::RDAR
__IO uint32_t RDAR
Definition MK60D10.h:4643
AIPS_Type::PACRF
__IO uint32_t PACRF
Definition MK60D10.h:735
FTM_Type::CNT
__IO uint32_t CNT
Definition MK60D10.h:6175
NV_Type::BACKKEY2
__I uint8_t BACKKEY2
Definition MK60D10.h:8237
CRC_Type::GPOLY
__IO uint32_t GPOLY
Definition MK60D10.h:3401
UART_Type::S1
__I uint8_t S1
Definition MK60D10.h:11452
CAN_Type::IMASK1
__IO uint32_t IMASK1
Definition MK60D10.h:2177
ENET_Type::RMON_R_RESVD_0
__IO uint32_t RMON_R_RESVD_0
Definition MK60D10.h:4724
ENET_Type::RMON_R_P128TO255
__IO uint32_t RMON_R_P128TO255
Definition MK60D10.h:4727
DMA_Type::DCHPRI15
__IO uint8_t DCHPRI15
Definition MK60D10.h:3740
I2S_Type::RMR
__IO uint32_t RMR
Definition MK60D10.h:7174
CRC_Type::CRCH
__IO uint16_t CRCH
Definition MK60D10.h:3386
RTC_Type::RAR
__IO uint32_t RAR
Definition MK60D10.h:9316
SIM_Type::SCGC4
__IO uint32_t SCGC4
Definition MK60D10.h:10132
AIPS_Type::PACRL
__IO uint32_t PACRL
Definition MK60D10.h:741
FTM_Type::SWOCTRL
__IO uint32_t SWOCTRL
Definition MK60D10.h:6199
PORT_Type::GPCLR
__O uint32_t GPCLR
Definition MK60D10.h:8834
UART_Type::PRE
__IO uint8_t PRE
Definition MK60D10.h:11490
CRC_Type::GPOLYLU
__IO uint8_t GPOLYLU
Definition MK60D10.h:3404
RTC_Type::TPR
__IO uint32_t TPR
Definition MK60D10.h:9307
TSI_Type::PEN
__IO uint32_t PEN
Definition MK60D10.h:11194
DMA_Type::CEEI
__O uint8_t CEEI
Definition MK60D10.h:3713
ENET_Type::RDSR
__IO uint32_t RDSR
Definition MK60D10.h:4668
SMC_Type::PMCTRL
__IO uint8_t PMCTRL
Definition MK60D10.h:10562
SDHC_Type::SYSCTL
__IO uint32_t SYSCTL
Definition MK60D10.h:9529
UART_Type::CPW
__IO uint8_t CPW
Definition MK60D10.h:11498
MCG_Type::C5
__IO uint8_t C5
Definition MK60D10.h:7880
FMC_Type::PFAPR
__IO uint32_t PFAPR
Definition MK60D10.h:5756
CMT_Type::CMD1
__IO uint8_t CMD1
Definition MK60D10.h:3248
DMA_Type::ES
__I uint32_t ES
Definition MK60D10.h:3708
FB_Type::CSAR
__IO uint32_t CSAR
Definition MK60D10.h:5624
ENET_Type::IEEE_R_MACERR
__IO uint32_t IEEE_R_MACERR
Definition MK60D10.h:4737
SPI_Type::TXFR1
__I uint32_t TXFR1
Definition MK60D10.h:10662
DMA_Type::DCHPRI6
__IO uint8_t DCHPRI6
Definition MK60D10.h:3733
PMC_Type::LVDSC2
__IO uint8_t LVDSC2
Definition MK60D10.h:8741
DMA_Type::DCHPRI1
__IO uint8_t DCHPRI1
Definition MK60D10.h:3730
CMT_Type::CGL1
__IO uint8_t CGL1
Definition MK60D10.h:3243
ENET_Type::ATCR
__IO uint32_t ATCR
Definition MK60D10.h:4741
SDHC_Type::BLKATTR
__IO uint32_t BLKATTR
Definition MK60D10.h:9522
PDB_Type::CNT
__I uint32_t CNT
Definition MK60D10.h:8456
UART_Type::WP7816T0
__IO uint8_t WP7816T0
Definition MK60D10.h:11476
SYSMPU_Type::EDR
__I uint32_t EDR
Definition MK60D10.h:10983
ENET_Type::RMON_R_MC_PKT
__IO uint32_t RMON_R_MC_PKT
Definition MK60D10.h:4718
I2S_Type::RCR2
__IO uint32_t RCR2
Definition MK60D10.h:7165
SDHC_Type::DSADDR
__IO uint32_t DSADDR
Definition MK60D10.h:9521
UART_Type::TL7816
__IO uint8_t TL7816
Definition MK60D10.h:11482
FTFL_Type::FDPROT
__IO uint8_t FDPROT
Definition MK60D10.h:5975
UART_Type::C6
__IO uint8_t C6
Definition MK60D10.h:11484
ENET_Type::MSCR
__IO uint32_t MSCR
Definition MK60D10.h:4649
I2S_Type::TCSR
__IO uint32_t TCSR
Definition MK60D10.h:7150
PIT_Type::MCR
__IO uint32_t MCR
Definition MK60D10.h:8641
CAU_Type::AESIC_CAA
__O uint32_t AESIC_CAA
Definition MK60D10.h:2623
ENET_Type::RMON_T_CRC_ALIGN
__IO uint32_t RMON_T_CRC_ALIGN
Definition MK60D10.h:4689
PDB_Type::S
__IO uint32_t S
Definition MK60D10.h:8460
FTM_Type::FLTCTRL
__IO uint32_t FLTCTRL
Definition MK60D10.h:6193
FTM_Type::COMBINE
__IO uint32_t COMBINE
Definition MK60D10.h:6187
DMA_Type::DOFF
__IO uint16_t DOFF
Definition MK60D10.h:3756
UART_Type::RCFIFO
__I uint8_t RCFIFO
Definition MK60D10.h:11470
CAU_Type::ADR_CAA
__O uint32_t ADR_CAA
Definition MK60D10.h:2603
SMC_Type::VLLSCTRL
__IO uint8_t VLLSCTRL
Definition MK60D10.h:10563
RTC_Type::CR
__IO uint32_t CR
Definition MK60D10.h:9310
USB_Type::OTGICR
__IO uint8_t OTGICR
Definition MK60D10.h:12100
DMA_Type::DCHPRI13
__IO uint8_t DCHPRI13
Definition MK60D10.h:3742
ENET_Type::TAFL
__IO uint32_t TAFL
Definition MK60D10.h:4678
RTC_Type::TAR
__IO uint32_t TAR
Definition MK60D10.h:9308
TSI_Type::CNTR3
__I uint32_t CNTR3
Definition MK60D10.h:11198
MCM_Type::CR
__IO uint32_t CR
Definition MK60D10.h:8117
RTC_Type::LR
__IO uint32_t LR
Definition MK60D10.h:9312
WDOG_Type::UNLOCK
__IO uint16_t UNLOCK
Definition MK60D10.h:12734
WDOG_Type::PRESC
__IO uint16_t PRESC
Definition MK60D10.h:12738
ADC_Type::CV1
__IO uint32_t CV1
Definition MK60D10.h:454
ENET_Type::EIMR
__IO uint32_t EIMR
Definition MK60D10.h:4641
SDHC_Type::IRQSTAT
__IO uint32_t IRQSTAT
Definition MK60D10.h:9530
FTFL_Type::FSEC
__I uint8_t FSEC
Definition MK60D10.h:5955
CRC_Type::CRCL
__IO uint16_t CRCL
Definition MK60D10.h:3385
ADC_Type::CV2
__IO uint32_t CV2
Definition MK60D10.h:455
ENET_Type::TFWR
__IO uint32_t TFWR
Definition MK60D10.h:4666
SDHC_Type::FEVT
__O uint32_t FEVT
Definition MK60D10.h:9537
ENET_Type::IEEE_R_FRAME_OK
__IO uint32_t IEEE_R_FRAME_OK
Definition MK60D10.h:4734
SIM_Type::CLKDIV2
__IO uint32_t CLKDIV2
Definition MK60D10.h:10137
ENET_Type::IALR
__IO uint32_t IALR
Definition MK60D10.h:4662
UART_Type::PFIFO
__IO uint8_t PFIFO
Definition MK60D10.h:11464
CAU_Type::ADR_CASR
__O uint32_t ADR_CASR
Definition MK60D10.h:2602
LLWU_Type::RST
__IO uint8_t RST
Definition MK60D10.h:7547
DAC_Type::SR
__IO uint8_t SR
Definition MK60D10.h:3579
SIM_Type::SOPT7
__IO uint32_t SOPT7
Definition MK60D10.h:10126
DMA_Type::DCHPRI11
__IO uint8_t DCHPRI11
Definition MK60D10.h:3736
RCM_Type::RPFC
__IO uint8_t RPFC
Definition MK60D10.h:8977
SIM_Type::FCFG1
__IO uint32_t FCFG1
Definition MK60D10.h:10138
SPI_Type::SR
__IO uint32_t SR
Definition MK60D10.h:10654
I2C_Type::FLT
__IO uint8_t FLT
Definition MK60D10.h:6954
WDOG_Type::TOVALH
__IO uint16_t TOVALH
Definition MK60D10.h:12729
WDOG_Type::TMROUTL
__IO uint16_t TMROUTL
Definition MK60D10.h:12736
SDHC_Type::PRSSTAT
__I uint32_t PRSSTAT
Definition MK60D10.h:9527
ENET_Type::FTRL
__IO uint32_t FTRL
Definition MK60D10.h:4680
ENET_Type::IEEE_T_MCOL
__IO uint32_t IEEE_T_MCOL
Definition MK60D10.h:4706
DMA_Type::EEI
__IO uint32_t EEI
Definition MK60D10.h:3712
MCM_Type::PID
__IO uint32_t PID
Definition MK60D10.h:8123
FTFL_Type::FCCOBB
__IO uint8_t FCCOBB
Definition MK60D10.h:5965
CMT_Type::CGH1
__IO uint8_t CGH1
Definition MK60D10.h:3242
CRC_Type::GPOLYHU
__IO uint8_t GPOLYHU
Definition MK60D10.h:3406
RNG_Type::OR
__I uint32_t OR
Definition MK60D10.h:9210
CMT_Type::MSC
__IO uint8_t MSC
Definition MK60D10.h:3247
CMT_Type::CGL2
__IO uint8_t CGL2
Definition MK60D10.h:3245
ENET_Type::GALR
__IO uint32_t GALR
Definition MK60D10.h:4664
USB_Type::CTL
__IO uint8_t CTL
Definition MK60D10.h:12116
ENET_Type::RMON_T_P64
__IO uint32_t RMON_T_P64
Definition MK60D10.h:4695
CAN_Type::MCR
__IO uint32_t MCR
Definition MK60D10.h:2167
ENET_Type::ATINC
__IO uint32_t ATINC
Definition MK60D10.h:4746
ENET_Type::RMON_R_UNDERSIZE
__IO uint32_t RMON_R_UNDERSIZE
Definition MK60D10.h:4720
FTM_Type::SYNC
__IO uint32_t SYNC
Definition MK60D10.h:6184
CAU_Type::XOR_CAA
__O uint32_t XOR_CAA
Definition MK60D10.h:2611
CAU_Type::LDR_CASR
__O uint32_t LDR_CASR
Definition MK60D10.h:2594
UART_Type::C5
__IO uint8_t C5
Definition MK60D10.h:11459
DAC_Type::DATH
__IO uint8_t DATH
Definition MK60D10.h:3577
UART_Type::IR
__IO uint8_t IR
Definition MK60D10.h:11462
CMP_Type::CR0
__IO uint8_t CR0
Definition MK60D10.h:3105
NV_Type::BACKKEY1
__I uint8_t BACKKEY1
Definition MK60D10.h:8238
UART_Type::S2
__IO uint8_t S2
Definition MK60D10.h:11453
SIM_Type::SDID
__I uint32_t SDID
Definition MK60D10.h:10128
UART_Type::ET7816
__IO uint8_t ET7816
Definition MK60D10.h:11481
USB_Type::OTGSTAT
__IO uint8_t OTGSTAT
Definition MK60D10.h:12102
PORT_Type::GPCHR
__O uint32_t GPCHR
Definition MK60D10.h:8835
FTM_Type::FMS
__IO uint32_t FMS
Definition MK60D10.h:6191
MCG_Type::C9
__I uint8_t C9
Definition MK60D10.h:7890
ENET_Type::RMON_R_PACKETS
__IO uint32_t RMON_R_PACKETS
Definition MK60D10.h:4716
ENET_Type::IEEE_T_LCOL
__IO uint32_t IEEE_T_LCOL
Definition MK60D10.h:4708
FMC_Type::PFB0CR
__IO uint32_t PFB0CR
Definition MK60D10.h:5757
SDHC_Type::VENDOR
__IO uint32_t VENDOR
Definition MK60D10.h:9541
MCG_Type::C8
__IO uint8_t C8
Definition MK60D10.h:7889
NV_Type::BACKKEY7
__I uint8_t BACKKEY7
Definition MK60D10.h:8240
LLWU_Type::ME
__IO uint8_t ME
Definition MK60D10.h:7541
ENET_Type::RMON_R_P1024TO2047
__IO uint32_t RMON_R_P1024TO2047
Definition MK60D10.h:4730
ENET_Type::RMON_T_P512TO1023
__IO uint32_t RMON_T_P512TO1023
Definition MK60D10.h:4699
ENET_Type::RMON_T_PACKETS
__IO uint32_t RMON_T_PACKETS
Definition MK60D10.h:4686
I2S_Type::TCR4
__IO uint32_t TCR4
Definition MK60D10.h:7154
DMA_Type::DCHPRI9
__IO uint8_t DCHPRI9
Definition MK60D10.h:3738
RTC_Type::SR
__IO uint32_t SR
Definition MK60D10.h:9311
SIM_Type::SCGC6
__IO uint32_t SCGC6
Definition MK60D10.h:10134
NV_Type::BACKKEY5
__I uint8_t BACKKEY5
Definition MK60D10.h:8242
CRC_Type::CRCLL
__IO uint8_t CRCLL
Definition MK60D10.h:3390
USB_Type::ENDPT
__IO uint8_t ENDPT
Definition MK60D10.h:12135
USB_Type::BDTPAGE1
__IO uint8_t BDTPAGE1
Definition MK60D10.h:12120
AIPS_Type::PACRM
__IO uint32_t PACRM
Definition MK60D10.h:742
DMA_Type::DCHPRI3
__IO uint8_t DCHPRI3
Definition MK60D10.h:3728
ADC_Type::CLM4
__IO uint32_t CLM4
Definition MK60D10.h:471
PDB_Type::MOD
__IO uint32_t MOD
Definition MK60D10.h:8455
CAN_Type::RXFGMASK
__IO uint32_t RXFGMASK
Definition MK60D10.h:2184
FTM_Type::EXTTRIG
__IO uint32_t EXTTRIG
Definition MK60D10.h:6189
UART_Type::S3
__IO uint8_t S3
Definition MK60D10.h:11494
CRC_Type::CRC
__IO uint32_t CRC
Definition MK60D10.h:3388
ENET_Type::RMON_R_P256TO511
__IO uint32_t RMON_R_P256TO511
Definition MK60D10.h:4728
PDB_Type::INT
__IO uint32_t INT
Definition MK60D10.h:8467
DMA_Type::DCHPRI4
__IO uint8_t DCHPRI4
Definition MK60D10.h:3735
MCG_Type::C4
__IO uint8_t C4
Definition MK60D10.h:7879
MCG_Type::ATCVL
__IO uint8_t ATCVL
Definition MK60D10.h:7887
DMA_Type::DADDR
__IO uint32_t DADDR
Definition MK60D10.h:3755
UART_Type::PCTL
__IO uint8_t PCTL
Definition MK60D10.h:11486
AIPS_Type::MPRA
__IO uint32_t MPRA
Definition MK60D10.h:727
AXBS_Type::MGPCR3
__IO uint32_t MGPCR3
Definition MK60D10.h:2046
ENET_Type::RMON_T_OCTETS
__I uint32_t RMON_T_OCTETS
Definition MK60D10.h:4702
LLWU_Type::PE3
__IO uint8_t PE3
Definition MK60D10.h:7539
CAN_Type::CS
__IO uint32_t CS
Definition MK60D10.h:2188
SMC_Type::PMPROT
__IO uint8_t PMPROT
Definition MK60D10.h:10561
SPI_Type::RXFR3
__I uint32_t RXFR3
Definition MK60D10.h:10669
FTM_Type::MOD
__IO uint32_t MOD
Definition MK60D10.h:6176
USB_Type::REV
__I uint8_t REV
Definition MK60D10.h:12094
I2S_Type::MDR
__IO uint32_t MDR
Definition MK60D10.h:7177
GPIO_Type::PTOR
__O uint32_t PTOR
Definition MK60D10.h:6856
WDOG_Type::TMROUTH
__IO uint16_t TMROUTH
Definition MK60D10.h:12735
DMA_Type::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition MK60D10.h:3764
FTFL_Type::FCCOB4
__IO uint8_t FCCOB4
Definition MK60D10.h:5964
FTM_Type::OUTINIT
__IO uint32_t OUTINIT
Definition MK60D10.h:6185
FTM_Type::CONF
__IO uint32_t CONF
Definition MK60D10.h:6195
DMA_Type::DLAST_SGA
__IO uint32_t DLAST_SGA
Definition MK60D10.h:3761
ENET_Type::IEEE_T_SQE
__IO uint32_t IEEE_T_SQE
Definition MK60D10.h:4712
USB_Type::FRMNUML
__IO uint8_t FRMNUML
Definition MK60D10.h:12122
FTFL_Type::FCCOB8
__IO uint8_t FCCOB8
Definition MK60D10.h:5968
ENET_Type::TIPG
__IO uint32_t TIPG
Definition MK60D10.h:4679
USB_Type::BDTPAGE2
__IO uint8_t BDTPAGE2
Definition MK60D10.h:12130
FTFL_Type::FCNFG
__IO uint8_t FCNFG
Definition MK60D10.h:5954
FTM_Type::FLTPOL
__IO uint32_t FLTPOL
Definition MK60D10.h:6196
USB_Type::ERRSTAT
__IO uint8_t ERRSTAT
Definition MK60D10.h:12110
LLWU_Type::PE1
__IO uint8_t PE1
Definition MK60D10.h:7537
SMC_Type::PMSTAT
__I uint8_t PMSTAT
Definition MK60D10.h:10564
SPI_Type::RXFR0
__I uint32_t RXFR0
Definition MK60D10.h:10666
PIT_Type::TFLG
__IO uint32_t TFLG
Definition MK60D10.h:8647
PORT_Type::DFWR
__IO uint32_t DFWR
Definition MK60D10.h:8841
UART_Type::D
__IO uint8_t D
Definition MK60D10.h:11455
ADC_Type::SC3
__IO uint32_t SC3
Definition MK60D10.h:457
ADC_Type::CLPD
__IO uint32_t CLPD
Definition MK60D10.h:461
SPI_Type::TCR
__IO uint32_t TCR
Definition MK60D10.h:10648
CAU_Type::RADR_CASR
__O uint32_t RADR_CASR
Definition MK60D10.h:2606
PIT_Type::CVAL
__I uint32_t CVAL
Definition MK60D10.h:8645
UART_Type::MODEM
__IO uint8_t MODEM
Definition MK60D10.h:11461
CAU_Type::XOR_CASR
__O uint32_t XOR_CASR
Definition MK60D10.h:2610
CAN_Type::TIMER
__IO uint32_t TIMER
Definition MK60D10.h:2169
FMC_Type::PFB1CR
__IO uint32_t PFB1CR
Definition MK60D10.h:5758
DMA_Type::INT
__IO uint32_t INT
Definition MK60D10.h:3722
DAC_Type::C1
__IO uint8_t C1
Definition MK60D10.h:3581
OSC_Type::CR
__IO uint8_t CR
Definition MK60D10.h:8390
NV_Type::FSEC
__I uint8_t FSEC
Definition MK60D10.h:8248
DMA_Type::ERR
__IO uint32_t ERR
Definition MK60D10.h:3724
USB_Type::INTEN
__IO uint8_t INTEN
Definition MK60D10.h:12108
AXBS_Type::MGPCR1
__IO uint32_t MGPCR1
Definition MK60D10.h:2042
CAU_Type::AESC_CAA
__O uint32_t AESC_CAA
Definition MK60D10.h:2619
UART_Type::B1T
__IO uint8_t B1T
Definition MK60D10.h:11487
SDHC_Type::PROCTL
__IO uint32_t PROCTL
Definition MK60D10.h:9528
I2S_Type::RCR5
__IO uint32_t RCR5
Definition MK60D10.h:7168
USB_Type::IDCOMP
__I uint8_t IDCOMP
Definition MK60D10.h:12092
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition MK60D10.h:336
kDmaRequestMux0UART4Tx
@ kDmaRequestMux0UART4Tx
Definition MK60D10.h:348
kDmaRequestMux0FTM1Channel0
@ kDmaRequestMux0FTM1Channel0
Definition MK60D10.h:369
kDmaRequestMux0DAC0
@ kDmaRequestMux0DAC0
Definition MK60D10.h:382
kDmaRequestMux0FTM0Channel7
@ kDmaRequestMux0FTM0Channel7
Definition MK60D10.h:368
kDmaRequestMux0UART2Tx
@ kDmaRequestMux0UART2Tx
Definition MK60D10.h:344
kDmaRequestMux0I2C0
@ kDmaRequestMux0I2C0
Definition MK60D10.h:359
kDmaRequestMux0CMP0
@ kDmaRequestMux0CMP0
Definition MK60D10.h:379
kDmaRequestMux0DAC1
@ kDmaRequestMux0DAC1
Definition MK60D10.h:383
kDmaRequestMux0UART3Tx
@ kDmaRequestMux0UART3Tx
Definition MK60D10.h:346
kDmaRequestMux0CMP1
@ kDmaRequestMux0CMP1
Definition MK60D10.h:380
kDmaRequestMux0SPI1Tx
@ kDmaRequestMux0SPI1Tx
Definition MK60D10.h:356
kDmaRequestMux0IEEE1588Timer1
@ kDmaRequestMux0IEEE1588Timer1
Definition MK60D10.h:374
kDmaRequestMux0FTM2Channel1
@ kDmaRequestMux0FTM2Channel1
Definition MK60D10.h:372
kDmaRequestMux0I2S0Tx
@ kDmaRequestMux0I2S0Tx
Definition MK60D10.h:352
kDmaRequestMux0UART5Tx
@ kDmaRequestMux0UART5Tx
Definition MK60D10.h:350
kDmaRequestMux0PortE
@ kDmaRequestMux0PortE
Definition MK60D10.h:390
kDmaRequestMux0AlwaysOn63
@ kDmaRequestMux0AlwaysOn63
Definition MK60D10.h:400
kDmaRequestMux0IEEE1588Timer3
@ kDmaRequestMux0IEEE1588Timer3
Definition MK60D10.h:376
kDmaRequestMux0SPI0Tx
@ kDmaRequestMux0SPI0Tx
Definition MK60D10.h:354
kDmaRequestMux0FTM0Channel1
@ kDmaRequestMux0FTM0Channel1
Definition MK60D10.h:362
kDmaRequestMux0FTM0Channel5
@ kDmaRequestMux0FTM0Channel5
Definition MK60D10.h:366
kDmaRequestMux0FTM2Channel0
@ kDmaRequestMux0FTM2Channel0
Definition MK60D10.h:371
kDmaRequestMux0AlwaysOn61
@ kDmaRequestMux0AlwaysOn61
Definition MK60D10.h:398
kDmaRequestMux0UART1Tx
@ kDmaRequestMux0UART1Tx
Definition MK60D10.h:342
kDmaRequestMux0AlwaysOn54
@ kDmaRequestMux0AlwaysOn54
Definition MK60D10.h:391
kDmaRequestMux0SPI2Tx
@ kDmaRequestMux0SPI2Tx
Definition MK60D10.h:358
kDmaRequestMux0FTM0Channel6
@ kDmaRequestMux0FTM0Channel6
Definition MK60D10.h:367
kDmaRequestMux0UART3Rx
@ kDmaRequestMux0UART3Rx
Definition MK60D10.h:345
kDmaRequestMux0AlwaysOn56
@ kDmaRequestMux0AlwaysOn56
Definition MK60D10.h:393
kDmaRequestMux0AlwaysOn55
@ kDmaRequestMux0AlwaysOn55
Definition MK60D10.h:392
kDmaRequestMux0PDB0
@ kDmaRequestMux0PDB0
Definition MK60D10.h:385
kDmaRequestMux0UART1Rx
@ kDmaRequestMux0UART1Rx
Definition MK60D10.h:341
kDmaRequestMux0PortB
@ kDmaRequestMux0PortB
Definition MK60D10.h:387
kDmaRequestMux0ADC1
@ kDmaRequestMux0ADC1
Definition MK60D10.h:378
kDmaRequestMux0PortC
@ kDmaRequestMux0PortC
Definition MK60D10.h:388
kDmaRequestMux0FTM1Channel1
@ kDmaRequestMux0FTM1Channel1
Definition MK60D10.h:370
kDmaRequestMux0CMP2
@ kDmaRequestMux0CMP2
Definition MK60D10.h:381
kDmaRequestMux0Reserved1
@ kDmaRequestMux0Reserved1
Definition MK60D10.h:338
kDmaRequestMux0FTM0Channel4
@ kDmaRequestMux0FTM0Channel4
Definition MK60D10.h:365
kDmaRequestMux0CMT
@ kDmaRequestMux0CMT
Definition MK60D10.h:384
kDmaRequestMux0SPI2Rx
@ kDmaRequestMux0SPI2Rx
Definition MK60D10.h:357
kDmaRequestMux0I2S0Rx
@ kDmaRequestMux0I2S0Rx
Definition MK60D10.h:351
kDmaRequestMux0AlwaysOn60
@ kDmaRequestMux0AlwaysOn60
Definition MK60D10.h:397
kDmaRequestMux0AlwaysOn58
@ kDmaRequestMux0AlwaysOn58
Definition MK60D10.h:395
kDmaRequestMux0IEEE1588Timer0
@ kDmaRequestMux0IEEE1588Timer0
Definition MK60D10.h:373
kDmaRequestMux0Disable
@ kDmaRequestMux0Disable
Definition MK60D10.h:337
kDmaRequestMux0UART5Rx
@ kDmaRequestMux0UART5Rx
Definition MK60D10.h:349
kDmaRequestMux0PortA
@ kDmaRequestMux0PortA
Definition MK60D10.h:386
kDmaRequestMux0PortD
@ kDmaRequestMux0PortD
Definition MK60D10.h:389
kDmaRequestMux0UART4Rx
@ kDmaRequestMux0UART4Rx
Definition MK60D10.h:347
kDmaRequestMux0UART2Rx
@ kDmaRequestMux0UART2Rx
Definition MK60D10.h:343
kDmaRequestMux0ADC0
@ kDmaRequestMux0ADC0
Definition MK60D10.h:377
kDmaRequestMux0FTM0Channel3
@ kDmaRequestMux0FTM0Channel3
Definition MK60D10.h:364
kDmaRequestMux0IEEE1588Timer2
@ kDmaRequestMux0IEEE1588Timer2
Definition MK60D10.h:375
kDmaRequestMux0UART0Rx
@ kDmaRequestMux0UART0Rx
Definition MK60D10.h:339
kDmaRequestMux0AlwaysOn59
@ kDmaRequestMux0AlwaysOn59
Definition MK60D10.h:396
kDmaRequestMux0FTM0Channel0
@ kDmaRequestMux0FTM0Channel0
Definition MK60D10.h:361
kDmaRequestMux0SPI1Rx
@ kDmaRequestMux0SPI1Rx
Definition MK60D10.h:355
kDmaRequestMux0AlwaysOn62
@ kDmaRequestMux0AlwaysOn62
Definition MK60D10.h:399
kDmaRequestMux0AlwaysOn57
@ kDmaRequestMux0AlwaysOn57
Definition MK60D10.h:394
kDmaRequestMux0FTM0Channel2
@ kDmaRequestMux0FTM0Channel2
Definition MK60D10.h:363
kDmaRequestMux0UART0Tx
@ kDmaRequestMux0UART0Tx
Definition MK60D10.h:340
kDmaRequestMux0SPI0Rx
@ kDmaRequestMux0SPI0Rx
Definition MK60D10.h:353
kDmaRequestMux0I2C1
@ kDmaRequestMux0I2C1
Definition MK60D10.h:360
ADC_Type
Definition MK60D10.h:449
AIPS_Type
Definition MK60D10.h:726
AXBS_Type
Definition MK60D10.h:2032
CAN_Type
Definition MK60D10.h:2166
CAU_Type
Definition MK60D10.h:2591
CMP_Type
Definition MK60D10.h:3104
CMT_Type
Definition MK60D10.h:3241
CRC_Type
Definition MK60D10.h:3382
DAC_Type
Definition MK60D10.h:3574
DMAMUX_Type
Definition MK60D10.h:4580
DMA_Type
Definition MK60D10.h:3706
ENET_Type
Definition MK60D10.h:4638
EWM_Type
Definition MK60D10.h:5537
FB_Type
Definition MK60D10.h:5622
FMC_Type
Definition MK60D10.h:5755
FTFL_Type
Definition MK60D10.h:5952
FTM_Type
Definition MK60D10.h:6173
GPIO_Type
Definition MK60D10.h:6852
I2C_Type
Definition MK60D10.h:6947
I2S_Type
Definition MK60D10.h:7149
LLWU_Type
Definition MK60D10.h:7536
LPTMR_Type
Definition MK60D10.h:7782
MCG_Type
Definition MK60D10.h:7875
MCM_Type
Definition MK60D10.h:8113
NV_Type
Definition MK60D10.h:8235
OSC_Type
Definition MK60D10.h:8389
PDB_Type
Definition MK60D10.h:8453
PIT_Type
Definition MK60D10.h:8640
PMC_Type
Definition MK60D10.h:8739
PORT_Type
Definition MK60D10.h:8832
RCM_Type
Definition MK60D10.h:8973
RFSYS_Type
Definition MK60D10.h:9084
RFVBAT_Type
Definition MK60D10.h:9145
RNG_Type
Definition MK60D10.h:9206
RTC_Type
Definition MK60D10.h:9305
SDHC_Type
Definition MK60D10.h:9520
SIM_Type
Definition MK60D10.h:10117
SMC_Type
Definition MK60D10.h:10560
SPI_Type
Definition MK60D10.h:10645
SYSMPU_Type
Definition MK60D10.h:10978
TSI_Type
Definition MK60D10.h:11191
UART_Type
Definition MK60D10.h:11447
USBDCD_Type
Definition MK60D10.h:12538
USB_Type
Definition MK60D10.h:12089
VREF_Type
Definition MK60D10.h:12656
WDOG_Type
Definition MK60D10.h:12726