mikroSDK Reference Manual
MK64F12.h
Go to the documentation of this file.
1/*
2** ###################################################################
3** Processors: MK64FN1M0CAJ12
4** MK64FN1M0VDC12
5** MK64FN1M0VLL12
6** MK64FN1M0VLQ12
7** MK64FN1M0VMD12
8** MK64FX512VDC12
9** MK64FX512VLL12
10** MK64FX512VLQ12
11** MK64FX512VMD12
12**
13** Compilers: Keil ARM C/C++ Compiler
14** Freescale C/C++ for Embedded ARM
15** GNU C Compiler
16** IAR ANSI C/C++ Compiler for ARM
17** MCUXpresso Compiler
18**
19** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
20** Version: rev. 2.9, 2016-03-21
21** Build: b180801
22**
23** Abstract:
24** CMSIS Peripheral Access Layer for MK64F12
25**
26** Copyright 1997-2016 Freescale Semiconductor, Inc.
27** Copyright 2016-2018 NXP
28**
29** SPDX-License-Identifier: BSD-3-Clause
30**
31** http: www.nxp.com
32** mail: support@nxp.com
33**
34** Revisions:
35** - rev. 1.0 (2013-08-12)
36** Initial version.
37** - rev. 2.0 (2013-10-29)
38** Register accessor macros added to the memory map.
39** Symbols for Processor Expert memory map compatibility added to the memory map.
40** Startup file for gcc has been updated according to CMSIS 3.2.
41** System initialization updated.
42** MCG - registers updated.
43** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
44** - rev. 2.1 (2013-10-30)
45** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
46** - rev. 2.2 (2013-12-09)
47** DMA - EARS register removed.
48** AIPS0, AIPS1 - MPRA register updated.
49** - rev. 2.3 (2014-01-24)
50** Update according to reference manual rev. 2
51** ENET, MCG, MCM, SIM, USB - registers updated
52** - rev. 2.4 (2014-02-10)
53** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
54** Update of SystemInit() and SystemCoreClockUpdate() functions.
55** - rev. 2.5 (2014-02-10)
56** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
57** Update of SystemInit() and SystemCoreClockUpdate() functions.
58** Module access macro module_BASES replaced by module_BASE_PTRS.
59** - rev. 2.6 (2014-08-28)
60** Update of system files - default clock configuration changed.
61** Update of startup files - possibility to override DefaultISR added.
62** - rev. 2.7 (2014-10-14)
63** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
64** - rev. 2.8 (2015-02-19)
65** Renamed interrupt vector LLW to LLWU.
66** - rev. 2.9 (2016-03-21)
67** Added MK64FN1M0CAJ12 part.
68** GPIO - renamed port instances: PTx -> GPIOx.
69**
70** ###################################################################
71*/
72
82#ifndef _MK64F12_H_
83#define _MK64F12_H_
87#define MCU_MEM_MAP_VERSION 0x0200U
89#define MCU_MEM_MAP_VERSION_MINOR 0x0009U
90
99#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
108#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
109#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
118#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
127#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
128
129/* ----------------------------------------------------------------------------
130 -- Interrupt vector numbers
131 ---------------------------------------------------------------------------- */
132
139#define NUMBER_OF_INT_VECTORS 102
141typedef enum IRQn {
142 /* Auxiliary constants */
143 NotAvail_IRQn = -128,
145 /* Core interrupts */
146 NonMaskableInt_IRQn = -14,
147 HardFault_IRQn = -13,
148 MemoryManagement_IRQn = -12,
149 BusFault_IRQn = -11,
150 UsageFault_IRQn = -10,
151 SVCall_IRQn = -5,
152 DebugMonitor_IRQn = -4,
153 PendSV_IRQn = -2,
154 SysTick_IRQn = -1,
156 /* Device specific interrupts */
157 DMA0_IRQn = 0,
158 DMA1_IRQn = 1,
159 DMA2_IRQn = 2,
160 DMA3_IRQn = 3,
161 DMA4_IRQn = 4,
162 DMA5_IRQn = 5,
163 DMA6_IRQn = 6,
164 DMA7_IRQn = 7,
165 DMA8_IRQn = 8,
166 DMA9_IRQn = 9,
167 DMA10_IRQn = 10,
168 DMA11_IRQn = 11,
169 DMA12_IRQn = 12,
170 DMA13_IRQn = 13,
171 DMA14_IRQn = 14,
172 DMA15_IRQn = 15,
173 DMA_Error_IRQn = 16,
174 MCM_IRQn = 17,
175 FTFE_IRQn = 18,
176 Read_Collision_IRQn = 19,
177 LVD_LVW_IRQn = 20,
178 LLWU_IRQn = 21,
179 WDOG_EWM_IRQn = 22,
180 RNG_IRQn = 23,
181 I2C0_IRQn = 24,
182 I2C1_IRQn = 25,
183 SPI0_IRQn = 26,
184 SPI1_IRQn = 27,
185 I2S0_Tx_IRQn = 28,
186 I2S0_Rx_IRQn = 29,
187 UART0_LON_IRQn = 30,
188 UART0_RX_TX_IRQn = 31,
189 UART0_ERR_IRQn = 32,
190 UART1_RX_TX_IRQn = 33,
191 UART1_ERR_IRQn = 34,
192 UART2_RX_TX_IRQn = 35,
193 UART2_ERR_IRQn = 36,
194 UART3_RX_TX_IRQn = 37,
195 UART3_ERR_IRQn = 38,
196 ADC0_IRQn = 39,
197 CMP0_IRQn = 40,
198 CMP1_IRQn = 41,
199 FTM0_IRQn = 42,
200 FTM1_IRQn = 43,
201 FTM2_IRQn = 44,
202 CMT_IRQn = 45,
203 RTC_IRQn = 46,
204 RTC_Seconds_IRQn = 47,
205 PIT0_IRQn = 48,
206 PIT1_IRQn = 49,
207 PIT2_IRQn = 50,
208 PIT3_IRQn = 51,
209 PDB0_IRQn = 52,
210 USB0_IRQn = 53,
211 USBDCD_IRQn = 54,
212 Reserved71_IRQn = 55,
213 DAC0_IRQn = 56,
214 MCG_IRQn = 57,
215 LPTMR0_IRQn = 58,
216 PORTA_IRQn = 59,
217 PORTB_IRQn = 60,
218 PORTC_IRQn = 61,
219 PORTD_IRQn = 62,
220 PORTE_IRQn = 63,
221 SWI_IRQn = 64,
222 SPI2_IRQn = 65,
223 UART4_RX_TX_IRQn = 66,
224 UART4_ERR_IRQn = 67,
225 UART5_RX_TX_IRQn = 68,
226 UART5_ERR_IRQn = 69,
227 CMP2_IRQn = 70,
228 FTM3_IRQn = 71,
229 DAC1_IRQn = 72,
230 ADC1_IRQn = 73,
231 I2C2_IRQn = 74,
232 CAN0_ORed_Message_buffer_IRQn = 75,
233 CAN0_Bus_Off_IRQn = 76,
234 CAN0_Error_IRQn = 77,
235 CAN0_Tx_Warning_IRQn = 78,
236 CAN0_Rx_Warning_IRQn = 79,
237 CAN0_Wake_Up_IRQn = 80,
238 SDHC_IRQn = 81,
239 ENET_1588_Timer_IRQn = 82,
240 ENET_Transmit_IRQn = 83,
241 ENET_Receive_IRQn = 84,
242 ENET_Error_IRQn = 85
243} IRQn_Type;
244
247 /* end of group Interrupt_vector_numbers */
248
249
250/* ----------------------------------------------------------------------------
251 -- Cortex M4 Core Configuration
252 ---------------------------------------------------------------------------- */
253
259#define __MPU_PRESENT 0
260#define __NVIC_PRIO_BITS 4
261#define __Vendor_SysTickConfig 0
262#define __FPU_PRESENT 1
264#include "core_cm4.h" /* Core Peripheral Access Layer */
265#ifndef __PROJECT_MIKROSDK_MIKROE__
266// Note: Added for MikroE implementation.
267#include "system_MK64F12.h" /* Device specific configuration file */
268#endif
269
272 /* end of group Cortex_Core_Configuration */
273
274
275/* ----------------------------------------------------------------------------
276 -- Mapping Information
277 ---------------------------------------------------------------------------- */
278
290/*******************************************************************************
291 * Definitions
292 ******************************************************************************/
293
301typedef enum _dma_request_source
302{
303 kDmaRequestMux0Disable = 0|0x100U,
304 kDmaRequestMux0Reserved1 = 1|0x100U,
305 kDmaRequestMux0UART0Rx = 2|0x100U,
306 kDmaRequestMux0UART0Tx = 3|0x100U,
307 kDmaRequestMux0UART1Rx = 4|0x100U,
308 kDmaRequestMux0UART1Tx = 5|0x100U,
309 kDmaRequestMux0UART2Rx = 6|0x100U,
310 kDmaRequestMux0UART2Tx = 7|0x100U,
311 kDmaRequestMux0UART3Rx = 8|0x100U,
312 kDmaRequestMux0UART3Tx = 9|0x100U,
313 kDmaRequestMux0UART4 = 10|0x100U,
314 kDmaRequestMux0UART5 = 11|0x100U,
315 kDmaRequestMux0I2S0Rx = 12|0x100U,
316 kDmaRequestMux0I2S0Tx = 13|0x100U,
317 kDmaRequestMux0SPI0Rx = 14|0x100U,
318 kDmaRequestMux0SPI0Tx = 15|0x100U,
319 kDmaRequestMux0SPI1 = 16|0x100U,
320 kDmaRequestMux0SPI2 = 17|0x100U,
321 kDmaRequestMux0I2C0 = 18|0x100U,
322 kDmaRequestMux0I2C1I2C2 = 19|0x100U,
323 kDmaRequestMux0I2C1 = 19|0x100U,
324 kDmaRequestMux0I2C2 = 19|0x100U,
325 kDmaRequestMux0FTM0Channel0 = 20|0x100U,
326 kDmaRequestMux0FTM0Channel1 = 21|0x100U,
327 kDmaRequestMux0FTM0Channel2 = 22|0x100U,
328 kDmaRequestMux0FTM0Channel3 = 23|0x100U,
329 kDmaRequestMux0FTM0Channel4 = 24|0x100U,
330 kDmaRequestMux0FTM0Channel5 = 25|0x100U,
331 kDmaRequestMux0FTM0Channel6 = 26|0x100U,
332 kDmaRequestMux0FTM0Channel7 = 27|0x100U,
333 kDmaRequestMux0FTM1Channel0 = 28|0x100U,
334 kDmaRequestMux0FTM1Channel1 = 29|0x100U,
335 kDmaRequestMux0FTM2Channel0 = 30|0x100U,
336 kDmaRequestMux0FTM2Channel1 = 31|0x100U,
337 kDmaRequestMux0FTM3Channel0 = 32|0x100U,
338 kDmaRequestMux0FTM3Channel1 = 33|0x100U,
339 kDmaRequestMux0FTM3Channel2 = 34|0x100U,
340 kDmaRequestMux0FTM3Channel3 = 35|0x100U,
341 kDmaRequestMux0FTM3Channel4 = 36|0x100U,
342 kDmaRequestMux0FTM3Channel5 = 37|0x100U,
343 kDmaRequestMux0FTM3Channel6 = 38|0x100U,
344 kDmaRequestMux0FTM3Channel7 = 39|0x100U,
345 kDmaRequestMux0ADC0 = 40|0x100U,
346 kDmaRequestMux0ADC1 = 41|0x100U,
347 kDmaRequestMux0CMP0 = 42|0x100U,
348 kDmaRequestMux0CMP1 = 43|0x100U,
349 kDmaRequestMux0CMP2 = 44|0x100U,
350 kDmaRequestMux0DAC0 = 45|0x100U,
351 kDmaRequestMux0DAC1 = 46|0x100U,
352 kDmaRequestMux0CMT = 47|0x100U,
353 kDmaRequestMux0PDB = 48|0x100U,
354 kDmaRequestMux0PortA = 49|0x100U,
355 kDmaRequestMux0PortB = 50|0x100U,
356 kDmaRequestMux0PortC = 51|0x100U,
357 kDmaRequestMux0PortD = 52|0x100U,
358 kDmaRequestMux0PortE = 53|0x100U,
359 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U,
360 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U,
361 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U,
362 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U,
363 kDmaRequestMux0AlwaysOn58 = 58|0x100U,
364 kDmaRequestMux0AlwaysOn59 = 59|0x100U,
365 kDmaRequestMux0AlwaysOn60 = 60|0x100U,
366 kDmaRequestMux0AlwaysOn61 = 61|0x100U,
367 kDmaRequestMux0AlwaysOn62 = 62|0x100U,
368 kDmaRequestMux0AlwaysOn63 = 63|0x100U,
369} dma_request_source_t;
370
371/* @} */
372
373
376 /* end of group Mapping_Information */
377
378
379/* ----------------------------------------------------------------------------
380 -- Device Peripheral Access Layer
381 ---------------------------------------------------------------------------- */
382
389/*
390** Start of section using anonymous unions
391*/
392
393#if defined(__ARMCC_VERSION)
394 #if (__ARMCC_VERSION >= 6010050)
395 #pragma clang diagnostic push
396 #else
397 #pragma push
398 #pragma anon_unions
399 #endif
400#elif defined(__CWCC__)
401 #pragma push
402 #pragma cpp_extensions on
403#elif defined(__GNUC__)
404 /* anonymous unions are enabled by default */
405#elif defined(__IAR_SYSTEMS_ICC__)
406 #pragma language=extended
407#else
408 #error Not supported compiler type
409#endif
410
411/* ----------------------------------------------------------------------------
412 -- ADC Peripheral Access Layer
413 ---------------------------------------------------------------------------- */
414
421typedef struct {
422 __IO uint32_t SC1[2];
423 __IO uint32_t CFG1;
424 __IO uint32_t CFG2;
425 __I uint32_t R[2];
426 __IO uint32_t CV1;
427 __IO uint32_t CV2;
428 __IO uint32_t SC2;
429 __IO uint32_t SC3;
430 __IO uint32_t OFS;
431 __IO uint32_t PG;
432 __IO uint32_t MG;
433 __IO uint32_t CLPD;
434 __IO uint32_t CLPS;
435 __IO uint32_t CLP4;
436 __IO uint32_t CLP3;
437 __IO uint32_t CLP2;
438 __IO uint32_t CLP1;
439 __IO uint32_t CLP0;
440 uint8_t RESERVED_0[4];
441 __IO uint32_t CLMD;
442 __IO uint32_t CLMS;
443 __IO uint32_t CLM4;
444 __IO uint32_t CLM3;
445 __IO uint32_t CLM2;
446 __IO uint32_t CLM1;
447 __IO uint32_t CLM0;
448} ADC_Type;
449
450/* ----------------------------------------------------------------------------
451 -- ADC Register Masks
452 ---------------------------------------------------------------------------- */
453
461#define ADC_SC1_ADCH_MASK (0x1FU)
462#define ADC_SC1_ADCH_SHIFT (0U)
497#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
498#define ADC_SC1_DIFF_MASK (0x20U)
499#define ADC_SC1_DIFF_SHIFT (5U)
504#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
505#define ADC_SC1_AIEN_MASK (0x40U)
506#define ADC_SC1_AIEN_SHIFT (6U)
511#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
512#define ADC_SC1_COCO_MASK (0x80U)
513#define ADC_SC1_COCO_SHIFT (7U)
518#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
521/* The count of ADC_SC1 */
522#define ADC_SC1_COUNT (2U)
523
526#define ADC_CFG1_ADICLK_MASK (0x3U)
527#define ADC_CFG1_ADICLK_SHIFT (0U)
534#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
535#define ADC_CFG1_MODE_MASK (0xCU)
536#define ADC_CFG1_MODE_SHIFT (2U)
543#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
544#define ADC_CFG1_ADLSMP_MASK (0x10U)
545#define ADC_CFG1_ADLSMP_SHIFT (4U)
550#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
551#define ADC_CFG1_ADIV_MASK (0x60U)
552#define ADC_CFG1_ADIV_SHIFT (5U)
559#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
560#define ADC_CFG1_ADLPC_MASK (0x80U)
561#define ADC_CFG1_ADLPC_SHIFT (7U)
566#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
571#define ADC_CFG2_ADLSTS_MASK (0x3U)
572#define ADC_CFG2_ADLSTS_SHIFT (0U)
579#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
580#define ADC_CFG2_ADHSC_MASK (0x4U)
581#define ADC_CFG2_ADHSC_SHIFT (2U)
586#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
587#define ADC_CFG2_ADACKEN_MASK (0x8U)
588#define ADC_CFG2_ADACKEN_SHIFT (3U)
593#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
594#define ADC_CFG2_MUXSEL_MASK (0x10U)
595#define ADC_CFG2_MUXSEL_SHIFT (4U)
600#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
605#define ADC_R_D_MASK (0xFFFFU)
606#define ADC_R_D_SHIFT (0U)
607#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
610/* The count of ADC_R */
611#define ADC_R_COUNT (2U)
612
615#define ADC_CV1_CV_MASK (0xFFFFU)
616#define ADC_CV1_CV_SHIFT (0U)
617#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
622#define ADC_CV2_CV_MASK (0xFFFFU)
623#define ADC_CV2_CV_SHIFT (0U)
624#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
629#define ADC_SC2_REFSEL_MASK (0x3U)
630#define ADC_SC2_REFSEL_SHIFT (0U)
637#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
638#define ADC_SC2_DMAEN_MASK (0x4U)
639#define ADC_SC2_DMAEN_SHIFT (2U)
644#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
645#define ADC_SC2_ACREN_MASK (0x8U)
646#define ADC_SC2_ACREN_SHIFT (3U)
651#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
652#define ADC_SC2_ACFGT_MASK (0x10U)
653#define ADC_SC2_ACFGT_SHIFT (4U)
658#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
659#define ADC_SC2_ACFE_MASK (0x20U)
660#define ADC_SC2_ACFE_SHIFT (5U)
665#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
666#define ADC_SC2_ADTRG_MASK (0x40U)
667#define ADC_SC2_ADTRG_SHIFT (6U)
672#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
673#define ADC_SC2_ADACT_MASK (0x80U)
674#define ADC_SC2_ADACT_SHIFT (7U)
679#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
684#define ADC_SC3_AVGS_MASK (0x3U)
685#define ADC_SC3_AVGS_SHIFT (0U)
692#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
693#define ADC_SC3_AVGE_MASK (0x4U)
694#define ADC_SC3_AVGE_SHIFT (2U)
699#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
700#define ADC_SC3_ADCO_MASK (0x8U)
701#define ADC_SC3_ADCO_SHIFT (3U)
706#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
707#define ADC_SC3_CALF_MASK (0x40U)
708#define ADC_SC3_CALF_SHIFT (6U)
713#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
714#define ADC_SC3_CAL_MASK (0x80U)
715#define ADC_SC3_CAL_SHIFT (7U)
716#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
721#define ADC_OFS_OFS_MASK (0xFFFFU)
722#define ADC_OFS_OFS_SHIFT (0U)
723#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
728#define ADC_PG_PG_MASK (0xFFFFU)
729#define ADC_PG_PG_SHIFT (0U)
730#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
735#define ADC_MG_MG_MASK (0xFFFFU)
736#define ADC_MG_MG_SHIFT (0U)
737#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
742#define ADC_CLPD_CLPD_MASK (0x3FU)
743#define ADC_CLPD_CLPD_SHIFT (0U)
744#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
749#define ADC_CLPS_CLPS_MASK (0x3FU)
750#define ADC_CLPS_CLPS_SHIFT (0U)
751#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
756#define ADC_CLP4_CLP4_MASK (0x3FFU)
757#define ADC_CLP4_CLP4_SHIFT (0U)
758#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
763#define ADC_CLP3_CLP3_MASK (0x1FFU)
764#define ADC_CLP3_CLP3_SHIFT (0U)
765#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
770#define ADC_CLP2_CLP2_MASK (0xFFU)
771#define ADC_CLP2_CLP2_SHIFT (0U)
772#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
777#define ADC_CLP1_CLP1_MASK (0x7FU)
778#define ADC_CLP1_CLP1_SHIFT (0U)
779#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
784#define ADC_CLP0_CLP0_MASK (0x3FU)
785#define ADC_CLP0_CLP0_SHIFT (0U)
786#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
791#define ADC_CLMD_CLMD_MASK (0x3FU)
792#define ADC_CLMD_CLMD_SHIFT (0U)
793#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
798#define ADC_CLMS_CLMS_MASK (0x3FU)
799#define ADC_CLMS_CLMS_SHIFT (0U)
800#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
805#define ADC_CLM4_CLM4_MASK (0x3FFU)
806#define ADC_CLM4_CLM4_SHIFT (0U)
807#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
812#define ADC_CLM3_CLM3_MASK (0x1FFU)
813#define ADC_CLM3_CLM3_SHIFT (0U)
814#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
819#define ADC_CLM2_CLM2_MASK (0xFFU)
820#define ADC_CLM2_CLM2_SHIFT (0U)
821#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
826#define ADC_CLM1_CLM1_MASK (0x7FU)
827#define ADC_CLM1_CLM1_SHIFT (0U)
828#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
833#define ADC_CLM0_CLM0_MASK (0x3FU)
834#define ADC_CLM0_CLM0_SHIFT (0U)
835#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
841 /* end of group ADC_Register_Masks */
842
843
844/* ADC - Peripheral instance base addresses */
846#define ADC0_BASE (0x4003B000u)
848#define ADC0 ((ADC_Type *)ADC0_BASE)
850#define ADC1_BASE (0x400BB000u)
852#define ADC1 ((ADC_Type *)ADC1_BASE)
854#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
856#define ADC_BASE_PTRS { ADC0, ADC1 }
858#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
859
862 /* end of group ADC_Peripheral_Access_Layer */
863
864
865/* ----------------------------------------------------------------------------
866 -- AIPS Peripheral Access Layer
867 ---------------------------------------------------------------------------- */
868
875typedef struct {
876 __IO uint32_t MPRA;
877 uint8_t RESERVED_0[28];
878 __IO uint32_t PACRA;
879 __IO uint32_t PACRB;
880 __IO uint32_t PACRC;
881 __IO uint32_t PACRD;
882 uint8_t RESERVED_1[16];
883 __IO uint32_t PACRE;
884 __IO uint32_t PACRF;
885 __IO uint32_t PACRG;
886 __IO uint32_t PACRH;
887 __IO uint32_t PACRI;
888 __IO uint32_t PACRJ;
889 __IO uint32_t PACRK;
890 __IO uint32_t PACRL;
891 __IO uint32_t PACRM;
892 __IO uint32_t PACRN;
893 __IO uint32_t PACRO;
894 __IO uint32_t PACRP;
895 uint8_t RESERVED_2[16];
896 __IO uint32_t PACRU;
897} AIPS_Type;
898
899/* ----------------------------------------------------------------------------
900 -- AIPS Register Masks
901 ---------------------------------------------------------------------------- */
902
910#define AIPS_MPRA_MPL5_MASK (0x100U)
911#define AIPS_MPRA_MPL5_SHIFT (8U)
916#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
917#define AIPS_MPRA_MTW5_MASK (0x200U)
918#define AIPS_MPRA_MTW5_SHIFT (9U)
923#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
924#define AIPS_MPRA_MTR5_MASK (0x400U)
925#define AIPS_MPRA_MTR5_SHIFT (10U)
930#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
931#define AIPS_MPRA_MPL4_MASK (0x1000U)
932#define AIPS_MPRA_MPL4_SHIFT (12U)
937#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
938#define AIPS_MPRA_MTW4_MASK (0x2000U)
939#define AIPS_MPRA_MTW4_SHIFT (13U)
944#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
945#define AIPS_MPRA_MTR4_MASK (0x4000U)
946#define AIPS_MPRA_MTR4_SHIFT (14U)
951#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
952#define AIPS_MPRA_MPL3_MASK (0x10000U)
953#define AIPS_MPRA_MPL3_SHIFT (16U)
958#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
959#define AIPS_MPRA_MTW3_MASK (0x20000U)
960#define AIPS_MPRA_MTW3_SHIFT (17U)
965#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
966#define AIPS_MPRA_MTR3_MASK (0x40000U)
967#define AIPS_MPRA_MTR3_SHIFT (18U)
972#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
973#define AIPS_MPRA_MPL2_MASK (0x100000U)
974#define AIPS_MPRA_MPL2_SHIFT (20U)
979#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
980#define AIPS_MPRA_MTW2_MASK (0x200000U)
981#define AIPS_MPRA_MTW2_SHIFT (21U)
986#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
987#define AIPS_MPRA_MTR2_MASK (0x400000U)
988#define AIPS_MPRA_MTR2_SHIFT (22U)
993#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
994#define AIPS_MPRA_MPL1_MASK (0x1000000U)
995#define AIPS_MPRA_MPL1_SHIFT (24U)
1000#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1001#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1002#define AIPS_MPRA_MTW1_SHIFT (25U)
1007#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1008#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1009#define AIPS_MPRA_MTR1_SHIFT (26U)
1014#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1015#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1016#define AIPS_MPRA_MPL0_SHIFT (28U)
1021#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1022#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1023#define AIPS_MPRA_MTW0_SHIFT (29U)
1028#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1029#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1030#define AIPS_MPRA_MTR0_SHIFT (30U)
1035#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1040#define AIPS_PACRA_TP7_MASK (0x1U)
1041#define AIPS_PACRA_TP7_SHIFT (0U)
1046#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1047#define AIPS_PACRA_WP7_MASK (0x2U)
1048#define AIPS_PACRA_WP7_SHIFT (1U)
1053#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1054#define AIPS_PACRA_SP7_MASK (0x4U)
1055#define AIPS_PACRA_SP7_SHIFT (2U)
1060#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1061#define AIPS_PACRA_TP6_MASK (0x10U)
1062#define AIPS_PACRA_TP6_SHIFT (4U)
1067#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1068#define AIPS_PACRA_WP6_MASK (0x20U)
1069#define AIPS_PACRA_WP6_SHIFT (5U)
1074#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1075#define AIPS_PACRA_SP6_MASK (0x40U)
1076#define AIPS_PACRA_SP6_SHIFT (6U)
1081#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1082#define AIPS_PACRA_TP5_MASK (0x100U)
1083#define AIPS_PACRA_TP5_SHIFT (8U)
1088#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1089#define AIPS_PACRA_WP5_MASK (0x200U)
1090#define AIPS_PACRA_WP5_SHIFT (9U)
1095#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1096#define AIPS_PACRA_SP5_MASK (0x400U)
1097#define AIPS_PACRA_SP5_SHIFT (10U)
1102#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1103#define AIPS_PACRA_TP4_MASK (0x1000U)
1104#define AIPS_PACRA_TP4_SHIFT (12U)
1109#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1110#define AIPS_PACRA_WP4_MASK (0x2000U)
1111#define AIPS_PACRA_WP4_SHIFT (13U)
1116#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1117#define AIPS_PACRA_SP4_MASK (0x4000U)
1118#define AIPS_PACRA_SP4_SHIFT (14U)
1123#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1124#define AIPS_PACRA_TP3_MASK (0x10000U)
1125#define AIPS_PACRA_TP3_SHIFT (16U)
1130#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1131#define AIPS_PACRA_WP3_MASK (0x20000U)
1132#define AIPS_PACRA_WP3_SHIFT (17U)
1137#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1138#define AIPS_PACRA_SP3_MASK (0x40000U)
1139#define AIPS_PACRA_SP3_SHIFT (18U)
1144#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1145#define AIPS_PACRA_TP2_MASK (0x100000U)
1146#define AIPS_PACRA_TP2_SHIFT (20U)
1151#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1152#define AIPS_PACRA_WP2_MASK (0x200000U)
1153#define AIPS_PACRA_WP2_SHIFT (21U)
1158#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1159#define AIPS_PACRA_SP2_MASK (0x400000U)
1160#define AIPS_PACRA_SP2_SHIFT (22U)
1165#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1166#define AIPS_PACRA_TP1_MASK (0x1000000U)
1167#define AIPS_PACRA_TP1_SHIFT (24U)
1172#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1173#define AIPS_PACRA_WP1_MASK (0x2000000U)
1174#define AIPS_PACRA_WP1_SHIFT (25U)
1179#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1180#define AIPS_PACRA_SP1_MASK (0x4000000U)
1181#define AIPS_PACRA_SP1_SHIFT (26U)
1186#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1187#define AIPS_PACRA_TP0_MASK (0x10000000U)
1188#define AIPS_PACRA_TP0_SHIFT (28U)
1193#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1194#define AIPS_PACRA_WP0_MASK (0x20000000U)
1195#define AIPS_PACRA_WP0_SHIFT (29U)
1200#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1201#define AIPS_PACRA_SP0_MASK (0x40000000U)
1202#define AIPS_PACRA_SP0_SHIFT (30U)
1207#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1212#define AIPS_PACRB_TP7_MASK (0x1U)
1213#define AIPS_PACRB_TP7_SHIFT (0U)
1218#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1219#define AIPS_PACRB_WP7_MASK (0x2U)
1220#define AIPS_PACRB_WP7_SHIFT (1U)
1225#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1226#define AIPS_PACRB_SP7_MASK (0x4U)
1227#define AIPS_PACRB_SP7_SHIFT (2U)
1232#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1233#define AIPS_PACRB_TP6_MASK (0x10U)
1234#define AIPS_PACRB_TP6_SHIFT (4U)
1239#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1240#define AIPS_PACRB_WP6_MASK (0x20U)
1241#define AIPS_PACRB_WP6_SHIFT (5U)
1246#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1247#define AIPS_PACRB_SP6_MASK (0x40U)
1248#define AIPS_PACRB_SP6_SHIFT (6U)
1253#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1254#define AIPS_PACRB_TP5_MASK (0x100U)
1255#define AIPS_PACRB_TP5_SHIFT (8U)
1260#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1261#define AIPS_PACRB_WP5_MASK (0x200U)
1262#define AIPS_PACRB_WP5_SHIFT (9U)
1267#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1268#define AIPS_PACRB_SP5_MASK (0x400U)
1269#define AIPS_PACRB_SP5_SHIFT (10U)
1274#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1275#define AIPS_PACRB_TP4_MASK (0x1000U)
1276#define AIPS_PACRB_TP4_SHIFT (12U)
1281#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1282#define AIPS_PACRB_WP4_MASK (0x2000U)
1283#define AIPS_PACRB_WP4_SHIFT (13U)
1288#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1289#define AIPS_PACRB_SP4_MASK (0x4000U)
1290#define AIPS_PACRB_SP4_SHIFT (14U)
1295#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1296#define AIPS_PACRB_TP3_MASK (0x10000U)
1297#define AIPS_PACRB_TP3_SHIFT (16U)
1302#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1303#define AIPS_PACRB_WP3_MASK (0x20000U)
1304#define AIPS_PACRB_WP3_SHIFT (17U)
1309#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1310#define AIPS_PACRB_SP3_MASK (0x40000U)
1311#define AIPS_PACRB_SP3_SHIFT (18U)
1316#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1317#define AIPS_PACRB_TP2_MASK (0x100000U)
1318#define AIPS_PACRB_TP2_SHIFT (20U)
1323#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1324#define AIPS_PACRB_WP2_MASK (0x200000U)
1325#define AIPS_PACRB_WP2_SHIFT (21U)
1330#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1331#define AIPS_PACRB_SP2_MASK (0x400000U)
1332#define AIPS_PACRB_SP2_SHIFT (22U)
1337#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1338#define AIPS_PACRB_TP1_MASK (0x1000000U)
1339#define AIPS_PACRB_TP1_SHIFT (24U)
1344#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1345#define AIPS_PACRB_WP1_MASK (0x2000000U)
1346#define AIPS_PACRB_WP1_SHIFT (25U)
1351#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1352#define AIPS_PACRB_SP1_MASK (0x4000000U)
1353#define AIPS_PACRB_SP1_SHIFT (26U)
1358#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1359#define AIPS_PACRB_TP0_MASK (0x10000000U)
1360#define AIPS_PACRB_TP0_SHIFT (28U)
1365#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1366#define AIPS_PACRB_WP0_MASK (0x20000000U)
1367#define AIPS_PACRB_WP0_SHIFT (29U)
1372#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1373#define AIPS_PACRB_SP0_MASK (0x40000000U)
1374#define AIPS_PACRB_SP0_SHIFT (30U)
1379#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1384#define AIPS_PACRC_TP7_MASK (0x1U)
1385#define AIPS_PACRC_TP7_SHIFT (0U)
1390#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1391#define AIPS_PACRC_WP7_MASK (0x2U)
1392#define AIPS_PACRC_WP7_SHIFT (1U)
1397#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1398#define AIPS_PACRC_SP7_MASK (0x4U)
1399#define AIPS_PACRC_SP7_SHIFT (2U)
1404#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1405#define AIPS_PACRC_TP6_MASK (0x10U)
1406#define AIPS_PACRC_TP6_SHIFT (4U)
1411#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1412#define AIPS_PACRC_WP6_MASK (0x20U)
1413#define AIPS_PACRC_WP6_SHIFT (5U)
1418#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1419#define AIPS_PACRC_SP6_MASK (0x40U)
1420#define AIPS_PACRC_SP6_SHIFT (6U)
1425#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1426#define AIPS_PACRC_TP5_MASK (0x100U)
1427#define AIPS_PACRC_TP5_SHIFT (8U)
1432#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1433#define AIPS_PACRC_WP5_MASK (0x200U)
1434#define AIPS_PACRC_WP5_SHIFT (9U)
1439#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1440#define AIPS_PACRC_SP5_MASK (0x400U)
1441#define AIPS_PACRC_SP5_SHIFT (10U)
1446#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1447#define AIPS_PACRC_TP4_MASK (0x1000U)
1448#define AIPS_PACRC_TP4_SHIFT (12U)
1453#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1454#define AIPS_PACRC_WP4_MASK (0x2000U)
1455#define AIPS_PACRC_WP4_SHIFT (13U)
1460#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1461#define AIPS_PACRC_SP4_MASK (0x4000U)
1462#define AIPS_PACRC_SP4_SHIFT (14U)
1467#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1468#define AIPS_PACRC_TP3_MASK (0x10000U)
1469#define AIPS_PACRC_TP3_SHIFT (16U)
1474#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1475#define AIPS_PACRC_WP3_MASK (0x20000U)
1476#define AIPS_PACRC_WP3_SHIFT (17U)
1481#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1482#define AIPS_PACRC_SP3_MASK (0x40000U)
1483#define AIPS_PACRC_SP3_SHIFT (18U)
1488#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1489#define AIPS_PACRC_TP2_MASK (0x100000U)
1490#define AIPS_PACRC_TP2_SHIFT (20U)
1495#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1496#define AIPS_PACRC_WP2_MASK (0x200000U)
1497#define AIPS_PACRC_WP2_SHIFT (21U)
1502#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1503#define AIPS_PACRC_SP2_MASK (0x400000U)
1504#define AIPS_PACRC_SP2_SHIFT (22U)
1509#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1510#define AIPS_PACRC_TP1_MASK (0x1000000U)
1511#define AIPS_PACRC_TP1_SHIFT (24U)
1516#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1517#define AIPS_PACRC_WP1_MASK (0x2000000U)
1518#define AIPS_PACRC_WP1_SHIFT (25U)
1523#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1524#define AIPS_PACRC_SP1_MASK (0x4000000U)
1525#define AIPS_PACRC_SP1_SHIFT (26U)
1530#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1531#define AIPS_PACRC_TP0_MASK (0x10000000U)
1532#define AIPS_PACRC_TP0_SHIFT (28U)
1537#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1538#define AIPS_PACRC_WP0_MASK (0x20000000U)
1539#define AIPS_PACRC_WP0_SHIFT (29U)
1544#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1545#define AIPS_PACRC_SP0_MASK (0x40000000U)
1546#define AIPS_PACRC_SP0_SHIFT (30U)
1551#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1556#define AIPS_PACRD_TP7_MASK (0x1U)
1557#define AIPS_PACRD_TP7_SHIFT (0U)
1562#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1563#define AIPS_PACRD_WP7_MASK (0x2U)
1564#define AIPS_PACRD_WP7_SHIFT (1U)
1569#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1570#define AIPS_PACRD_SP7_MASK (0x4U)
1571#define AIPS_PACRD_SP7_SHIFT (2U)
1576#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1577#define AIPS_PACRD_TP6_MASK (0x10U)
1578#define AIPS_PACRD_TP6_SHIFT (4U)
1583#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1584#define AIPS_PACRD_WP6_MASK (0x20U)
1585#define AIPS_PACRD_WP6_SHIFT (5U)
1590#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1591#define AIPS_PACRD_SP6_MASK (0x40U)
1592#define AIPS_PACRD_SP6_SHIFT (6U)
1597#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1598#define AIPS_PACRD_TP5_MASK (0x100U)
1599#define AIPS_PACRD_TP5_SHIFT (8U)
1604#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1605#define AIPS_PACRD_WP5_MASK (0x200U)
1606#define AIPS_PACRD_WP5_SHIFT (9U)
1611#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1612#define AIPS_PACRD_SP5_MASK (0x400U)
1613#define AIPS_PACRD_SP5_SHIFT (10U)
1618#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1619#define AIPS_PACRD_TP4_MASK (0x1000U)
1620#define AIPS_PACRD_TP4_SHIFT (12U)
1625#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1626#define AIPS_PACRD_WP4_MASK (0x2000U)
1627#define AIPS_PACRD_WP4_SHIFT (13U)
1632#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1633#define AIPS_PACRD_SP4_MASK (0x4000U)
1634#define AIPS_PACRD_SP4_SHIFT (14U)
1639#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1640#define AIPS_PACRD_TP3_MASK (0x10000U)
1641#define AIPS_PACRD_TP3_SHIFT (16U)
1646#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1647#define AIPS_PACRD_WP3_MASK (0x20000U)
1648#define AIPS_PACRD_WP3_SHIFT (17U)
1653#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1654#define AIPS_PACRD_SP3_MASK (0x40000U)
1655#define AIPS_PACRD_SP3_SHIFT (18U)
1660#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1661#define AIPS_PACRD_TP2_MASK (0x100000U)
1662#define AIPS_PACRD_TP2_SHIFT (20U)
1667#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1668#define AIPS_PACRD_WP2_MASK (0x200000U)
1669#define AIPS_PACRD_WP2_SHIFT (21U)
1674#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1675#define AIPS_PACRD_SP2_MASK (0x400000U)
1676#define AIPS_PACRD_SP2_SHIFT (22U)
1681#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1682#define AIPS_PACRD_TP1_MASK (0x1000000U)
1683#define AIPS_PACRD_TP1_SHIFT (24U)
1688#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1689#define AIPS_PACRD_WP1_MASK (0x2000000U)
1690#define AIPS_PACRD_WP1_SHIFT (25U)
1695#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1696#define AIPS_PACRD_SP1_MASK (0x4000000U)
1697#define AIPS_PACRD_SP1_SHIFT (26U)
1702#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1703#define AIPS_PACRD_TP0_MASK (0x10000000U)
1704#define AIPS_PACRD_TP0_SHIFT (28U)
1709#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1710#define AIPS_PACRD_WP0_MASK (0x20000000U)
1711#define AIPS_PACRD_WP0_SHIFT (29U)
1716#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1717#define AIPS_PACRD_SP0_MASK (0x40000000U)
1718#define AIPS_PACRD_SP0_SHIFT (30U)
1723#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1728#define AIPS_PACRE_TP7_MASK (0x1U)
1729#define AIPS_PACRE_TP7_SHIFT (0U)
1734#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1735#define AIPS_PACRE_WP7_MASK (0x2U)
1736#define AIPS_PACRE_WP7_SHIFT (1U)
1741#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1742#define AIPS_PACRE_SP7_MASK (0x4U)
1743#define AIPS_PACRE_SP7_SHIFT (2U)
1748#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1749#define AIPS_PACRE_TP6_MASK (0x10U)
1750#define AIPS_PACRE_TP6_SHIFT (4U)
1755#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1756#define AIPS_PACRE_WP6_MASK (0x20U)
1757#define AIPS_PACRE_WP6_SHIFT (5U)
1762#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1763#define AIPS_PACRE_SP6_MASK (0x40U)
1764#define AIPS_PACRE_SP6_SHIFT (6U)
1769#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1770#define AIPS_PACRE_TP5_MASK (0x100U)
1771#define AIPS_PACRE_TP5_SHIFT (8U)
1776#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1777#define AIPS_PACRE_WP5_MASK (0x200U)
1778#define AIPS_PACRE_WP5_SHIFT (9U)
1783#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1784#define AIPS_PACRE_SP5_MASK (0x400U)
1785#define AIPS_PACRE_SP5_SHIFT (10U)
1790#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1791#define AIPS_PACRE_TP4_MASK (0x1000U)
1792#define AIPS_PACRE_TP4_SHIFT (12U)
1797#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1798#define AIPS_PACRE_WP4_MASK (0x2000U)
1799#define AIPS_PACRE_WP4_SHIFT (13U)
1804#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1805#define AIPS_PACRE_SP4_MASK (0x4000U)
1806#define AIPS_PACRE_SP4_SHIFT (14U)
1811#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1812#define AIPS_PACRE_TP3_MASK (0x10000U)
1813#define AIPS_PACRE_TP3_SHIFT (16U)
1818#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1819#define AIPS_PACRE_WP3_MASK (0x20000U)
1820#define AIPS_PACRE_WP3_SHIFT (17U)
1825#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1826#define AIPS_PACRE_SP3_MASK (0x40000U)
1827#define AIPS_PACRE_SP3_SHIFT (18U)
1832#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1833#define AIPS_PACRE_TP2_MASK (0x100000U)
1834#define AIPS_PACRE_TP2_SHIFT (20U)
1839#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1840#define AIPS_PACRE_WP2_MASK (0x200000U)
1841#define AIPS_PACRE_WP2_SHIFT (21U)
1846#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1847#define AIPS_PACRE_SP2_MASK (0x400000U)
1848#define AIPS_PACRE_SP2_SHIFT (22U)
1853#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1854#define AIPS_PACRE_TP1_MASK (0x1000000U)
1855#define AIPS_PACRE_TP1_SHIFT (24U)
1860#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1861#define AIPS_PACRE_WP1_MASK (0x2000000U)
1862#define AIPS_PACRE_WP1_SHIFT (25U)
1867#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1868#define AIPS_PACRE_SP1_MASK (0x4000000U)
1869#define AIPS_PACRE_SP1_SHIFT (26U)
1874#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1875#define AIPS_PACRE_TP0_MASK (0x10000000U)
1876#define AIPS_PACRE_TP0_SHIFT (28U)
1881#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1882#define AIPS_PACRE_WP0_MASK (0x20000000U)
1883#define AIPS_PACRE_WP0_SHIFT (29U)
1888#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1889#define AIPS_PACRE_SP0_MASK (0x40000000U)
1890#define AIPS_PACRE_SP0_SHIFT (30U)
1895#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1900#define AIPS_PACRF_TP7_MASK (0x1U)
1901#define AIPS_PACRF_TP7_SHIFT (0U)
1906#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1907#define AIPS_PACRF_WP7_MASK (0x2U)
1908#define AIPS_PACRF_WP7_SHIFT (1U)
1913#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1914#define AIPS_PACRF_SP7_MASK (0x4U)
1915#define AIPS_PACRF_SP7_SHIFT (2U)
1920#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1921#define AIPS_PACRF_TP6_MASK (0x10U)
1922#define AIPS_PACRF_TP6_SHIFT (4U)
1927#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1928#define AIPS_PACRF_WP6_MASK (0x20U)
1929#define AIPS_PACRF_WP6_SHIFT (5U)
1934#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1935#define AIPS_PACRF_SP6_MASK (0x40U)
1936#define AIPS_PACRF_SP6_SHIFT (6U)
1941#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1942#define AIPS_PACRF_TP5_MASK (0x100U)
1943#define AIPS_PACRF_TP5_SHIFT (8U)
1948#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1949#define AIPS_PACRF_WP5_MASK (0x200U)
1950#define AIPS_PACRF_WP5_SHIFT (9U)
1955#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1956#define AIPS_PACRF_SP5_MASK (0x400U)
1957#define AIPS_PACRF_SP5_SHIFT (10U)
1962#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1963#define AIPS_PACRF_TP4_MASK (0x1000U)
1964#define AIPS_PACRF_TP4_SHIFT (12U)
1969#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
1970#define AIPS_PACRF_WP4_MASK (0x2000U)
1971#define AIPS_PACRF_WP4_SHIFT (13U)
1976#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
1977#define AIPS_PACRF_SP4_MASK (0x4000U)
1978#define AIPS_PACRF_SP4_SHIFT (14U)
1983#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
1984#define AIPS_PACRF_TP3_MASK (0x10000U)
1985#define AIPS_PACRF_TP3_SHIFT (16U)
1990#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
1991#define AIPS_PACRF_WP3_MASK (0x20000U)
1992#define AIPS_PACRF_WP3_SHIFT (17U)
1997#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
1998#define AIPS_PACRF_SP3_MASK (0x40000U)
1999#define AIPS_PACRF_SP3_SHIFT (18U)
2004#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2005#define AIPS_PACRF_TP2_MASK (0x100000U)
2006#define AIPS_PACRF_TP2_SHIFT (20U)
2011#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2012#define AIPS_PACRF_WP2_MASK (0x200000U)
2013#define AIPS_PACRF_WP2_SHIFT (21U)
2018#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2019#define AIPS_PACRF_SP2_MASK (0x400000U)
2020#define AIPS_PACRF_SP2_SHIFT (22U)
2025#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2026#define AIPS_PACRF_TP1_MASK (0x1000000U)
2027#define AIPS_PACRF_TP1_SHIFT (24U)
2032#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2033#define AIPS_PACRF_WP1_MASK (0x2000000U)
2034#define AIPS_PACRF_WP1_SHIFT (25U)
2039#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2040#define AIPS_PACRF_SP1_MASK (0x4000000U)
2041#define AIPS_PACRF_SP1_SHIFT (26U)
2046#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2047#define AIPS_PACRF_TP0_MASK (0x10000000U)
2048#define AIPS_PACRF_TP0_SHIFT (28U)
2053#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2054#define AIPS_PACRF_WP0_MASK (0x20000000U)
2055#define AIPS_PACRF_WP0_SHIFT (29U)
2060#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2061#define AIPS_PACRF_SP0_MASK (0x40000000U)
2062#define AIPS_PACRF_SP0_SHIFT (30U)
2067#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2072#define AIPS_PACRG_TP7_MASK (0x1U)
2073#define AIPS_PACRG_TP7_SHIFT (0U)
2078#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2079#define AIPS_PACRG_WP7_MASK (0x2U)
2080#define AIPS_PACRG_WP7_SHIFT (1U)
2085#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2086#define AIPS_PACRG_SP7_MASK (0x4U)
2087#define AIPS_PACRG_SP7_SHIFT (2U)
2092#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2093#define AIPS_PACRG_TP6_MASK (0x10U)
2094#define AIPS_PACRG_TP6_SHIFT (4U)
2099#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2100#define AIPS_PACRG_WP6_MASK (0x20U)
2101#define AIPS_PACRG_WP6_SHIFT (5U)
2106#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2107#define AIPS_PACRG_SP6_MASK (0x40U)
2108#define AIPS_PACRG_SP6_SHIFT (6U)
2113#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2114#define AIPS_PACRG_TP5_MASK (0x100U)
2115#define AIPS_PACRG_TP5_SHIFT (8U)
2120#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2121#define AIPS_PACRG_WP5_MASK (0x200U)
2122#define AIPS_PACRG_WP5_SHIFT (9U)
2127#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2128#define AIPS_PACRG_SP5_MASK (0x400U)
2129#define AIPS_PACRG_SP5_SHIFT (10U)
2134#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2135#define AIPS_PACRG_TP4_MASK (0x1000U)
2136#define AIPS_PACRG_TP4_SHIFT (12U)
2141#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2142#define AIPS_PACRG_WP4_MASK (0x2000U)
2143#define AIPS_PACRG_WP4_SHIFT (13U)
2148#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2149#define AIPS_PACRG_SP4_MASK (0x4000U)
2150#define AIPS_PACRG_SP4_SHIFT (14U)
2155#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2156#define AIPS_PACRG_TP3_MASK (0x10000U)
2157#define AIPS_PACRG_TP3_SHIFT (16U)
2162#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2163#define AIPS_PACRG_WP3_MASK (0x20000U)
2164#define AIPS_PACRG_WP3_SHIFT (17U)
2169#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2170#define AIPS_PACRG_SP3_MASK (0x40000U)
2171#define AIPS_PACRG_SP3_SHIFT (18U)
2176#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2177#define AIPS_PACRG_TP2_MASK (0x100000U)
2178#define AIPS_PACRG_TP2_SHIFT (20U)
2183#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2184#define AIPS_PACRG_WP2_MASK (0x200000U)
2185#define AIPS_PACRG_WP2_SHIFT (21U)
2190#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2191#define AIPS_PACRG_SP2_MASK (0x400000U)
2192#define AIPS_PACRG_SP2_SHIFT (22U)
2197#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2198#define AIPS_PACRG_TP1_MASK (0x1000000U)
2199#define AIPS_PACRG_TP1_SHIFT (24U)
2204#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2205#define AIPS_PACRG_WP1_MASK (0x2000000U)
2206#define AIPS_PACRG_WP1_SHIFT (25U)
2211#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2212#define AIPS_PACRG_SP1_MASK (0x4000000U)
2213#define AIPS_PACRG_SP1_SHIFT (26U)
2218#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2219#define AIPS_PACRG_TP0_MASK (0x10000000U)
2220#define AIPS_PACRG_TP0_SHIFT (28U)
2225#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2226#define AIPS_PACRG_WP0_MASK (0x20000000U)
2227#define AIPS_PACRG_WP0_SHIFT (29U)
2232#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2233#define AIPS_PACRG_SP0_MASK (0x40000000U)
2234#define AIPS_PACRG_SP0_SHIFT (30U)
2239#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2244#define AIPS_PACRH_TP7_MASK (0x1U)
2245#define AIPS_PACRH_TP7_SHIFT (0U)
2250#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2251#define AIPS_PACRH_WP7_MASK (0x2U)
2252#define AIPS_PACRH_WP7_SHIFT (1U)
2257#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2258#define AIPS_PACRH_SP7_MASK (0x4U)
2259#define AIPS_PACRH_SP7_SHIFT (2U)
2264#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2265#define AIPS_PACRH_TP6_MASK (0x10U)
2266#define AIPS_PACRH_TP6_SHIFT (4U)
2271#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2272#define AIPS_PACRH_WP6_MASK (0x20U)
2273#define AIPS_PACRH_WP6_SHIFT (5U)
2278#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2279#define AIPS_PACRH_SP6_MASK (0x40U)
2280#define AIPS_PACRH_SP6_SHIFT (6U)
2285#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2286#define AIPS_PACRH_TP5_MASK (0x100U)
2287#define AIPS_PACRH_TP5_SHIFT (8U)
2292#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2293#define AIPS_PACRH_WP5_MASK (0x200U)
2294#define AIPS_PACRH_WP5_SHIFT (9U)
2299#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2300#define AIPS_PACRH_SP5_MASK (0x400U)
2301#define AIPS_PACRH_SP5_SHIFT (10U)
2306#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2307#define AIPS_PACRH_TP4_MASK (0x1000U)
2308#define AIPS_PACRH_TP4_SHIFT (12U)
2313#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2314#define AIPS_PACRH_WP4_MASK (0x2000U)
2315#define AIPS_PACRH_WP4_SHIFT (13U)
2320#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2321#define AIPS_PACRH_SP4_MASK (0x4000U)
2322#define AIPS_PACRH_SP4_SHIFT (14U)
2327#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2328#define AIPS_PACRH_TP3_MASK (0x10000U)
2329#define AIPS_PACRH_TP3_SHIFT (16U)
2334#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2335#define AIPS_PACRH_WP3_MASK (0x20000U)
2336#define AIPS_PACRH_WP3_SHIFT (17U)
2341#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2342#define AIPS_PACRH_SP3_MASK (0x40000U)
2343#define AIPS_PACRH_SP3_SHIFT (18U)
2348#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2349#define AIPS_PACRH_TP2_MASK (0x100000U)
2350#define AIPS_PACRH_TP2_SHIFT (20U)
2355#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2356#define AIPS_PACRH_WP2_MASK (0x200000U)
2357#define AIPS_PACRH_WP2_SHIFT (21U)
2362#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2363#define AIPS_PACRH_SP2_MASK (0x400000U)
2364#define AIPS_PACRH_SP2_SHIFT (22U)
2369#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2370#define AIPS_PACRH_TP1_MASK (0x1000000U)
2371#define AIPS_PACRH_TP1_SHIFT (24U)
2376#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2377#define AIPS_PACRH_WP1_MASK (0x2000000U)
2378#define AIPS_PACRH_WP1_SHIFT (25U)
2383#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2384#define AIPS_PACRH_SP1_MASK (0x4000000U)
2385#define AIPS_PACRH_SP1_SHIFT (26U)
2390#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2391#define AIPS_PACRH_TP0_MASK (0x10000000U)
2392#define AIPS_PACRH_TP0_SHIFT (28U)
2397#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2398#define AIPS_PACRH_WP0_MASK (0x20000000U)
2399#define AIPS_PACRH_WP0_SHIFT (29U)
2404#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2405#define AIPS_PACRH_SP0_MASK (0x40000000U)
2406#define AIPS_PACRH_SP0_SHIFT (30U)
2411#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2416#define AIPS_PACRI_TP7_MASK (0x1U)
2417#define AIPS_PACRI_TP7_SHIFT (0U)
2422#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2423#define AIPS_PACRI_WP7_MASK (0x2U)
2424#define AIPS_PACRI_WP7_SHIFT (1U)
2429#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2430#define AIPS_PACRI_SP7_MASK (0x4U)
2431#define AIPS_PACRI_SP7_SHIFT (2U)
2436#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2437#define AIPS_PACRI_TP6_MASK (0x10U)
2438#define AIPS_PACRI_TP6_SHIFT (4U)
2443#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2444#define AIPS_PACRI_WP6_MASK (0x20U)
2445#define AIPS_PACRI_WP6_SHIFT (5U)
2450#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2451#define AIPS_PACRI_SP6_MASK (0x40U)
2452#define AIPS_PACRI_SP6_SHIFT (6U)
2457#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2458#define AIPS_PACRI_TP5_MASK (0x100U)
2459#define AIPS_PACRI_TP5_SHIFT (8U)
2464#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2465#define AIPS_PACRI_WP5_MASK (0x200U)
2466#define AIPS_PACRI_WP5_SHIFT (9U)
2471#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2472#define AIPS_PACRI_SP5_MASK (0x400U)
2473#define AIPS_PACRI_SP5_SHIFT (10U)
2478#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2479#define AIPS_PACRI_TP4_MASK (0x1000U)
2480#define AIPS_PACRI_TP4_SHIFT (12U)
2485#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2486#define AIPS_PACRI_WP4_MASK (0x2000U)
2487#define AIPS_PACRI_WP4_SHIFT (13U)
2492#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2493#define AIPS_PACRI_SP4_MASK (0x4000U)
2494#define AIPS_PACRI_SP4_SHIFT (14U)
2499#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2500#define AIPS_PACRI_TP3_MASK (0x10000U)
2501#define AIPS_PACRI_TP3_SHIFT (16U)
2506#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2507#define AIPS_PACRI_WP3_MASK (0x20000U)
2508#define AIPS_PACRI_WP3_SHIFT (17U)
2513#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2514#define AIPS_PACRI_SP3_MASK (0x40000U)
2515#define AIPS_PACRI_SP3_SHIFT (18U)
2520#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2521#define AIPS_PACRI_TP2_MASK (0x100000U)
2522#define AIPS_PACRI_TP2_SHIFT (20U)
2527#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2528#define AIPS_PACRI_WP2_MASK (0x200000U)
2529#define AIPS_PACRI_WP2_SHIFT (21U)
2534#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2535#define AIPS_PACRI_SP2_MASK (0x400000U)
2536#define AIPS_PACRI_SP2_SHIFT (22U)
2541#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2542#define AIPS_PACRI_TP1_MASK (0x1000000U)
2543#define AIPS_PACRI_TP1_SHIFT (24U)
2548#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2549#define AIPS_PACRI_WP1_MASK (0x2000000U)
2550#define AIPS_PACRI_WP1_SHIFT (25U)
2555#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2556#define AIPS_PACRI_SP1_MASK (0x4000000U)
2557#define AIPS_PACRI_SP1_SHIFT (26U)
2562#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2563#define AIPS_PACRI_TP0_MASK (0x10000000U)
2564#define AIPS_PACRI_TP0_SHIFT (28U)
2569#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2570#define AIPS_PACRI_WP0_MASK (0x20000000U)
2571#define AIPS_PACRI_WP0_SHIFT (29U)
2576#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2577#define AIPS_PACRI_SP0_MASK (0x40000000U)
2578#define AIPS_PACRI_SP0_SHIFT (30U)
2583#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2588#define AIPS_PACRJ_TP7_MASK (0x1U)
2589#define AIPS_PACRJ_TP7_SHIFT (0U)
2594#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2595#define AIPS_PACRJ_WP7_MASK (0x2U)
2596#define AIPS_PACRJ_WP7_SHIFT (1U)
2601#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2602#define AIPS_PACRJ_SP7_MASK (0x4U)
2603#define AIPS_PACRJ_SP7_SHIFT (2U)
2608#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2609#define AIPS_PACRJ_TP6_MASK (0x10U)
2610#define AIPS_PACRJ_TP6_SHIFT (4U)
2615#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2616#define AIPS_PACRJ_WP6_MASK (0x20U)
2617#define AIPS_PACRJ_WP6_SHIFT (5U)
2622#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2623#define AIPS_PACRJ_SP6_MASK (0x40U)
2624#define AIPS_PACRJ_SP6_SHIFT (6U)
2629#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2630#define AIPS_PACRJ_TP5_MASK (0x100U)
2631#define AIPS_PACRJ_TP5_SHIFT (8U)
2636#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2637#define AIPS_PACRJ_WP5_MASK (0x200U)
2638#define AIPS_PACRJ_WP5_SHIFT (9U)
2643#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2644#define AIPS_PACRJ_SP5_MASK (0x400U)
2645#define AIPS_PACRJ_SP5_SHIFT (10U)
2650#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2651#define AIPS_PACRJ_TP4_MASK (0x1000U)
2652#define AIPS_PACRJ_TP4_SHIFT (12U)
2657#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2658#define AIPS_PACRJ_WP4_MASK (0x2000U)
2659#define AIPS_PACRJ_WP4_SHIFT (13U)
2664#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2665#define AIPS_PACRJ_SP4_MASK (0x4000U)
2666#define AIPS_PACRJ_SP4_SHIFT (14U)
2671#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2672#define AIPS_PACRJ_TP3_MASK (0x10000U)
2673#define AIPS_PACRJ_TP3_SHIFT (16U)
2678#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2679#define AIPS_PACRJ_WP3_MASK (0x20000U)
2680#define AIPS_PACRJ_WP3_SHIFT (17U)
2685#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2686#define AIPS_PACRJ_SP3_MASK (0x40000U)
2687#define AIPS_PACRJ_SP3_SHIFT (18U)
2692#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2693#define AIPS_PACRJ_TP2_MASK (0x100000U)
2694#define AIPS_PACRJ_TP2_SHIFT (20U)
2699#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2700#define AIPS_PACRJ_WP2_MASK (0x200000U)
2701#define AIPS_PACRJ_WP2_SHIFT (21U)
2706#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2707#define AIPS_PACRJ_SP2_MASK (0x400000U)
2708#define AIPS_PACRJ_SP2_SHIFT (22U)
2713#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2714#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2715#define AIPS_PACRJ_TP1_SHIFT (24U)
2720#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2721#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2722#define AIPS_PACRJ_WP1_SHIFT (25U)
2727#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2728#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2729#define AIPS_PACRJ_SP1_SHIFT (26U)
2734#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2735#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2736#define AIPS_PACRJ_TP0_SHIFT (28U)
2741#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2742#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2743#define AIPS_PACRJ_WP0_SHIFT (29U)
2748#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2749#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2750#define AIPS_PACRJ_SP0_SHIFT (30U)
2755#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2760#define AIPS_PACRK_TP7_MASK (0x1U)
2761#define AIPS_PACRK_TP7_SHIFT (0U)
2766#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2767#define AIPS_PACRK_WP7_MASK (0x2U)
2768#define AIPS_PACRK_WP7_SHIFT (1U)
2773#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2774#define AIPS_PACRK_SP7_MASK (0x4U)
2775#define AIPS_PACRK_SP7_SHIFT (2U)
2780#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2781#define AIPS_PACRK_TP6_MASK (0x10U)
2782#define AIPS_PACRK_TP6_SHIFT (4U)
2787#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2788#define AIPS_PACRK_WP6_MASK (0x20U)
2789#define AIPS_PACRK_WP6_SHIFT (5U)
2794#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2795#define AIPS_PACRK_SP6_MASK (0x40U)
2796#define AIPS_PACRK_SP6_SHIFT (6U)
2801#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
2802#define AIPS_PACRK_TP5_MASK (0x100U)
2803#define AIPS_PACRK_TP5_SHIFT (8U)
2808#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
2809#define AIPS_PACRK_WP5_MASK (0x200U)
2810#define AIPS_PACRK_WP5_SHIFT (9U)
2815#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
2816#define AIPS_PACRK_SP5_MASK (0x400U)
2817#define AIPS_PACRK_SP5_SHIFT (10U)
2822#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
2823#define AIPS_PACRK_TP4_MASK (0x1000U)
2824#define AIPS_PACRK_TP4_SHIFT (12U)
2829#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
2830#define AIPS_PACRK_WP4_MASK (0x2000U)
2831#define AIPS_PACRK_WP4_SHIFT (13U)
2836#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
2837#define AIPS_PACRK_SP4_MASK (0x4000U)
2838#define AIPS_PACRK_SP4_SHIFT (14U)
2843#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
2844#define AIPS_PACRK_TP3_MASK (0x10000U)
2845#define AIPS_PACRK_TP3_SHIFT (16U)
2850#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
2851#define AIPS_PACRK_WP3_MASK (0x20000U)
2852#define AIPS_PACRK_WP3_SHIFT (17U)
2857#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
2858#define AIPS_PACRK_SP3_MASK (0x40000U)
2859#define AIPS_PACRK_SP3_SHIFT (18U)
2864#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
2865#define AIPS_PACRK_TP2_MASK (0x100000U)
2866#define AIPS_PACRK_TP2_SHIFT (20U)
2871#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
2872#define AIPS_PACRK_WP2_MASK (0x200000U)
2873#define AIPS_PACRK_WP2_SHIFT (21U)
2878#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
2879#define AIPS_PACRK_SP2_MASK (0x400000U)
2880#define AIPS_PACRK_SP2_SHIFT (22U)
2885#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
2886#define AIPS_PACRK_TP1_MASK (0x1000000U)
2887#define AIPS_PACRK_TP1_SHIFT (24U)
2892#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
2893#define AIPS_PACRK_WP1_MASK (0x2000000U)
2894#define AIPS_PACRK_WP1_SHIFT (25U)
2899#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
2900#define AIPS_PACRK_SP1_MASK (0x4000000U)
2901#define AIPS_PACRK_SP1_SHIFT (26U)
2906#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
2907#define AIPS_PACRK_TP0_MASK (0x10000000U)
2908#define AIPS_PACRK_TP0_SHIFT (28U)
2913#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
2914#define AIPS_PACRK_WP0_MASK (0x20000000U)
2915#define AIPS_PACRK_WP0_SHIFT (29U)
2920#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
2921#define AIPS_PACRK_SP0_MASK (0x40000000U)
2922#define AIPS_PACRK_SP0_SHIFT (30U)
2927#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
2932#define AIPS_PACRL_TP7_MASK (0x1U)
2933#define AIPS_PACRL_TP7_SHIFT (0U)
2938#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
2939#define AIPS_PACRL_WP7_MASK (0x2U)
2940#define AIPS_PACRL_WP7_SHIFT (1U)
2945#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
2946#define AIPS_PACRL_SP7_MASK (0x4U)
2947#define AIPS_PACRL_SP7_SHIFT (2U)
2952#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
2953#define AIPS_PACRL_TP6_MASK (0x10U)
2954#define AIPS_PACRL_TP6_SHIFT (4U)
2959#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
2960#define AIPS_PACRL_WP6_MASK (0x20U)
2961#define AIPS_PACRL_WP6_SHIFT (5U)
2966#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
2967#define AIPS_PACRL_SP6_MASK (0x40U)
2968#define AIPS_PACRL_SP6_SHIFT (6U)
2973#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
2974#define AIPS_PACRL_TP5_MASK (0x100U)
2975#define AIPS_PACRL_TP5_SHIFT (8U)
2980#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
2981#define AIPS_PACRL_WP5_MASK (0x200U)
2982#define AIPS_PACRL_WP5_SHIFT (9U)
2987#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
2988#define AIPS_PACRL_SP5_MASK (0x400U)
2989#define AIPS_PACRL_SP5_SHIFT (10U)
2994#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
2995#define AIPS_PACRL_TP4_MASK (0x1000U)
2996#define AIPS_PACRL_TP4_SHIFT (12U)
3001#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3002#define AIPS_PACRL_WP4_MASK (0x2000U)
3003#define AIPS_PACRL_WP4_SHIFT (13U)
3008#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3009#define AIPS_PACRL_SP4_MASK (0x4000U)
3010#define AIPS_PACRL_SP4_SHIFT (14U)
3015#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3016#define AIPS_PACRL_TP3_MASK (0x10000U)
3017#define AIPS_PACRL_TP3_SHIFT (16U)
3022#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3023#define AIPS_PACRL_WP3_MASK (0x20000U)
3024#define AIPS_PACRL_WP3_SHIFT (17U)
3029#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3030#define AIPS_PACRL_SP3_MASK (0x40000U)
3031#define AIPS_PACRL_SP3_SHIFT (18U)
3036#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3037#define AIPS_PACRL_TP2_MASK (0x100000U)
3038#define AIPS_PACRL_TP2_SHIFT (20U)
3043#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3044#define AIPS_PACRL_WP2_MASK (0x200000U)
3045#define AIPS_PACRL_WP2_SHIFT (21U)
3050#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3051#define AIPS_PACRL_SP2_MASK (0x400000U)
3052#define AIPS_PACRL_SP2_SHIFT (22U)
3057#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3058#define AIPS_PACRL_TP1_MASK (0x1000000U)
3059#define AIPS_PACRL_TP1_SHIFT (24U)
3064#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3065#define AIPS_PACRL_WP1_MASK (0x2000000U)
3066#define AIPS_PACRL_WP1_SHIFT (25U)
3071#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3072#define AIPS_PACRL_SP1_MASK (0x4000000U)
3073#define AIPS_PACRL_SP1_SHIFT (26U)
3078#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3079#define AIPS_PACRL_TP0_MASK (0x10000000U)
3080#define AIPS_PACRL_TP0_SHIFT (28U)
3085#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3086#define AIPS_PACRL_WP0_MASK (0x20000000U)
3087#define AIPS_PACRL_WP0_SHIFT (29U)
3092#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3093#define AIPS_PACRL_SP0_MASK (0x40000000U)
3094#define AIPS_PACRL_SP0_SHIFT (30U)
3099#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3104#define AIPS_PACRM_TP7_MASK (0x1U)
3105#define AIPS_PACRM_TP7_SHIFT (0U)
3110#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3111#define AIPS_PACRM_WP7_MASK (0x2U)
3112#define AIPS_PACRM_WP7_SHIFT (1U)
3117#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3118#define AIPS_PACRM_SP7_MASK (0x4U)
3119#define AIPS_PACRM_SP7_SHIFT (2U)
3124#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3125#define AIPS_PACRM_TP6_MASK (0x10U)
3126#define AIPS_PACRM_TP6_SHIFT (4U)
3131#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3132#define AIPS_PACRM_WP6_MASK (0x20U)
3133#define AIPS_PACRM_WP6_SHIFT (5U)
3138#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3139#define AIPS_PACRM_SP6_MASK (0x40U)
3140#define AIPS_PACRM_SP6_SHIFT (6U)
3145#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3146#define AIPS_PACRM_TP5_MASK (0x100U)
3147#define AIPS_PACRM_TP5_SHIFT (8U)
3152#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3153#define AIPS_PACRM_WP5_MASK (0x200U)
3154#define AIPS_PACRM_WP5_SHIFT (9U)
3159#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3160#define AIPS_PACRM_SP5_MASK (0x400U)
3161#define AIPS_PACRM_SP5_SHIFT (10U)
3166#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3167#define AIPS_PACRM_TP4_MASK (0x1000U)
3168#define AIPS_PACRM_TP4_SHIFT (12U)
3173#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3174#define AIPS_PACRM_WP4_MASK (0x2000U)
3175#define AIPS_PACRM_WP4_SHIFT (13U)
3180#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3181#define AIPS_PACRM_SP4_MASK (0x4000U)
3182#define AIPS_PACRM_SP4_SHIFT (14U)
3187#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3188#define AIPS_PACRM_TP3_MASK (0x10000U)
3189#define AIPS_PACRM_TP3_SHIFT (16U)
3194#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3195#define AIPS_PACRM_WP3_MASK (0x20000U)
3196#define AIPS_PACRM_WP3_SHIFT (17U)
3201#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3202#define AIPS_PACRM_SP3_MASK (0x40000U)
3203#define AIPS_PACRM_SP3_SHIFT (18U)
3208#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3209#define AIPS_PACRM_TP2_MASK (0x100000U)
3210#define AIPS_PACRM_TP2_SHIFT (20U)
3215#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3216#define AIPS_PACRM_WP2_MASK (0x200000U)
3217#define AIPS_PACRM_WP2_SHIFT (21U)
3222#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3223#define AIPS_PACRM_SP2_MASK (0x400000U)
3224#define AIPS_PACRM_SP2_SHIFT (22U)
3229#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3230#define AIPS_PACRM_TP1_MASK (0x1000000U)
3231#define AIPS_PACRM_TP1_SHIFT (24U)
3236#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3237#define AIPS_PACRM_WP1_MASK (0x2000000U)
3238#define AIPS_PACRM_WP1_SHIFT (25U)
3243#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3244#define AIPS_PACRM_SP1_MASK (0x4000000U)
3245#define AIPS_PACRM_SP1_SHIFT (26U)
3250#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3251#define AIPS_PACRM_TP0_MASK (0x10000000U)
3252#define AIPS_PACRM_TP0_SHIFT (28U)
3257#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3258#define AIPS_PACRM_WP0_MASK (0x20000000U)
3259#define AIPS_PACRM_WP0_SHIFT (29U)
3264#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3265#define AIPS_PACRM_SP0_MASK (0x40000000U)
3266#define AIPS_PACRM_SP0_SHIFT (30U)
3271#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3276#define AIPS_PACRN_TP7_MASK (0x1U)
3277#define AIPS_PACRN_TP7_SHIFT (0U)
3282#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3283#define AIPS_PACRN_WP7_MASK (0x2U)
3284#define AIPS_PACRN_WP7_SHIFT (1U)
3289#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3290#define AIPS_PACRN_SP7_MASK (0x4U)
3291#define AIPS_PACRN_SP7_SHIFT (2U)
3296#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3297#define AIPS_PACRN_TP6_MASK (0x10U)
3298#define AIPS_PACRN_TP6_SHIFT (4U)
3303#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3304#define AIPS_PACRN_WP6_MASK (0x20U)
3305#define AIPS_PACRN_WP6_SHIFT (5U)
3310#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3311#define AIPS_PACRN_SP6_MASK (0x40U)
3312#define AIPS_PACRN_SP6_SHIFT (6U)
3317#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3318#define AIPS_PACRN_TP5_MASK (0x100U)
3319#define AIPS_PACRN_TP5_SHIFT (8U)
3324#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3325#define AIPS_PACRN_WP5_MASK (0x200U)
3326#define AIPS_PACRN_WP5_SHIFT (9U)
3331#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3332#define AIPS_PACRN_SP5_MASK (0x400U)
3333#define AIPS_PACRN_SP5_SHIFT (10U)
3338#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3339#define AIPS_PACRN_TP4_MASK (0x1000U)
3340#define AIPS_PACRN_TP4_SHIFT (12U)
3345#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3346#define AIPS_PACRN_WP4_MASK (0x2000U)
3347#define AIPS_PACRN_WP4_SHIFT (13U)
3352#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3353#define AIPS_PACRN_SP4_MASK (0x4000U)
3354#define AIPS_PACRN_SP4_SHIFT (14U)
3359#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3360#define AIPS_PACRN_TP3_MASK (0x10000U)
3361#define AIPS_PACRN_TP3_SHIFT (16U)
3366#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3367#define AIPS_PACRN_WP3_MASK (0x20000U)
3368#define AIPS_PACRN_WP3_SHIFT (17U)
3373#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3374#define AIPS_PACRN_SP3_MASK (0x40000U)
3375#define AIPS_PACRN_SP3_SHIFT (18U)
3380#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3381#define AIPS_PACRN_TP2_MASK (0x100000U)
3382#define AIPS_PACRN_TP2_SHIFT (20U)
3387#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3388#define AIPS_PACRN_WP2_MASK (0x200000U)
3389#define AIPS_PACRN_WP2_SHIFT (21U)
3394#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3395#define AIPS_PACRN_SP2_MASK (0x400000U)
3396#define AIPS_PACRN_SP2_SHIFT (22U)
3401#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3402#define AIPS_PACRN_TP1_MASK (0x1000000U)
3403#define AIPS_PACRN_TP1_SHIFT (24U)
3408#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3409#define AIPS_PACRN_WP1_MASK (0x2000000U)
3410#define AIPS_PACRN_WP1_SHIFT (25U)
3415#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3416#define AIPS_PACRN_SP1_MASK (0x4000000U)
3417#define AIPS_PACRN_SP1_SHIFT (26U)
3422#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3423#define AIPS_PACRN_TP0_MASK (0x10000000U)
3424#define AIPS_PACRN_TP0_SHIFT (28U)
3429#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3430#define AIPS_PACRN_WP0_MASK (0x20000000U)
3431#define AIPS_PACRN_WP0_SHIFT (29U)
3436#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3437#define AIPS_PACRN_SP0_MASK (0x40000000U)
3438#define AIPS_PACRN_SP0_SHIFT (30U)
3443#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3448#define AIPS_PACRO_TP7_MASK (0x1U)
3449#define AIPS_PACRO_TP7_SHIFT (0U)
3454#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3455#define AIPS_PACRO_WP7_MASK (0x2U)
3456#define AIPS_PACRO_WP7_SHIFT (1U)
3461#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3462#define AIPS_PACRO_SP7_MASK (0x4U)
3463#define AIPS_PACRO_SP7_SHIFT (2U)
3468#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3469#define AIPS_PACRO_TP6_MASK (0x10U)
3470#define AIPS_PACRO_TP6_SHIFT (4U)
3475#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3476#define AIPS_PACRO_WP6_MASK (0x20U)
3477#define AIPS_PACRO_WP6_SHIFT (5U)
3482#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3483#define AIPS_PACRO_SP6_MASK (0x40U)
3484#define AIPS_PACRO_SP6_SHIFT (6U)
3489#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3490#define AIPS_PACRO_TP5_MASK (0x100U)
3491#define AIPS_PACRO_TP5_SHIFT (8U)
3496#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3497#define AIPS_PACRO_WP5_MASK (0x200U)
3498#define AIPS_PACRO_WP5_SHIFT (9U)
3503#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3504#define AIPS_PACRO_SP5_MASK (0x400U)
3505#define AIPS_PACRO_SP5_SHIFT (10U)
3510#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3511#define AIPS_PACRO_TP4_MASK (0x1000U)
3512#define AIPS_PACRO_TP4_SHIFT (12U)
3517#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3518#define AIPS_PACRO_WP4_MASK (0x2000U)
3519#define AIPS_PACRO_WP4_SHIFT (13U)
3524#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3525#define AIPS_PACRO_SP4_MASK (0x4000U)
3526#define AIPS_PACRO_SP4_SHIFT (14U)
3531#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3532#define AIPS_PACRO_TP3_MASK (0x10000U)
3533#define AIPS_PACRO_TP3_SHIFT (16U)
3538#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3539#define AIPS_PACRO_WP3_MASK (0x20000U)
3540#define AIPS_PACRO_WP3_SHIFT (17U)
3545#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3546#define AIPS_PACRO_SP3_MASK (0x40000U)
3547#define AIPS_PACRO_SP3_SHIFT (18U)
3552#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3553#define AIPS_PACRO_TP2_MASK (0x100000U)
3554#define AIPS_PACRO_TP2_SHIFT (20U)
3559#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3560#define AIPS_PACRO_WP2_MASK (0x200000U)
3561#define AIPS_PACRO_WP2_SHIFT (21U)
3566#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3567#define AIPS_PACRO_SP2_MASK (0x400000U)
3568#define AIPS_PACRO_SP2_SHIFT (22U)
3573#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3574#define AIPS_PACRO_TP1_MASK (0x1000000U)
3575#define AIPS_PACRO_TP1_SHIFT (24U)
3580#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3581#define AIPS_PACRO_WP1_MASK (0x2000000U)
3582#define AIPS_PACRO_WP1_SHIFT (25U)
3587#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3588#define AIPS_PACRO_SP1_MASK (0x4000000U)
3589#define AIPS_PACRO_SP1_SHIFT (26U)
3594#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3595#define AIPS_PACRO_TP0_MASK (0x10000000U)
3596#define AIPS_PACRO_TP0_SHIFT (28U)
3601#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3602#define AIPS_PACRO_WP0_MASK (0x20000000U)
3603#define AIPS_PACRO_WP0_SHIFT (29U)
3608#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3609#define AIPS_PACRO_SP0_MASK (0x40000000U)
3610#define AIPS_PACRO_SP0_SHIFT (30U)
3615#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3620#define AIPS_PACRP_TP7_MASK (0x1U)
3621#define AIPS_PACRP_TP7_SHIFT (0U)
3626#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3627#define AIPS_PACRP_WP7_MASK (0x2U)
3628#define AIPS_PACRP_WP7_SHIFT (1U)
3633#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3634#define AIPS_PACRP_SP7_MASK (0x4U)
3635#define AIPS_PACRP_SP7_SHIFT (2U)
3640#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3641#define AIPS_PACRP_TP6_MASK (0x10U)
3642#define AIPS_PACRP_TP6_SHIFT (4U)
3647#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3648#define AIPS_PACRP_WP6_MASK (0x20U)
3649#define AIPS_PACRP_WP6_SHIFT (5U)
3654#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3655#define AIPS_PACRP_SP6_MASK (0x40U)
3656#define AIPS_PACRP_SP6_SHIFT (6U)
3661#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3662#define AIPS_PACRP_TP5_MASK (0x100U)
3663#define AIPS_PACRP_TP5_SHIFT (8U)
3668#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3669#define AIPS_PACRP_WP5_MASK (0x200U)
3670#define AIPS_PACRP_WP5_SHIFT (9U)
3675#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3676#define AIPS_PACRP_SP5_MASK (0x400U)
3677#define AIPS_PACRP_SP5_SHIFT (10U)
3682#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3683#define AIPS_PACRP_TP4_MASK (0x1000U)
3684#define AIPS_PACRP_TP4_SHIFT (12U)
3689#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3690#define AIPS_PACRP_WP4_MASK (0x2000U)
3691#define AIPS_PACRP_WP4_SHIFT (13U)
3696#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3697#define AIPS_PACRP_SP4_MASK (0x4000U)
3698#define AIPS_PACRP_SP4_SHIFT (14U)
3703#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3704#define AIPS_PACRP_TP3_MASK (0x10000U)
3705#define AIPS_PACRP_TP3_SHIFT (16U)
3710#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3711#define AIPS_PACRP_WP3_MASK (0x20000U)
3712#define AIPS_PACRP_WP3_SHIFT (17U)
3717#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3718#define AIPS_PACRP_SP3_MASK (0x40000U)
3719#define AIPS_PACRP_SP3_SHIFT (18U)
3724#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3725#define AIPS_PACRP_TP2_MASK (0x100000U)
3726#define AIPS_PACRP_TP2_SHIFT (20U)
3731#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3732#define AIPS_PACRP_WP2_MASK (0x200000U)
3733#define AIPS_PACRP_WP2_SHIFT (21U)
3738#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3739#define AIPS_PACRP_SP2_MASK (0x400000U)
3740#define AIPS_PACRP_SP2_SHIFT (22U)
3745#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3746#define AIPS_PACRP_TP1_MASK (0x1000000U)
3747#define AIPS_PACRP_TP1_SHIFT (24U)
3752#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3753#define AIPS_PACRP_WP1_MASK (0x2000000U)
3754#define AIPS_PACRP_WP1_SHIFT (25U)
3759#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3760#define AIPS_PACRP_SP1_MASK (0x4000000U)
3761#define AIPS_PACRP_SP1_SHIFT (26U)
3766#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3767#define AIPS_PACRP_TP0_MASK (0x10000000U)
3768#define AIPS_PACRP_TP0_SHIFT (28U)
3773#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3774#define AIPS_PACRP_WP0_MASK (0x20000000U)
3775#define AIPS_PACRP_WP0_SHIFT (29U)
3780#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3781#define AIPS_PACRP_SP0_MASK (0x40000000U)
3782#define AIPS_PACRP_SP0_SHIFT (30U)
3787#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3792#define AIPS_PACRU_TP1_MASK (0x1000000U)
3793#define AIPS_PACRU_TP1_SHIFT (24U)
3798#define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK)
3799#define AIPS_PACRU_WP1_MASK (0x2000000U)
3800#define AIPS_PACRU_WP1_SHIFT (25U)
3805#define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK)
3806#define AIPS_PACRU_SP1_MASK (0x4000000U)
3807#define AIPS_PACRU_SP1_SHIFT (26U)
3812#define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK)
3813#define AIPS_PACRU_TP0_MASK (0x10000000U)
3814#define AIPS_PACRU_TP0_SHIFT (28U)
3819#define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK)
3820#define AIPS_PACRU_WP0_MASK (0x20000000U)
3821#define AIPS_PACRU_WP0_SHIFT (29U)
3826#define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK)
3827#define AIPS_PACRU_SP0_MASK (0x40000000U)
3828#define AIPS_PACRU_SP0_SHIFT (30U)
3833#define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK)
3839 /* end of group AIPS_Register_Masks */
3840
3841
3842/* AIPS - Peripheral instance base addresses */
3844#define AIPS0_BASE (0x40000000u)
3846#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
3848#define AIPS1_BASE (0x40080000u)
3850#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
3852#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
3854#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
3855
3858 /* end of group AIPS_Peripheral_Access_Layer */
3859
3860
3861/* ----------------------------------------------------------------------------
3862 -- AXBS Peripheral Access Layer
3863 ---------------------------------------------------------------------------- */
3864
3871typedef struct {
3872 struct { /* offset: 0x0, array step: 0x100 */
3873 __IO uint32_t PRS;
3874 uint8_t RESERVED_0[12];
3875 __IO uint32_t CRS;
3876 uint8_t RESERVED_1[236];
3877 } SLAVE[5];
3878 uint8_t RESERVED_0[768];
3879 __IO uint32_t MGPCR0;
3880 uint8_t RESERVED_1[252];
3881 __IO uint32_t MGPCR1;
3882 uint8_t RESERVED_2[252];
3883 __IO uint32_t MGPCR2;
3884 uint8_t RESERVED_3[252];
3885 __IO uint32_t MGPCR3;
3886 uint8_t RESERVED_4[252];
3887 __IO uint32_t MGPCR4;
3888 uint8_t RESERVED_5[252];
3889 __IO uint32_t MGPCR5;
3890} AXBS_Type;
3891
3892/* ----------------------------------------------------------------------------
3893 -- AXBS Register Masks
3894 ---------------------------------------------------------------------------- */
3895
3903#define AXBS_PRS_M0_MASK (0x7U)
3904#define AXBS_PRS_M0_SHIFT (0U)
3915#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
3916#define AXBS_PRS_M1_MASK (0x70U)
3917#define AXBS_PRS_M1_SHIFT (4U)
3928#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
3929#define AXBS_PRS_M2_MASK (0x700U)
3930#define AXBS_PRS_M2_SHIFT (8U)
3941#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
3942#define AXBS_PRS_M3_MASK (0x7000U)
3943#define AXBS_PRS_M3_SHIFT (12U)
3954#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
3955#define AXBS_PRS_M4_MASK (0x70000U)
3956#define AXBS_PRS_M4_SHIFT (16U)
3967#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
3968#define AXBS_PRS_M5_MASK (0x700000U)
3969#define AXBS_PRS_M5_SHIFT (20U)
3980#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
3983/* The count of AXBS_PRS */
3984#define AXBS_PRS_COUNT (5U)
3985
3988#define AXBS_CRS_PARK_MASK (0x7U)
3989#define AXBS_CRS_PARK_SHIFT (0U)
4000#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
4001#define AXBS_CRS_PCTL_MASK (0x30U)
4002#define AXBS_CRS_PCTL_SHIFT (4U)
4009#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
4010#define AXBS_CRS_ARB_MASK (0x300U)
4011#define AXBS_CRS_ARB_SHIFT (8U)
4018#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
4019#define AXBS_CRS_HLP_MASK (0x40000000U)
4020#define AXBS_CRS_HLP_SHIFT (30U)
4025#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
4026#define AXBS_CRS_RO_MASK (0x80000000U)
4027#define AXBS_CRS_RO_SHIFT (31U)
4032#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4035/* The count of AXBS_CRS */
4036#define AXBS_CRS_COUNT (5U)
4037
4040#define AXBS_MGPCR0_AULB_MASK (0x7U)
4041#define AXBS_MGPCR0_AULB_SHIFT (0U)
4052#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4057#define AXBS_MGPCR1_AULB_MASK (0x7U)
4058#define AXBS_MGPCR1_AULB_SHIFT (0U)
4069#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4074#define AXBS_MGPCR2_AULB_MASK (0x7U)
4075#define AXBS_MGPCR2_AULB_SHIFT (0U)
4086#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4091#define AXBS_MGPCR3_AULB_MASK (0x7U)
4092#define AXBS_MGPCR3_AULB_SHIFT (0U)
4103#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
4108#define AXBS_MGPCR4_AULB_MASK (0x7U)
4109#define AXBS_MGPCR4_AULB_SHIFT (0U)
4120#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
4125#define AXBS_MGPCR5_AULB_MASK (0x7U)
4126#define AXBS_MGPCR5_AULB_SHIFT (0U)
4137#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
4143 /* end of group AXBS_Register_Masks */
4144
4145
4146/* AXBS - Peripheral instance base addresses */
4148#define AXBS_BASE (0x40004000u)
4150#define AXBS ((AXBS_Type *)AXBS_BASE)
4152#define AXBS_BASE_ADDRS { AXBS_BASE }
4154#define AXBS_BASE_PTRS { AXBS }
4155
4158 /* end of group AXBS_Peripheral_Access_Layer */
4159
4160
4161/* ----------------------------------------------------------------------------
4162 -- CAN Peripheral Access Layer
4163 ---------------------------------------------------------------------------- */
4164
4171typedef struct {
4172 __IO uint32_t MCR;
4173 __IO uint32_t CTRL1;
4174 __IO uint32_t TIMER;
4175 uint8_t RESERVED_0[4];
4176 __IO uint32_t RXMGMASK;
4177 __IO uint32_t RX14MASK;
4178 __IO uint32_t RX15MASK;
4179 __IO uint32_t ECR;
4180 __IO uint32_t ESR1;
4181 uint8_t RESERVED_1[4];
4182 __IO uint32_t IMASK1;
4183 uint8_t RESERVED_2[4];
4184 __IO uint32_t IFLAG1;
4185 __IO uint32_t CTRL2;
4186 __I uint32_t ESR2;
4187 uint8_t RESERVED_3[8];
4188 __I uint32_t CRCR;
4189 __IO uint32_t RXFGMASK;
4190 __I uint32_t RXFIR;
4191 uint8_t RESERVED_4[48];
4192 struct { /* offset: 0x80, array step: 0x10 */
4193 __IO uint32_t CS;
4194 __IO uint32_t ID;
4195 __IO uint32_t WORD0;
4196 __IO uint32_t WORD1;
4197 } MB[16];
4198 uint8_t RESERVED_5[1792];
4199 __IO uint32_t RXIMR[16];
4200} CAN_Type;
4201
4202/* ----------------------------------------------------------------------------
4203 -- CAN Register Masks
4204 ---------------------------------------------------------------------------- */
4205
4213#define CAN_MCR_MAXMB_MASK (0x7FU)
4214#define CAN_MCR_MAXMB_SHIFT (0U)
4215#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4216#define CAN_MCR_IDAM_MASK (0x300U)
4217#define CAN_MCR_IDAM_SHIFT (8U)
4224#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4225#define CAN_MCR_AEN_MASK (0x1000U)
4226#define CAN_MCR_AEN_SHIFT (12U)
4231#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4232#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4233#define CAN_MCR_LPRIOEN_SHIFT (13U)
4238#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4239#define CAN_MCR_IRMQ_MASK (0x10000U)
4240#define CAN_MCR_IRMQ_SHIFT (16U)
4245#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4246#define CAN_MCR_SRXDIS_MASK (0x20000U)
4247#define CAN_MCR_SRXDIS_SHIFT (17U)
4252#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4253#define CAN_MCR_WAKSRC_MASK (0x80000U)
4254#define CAN_MCR_WAKSRC_SHIFT (19U)
4259#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4260#define CAN_MCR_LPMACK_MASK (0x100000U)
4261#define CAN_MCR_LPMACK_SHIFT (20U)
4266#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4267#define CAN_MCR_WRNEN_MASK (0x200000U)
4268#define CAN_MCR_WRNEN_SHIFT (21U)
4273#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4274#define CAN_MCR_SLFWAK_MASK (0x400000U)
4275#define CAN_MCR_SLFWAK_SHIFT (22U)
4280#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4281#define CAN_MCR_SUPV_MASK (0x800000U)
4282#define CAN_MCR_SUPV_SHIFT (23U)
4287#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4288#define CAN_MCR_FRZACK_MASK (0x1000000U)
4289#define CAN_MCR_FRZACK_SHIFT (24U)
4294#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4295#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4296#define CAN_MCR_SOFTRST_SHIFT (25U)
4301#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4302#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4303#define CAN_MCR_WAKMSK_SHIFT (26U)
4308#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4309#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4310#define CAN_MCR_NOTRDY_SHIFT (27U)
4315#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4316#define CAN_MCR_HALT_MASK (0x10000000U)
4317#define CAN_MCR_HALT_SHIFT (28U)
4322#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4323#define CAN_MCR_RFEN_MASK (0x20000000U)
4324#define CAN_MCR_RFEN_SHIFT (29U)
4329#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4330#define CAN_MCR_FRZ_MASK (0x40000000U)
4331#define CAN_MCR_FRZ_SHIFT (30U)
4336#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4337#define CAN_MCR_MDIS_MASK (0x80000000U)
4338#define CAN_MCR_MDIS_SHIFT (31U)
4343#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4348#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4349#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4350#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4351#define CAN_CTRL1_LOM_MASK (0x8U)
4352#define CAN_CTRL1_LOM_SHIFT (3U)
4357#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4358#define CAN_CTRL1_LBUF_MASK (0x10U)
4359#define CAN_CTRL1_LBUF_SHIFT (4U)
4364#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4365#define CAN_CTRL1_TSYN_MASK (0x20U)
4366#define CAN_CTRL1_TSYN_SHIFT (5U)
4371#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4372#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4373#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4378#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4379#define CAN_CTRL1_SMP_MASK (0x80U)
4380#define CAN_CTRL1_SMP_SHIFT (7U)
4385#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4386#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4387#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4392#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4393#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4394#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4399#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4400#define CAN_CTRL1_LPB_MASK (0x1000U)
4401#define CAN_CTRL1_LPB_SHIFT (12U)
4406#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4407#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4408#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4413#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4414#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4415#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4420#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4421#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4422#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4427#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4428#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4429#define CAN_CTRL1_PSEG2_SHIFT (16U)
4430#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4431#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4432#define CAN_CTRL1_PSEG1_SHIFT (19U)
4433#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4434#define CAN_CTRL1_RJW_MASK (0xC00000U)
4435#define CAN_CTRL1_RJW_SHIFT (22U)
4436#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4437#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4438#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4439#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4444#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4445#define CAN_TIMER_TIMER_SHIFT (0U)
4446#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4451#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4452#define CAN_RXMGMASK_MG_SHIFT (0U)
4457#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4462#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4463#define CAN_RX14MASK_RX14M_SHIFT (0U)
4468#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4473#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4474#define CAN_RX15MASK_RX15M_SHIFT (0U)
4479#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4484#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4485#define CAN_ECR_TXERRCNT_SHIFT (0U)
4486#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4487#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4488#define CAN_ECR_RXERRCNT_SHIFT (8U)
4489#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4494#define CAN_ESR1_WAKINT_MASK (0x1U)
4495#define CAN_ESR1_WAKINT_SHIFT (0U)
4500#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4501#define CAN_ESR1_ERRINT_MASK (0x2U)
4502#define CAN_ESR1_ERRINT_SHIFT (1U)
4507#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4508#define CAN_ESR1_BOFFINT_MASK (0x4U)
4509#define CAN_ESR1_BOFFINT_SHIFT (2U)
4514#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4515#define CAN_ESR1_RX_MASK (0x8U)
4516#define CAN_ESR1_RX_SHIFT (3U)
4521#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4522#define CAN_ESR1_FLTCONF_MASK (0x30U)
4523#define CAN_ESR1_FLTCONF_SHIFT (4U)
4529#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4530#define CAN_ESR1_TX_MASK (0x40U)
4531#define CAN_ESR1_TX_SHIFT (6U)
4536#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4537#define CAN_ESR1_IDLE_MASK (0x80U)
4538#define CAN_ESR1_IDLE_SHIFT (7U)
4543#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4544#define CAN_ESR1_RXWRN_MASK (0x100U)
4545#define CAN_ESR1_RXWRN_SHIFT (8U)
4550#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4551#define CAN_ESR1_TXWRN_MASK (0x200U)
4552#define CAN_ESR1_TXWRN_SHIFT (9U)
4557#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4558#define CAN_ESR1_STFERR_MASK (0x400U)
4559#define CAN_ESR1_STFERR_SHIFT (10U)
4564#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4565#define CAN_ESR1_FRMERR_MASK (0x800U)
4566#define CAN_ESR1_FRMERR_SHIFT (11U)
4571#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4572#define CAN_ESR1_CRCERR_MASK (0x1000U)
4573#define CAN_ESR1_CRCERR_SHIFT (12U)
4578#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4579#define CAN_ESR1_ACKERR_MASK (0x2000U)
4580#define CAN_ESR1_ACKERR_SHIFT (13U)
4585#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4586#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4587#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4592#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4593#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4594#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4599#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4600#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4601#define CAN_ESR1_RWRNINT_SHIFT (16U)
4606#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4607#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4608#define CAN_ESR1_TWRNINT_SHIFT (17U)
4613#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4614#define CAN_ESR1_SYNCH_MASK (0x40000U)
4615#define CAN_ESR1_SYNCH_SHIFT (18U)
4620#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4625#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4626#define CAN_IMASK1_BUFLM_SHIFT (0U)
4631#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4636#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4637#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4642#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4643#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4644#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4649#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4650#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4651#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4656#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4657#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4658#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4663#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4664#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4665#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4670#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4671#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4672#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4677#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4682#define CAN_CTRL2_EACEN_MASK (0x10000U)
4683#define CAN_CTRL2_EACEN_SHIFT (16U)
4688#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4689#define CAN_CTRL2_RRS_MASK (0x20000U)
4690#define CAN_CTRL2_RRS_SHIFT (17U)
4695#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4696#define CAN_CTRL2_MRP_MASK (0x40000U)
4697#define CAN_CTRL2_MRP_SHIFT (18U)
4702#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4703#define CAN_CTRL2_TASD_MASK (0xF80000U)
4704#define CAN_CTRL2_TASD_SHIFT (19U)
4705#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4706#define CAN_CTRL2_RFFN_MASK (0xF000000U)
4707#define CAN_CTRL2_RFFN_SHIFT (24U)
4708#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4709#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4710#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4715#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4720#define CAN_ESR2_IMB_MASK (0x2000U)
4721#define CAN_ESR2_IMB_SHIFT (13U)
4726#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4727#define CAN_ESR2_VPS_MASK (0x4000U)
4728#define CAN_ESR2_VPS_SHIFT (14U)
4733#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4734#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4735#define CAN_ESR2_LPTM_SHIFT (16U)
4736#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4741#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4742#define CAN_CRCR_TXCRC_SHIFT (0U)
4743#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4744#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4745#define CAN_CRCR_MBCRC_SHIFT (16U)
4746#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4751#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4752#define CAN_RXFGMASK_FGM_SHIFT (0U)
4757#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4762#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4763#define CAN_RXFIR_IDHIT_SHIFT (0U)
4764#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4769#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4770#define CAN_CS_TIME_STAMP_SHIFT (0U)
4771#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4772#define CAN_CS_DLC_MASK (0xF0000U)
4773#define CAN_CS_DLC_SHIFT (16U)
4774#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4775#define CAN_CS_RTR_MASK (0x100000U)
4776#define CAN_CS_RTR_SHIFT (20U)
4777#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4778#define CAN_CS_IDE_MASK (0x200000U)
4779#define CAN_CS_IDE_SHIFT (21U)
4780#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4781#define CAN_CS_SRR_MASK (0x400000U)
4782#define CAN_CS_SRR_SHIFT (22U)
4783#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4784#define CAN_CS_CODE_MASK (0xF000000U)
4785#define CAN_CS_CODE_SHIFT (24U)
4786#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4789/* The count of CAN_CS */
4790#define CAN_CS_COUNT (16U)
4791
4794#define CAN_ID_EXT_MASK (0x3FFFFU)
4795#define CAN_ID_EXT_SHIFT (0U)
4796#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4797#define CAN_ID_STD_MASK (0x1FFC0000U)
4798#define CAN_ID_STD_SHIFT (18U)
4799#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4800#define CAN_ID_PRIO_MASK (0xE0000000U)
4801#define CAN_ID_PRIO_SHIFT (29U)
4802#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4805/* The count of CAN_ID */
4806#define CAN_ID_COUNT (16U)
4807
4810#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4811#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4812#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4813#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4814#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4815#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4816#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4817#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4818#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4819#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4820#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4821#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4824/* The count of CAN_WORD0 */
4825#define CAN_WORD0_COUNT (16U)
4826
4829#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4830#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4831#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4832#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4833#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4834#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4835#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4836#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4837#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4838#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4839#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4840#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4843/* The count of CAN_WORD1 */
4844#define CAN_WORD1_COUNT (16U)
4845
4848#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4849#define CAN_RXIMR_MI_SHIFT (0U)
4854#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4857/* The count of CAN_RXIMR */
4858#define CAN_RXIMR_COUNT (16U)
4859
4860
4863 /* end of group CAN_Register_Masks */
4864
4865
4866/* CAN - Peripheral instance base addresses */
4868#define CAN0_BASE (0x40024000u)
4870#define CAN0 ((CAN_Type *)CAN0_BASE)
4872#define CAN_BASE_ADDRS { CAN0_BASE }
4874#define CAN_BASE_PTRS { CAN0 }
4876#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
4877#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
4878#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
4879#define CAN_Error_IRQS { CAN0_Error_IRQn }
4880#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
4881#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
4882
4885 /* end of group CAN_Peripheral_Access_Layer */
4886
4887
4888/* ----------------------------------------------------------------------------
4889 -- CAU Peripheral Access Layer
4890 ---------------------------------------------------------------------------- */
4891
4898typedef struct {
4899 __O uint32_t DIRECT[16];
4900 uint8_t RESERVED_0[2048];
4901 __O uint32_t LDR_CASR;
4902 __O uint32_t LDR_CAA;
4903 __O uint32_t LDR_CA[9];
4904 uint8_t RESERVED_1[20];
4905 __I uint32_t STR_CASR;
4906 __I uint32_t STR_CAA;
4907 __I uint32_t STR_CA[9];
4908 uint8_t RESERVED_2[20];
4909 __O uint32_t ADR_CASR;
4910 __O uint32_t ADR_CAA;
4911 __O uint32_t ADR_CA[9];
4912 uint8_t RESERVED_3[20];
4913 __O uint32_t RADR_CASR;
4914 __O uint32_t RADR_CAA;
4915 __O uint32_t RADR_CA[9];
4916 uint8_t RESERVED_4[84];
4917 __O uint32_t XOR_CASR;
4918 __O uint32_t XOR_CAA;
4919 __O uint32_t XOR_CA[9];
4920 uint8_t RESERVED_5[20];
4921 __O uint32_t ROTL_CASR;
4922 __O uint32_t ROTL_CAA;
4923 __O uint32_t ROTL_CA[9];
4924 uint8_t RESERVED_6[276];
4925 __O uint32_t AESC_CASR;
4926 __O uint32_t AESC_CAA;
4927 __O uint32_t AESC_CA[9];
4928 uint8_t RESERVED_7[20];
4929 __O uint32_t AESIC_CASR;
4930 __O uint32_t AESIC_CAA;
4931 __O uint32_t AESIC_CA[9];
4932} CAU_Type;
4933
4934/* ----------------------------------------------------------------------------
4935 -- CAU Register Masks
4936 ---------------------------------------------------------------------------- */
4937
4945#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
4946#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
4947#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
4948#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
4949#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
4950#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
4951#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
4952#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
4953#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
4954#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
4955#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
4956#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
4957#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
4958#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
4959#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
4960#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
4961#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
4962#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
4963#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
4964#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
4965#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
4966#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
4967#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
4968#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
4969#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
4970#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
4971#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
4972#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
4973#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
4974#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
4975#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
4976#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
4977#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
4978#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
4979#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
4980#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
4981#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
4982#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
4983#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
4984#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
4985#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
4986#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
4987#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
4988#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
4989#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
4990#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
4991#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
4992#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
4995/* The count of CAU_DIRECT */
4996#define CAU_DIRECT_COUNT (16U)
4997
5000#define CAU_LDR_CASR_IC_MASK (0x1U)
5001#define CAU_LDR_CASR_IC_SHIFT (0U)
5006#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
5007#define CAU_LDR_CASR_DPE_MASK (0x2U)
5008#define CAU_LDR_CASR_DPE_SHIFT (1U)
5013#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
5014#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
5015#define CAU_LDR_CASR_VER_SHIFT (28U)
5020#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
5025#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
5026#define CAU_LDR_CAA_ACC_SHIFT (0U)
5027#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
5032#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
5033#define CAU_LDR_CA_CA0_SHIFT (0U)
5034#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
5035#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
5036#define CAU_LDR_CA_CA1_SHIFT (0U)
5037#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
5038#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
5039#define CAU_LDR_CA_CA2_SHIFT (0U)
5040#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
5041#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
5042#define CAU_LDR_CA_CA3_SHIFT (0U)
5043#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
5044#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
5045#define CAU_LDR_CA_CA4_SHIFT (0U)
5046#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
5047#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
5048#define CAU_LDR_CA_CA5_SHIFT (0U)
5049#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
5050#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
5051#define CAU_LDR_CA_CA6_SHIFT (0U)
5052#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
5053#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
5054#define CAU_LDR_CA_CA7_SHIFT (0U)
5055#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
5056#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
5057#define CAU_LDR_CA_CA8_SHIFT (0U)
5058#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
5061/* The count of CAU_LDR_CA */
5062#define CAU_LDR_CA_COUNT (9U)
5063
5066#define CAU_STR_CASR_IC_MASK (0x1U)
5067#define CAU_STR_CASR_IC_SHIFT (0U)
5072#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
5073#define CAU_STR_CASR_DPE_MASK (0x2U)
5074#define CAU_STR_CASR_DPE_SHIFT (1U)
5079#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
5080#define CAU_STR_CASR_VER_MASK (0xF0000000U)
5081#define CAU_STR_CASR_VER_SHIFT (28U)
5086#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
5091#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
5092#define CAU_STR_CAA_ACC_SHIFT (0U)
5093#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
5098#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
5099#define CAU_STR_CA_CA0_SHIFT (0U)
5100#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
5101#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
5102#define CAU_STR_CA_CA1_SHIFT (0U)
5103#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
5104#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
5105#define CAU_STR_CA_CA2_SHIFT (0U)
5106#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
5107#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
5108#define CAU_STR_CA_CA3_SHIFT (0U)
5109#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
5110#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
5111#define CAU_STR_CA_CA4_SHIFT (0U)
5112#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
5113#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
5114#define CAU_STR_CA_CA5_SHIFT (0U)
5115#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
5116#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
5117#define CAU_STR_CA_CA6_SHIFT (0U)
5118#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
5119#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
5120#define CAU_STR_CA_CA7_SHIFT (0U)
5121#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
5122#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
5123#define CAU_STR_CA_CA8_SHIFT (0U)
5124#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
5127/* The count of CAU_STR_CA */
5128#define CAU_STR_CA_COUNT (9U)
5129
5132#define CAU_ADR_CASR_IC_MASK (0x1U)
5133#define CAU_ADR_CASR_IC_SHIFT (0U)
5138#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
5139#define CAU_ADR_CASR_DPE_MASK (0x2U)
5140#define CAU_ADR_CASR_DPE_SHIFT (1U)
5145#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
5146#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
5147#define CAU_ADR_CASR_VER_SHIFT (28U)
5152#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
5157#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
5158#define CAU_ADR_CAA_ACC_SHIFT (0U)
5159#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
5164#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
5165#define CAU_ADR_CA_CA0_SHIFT (0U)
5166#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
5167#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
5168#define CAU_ADR_CA_CA1_SHIFT (0U)
5169#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
5170#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
5171#define CAU_ADR_CA_CA2_SHIFT (0U)
5172#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
5173#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
5174#define CAU_ADR_CA_CA3_SHIFT (0U)
5175#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
5176#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
5177#define CAU_ADR_CA_CA4_SHIFT (0U)
5178#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
5179#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
5180#define CAU_ADR_CA_CA5_SHIFT (0U)
5181#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
5182#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
5183#define CAU_ADR_CA_CA6_SHIFT (0U)
5184#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
5185#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
5186#define CAU_ADR_CA_CA7_SHIFT (0U)
5187#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
5188#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
5189#define CAU_ADR_CA_CA8_SHIFT (0U)
5190#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
5193/* The count of CAU_ADR_CA */
5194#define CAU_ADR_CA_COUNT (9U)
5195
5198#define CAU_RADR_CASR_IC_MASK (0x1U)
5199#define CAU_RADR_CASR_IC_SHIFT (0U)
5204#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
5205#define CAU_RADR_CASR_DPE_MASK (0x2U)
5206#define CAU_RADR_CASR_DPE_SHIFT (1U)
5211#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
5212#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
5213#define CAU_RADR_CASR_VER_SHIFT (28U)
5218#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
5223#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
5224#define CAU_RADR_CAA_ACC_SHIFT (0U)
5225#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
5230#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
5231#define CAU_RADR_CA_CA0_SHIFT (0U)
5232#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
5233#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
5234#define CAU_RADR_CA_CA1_SHIFT (0U)
5235#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
5236#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
5237#define CAU_RADR_CA_CA2_SHIFT (0U)
5238#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
5239#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
5240#define CAU_RADR_CA_CA3_SHIFT (0U)
5241#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
5242#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
5243#define CAU_RADR_CA_CA4_SHIFT (0U)
5244#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
5245#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
5246#define CAU_RADR_CA_CA5_SHIFT (0U)
5247#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
5248#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
5249#define CAU_RADR_CA_CA6_SHIFT (0U)
5250#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
5251#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
5252#define CAU_RADR_CA_CA7_SHIFT (0U)
5253#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
5254#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
5255#define CAU_RADR_CA_CA8_SHIFT (0U)
5256#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
5259/* The count of CAU_RADR_CA */
5260#define CAU_RADR_CA_COUNT (9U)
5261
5264#define CAU_XOR_CASR_IC_MASK (0x1U)
5265#define CAU_XOR_CASR_IC_SHIFT (0U)
5270#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
5271#define CAU_XOR_CASR_DPE_MASK (0x2U)
5272#define CAU_XOR_CASR_DPE_SHIFT (1U)
5277#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
5278#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
5279#define CAU_XOR_CASR_VER_SHIFT (28U)
5284#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
5289#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
5290#define CAU_XOR_CAA_ACC_SHIFT (0U)
5291#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
5296#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
5297#define CAU_XOR_CA_CA0_SHIFT (0U)
5298#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
5299#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
5300#define CAU_XOR_CA_CA1_SHIFT (0U)
5301#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
5302#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
5303#define CAU_XOR_CA_CA2_SHIFT (0U)
5304#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
5305#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
5306#define CAU_XOR_CA_CA3_SHIFT (0U)
5307#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
5308#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
5309#define CAU_XOR_CA_CA4_SHIFT (0U)
5310#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
5311#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
5312#define CAU_XOR_CA_CA5_SHIFT (0U)
5313#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
5314#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
5315#define CAU_XOR_CA_CA6_SHIFT (0U)
5316#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
5317#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
5318#define CAU_XOR_CA_CA7_SHIFT (0U)
5319#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
5320#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
5321#define CAU_XOR_CA_CA8_SHIFT (0U)
5322#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
5325/* The count of CAU_XOR_CA */
5326#define CAU_XOR_CA_COUNT (9U)
5327
5330#define CAU_ROTL_CASR_IC_MASK (0x1U)
5331#define CAU_ROTL_CASR_IC_SHIFT (0U)
5336#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
5337#define CAU_ROTL_CASR_DPE_MASK (0x2U)
5338#define CAU_ROTL_CASR_DPE_SHIFT (1U)
5343#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
5344#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
5345#define CAU_ROTL_CASR_VER_SHIFT (28U)
5350#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
5355#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
5356#define CAU_ROTL_CAA_ACC_SHIFT (0U)
5357#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
5362#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
5363#define CAU_ROTL_CA_CA0_SHIFT (0U)
5364#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
5365#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
5366#define CAU_ROTL_CA_CA1_SHIFT (0U)
5367#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
5368#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
5369#define CAU_ROTL_CA_CA2_SHIFT (0U)
5370#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
5371#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
5372#define CAU_ROTL_CA_CA3_SHIFT (0U)
5373#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
5374#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
5375#define CAU_ROTL_CA_CA4_SHIFT (0U)
5376#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
5377#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
5378#define CAU_ROTL_CA_CA5_SHIFT (0U)
5379#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
5380#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
5381#define CAU_ROTL_CA_CA6_SHIFT (0U)
5382#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
5383#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
5384#define CAU_ROTL_CA_CA7_SHIFT (0U)
5385#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
5386#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
5387#define CAU_ROTL_CA_CA8_SHIFT (0U)
5388#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
5391/* The count of CAU_ROTL_CA */
5392#define CAU_ROTL_CA_COUNT (9U)
5393
5396#define CAU_AESC_CASR_IC_MASK (0x1U)
5397#define CAU_AESC_CASR_IC_SHIFT (0U)
5402#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
5403#define CAU_AESC_CASR_DPE_MASK (0x2U)
5404#define CAU_AESC_CASR_DPE_SHIFT (1U)
5409#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
5410#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
5411#define CAU_AESC_CASR_VER_SHIFT (28U)
5416#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
5421#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
5422#define CAU_AESC_CAA_ACC_SHIFT (0U)
5423#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
5428#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
5429#define CAU_AESC_CA_CA0_SHIFT (0U)
5430#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
5431#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
5432#define CAU_AESC_CA_CA1_SHIFT (0U)
5433#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
5434#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
5435#define CAU_AESC_CA_CA2_SHIFT (0U)
5436#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
5437#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
5438#define CAU_AESC_CA_CA3_SHIFT (0U)
5439#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
5440#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
5441#define CAU_AESC_CA_CA4_SHIFT (0U)
5442#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
5443#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
5444#define CAU_AESC_CA_CA5_SHIFT (0U)
5445#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
5446#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
5447#define CAU_AESC_CA_CA6_SHIFT (0U)
5448#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
5449#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
5450#define CAU_AESC_CA_CA7_SHIFT (0U)
5451#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
5452#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
5453#define CAU_AESC_CA_CA8_SHIFT (0U)
5454#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
5457/* The count of CAU_AESC_CA */
5458#define CAU_AESC_CA_COUNT (9U)
5459
5462#define CAU_AESIC_CASR_IC_MASK (0x1U)
5463#define CAU_AESIC_CASR_IC_SHIFT (0U)
5468#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
5469#define CAU_AESIC_CASR_DPE_MASK (0x2U)
5470#define CAU_AESIC_CASR_DPE_SHIFT (1U)
5475#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
5476#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
5477#define CAU_AESIC_CASR_VER_SHIFT (28U)
5482#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
5487#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
5488#define CAU_AESIC_CAA_ACC_SHIFT (0U)
5489#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
5494#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
5495#define CAU_AESIC_CA_CA0_SHIFT (0U)
5496#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
5497#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
5498#define CAU_AESIC_CA_CA1_SHIFT (0U)
5499#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
5500#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
5501#define CAU_AESIC_CA_CA2_SHIFT (0U)
5502#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
5503#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
5504#define CAU_AESIC_CA_CA3_SHIFT (0U)
5505#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
5506#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
5507#define CAU_AESIC_CA_CA4_SHIFT (0U)
5508#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
5509#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
5510#define CAU_AESIC_CA_CA5_SHIFT (0U)
5511#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
5512#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
5513#define CAU_AESIC_CA_CA6_SHIFT (0U)
5514#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
5515#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
5516#define CAU_AESIC_CA_CA7_SHIFT (0U)
5517#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
5518#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
5519#define CAU_AESIC_CA_CA8_SHIFT (0U)
5520#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
5523/* The count of CAU_AESIC_CA */
5524#define CAU_AESIC_CA_COUNT (9U)
5525
5526
5529 /* end of group CAU_Register_Masks */
5530
5531
5532/* CAU - Peripheral instance base addresses */
5534#define CAU_BASE (0xE0081000u)
5536#define CAU ((CAU_Type *)CAU_BASE)
5538#define CAU_BASE_ADDRS { CAU_BASE }
5540#define CAU_BASE_PTRS { CAU }
5541
5544 /* end of group CAU_Peripheral_Access_Layer */
5545
5546
5547/* ----------------------------------------------------------------------------
5548 -- CMP Peripheral Access Layer
5549 ---------------------------------------------------------------------------- */
5550
5557typedef struct {
5558 __IO uint8_t CR0;
5559 __IO uint8_t CR1;
5560 __IO uint8_t FPR;
5561 __IO uint8_t SCR;
5562 __IO uint8_t DACCR;
5563 __IO uint8_t MUXCR;
5564} CMP_Type;
5565
5566/* ----------------------------------------------------------------------------
5567 -- CMP Register Masks
5568 ---------------------------------------------------------------------------- */
5569
5577#define CMP_CR0_HYSTCTR_MASK (0x3U)
5578#define CMP_CR0_HYSTCTR_SHIFT (0U)
5585#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
5586#define CMP_CR0_FILTER_CNT_MASK (0x70U)
5587#define CMP_CR0_FILTER_CNT_SHIFT (4U)
5598#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
5603#define CMP_CR1_EN_MASK (0x1U)
5604#define CMP_CR1_EN_SHIFT (0U)
5609#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
5610#define CMP_CR1_OPE_MASK (0x2U)
5611#define CMP_CR1_OPE_SHIFT (1U)
5616#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
5617#define CMP_CR1_COS_MASK (0x4U)
5618#define CMP_CR1_COS_SHIFT (2U)
5623#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
5624#define CMP_CR1_INV_MASK (0x8U)
5625#define CMP_CR1_INV_SHIFT (3U)
5630#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
5631#define CMP_CR1_PMODE_MASK (0x10U)
5632#define CMP_CR1_PMODE_SHIFT (4U)
5637#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
5638#define CMP_CR1_WE_MASK (0x40U)
5639#define CMP_CR1_WE_SHIFT (6U)
5644#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
5645#define CMP_CR1_SE_MASK (0x80U)
5646#define CMP_CR1_SE_SHIFT (7U)
5651#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
5656#define CMP_FPR_FILT_PER_MASK (0xFFU)
5657#define CMP_FPR_FILT_PER_SHIFT (0U)
5658#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
5663#define CMP_SCR_COUT_MASK (0x1U)
5664#define CMP_SCR_COUT_SHIFT (0U)
5665#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
5666#define CMP_SCR_CFF_MASK (0x2U)
5667#define CMP_SCR_CFF_SHIFT (1U)
5672#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
5673#define CMP_SCR_CFR_MASK (0x4U)
5674#define CMP_SCR_CFR_SHIFT (2U)
5679#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
5680#define CMP_SCR_IEF_MASK (0x8U)
5681#define CMP_SCR_IEF_SHIFT (3U)
5686#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
5687#define CMP_SCR_IER_MASK (0x10U)
5688#define CMP_SCR_IER_SHIFT (4U)
5693#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
5694#define CMP_SCR_DMAEN_MASK (0x40U)
5695#define CMP_SCR_DMAEN_SHIFT (6U)
5700#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
5705#define CMP_DACCR_VOSEL_MASK (0x3FU)
5706#define CMP_DACCR_VOSEL_SHIFT (0U)
5707#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
5708#define CMP_DACCR_VRSEL_MASK (0x40U)
5709#define CMP_DACCR_VRSEL_SHIFT (6U)
5714#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
5715#define CMP_DACCR_DACEN_MASK (0x80U)
5716#define CMP_DACCR_DACEN_SHIFT (7U)
5721#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
5726#define CMP_MUXCR_MSEL_MASK (0x7U)
5727#define CMP_MUXCR_MSEL_SHIFT (0U)
5738#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
5739#define CMP_MUXCR_PSEL_MASK (0x38U)
5740#define CMP_MUXCR_PSEL_SHIFT (3U)
5751#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
5752#define CMP_MUXCR_PSTM_MASK (0x80U)
5753#define CMP_MUXCR_PSTM_SHIFT (7U)
5758#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
5764 /* end of group CMP_Register_Masks */
5765
5766
5767/* CMP - Peripheral instance base addresses */
5769#define CMP0_BASE (0x40073000u)
5771#define CMP0 ((CMP_Type *)CMP0_BASE)
5773#define CMP1_BASE (0x40073008u)
5775#define CMP1 ((CMP_Type *)CMP1_BASE)
5777#define CMP2_BASE (0x40073010u)
5779#define CMP2 ((CMP_Type *)CMP2_BASE)
5781#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
5783#define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
5785#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
5786
5789 /* end of group CMP_Peripheral_Access_Layer */
5790
5791
5792/* ----------------------------------------------------------------------------
5793 -- CMT Peripheral Access Layer
5794 ---------------------------------------------------------------------------- */
5795
5802typedef struct {
5803 __IO uint8_t CGH1;
5804 __IO uint8_t CGL1;
5805 __IO uint8_t CGH2;
5806 __IO uint8_t CGL2;
5807 __IO uint8_t OC;
5808 __IO uint8_t MSC;
5809 __IO uint8_t CMD1;
5810 __IO uint8_t CMD2;
5811 __IO uint8_t CMD3;
5812 __IO uint8_t CMD4;
5813 __IO uint8_t PPS;
5814 __IO uint8_t DMA;
5815} CMT_Type;
5816
5817/* ----------------------------------------------------------------------------
5818 -- CMT Register Masks
5819 ---------------------------------------------------------------------------- */
5820
5828#define CMT_CGH1_PH_MASK (0xFFU)
5829#define CMT_CGH1_PH_SHIFT (0U)
5830#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
5835#define CMT_CGL1_PL_MASK (0xFFU)
5836#define CMT_CGL1_PL_SHIFT (0U)
5837#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
5842#define CMT_CGH2_SH_MASK (0xFFU)
5843#define CMT_CGH2_SH_SHIFT (0U)
5844#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
5849#define CMT_CGL2_SL_MASK (0xFFU)
5850#define CMT_CGL2_SL_SHIFT (0U)
5851#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
5856#define CMT_OC_IROPEN_MASK (0x20U)
5857#define CMT_OC_IROPEN_SHIFT (5U)
5862#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
5863#define CMT_OC_CMTPOL_MASK (0x40U)
5864#define CMT_OC_CMTPOL_SHIFT (6U)
5869#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
5870#define CMT_OC_IROL_MASK (0x80U)
5871#define CMT_OC_IROL_SHIFT (7U)
5872#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
5877#define CMT_MSC_MCGEN_MASK (0x1U)
5878#define CMT_MSC_MCGEN_SHIFT (0U)
5883#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
5884#define CMT_MSC_EOCIE_MASK (0x2U)
5885#define CMT_MSC_EOCIE_SHIFT (1U)
5890#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
5891#define CMT_MSC_FSK_MASK (0x4U)
5892#define CMT_MSC_FSK_SHIFT (2U)
5897#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
5898#define CMT_MSC_BASE_MASK (0x8U)
5899#define CMT_MSC_BASE_SHIFT (3U)
5904#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
5905#define CMT_MSC_EXSPC_MASK (0x10U)
5906#define CMT_MSC_EXSPC_SHIFT (4U)
5911#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
5912#define CMT_MSC_CMTDIV_MASK (0x60U)
5913#define CMT_MSC_CMTDIV_SHIFT (5U)
5920#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
5921#define CMT_MSC_EOCF_MASK (0x80U)
5922#define CMT_MSC_EOCF_SHIFT (7U)
5927#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
5932#define CMT_CMD1_MB_MASK (0xFFU)
5933#define CMT_CMD1_MB_SHIFT (0U)
5934#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
5939#define CMT_CMD2_MB_MASK (0xFFU)
5940#define CMT_CMD2_MB_SHIFT (0U)
5941#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
5946#define CMT_CMD3_SB_MASK (0xFFU)
5947#define CMT_CMD3_SB_SHIFT (0U)
5948#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
5953#define CMT_CMD4_SB_MASK (0xFFU)
5954#define CMT_CMD4_SB_SHIFT (0U)
5955#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
5960#define CMT_PPS_PPSDIV_MASK (0xFU)
5961#define CMT_PPS_PPSDIV_SHIFT (0U)
5980#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
5985#define CMT_DMA_DMA_MASK (0x1U)
5986#define CMT_DMA_DMA_SHIFT (0U)
5991#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
5997 /* end of group CMT_Register_Masks */
5998
5999
6000/* CMT - Peripheral instance base addresses */
6002#define CMT_BASE (0x40062000u)
6004#define CMT ((CMT_Type *)CMT_BASE)
6006#define CMT_BASE_ADDRS { CMT_BASE }
6008#define CMT_BASE_PTRS { CMT }
6010#define CMT_IRQS { CMT_IRQn }
6011
6014 /* end of group CMT_Peripheral_Access_Layer */
6015
6016
6017/* ----------------------------------------------------------------------------
6018 -- CRC Peripheral Access Layer
6019 ---------------------------------------------------------------------------- */
6020
6027typedef struct {
6028 union { /* offset: 0x0 */
6029 struct { /* offset: 0x0 */
6030 __IO uint16_t DATAL;
6031 __IO uint16_t DATAH;
6032 } ACCESS16BIT;
6033 __IO uint32_t DATA;
6034 struct { /* offset: 0x0 */
6035 __IO uint8_t DATALL;
6036 __IO uint8_t DATALU;
6037 __IO uint8_t DATAHL;
6038 __IO uint8_t DATAHU;
6039 } ACCESS8BIT;
6040 };
6041 union { /* offset: 0x4 */
6042 struct { /* offset: 0x4 */
6043 __IO uint16_t GPOLYL;
6044 __IO uint16_t GPOLYH;
6045 } GPOLY_ACCESS16BIT;
6046 __IO uint32_t GPOLY;
6047 struct { /* offset: 0x4 */
6048 __IO uint8_t GPOLYLL;
6049 __IO uint8_t GPOLYLU;
6050 __IO uint8_t GPOLYHL;
6051 __IO uint8_t GPOLYHU;
6052 } GPOLY_ACCESS8BIT;
6053 };
6054 union { /* offset: 0x8 */
6055 __IO uint32_t CTRL;
6056 struct { /* offset: 0x8 */
6057 uint8_t RESERVED_0[3];
6058 __IO uint8_t CTRLHU;
6059 } CTRL_ACCESS8BIT;
6060 };
6061} CRC_Type;
6062
6063/* ----------------------------------------------------------------------------
6064 -- CRC Register Masks
6065 ---------------------------------------------------------------------------- */
6066
6074#define CRC_DATAL_DATAL_MASK (0xFFFFU)
6075#define CRC_DATAL_DATAL_SHIFT (0U)
6076#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
6081#define CRC_DATAH_DATAH_MASK (0xFFFFU)
6082#define CRC_DATAH_DATAH_SHIFT (0U)
6083#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
6088#define CRC_DATA_LL_MASK (0xFFU)
6089#define CRC_DATA_LL_SHIFT (0U)
6090#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
6091#define CRC_DATA_LU_MASK (0xFF00U)
6092#define CRC_DATA_LU_SHIFT (8U)
6093#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
6094#define CRC_DATA_HL_MASK (0xFF0000U)
6095#define CRC_DATA_HL_SHIFT (16U)
6096#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
6097#define CRC_DATA_HU_MASK (0xFF000000U)
6098#define CRC_DATA_HU_SHIFT (24U)
6099#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
6104#define CRC_DATALL_DATALL_MASK (0xFFU)
6105#define CRC_DATALL_DATALL_SHIFT (0U)
6106#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
6111#define CRC_DATALU_DATALU_MASK (0xFFU)
6112#define CRC_DATALU_DATALU_SHIFT (0U)
6113#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
6118#define CRC_DATAHL_DATAHL_MASK (0xFFU)
6119#define CRC_DATAHL_DATAHL_SHIFT (0U)
6120#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
6125#define CRC_DATAHU_DATAHU_MASK (0xFFU)
6126#define CRC_DATAHU_DATAHU_SHIFT (0U)
6127#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
6132#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
6133#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
6134#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
6139#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
6140#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
6141#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
6146#define CRC_GPOLY_LOW_MASK (0xFFFFU)
6147#define CRC_GPOLY_LOW_SHIFT (0U)
6148#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
6149#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
6150#define CRC_GPOLY_HIGH_SHIFT (16U)
6151#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
6156#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
6157#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
6158#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
6163#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
6164#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
6165#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
6170#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
6171#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
6172#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
6177#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
6178#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
6179#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
6184#define CRC_CTRL_TCRC_MASK (0x1000000U)
6185#define CRC_CTRL_TCRC_SHIFT (24U)
6190#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
6191#define CRC_CTRL_WAS_MASK (0x2000000U)
6192#define CRC_CTRL_WAS_SHIFT (25U)
6197#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
6198#define CRC_CTRL_FXOR_MASK (0x4000000U)
6199#define CRC_CTRL_FXOR_SHIFT (26U)
6204#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
6205#define CRC_CTRL_TOTR_MASK (0x30000000U)
6206#define CRC_CTRL_TOTR_SHIFT (28U)
6213#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
6214#define CRC_CTRL_TOT_MASK (0xC0000000U)
6215#define CRC_CTRL_TOT_SHIFT (30U)
6222#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
6227#define CRC_CTRLHU_TCRC_MASK (0x1U)
6228#define CRC_CTRLHU_TCRC_SHIFT (0U)
6233#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
6234#define CRC_CTRLHU_WAS_MASK (0x2U)
6235#define CRC_CTRLHU_WAS_SHIFT (1U)
6240#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
6241#define CRC_CTRLHU_FXOR_MASK (0x4U)
6242#define CRC_CTRLHU_FXOR_SHIFT (2U)
6247#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
6248#define CRC_CTRLHU_TOTR_MASK (0x30U)
6249#define CRC_CTRLHU_TOTR_SHIFT (4U)
6256#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
6257#define CRC_CTRLHU_TOT_MASK (0xC0U)
6258#define CRC_CTRLHU_TOT_SHIFT (6U)
6265#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
6271 /* end of group CRC_Register_Masks */
6272
6273
6274/* CRC - Peripheral instance base addresses */
6276#define CRC_BASE (0x40032000u)
6278#define CRC0 ((CRC_Type *)CRC_BASE)
6280#define CRC_BASE_ADDRS { CRC_BASE }
6282#define CRC_BASE_PTRS { CRC0 }
6283
6286 /* end of group CRC_Peripheral_Access_Layer */
6287
6288
6289/* ----------------------------------------------------------------------------
6290 -- DAC Peripheral Access Layer
6291 ---------------------------------------------------------------------------- */
6292
6299typedef struct {
6300 struct { /* offset: 0x0, array step: 0x2 */
6301 __IO uint8_t DATL;
6302 __IO uint8_t DATH;
6303 } DAT[16];
6304 __IO uint8_t SR;
6305 __IO uint8_t C0;
6306 __IO uint8_t C1;
6307 __IO uint8_t C2;
6308} DAC_Type;
6309
6310/* ----------------------------------------------------------------------------
6311 -- DAC Register Masks
6312 ---------------------------------------------------------------------------- */
6313
6321#define DAC_DATL_DATA0_MASK (0xFFU)
6322#define DAC_DATL_DATA0_SHIFT (0U)
6323#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
6326/* The count of DAC_DATL */
6327#define DAC_DATL_COUNT (16U)
6328
6331#define DAC_DATH_DATA1_MASK (0xFU)
6332#define DAC_DATH_DATA1_SHIFT (0U)
6333#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
6336/* The count of DAC_DATH */
6337#define DAC_DATH_COUNT (16U)
6338
6341#define DAC_SR_DACBFRPBF_MASK (0x1U)
6342#define DAC_SR_DACBFRPBF_SHIFT (0U)
6347#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
6348#define DAC_SR_DACBFRPTF_MASK (0x2U)
6349#define DAC_SR_DACBFRPTF_SHIFT (1U)
6354#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
6355#define DAC_SR_DACBFWMF_MASK (0x4U)
6356#define DAC_SR_DACBFWMF_SHIFT (2U)
6361#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
6366#define DAC_C0_DACBBIEN_MASK (0x1U)
6367#define DAC_C0_DACBBIEN_SHIFT (0U)
6372#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
6373#define DAC_C0_DACBTIEN_MASK (0x2U)
6374#define DAC_C0_DACBTIEN_SHIFT (1U)
6379#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
6380#define DAC_C0_DACBWIEN_MASK (0x4U)
6381#define DAC_C0_DACBWIEN_SHIFT (2U)
6386#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
6387#define DAC_C0_LPEN_MASK (0x8U)
6388#define DAC_C0_LPEN_SHIFT (3U)
6393#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
6394#define DAC_C0_DACSWTRG_MASK (0x10U)
6395#define DAC_C0_DACSWTRG_SHIFT (4U)
6400#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
6401#define DAC_C0_DACTRGSEL_MASK (0x20U)
6402#define DAC_C0_DACTRGSEL_SHIFT (5U)
6407#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
6408#define DAC_C0_DACRFS_MASK (0x40U)
6409#define DAC_C0_DACRFS_SHIFT (6U)
6414#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
6415#define DAC_C0_DACEN_MASK (0x80U)
6416#define DAC_C0_DACEN_SHIFT (7U)
6421#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
6426#define DAC_C1_DACBFEN_MASK (0x1U)
6427#define DAC_C1_DACBFEN_SHIFT (0U)
6432#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
6433#define DAC_C1_DACBFMD_MASK (0x6U)
6434#define DAC_C1_DACBFMD_SHIFT (1U)
6441#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
6442#define DAC_C1_DACBFWM_MASK (0x18U)
6443#define DAC_C1_DACBFWM_SHIFT (3U)
6450#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
6451#define DAC_C1_DMAEN_MASK (0x80U)
6452#define DAC_C1_DMAEN_SHIFT (7U)
6457#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
6462#define DAC_C2_DACBFUP_MASK (0xFU)
6463#define DAC_C2_DACBFUP_SHIFT (0U)
6464#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
6465#define DAC_C2_DACBFRP_MASK (0xF0U)
6466#define DAC_C2_DACBFRP_SHIFT (4U)
6467#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
6473 /* end of group DAC_Register_Masks */
6474
6475
6476/* DAC - Peripheral instance base addresses */
6478#define DAC0_BASE (0x400CC000u)
6480#define DAC0 ((DAC_Type *)DAC0_BASE)
6482#define DAC1_BASE (0x400CD000u)
6484#define DAC1 ((DAC_Type *)DAC1_BASE)
6486#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
6488#define DAC_BASE_PTRS { DAC0, DAC1 }
6490#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
6491
6494 /* end of group DAC_Peripheral_Access_Layer */
6495
6496
6497/* ----------------------------------------------------------------------------
6498 -- DMA Peripheral Access Layer
6499 ---------------------------------------------------------------------------- */
6500
6507typedef struct {
6508 __IO uint32_t CR;
6509 __I uint32_t ES;
6510 uint8_t RESERVED_0[4];
6511 __IO uint32_t ERQ;
6512 uint8_t RESERVED_1[4];
6513 __IO uint32_t EEI;
6514 __O uint8_t CEEI;
6515 __O uint8_t SEEI;
6516 __O uint8_t CERQ;
6517 __O uint8_t SERQ;
6518 __O uint8_t CDNE;
6519 __O uint8_t SSRT;
6520 __O uint8_t CERR;
6521 __O uint8_t CINT;
6522 uint8_t RESERVED_2[4];
6523 __IO uint32_t INT;
6524 uint8_t RESERVED_3[4];
6525 __IO uint32_t ERR;
6526 uint8_t RESERVED_4[4];
6527 __I uint32_t HRS;
6528 uint8_t RESERVED_5[200];
6529 __IO uint8_t DCHPRI3;
6530 __IO uint8_t DCHPRI2;
6531 __IO uint8_t DCHPRI1;
6532 __IO uint8_t DCHPRI0;
6533 __IO uint8_t DCHPRI7;
6534 __IO uint8_t DCHPRI6;
6535 __IO uint8_t DCHPRI5;
6536 __IO uint8_t DCHPRI4;
6537 __IO uint8_t DCHPRI11;
6538 __IO uint8_t DCHPRI10;
6539 __IO uint8_t DCHPRI9;
6540 __IO uint8_t DCHPRI8;
6541 __IO uint8_t DCHPRI15;
6542 __IO uint8_t DCHPRI14;
6543 __IO uint8_t DCHPRI13;
6544 __IO uint8_t DCHPRI12;
6545 uint8_t RESERVED_6[3824];
6546 struct { /* offset: 0x1000, array step: 0x20 */
6547 __IO uint32_t SADDR;
6548 __IO uint16_t SOFF;
6549 __IO uint16_t ATTR;
6550 union { /* offset: 0x1008, array step: 0x20 */
6551 __IO uint32_t NBYTES_MLNO;
6552 __IO uint32_t NBYTES_MLOFFNO;
6553 __IO uint32_t NBYTES_MLOFFYES;
6554 };
6555 __IO uint32_t SLAST;
6556 __IO uint32_t DADDR;
6557 __IO uint16_t DOFF;
6558 union { /* offset: 0x1016, array step: 0x20 */
6559 __IO uint16_t CITER_ELINKNO;
6560 __IO uint16_t CITER_ELINKYES;
6561 };
6562 __IO uint32_t DLAST_SGA;
6563 __IO uint16_t CSR;
6564 union { /* offset: 0x101E, array step: 0x20 */
6565 __IO uint16_t BITER_ELINKNO;
6566 __IO uint16_t BITER_ELINKYES;
6567 };
6568 } TCD[16];
6569} DMA_Type;
6570
6571/* ----------------------------------------------------------------------------
6572 -- DMA Register Masks
6573 ---------------------------------------------------------------------------- */
6574
6582#define DMA_CR_EDBG_MASK (0x2U)
6583#define DMA_CR_EDBG_SHIFT (1U)
6588#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
6589#define DMA_CR_ERCA_MASK (0x4U)
6590#define DMA_CR_ERCA_SHIFT (2U)
6595#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
6596#define DMA_CR_HOE_MASK (0x10U)
6597#define DMA_CR_HOE_SHIFT (4U)
6602#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
6603#define DMA_CR_HALT_MASK (0x20U)
6604#define DMA_CR_HALT_SHIFT (5U)
6609#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
6610#define DMA_CR_CLM_MASK (0x40U)
6611#define DMA_CR_CLM_SHIFT (6U)
6616#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
6617#define DMA_CR_EMLM_MASK (0x80U)
6618#define DMA_CR_EMLM_SHIFT (7U)
6623#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
6624#define DMA_CR_ECX_MASK (0x10000U)
6625#define DMA_CR_ECX_SHIFT (16U)
6630#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
6631#define DMA_CR_CX_MASK (0x20000U)
6632#define DMA_CR_CX_SHIFT (17U)
6637#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
6642#define DMA_ES_DBE_MASK (0x1U)
6643#define DMA_ES_DBE_SHIFT (0U)
6648#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
6649#define DMA_ES_SBE_MASK (0x2U)
6650#define DMA_ES_SBE_SHIFT (1U)
6655#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
6656#define DMA_ES_SGE_MASK (0x4U)
6657#define DMA_ES_SGE_SHIFT (2U)
6662#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
6663#define DMA_ES_NCE_MASK (0x8U)
6664#define DMA_ES_NCE_SHIFT (3U)
6669#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
6670#define DMA_ES_DOE_MASK (0x10U)
6671#define DMA_ES_DOE_SHIFT (4U)
6676#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
6677#define DMA_ES_DAE_MASK (0x20U)
6678#define DMA_ES_DAE_SHIFT (5U)
6683#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
6684#define DMA_ES_SOE_MASK (0x40U)
6685#define DMA_ES_SOE_SHIFT (6U)
6690#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
6691#define DMA_ES_SAE_MASK (0x80U)
6692#define DMA_ES_SAE_SHIFT (7U)
6697#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
6698#define DMA_ES_ERRCHN_MASK (0xF00U)
6699#define DMA_ES_ERRCHN_SHIFT (8U)
6700#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
6701#define DMA_ES_CPE_MASK (0x4000U)
6702#define DMA_ES_CPE_SHIFT (14U)
6707#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
6708#define DMA_ES_ECX_MASK (0x10000U)
6709#define DMA_ES_ECX_SHIFT (16U)
6714#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
6715#define DMA_ES_VLD_MASK (0x80000000U)
6716#define DMA_ES_VLD_SHIFT (31U)
6721#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
6726#define DMA_ERQ_ERQ0_MASK (0x1U)
6727#define DMA_ERQ_ERQ0_SHIFT (0U)
6732#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
6733#define DMA_ERQ_ERQ1_MASK (0x2U)
6734#define DMA_ERQ_ERQ1_SHIFT (1U)
6739#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
6740#define DMA_ERQ_ERQ2_MASK (0x4U)
6741#define DMA_ERQ_ERQ2_SHIFT (2U)
6746#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
6747#define DMA_ERQ_ERQ3_MASK (0x8U)
6748#define DMA_ERQ_ERQ3_SHIFT (3U)
6753#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
6754#define DMA_ERQ_ERQ4_MASK (0x10U)
6755#define DMA_ERQ_ERQ4_SHIFT (4U)
6760#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
6761#define DMA_ERQ_ERQ5_MASK (0x20U)
6762#define DMA_ERQ_ERQ5_SHIFT (5U)
6767#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
6768#define DMA_ERQ_ERQ6_MASK (0x40U)
6769#define DMA_ERQ_ERQ6_SHIFT (6U)
6774#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
6775#define DMA_ERQ_ERQ7_MASK (0x80U)
6776#define DMA_ERQ_ERQ7_SHIFT (7U)
6781#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
6782#define DMA_ERQ_ERQ8_MASK (0x100U)
6783#define DMA_ERQ_ERQ8_SHIFT (8U)
6788#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
6789#define DMA_ERQ_ERQ9_MASK (0x200U)
6790#define DMA_ERQ_ERQ9_SHIFT (9U)
6795#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
6796#define DMA_ERQ_ERQ10_MASK (0x400U)
6797#define DMA_ERQ_ERQ10_SHIFT (10U)
6802#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
6803#define DMA_ERQ_ERQ11_MASK (0x800U)
6804#define DMA_ERQ_ERQ11_SHIFT (11U)
6809#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
6810#define DMA_ERQ_ERQ12_MASK (0x1000U)
6811#define DMA_ERQ_ERQ12_SHIFT (12U)
6816#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
6817#define DMA_ERQ_ERQ13_MASK (0x2000U)
6818#define DMA_ERQ_ERQ13_SHIFT (13U)
6823#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
6824#define DMA_ERQ_ERQ14_MASK (0x4000U)
6825#define DMA_ERQ_ERQ14_SHIFT (14U)
6830#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
6831#define DMA_ERQ_ERQ15_MASK (0x8000U)
6832#define DMA_ERQ_ERQ15_SHIFT (15U)
6837#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
6842#define DMA_EEI_EEI0_MASK (0x1U)
6843#define DMA_EEI_EEI0_SHIFT (0U)
6848#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
6849#define DMA_EEI_EEI1_MASK (0x2U)
6850#define DMA_EEI_EEI1_SHIFT (1U)
6855#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
6856#define DMA_EEI_EEI2_MASK (0x4U)
6857#define DMA_EEI_EEI2_SHIFT (2U)
6862#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
6863#define DMA_EEI_EEI3_MASK (0x8U)
6864#define DMA_EEI_EEI3_SHIFT (3U)
6869#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
6870#define DMA_EEI_EEI4_MASK (0x10U)
6871#define DMA_EEI_EEI4_SHIFT (4U)
6876#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
6877#define DMA_EEI_EEI5_MASK (0x20U)
6878#define DMA_EEI_EEI5_SHIFT (5U)
6883#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
6884#define DMA_EEI_EEI6_MASK (0x40U)
6885#define DMA_EEI_EEI6_SHIFT (6U)
6890#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
6891#define DMA_EEI_EEI7_MASK (0x80U)
6892#define DMA_EEI_EEI7_SHIFT (7U)
6897#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
6898#define DMA_EEI_EEI8_MASK (0x100U)
6899#define DMA_EEI_EEI8_SHIFT (8U)
6904#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
6905#define DMA_EEI_EEI9_MASK (0x200U)
6906#define DMA_EEI_EEI9_SHIFT (9U)
6911#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
6912#define DMA_EEI_EEI10_MASK (0x400U)
6913#define DMA_EEI_EEI10_SHIFT (10U)
6918#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
6919#define DMA_EEI_EEI11_MASK (0x800U)
6920#define DMA_EEI_EEI11_SHIFT (11U)
6925#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
6926#define DMA_EEI_EEI12_MASK (0x1000U)
6927#define DMA_EEI_EEI12_SHIFT (12U)
6932#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
6933#define DMA_EEI_EEI13_MASK (0x2000U)
6934#define DMA_EEI_EEI13_SHIFT (13U)
6939#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
6940#define DMA_EEI_EEI14_MASK (0x4000U)
6941#define DMA_EEI_EEI14_SHIFT (14U)
6946#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
6947#define DMA_EEI_EEI15_MASK (0x8000U)
6948#define DMA_EEI_EEI15_SHIFT (15U)
6953#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
6958#define DMA_CEEI_CEEI_MASK (0xFU)
6959#define DMA_CEEI_CEEI_SHIFT (0U)
6960#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
6961#define DMA_CEEI_CAEE_MASK (0x40U)
6962#define DMA_CEEI_CAEE_SHIFT (6U)
6967#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
6968#define DMA_CEEI_NOP_MASK (0x80U)
6969#define DMA_CEEI_NOP_SHIFT (7U)
6974#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
6979#define DMA_SEEI_SEEI_MASK (0xFU)
6980#define DMA_SEEI_SEEI_SHIFT (0U)
6981#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
6982#define DMA_SEEI_SAEE_MASK (0x40U)
6983#define DMA_SEEI_SAEE_SHIFT (6U)
6988#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
6989#define DMA_SEEI_NOP_MASK (0x80U)
6990#define DMA_SEEI_NOP_SHIFT (7U)
6995#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
7000#define DMA_CERQ_CERQ_MASK (0xFU)
7001#define DMA_CERQ_CERQ_SHIFT (0U)
7002#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
7003#define DMA_CERQ_CAER_MASK (0x40U)
7004#define DMA_CERQ_CAER_SHIFT (6U)
7009#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
7010#define DMA_CERQ_NOP_MASK (0x80U)
7011#define DMA_CERQ_NOP_SHIFT (7U)
7016#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
7021#define DMA_SERQ_SERQ_MASK (0xFU)
7022#define DMA_SERQ_SERQ_SHIFT (0U)
7023#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
7024#define DMA_SERQ_SAER_MASK (0x40U)
7025#define DMA_SERQ_SAER_SHIFT (6U)
7030#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
7031#define DMA_SERQ_NOP_MASK (0x80U)
7032#define DMA_SERQ_NOP_SHIFT (7U)
7037#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
7042#define DMA_CDNE_CDNE_MASK (0xFU)
7043#define DMA_CDNE_CDNE_SHIFT (0U)
7044#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
7045#define DMA_CDNE_CADN_MASK (0x40U)
7046#define DMA_CDNE_CADN_SHIFT (6U)
7051#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
7052#define DMA_CDNE_NOP_MASK (0x80U)
7053#define DMA_CDNE_NOP_SHIFT (7U)
7058#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
7063#define DMA_SSRT_SSRT_MASK (0xFU)
7064#define DMA_SSRT_SSRT_SHIFT (0U)
7065#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
7066#define DMA_SSRT_SAST_MASK (0x40U)
7067#define DMA_SSRT_SAST_SHIFT (6U)
7072#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
7073#define DMA_SSRT_NOP_MASK (0x80U)
7074#define DMA_SSRT_NOP_SHIFT (7U)
7079#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
7084#define DMA_CERR_CERR_MASK (0xFU)
7085#define DMA_CERR_CERR_SHIFT (0U)
7086#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
7087#define DMA_CERR_CAEI_MASK (0x40U)
7088#define DMA_CERR_CAEI_SHIFT (6U)
7093#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
7094#define DMA_CERR_NOP_MASK (0x80U)
7095#define DMA_CERR_NOP_SHIFT (7U)
7100#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
7105#define DMA_CINT_CINT_MASK (0xFU)
7106#define DMA_CINT_CINT_SHIFT (0U)
7107#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
7108#define DMA_CINT_CAIR_MASK (0x40U)
7109#define DMA_CINT_CAIR_SHIFT (6U)
7114#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
7115#define DMA_CINT_NOP_MASK (0x80U)
7116#define DMA_CINT_NOP_SHIFT (7U)
7121#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
7126#define DMA_INT_INT0_MASK (0x1U)
7127#define DMA_INT_INT0_SHIFT (0U)
7132#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
7133#define DMA_INT_INT1_MASK (0x2U)
7134#define DMA_INT_INT1_SHIFT (1U)
7139#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
7140#define DMA_INT_INT2_MASK (0x4U)
7141#define DMA_INT_INT2_SHIFT (2U)
7146#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
7147#define DMA_INT_INT3_MASK (0x8U)
7148#define DMA_INT_INT3_SHIFT (3U)
7153#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
7154#define DMA_INT_INT4_MASK (0x10U)
7155#define DMA_INT_INT4_SHIFT (4U)
7160#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
7161#define DMA_INT_INT5_MASK (0x20U)
7162#define DMA_INT_INT5_SHIFT (5U)
7167#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
7168#define DMA_INT_INT6_MASK (0x40U)
7169#define DMA_INT_INT6_SHIFT (6U)
7174#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
7175#define DMA_INT_INT7_MASK (0x80U)
7176#define DMA_INT_INT7_SHIFT (7U)
7181#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
7182#define DMA_INT_INT8_MASK (0x100U)
7183#define DMA_INT_INT8_SHIFT (8U)
7188#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
7189#define DMA_INT_INT9_MASK (0x200U)
7190#define DMA_INT_INT9_SHIFT (9U)
7195#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
7196#define DMA_INT_INT10_MASK (0x400U)
7197#define DMA_INT_INT10_SHIFT (10U)
7202#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
7203#define DMA_INT_INT11_MASK (0x800U)
7204#define DMA_INT_INT11_SHIFT (11U)
7209#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
7210#define DMA_INT_INT12_MASK (0x1000U)
7211#define DMA_INT_INT12_SHIFT (12U)
7216#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
7217#define DMA_INT_INT13_MASK (0x2000U)
7218#define DMA_INT_INT13_SHIFT (13U)
7223#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
7224#define DMA_INT_INT14_MASK (0x4000U)
7225#define DMA_INT_INT14_SHIFT (14U)
7230#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
7231#define DMA_INT_INT15_MASK (0x8000U)
7232#define DMA_INT_INT15_SHIFT (15U)
7237#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
7242#define DMA_ERR_ERR0_MASK (0x1U)
7243#define DMA_ERR_ERR0_SHIFT (0U)
7248#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
7249#define DMA_ERR_ERR1_MASK (0x2U)
7250#define DMA_ERR_ERR1_SHIFT (1U)
7255#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
7256#define DMA_ERR_ERR2_MASK (0x4U)
7257#define DMA_ERR_ERR2_SHIFT (2U)
7262#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
7263#define DMA_ERR_ERR3_MASK (0x8U)
7264#define DMA_ERR_ERR3_SHIFT (3U)
7269#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
7270#define DMA_ERR_ERR4_MASK (0x10U)
7271#define DMA_ERR_ERR4_SHIFT (4U)
7276#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
7277#define DMA_ERR_ERR5_MASK (0x20U)
7278#define DMA_ERR_ERR5_SHIFT (5U)
7283#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
7284#define DMA_ERR_ERR6_MASK (0x40U)
7285#define DMA_ERR_ERR6_SHIFT (6U)
7290#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
7291#define DMA_ERR_ERR7_MASK (0x80U)
7292#define DMA_ERR_ERR7_SHIFT (7U)
7297#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
7298#define DMA_ERR_ERR8_MASK (0x100U)
7299#define DMA_ERR_ERR8_SHIFT (8U)
7304#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
7305#define DMA_ERR_ERR9_MASK (0x200U)
7306#define DMA_ERR_ERR9_SHIFT (9U)
7311#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
7312#define DMA_ERR_ERR10_MASK (0x400U)
7313#define DMA_ERR_ERR10_SHIFT (10U)
7318#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
7319#define DMA_ERR_ERR11_MASK (0x800U)
7320#define DMA_ERR_ERR11_SHIFT (11U)
7325#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
7326#define DMA_ERR_ERR12_MASK (0x1000U)
7327#define DMA_ERR_ERR12_SHIFT (12U)
7332#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
7333#define DMA_ERR_ERR13_MASK (0x2000U)
7334#define DMA_ERR_ERR13_SHIFT (13U)
7339#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
7340#define DMA_ERR_ERR14_MASK (0x4000U)
7341#define DMA_ERR_ERR14_SHIFT (14U)
7346#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
7347#define DMA_ERR_ERR15_MASK (0x8000U)
7348#define DMA_ERR_ERR15_SHIFT (15U)
7353#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
7358#define DMA_HRS_HRS0_MASK (0x1U)
7359#define DMA_HRS_HRS0_SHIFT (0U)
7364#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
7365#define DMA_HRS_HRS1_MASK (0x2U)
7366#define DMA_HRS_HRS1_SHIFT (1U)
7371#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
7372#define DMA_HRS_HRS2_MASK (0x4U)
7373#define DMA_HRS_HRS2_SHIFT (2U)
7378#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
7379#define DMA_HRS_HRS3_MASK (0x8U)
7380#define DMA_HRS_HRS3_SHIFT (3U)
7385#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
7386#define DMA_HRS_HRS4_MASK (0x10U)
7387#define DMA_HRS_HRS4_SHIFT (4U)
7392#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
7393#define DMA_HRS_HRS5_MASK (0x20U)
7394#define DMA_HRS_HRS5_SHIFT (5U)
7399#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
7400#define DMA_HRS_HRS6_MASK (0x40U)
7401#define DMA_HRS_HRS6_SHIFT (6U)
7406#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
7407#define DMA_HRS_HRS7_MASK (0x80U)
7408#define DMA_HRS_HRS7_SHIFT (7U)
7413#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
7414#define DMA_HRS_HRS8_MASK (0x100U)
7415#define DMA_HRS_HRS8_SHIFT (8U)
7420#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
7421#define DMA_HRS_HRS9_MASK (0x200U)
7422#define DMA_HRS_HRS9_SHIFT (9U)
7427#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
7428#define DMA_HRS_HRS10_MASK (0x400U)
7429#define DMA_HRS_HRS10_SHIFT (10U)
7434#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
7435#define DMA_HRS_HRS11_MASK (0x800U)
7436#define DMA_HRS_HRS11_SHIFT (11U)
7441#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
7442#define DMA_HRS_HRS12_MASK (0x1000U)
7443#define DMA_HRS_HRS12_SHIFT (12U)
7448#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
7449#define DMA_HRS_HRS13_MASK (0x2000U)
7450#define DMA_HRS_HRS13_SHIFT (13U)
7455#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
7456#define DMA_HRS_HRS14_MASK (0x4000U)
7457#define DMA_HRS_HRS14_SHIFT (14U)
7462#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
7463#define DMA_HRS_HRS15_MASK (0x8000U)
7464#define DMA_HRS_HRS15_SHIFT (15U)
7469#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
7474#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
7475#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
7476#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
7477#define DMA_DCHPRI3_DPA_MASK (0x40U)
7478#define DMA_DCHPRI3_DPA_SHIFT (6U)
7483#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
7484#define DMA_DCHPRI3_ECP_MASK (0x80U)
7485#define DMA_DCHPRI3_ECP_SHIFT (7U)
7490#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
7495#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
7496#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
7497#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
7498#define DMA_DCHPRI2_DPA_MASK (0x40U)
7499#define DMA_DCHPRI2_DPA_SHIFT (6U)
7504#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
7505#define DMA_DCHPRI2_ECP_MASK (0x80U)
7506#define DMA_DCHPRI2_ECP_SHIFT (7U)
7511#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
7516#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
7517#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
7518#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
7519#define DMA_DCHPRI1_DPA_MASK (0x40U)
7520#define DMA_DCHPRI1_DPA_SHIFT (6U)
7525#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
7526#define DMA_DCHPRI1_ECP_MASK (0x80U)
7527#define DMA_DCHPRI1_ECP_SHIFT (7U)
7532#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
7537#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
7538#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
7539#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
7540#define DMA_DCHPRI0_DPA_MASK (0x40U)
7541#define DMA_DCHPRI0_DPA_SHIFT (6U)
7546#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
7547#define DMA_DCHPRI0_ECP_MASK (0x80U)
7548#define DMA_DCHPRI0_ECP_SHIFT (7U)
7553#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
7558#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
7559#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
7560#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
7561#define DMA_DCHPRI7_DPA_MASK (0x40U)
7562#define DMA_DCHPRI7_DPA_SHIFT (6U)
7567#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
7568#define DMA_DCHPRI7_ECP_MASK (0x80U)
7569#define DMA_DCHPRI7_ECP_SHIFT (7U)
7574#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
7579#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
7580#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
7581#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
7582#define DMA_DCHPRI6_DPA_MASK (0x40U)
7583#define DMA_DCHPRI6_DPA_SHIFT (6U)
7588#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
7589#define DMA_DCHPRI6_ECP_MASK (0x80U)
7590#define DMA_DCHPRI6_ECP_SHIFT (7U)
7595#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
7600#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
7601#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
7602#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
7603#define DMA_DCHPRI5_DPA_MASK (0x40U)
7604#define DMA_DCHPRI5_DPA_SHIFT (6U)
7609#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
7610#define DMA_DCHPRI5_ECP_MASK (0x80U)
7611#define DMA_DCHPRI5_ECP_SHIFT (7U)
7616#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
7621#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
7622#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
7623#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
7624#define DMA_DCHPRI4_DPA_MASK (0x40U)
7625#define DMA_DCHPRI4_DPA_SHIFT (6U)
7630#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
7631#define DMA_DCHPRI4_ECP_MASK (0x80U)
7632#define DMA_DCHPRI4_ECP_SHIFT (7U)
7637#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
7642#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
7643#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
7644#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
7645#define DMA_DCHPRI11_DPA_MASK (0x40U)
7646#define DMA_DCHPRI11_DPA_SHIFT (6U)
7651#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
7652#define DMA_DCHPRI11_ECP_MASK (0x80U)
7653#define DMA_DCHPRI11_ECP_SHIFT (7U)
7658#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
7663#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
7664#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
7665#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
7666#define DMA_DCHPRI10_DPA_MASK (0x40U)
7667#define DMA_DCHPRI10_DPA_SHIFT (6U)
7672#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
7673#define DMA_DCHPRI10_ECP_MASK (0x80U)
7674#define DMA_DCHPRI10_ECP_SHIFT (7U)
7679#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
7684#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
7685#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
7686#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
7687#define DMA_DCHPRI9_DPA_MASK (0x40U)
7688#define DMA_DCHPRI9_DPA_SHIFT (6U)
7693#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
7694#define DMA_DCHPRI9_ECP_MASK (0x80U)
7695#define DMA_DCHPRI9_ECP_SHIFT (7U)
7700#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
7705#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
7706#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
7707#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
7708#define DMA_DCHPRI8_DPA_MASK (0x40U)
7709#define DMA_DCHPRI8_DPA_SHIFT (6U)
7714#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
7715#define DMA_DCHPRI8_ECP_MASK (0x80U)
7716#define DMA_DCHPRI8_ECP_SHIFT (7U)
7721#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
7726#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
7727#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
7728#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
7729#define DMA_DCHPRI15_DPA_MASK (0x40U)
7730#define DMA_DCHPRI15_DPA_SHIFT (6U)
7735#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
7736#define DMA_DCHPRI15_ECP_MASK (0x80U)
7737#define DMA_DCHPRI15_ECP_SHIFT (7U)
7742#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
7747#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
7748#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
7749#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
7750#define DMA_DCHPRI14_DPA_MASK (0x40U)
7751#define DMA_DCHPRI14_DPA_SHIFT (6U)
7756#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
7757#define DMA_DCHPRI14_ECP_MASK (0x80U)
7758#define DMA_DCHPRI14_ECP_SHIFT (7U)
7763#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
7768#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
7769#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
7770#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
7771#define DMA_DCHPRI13_DPA_MASK (0x40U)
7772#define DMA_DCHPRI13_DPA_SHIFT (6U)
7777#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
7778#define DMA_DCHPRI13_ECP_MASK (0x80U)
7779#define DMA_DCHPRI13_ECP_SHIFT (7U)
7784#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
7789#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
7790#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
7791#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
7792#define DMA_DCHPRI12_DPA_MASK (0x40U)
7793#define DMA_DCHPRI12_DPA_SHIFT (6U)
7798#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
7799#define DMA_DCHPRI12_ECP_MASK (0x80U)
7800#define DMA_DCHPRI12_ECP_SHIFT (7U)
7805#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
7810#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
7811#define DMA_SADDR_SADDR_SHIFT (0U)
7812#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
7815/* The count of DMA_SADDR */
7816#define DMA_SADDR_COUNT (16U)
7817
7820#define DMA_SOFF_SOFF_MASK (0xFFFFU)
7821#define DMA_SOFF_SOFF_SHIFT (0U)
7822#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
7825/* The count of DMA_SOFF */
7826#define DMA_SOFF_COUNT (16U)
7827
7830#define DMA_ATTR_DSIZE_MASK (0x7U)
7831#define DMA_ATTR_DSIZE_SHIFT (0U)
7832#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
7833#define DMA_ATTR_DMOD_MASK (0xF8U)
7834#define DMA_ATTR_DMOD_SHIFT (3U)
7835#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
7836#define DMA_ATTR_SSIZE_MASK (0x700U)
7837#define DMA_ATTR_SSIZE_SHIFT (8U)
7848#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
7849#define DMA_ATTR_SMOD_MASK (0xF800U)
7850#define DMA_ATTR_SMOD_SHIFT (11U)
7854#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
7857/* The count of DMA_ATTR */
7858#define DMA_ATTR_COUNT (16U)
7859
7862#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
7863#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
7864#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
7867/* The count of DMA_NBYTES_MLNO */
7868#define DMA_NBYTES_MLNO_COUNT (16U)
7869
7872#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
7873#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
7874#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
7875#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
7876#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
7881#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
7882#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
7883#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
7888#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
7891/* The count of DMA_NBYTES_MLOFFNO */
7892#define DMA_NBYTES_MLOFFNO_COUNT (16U)
7893
7896#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
7897#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
7898#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
7899#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
7900#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
7901#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
7902#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
7903#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
7908#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
7909#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
7910#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
7915#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
7918/* The count of DMA_NBYTES_MLOFFYES */
7919#define DMA_NBYTES_MLOFFYES_COUNT (16U)
7920
7923#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
7924#define DMA_SLAST_SLAST_SHIFT (0U)
7925#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
7928/* The count of DMA_SLAST */
7929#define DMA_SLAST_COUNT (16U)
7930
7933#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
7934#define DMA_DADDR_DADDR_SHIFT (0U)
7935#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
7938/* The count of DMA_DADDR */
7939#define DMA_DADDR_COUNT (16U)
7940
7943#define DMA_DOFF_DOFF_MASK (0xFFFFU)
7944#define DMA_DOFF_DOFF_SHIFT (0U)
7945#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
7948/* The count of DMA_DOFF */
7949#define DMA_DOFF_COUNT (16U)
7950
7953#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
7954#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
7955#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
7956#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
7957#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
7962#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
7965/* The count of DMA_CITER_ELINKNO */
7966#define DMA_CITER_ELINKNO_COUNT (16U)
7967
7970#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
7971#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
7972#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
7973#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
7974#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
7975#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
7976#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
7977#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
7982#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
7985/* The count of DMA_CITER_ELINKYES */
7986#define DMA_CITER_ELINKYES_COUNT (16U)
7987
7990#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
7991#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
7992#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
7995/* The count of DMA_DLAST_SGA */
7996#define DMA_DLAST_SGA_COUNT (16U)
7997
8000#define DMA_CSR_START_MASK (0x1U)
8001#define DMA_CSR_START_SHIFT (0U)
8006#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
8007#define DMA_CSR_INTMAJOR_MASK (0x2U)
8008#define DMA_CSR_INTMAJOR_SHIFT (1U)
8013#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
8014#define DMA_CSR_INTHALF_MASK (0x4U)
8015#define DMA_CSR_INTHALF_SHIFT (2U)
8020#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
8021#define DMA_CSR_DREQ_MASK (0x8U)
8022#define DMA_CSR_DREQ_SHIFT (3U)
8027#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
8028#define DMA_CSR_ESG_MASK (0x10U)
8029#define DMA_CSR_ESG_SHIFT (4U)
8034#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
8035#define DMA_CSR_MAJORELINK_MASK (0x20U)
8036#define DMA_CSR_MAJORELINK_SHIFT (5U)
8041#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
8042#define DMA_CSR_ACTIVE_MASK (0x40U)
8043#define DMA_CSR_ACTIVE_SHIFT (6U)
8044#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
8045#define DMA_CSR_DONE_MASK (0x80U)
8046#define DMA_CSR_DONE_SHIFT (7U)
8047#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
8048#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
8049#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
8050#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
8051#define DMA_CSR_BWC_MASK (0xC000U)
8052#define DMA_CSR_BWC_SHIFT (14U)
8059#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
8062/* The count of DMA_CSR */
8063#define DMA_CSR_COUNT (16U)
8064
8067#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
8068#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
8069#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
8070#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
8071#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
8076#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
8079/* The count of DMA_BITER_ELINKNO */
8080#define DMA_BITER_ELINKNO_COUNT (16U)
8081
8084#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
8085#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
8086#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
8087#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
8088#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
8089#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
8090#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
8091#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
8096#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
8099/* The count of DMA_BITER_ELINKYES */
8100#define DMA_BITER_ELINKYES_COUNT (16U)
8101
8102
8105 /* end of group DMA_Register_Masks */
8106
8107
8108/* DMA - Peripheral instance base addresses */
8110#define DMA_BASE (0x40008000u)
8112#define DMA0 ((DMA_Type *)DMA_BASE)
8114#define DMA_BASE_ADDRS { DMA_BASE }
8116#define DMA_BASE_PTRS { DMA0 }
8118#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
8119#define DMA_ERROR_IRQS { DMA_Error_IRQn }
8120
8123 /* end of group DMA_Peripheral_Access_Layer */
8124
8125
8126/* ----------------------------------------------------------------------------
8127 -- DMAMUX Peripheral Access Layer
8128 ---------------------------------------------------------------------------- */
8129
8136typedef struct {
8137 __IO uint8_t CHCFG[16];
8138} DMAMUX_Type;
8139
8140/* ----------------------------------------------------------------------------
8141 -- DMAMUX Register Masks
8142 ---------------------------------------------------------------------------- */
8143
8151#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
8152#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
8218#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
8219#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
8220#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
8225#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
8226#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
8227#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
8232#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
8235/* The count of DMAMUX_CHCFG */
8236#define DMAMUX_CHCFG_COUNT (16U)
8237
8238
8241 /* end of group DMAMUX_Register_Masks */
8242
8243
8244/* DMAMUX - Peripheral instance base addresses */
8246#define DMAMUX_BASE (0x40021000u)
8248#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
8250#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
8252#define DMAMUX_BASE_PTRS { DMAMUX }
8253
8256 /* end of group DMAMUX_Peripheral_Access_Layer */
8257
8258
8259/* ----------------------------------------------------------------------------
8260 -- ENET Peripheral Access Layer
8261 ---------------------------------------------------------------------------- */
8262
8269typedef struct {
8270 uint8_t RESERVED_0[4];
8271 __IO uint32_t EIR;
8272 __IO uint32_t EIMR;
8273 uint8_t RESERVED_1[4];
8274 __IO uint32_t RDAR;
8275 __IO uint32_t TDAR;
8276 uint8_t RESERVED_2[12];
8277 __IO uint32_t ECR;
8278 uint8_t RESERVED_3[24];
8279 __IO uint32_t MMFR;
8280 __IO uint32_t MSCR;
8281 uint8_t RESERVED_4[28];
8282 __IO uint32_t MIBC;
8283 uint8_t RESERVED_5[28];
8284 __IO uint32_t RCR;
8285 uint8_t RESERVED_6[60];
8286 __IO uint32_t TCR;
8287 uint8_t RESERVED_7[28];
8288 __IO uint32_t PALR;
8289 __IO uint32_t PAUR;
8290 __IO uint32_t OPD;
8291 uint8_t RESERVED_8[40];
8292 __IO uint32_t IAUR;
8293 __IO uint32_t IALR;
8294 __IO uint32_t GAUR;
8295 __IO uint32_t GALR;
8296 uint8_t RESERVED_9[28];
8297 __IO uint32_t TFWR;
8298 uint8_t RESERVED_10[56];
8299 __IO uint32_t RDSR;
8300 __IO uint32_t TDSR;
8301 __IO uint32_t MRBR;
8302 uint8_t RESERVED_11[4];
8303 __IO uint32_t RSFL;
8304 __IO uint32_t RSEM;
8305 __IO uint32_t RAEM;
8306 __IO uint32_t RAFL;
8307 __IO uint32_t TSEM;
8308 __IO uint32_t TAEM;
8309 __IO uint32_t TAFL;
8310 __IO uint32_t TIPG;
8311 __IO uint32_t FTRL;
8312 uint8_t RESERVED_12[12];
8313 __IO uint32_t TACC;
8314 __IO uint32_t RACC;
8315 uint8_t RESERVED_13[60];
8316 __I uint32_t RMON_T_PACKETS;
8317 __I uint32_t RMON_T_BC_PKT;
8318 __I uint32_t RMON_T_MC_PKT;
8319 __I uint32_t RMON_T_CRC_ALIGN;
8320 __I uint32_t RMON_T_UNDERSIZE;
8321 __I uint32_t RMON_T_OVERSIZE;
8322 __I uint32_t RMON_T_FRAG;
8323 __I uint32_t RMON_T_JAB;
8324 __I uint32_t RMON_T_COL;
8325 __I uint32_t RMON_T_P64;
8326 __I uint32_t RMON_T_P65TO127;
8327 __I uint32_t RMON_T_P128TO255;
8328 __I uint32_t RMON_T_P256TO511;
8329 __I uint32_t RMON_T_P512TO1023;
8330 __I uint32_t RMON_T_P1024TO2047;
8331 __I uint32_t RMON_T_P_GTE2048;
8332 __I uint32_t RMON_T_OCTETS;
8333 uint8_t RESERVED_14[4];
8334 __I uint32_t IEEE_T_FRAME_OK;
8335 __I uint32_t IEEE_T_1COL;
8336 __I uint32_t IEEE_T_MCOL;
8337 __I uint32_t IEEE_T_DEF;
8338 __I uint32_t IEEE_T_LCOL;
8339 __I uint32_t IEEE_T_EXCOL;
8340 __I uint32_t IEEE_T_MACERR;
8341 __I uint32_t IEEE_T_CSERR;
8342 uint8_t RESERVED_15[4];
8343 __I uint32_t IEEE_T_FDXFC;
8344 __I uint32_t IEEE_T_OCTETS_OK;
8345 uint8_t RESERVED_16[12];
8346 __I uint32_t RMON_R_PACKETS;
8347 __I uint32_t RMON_R_BC_PKT;
8348 __I uint32_t RMON_R_MC_PKT;
8349 __I uint32_t RMON_R_CRC_ALIGN;
8350 __I uint32_t RMON_R_UNDERSIZE;
8351 __I uint32_t RMON_R_OVERSIZE;
8352 __I uint32_t RMON_R_FRAG;
8353 __I uint32_t RMON_R_JAB;
8354 uint8_t RESERVED_17[4];
8355 __I uint32_t RMON_R_P64;
8356 __I uint32_t RMON_R_P65TO127;
8357 __I uint32_t RMON_R_P128TO255;
8358 __I uint32_t RMON_R_P256TO511;
8359 __I uint32_t RMON_R_P512TO1023;
8360 __I uint32_t RMON_R_P1024TO2047;
8361 __I uint32_t RMON_R_P_GTE2048;
8362 __I uint32_t RMON_R_OCTETS;
8363 __I uint32_t IEEE_R_DROP;
8364 __I uint32_t IEEE_R_FRAME_OK;
8365 __I uint32_t IEEE_R_CRC;
8366 __I uint32_t IEEE_R_ALIGN;
8367 __I uint32_t IEEE_R_MACERR;
8368 __I uint32_t IEEE_R_FDXFC;
8369 __I uint32_t IEEE_R_OCTETS_OK;
8370 uint8_t RESERVED_18[284];
8371 __IO uint32_t ATCR;
8372 __IO uint32_t ATVR;
8373 __IO uint32_t ATOFF;
8374 __IO uint32_t ATPER;
8375 __IO uint32_t ATCOR;
8376 __IO uint32_t ATINC;
8377 __I uint32_t ATSTMP;
8378 uint8_t RESERVED_19[488];
8379 __IO uint32_t TGSR;
8380 struct { /* offset: 0x608, array step: 0x8 */
8381 __IO uint32_t TCSR;
8382 __IO uint32_t TCCR;
8383 } CHANNEL[4];
8384} ENET_Type;
8385
8386/* ----------------------------------------------------------------------------
8387 -- ENET Register Masks
8388 ---------------------------------------------------------------------------- */
8389
8397#define ENET_EIR_TS_TIMER_MASK (0x8000U)
8398#define ENET_EIR_TS_TIMER_SHIFT (15U)
8399#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
8400#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
8401#define ENET_EIR_TS_AVAIL_SHIFT (16U)
8402#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
8403#define ENET_EIR_WAKEUP_MASK (0x20000U)
8404#define ENET_EIR_WAKEUP_SHIFT (17U)
8405#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
8406#define ENET_EIR_PLR_MASK (0x40000U)
8407#define ENET_EIR_PLR_SHIFT (18U)
8408#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
8409#define ENET_EIR_UN_MASK (0x80000U)
8410#define ENET_EIR_UN_SHIFT (19U)
8411#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
8412#define ENET_EIR_RL_MASK (0x100000U)
8413#define ENET_EIR_RL_SHIFT (20U)
8414#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
8415#define ENET_EIR_LC_MASK (0x200000U)
8416#define ENET_EIR_LC_SHIFT (21U)
8417#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
8418#define ENET_EIR_EBERR_MASK (0x400000U)
8419#define ENET_EIR_EBERR_SHIFT (22U)
8420#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
8421#define ENET_EIR_MII_MASK (0x800000U)
8422#define ENET_EIR_MII_SHIFT (23U)
8423#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
8424#define ENET_EIR_RXB_MASK (0x1000000U)
8425#define ENET_EIR_RXB_SHIFT (24U)
8426#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
8427#define ENET_EIR_RXF_MASK (0x2000000U)
8428#define ENET_EIR_RXF_SHIFT (25U)
8429#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
8430#define ENET_EIR_TXB_MASK (0x4000000U)
8431#define ENET_EIR_TXB_SHIFT (26U)
8432#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
8433#define ENET_EIR_TXF_MASK (0x8000000U)
8434#define ENET_EIR_TXF_SHIFT (27U)
8435#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
8436#define ENET_EIR_GRA_MASK (0x10000000U)
8437#define ENET_EIR_GRA_SHIFT (28U)
8438#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
8439#define ENET_EIR_BABT_MASK (0x20000000U)
8440#define ENET_EIR_BABT_SHIFT (29U)
8441#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
8442#define ENET_EIR_BABR_MASK (0x40000000U)
8443#define ENET_EIR_BABR_SHIFT (30U)
8444#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
8449#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
8450#define ENET_EIMR_TS_TIMER_SHIFT (15U)
8451#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
8452#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
8453#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
8454#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
8455#define ENET_EIMR_WAKEUP_MASK (0x20000U)
8456#define ENET_EIMR_WAKEUP_SHIFT (17U)
8457#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
8458#define ENET_EIMR_PLR_MASK (0x40000U)
8459#define ENET_EIMR_PLR_SHIFT (18U)
8460#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
8461#define ENET_EIMR_UN_MASK (0x80000U)
8462#define ENET_EIMR_UN_SHIFT (19U)
8463#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
8464#define ENET_EIMR_RL_MASK (0x100000U)
8465#define ENET_EIMR_RL_SHIFT (20U)
8466#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
8467#define ENET_EIMR_LC_MASK (0x200000U)
8468#define ENET_EIMR_LC_SHIFT (21U)
8469#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
8470#define ENET_EIMR_EBERR_MASK (0x400000U)
8471#define ENET_EIMR_EBERR_SHIFT (22U)
8472#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
8473#define ENET_EIMR_MII_MASK (0x800000U)
8474#define ENET_EIMR_MII_SHIFT (23U)
8475#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
8476#define ENET_EIMR_RXB_MASK (0x1000000U)
8477#define ENET_EIMR_RXB_SHIFT (24U)
8478#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
8479#define ENET_EIMR_RXF_MASK (0x2000000U)
8480#define ENET_EIMR_RXF_SHIFT (25U)
8481#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
8482#define ENET_EIMR_TXB_MASK (0x4000000U)
8483#define ENET_EIMR_TXB_SHIFT (26U)
8488#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
8489#define ENET_EIMR_TXF_MASK (0x8000000U)
8490#define ENET_EIMR_TXF_SHIFT (27U)
8495#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
8496#define ENET_EIMR_GRA_MASK (0x10000000U)
8497#define ENET_EIMR_GRA_SHIFT (28U)
8502#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
8503#define ENET_EIMR_BABT_MASK (0x20000000U)
8504#define ENET_EIMR_BABT_SHIFT (29U)
8509#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
8510#define ENET_EIMR_BABR_MASK (0x40000000U)
8511#define ENET_EIMR_BABR_SHIFT (30U)
8516#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
8521#define ENET_RDAR_RDAR_MASK (0x1000000U)
8522#define ENET_RDAR_RDAR_SHIFT (24U)
8523#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
8528#define ENET_TDAR_TDAR_MASK (0x1000000U)
8529#define ENET_TDAR_TDAR_SHIFT (24U)
8530#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
8535#define ENET_ECR_RESET_MASK (0x1U)
8536#define ENET_ECR_RESET_SHIFT (0U)
8537#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
8538#define ENET_ECR_ETHEREN_MASK (0x2U)
8539#define ENET_ECR_ETHEREN_SHIFT (1U)
8544#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
8545#define ENET_ECR_MAGICEN_MASK (0x4U)
8546#define ENET_ECR_MAGICEN_SHIFT (2U)
8551#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
8552#define ENET_ECR_SLEEP_MASK (0x8U)
8553#define ENET_ECR_SLEEP_SHIFT (3U)
8558#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
8559#define ENET_ECR_EN1588_MASK (0x10U)
8560#define ENET_ECR_EN1588_SHIFT (4U)
8565#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
8566#define ENET_ECR_DBGEN_MASK (0x40U)
8567#define ENET_ECR_DBGEN_SHIFT (6U)
8572#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
8573#define ENET_ECR_STOPEN_MASK (0x80U)
8574#define ENET_ECR_STOPEN_SHIFT (7U)
8575#define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
8576#define ENET_ECR_DBSWP_MASK (0x100U)
8577#define ENET_ECR_DBSWP_SHIFT (8U)
8582#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
8587#define ENET_MMFR_DATA_MASK (0xFFFFU)
8588#define ENET_MMFR_DATA_SHIFT (0U)
8589#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
8590#define ENET_MMFR_TA_MASK (0x30000U)
8591#define ENET_MMFR_TA_SHIFT (16U)
8592#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
8593#define ENET_MMFR_RA_MASK (0x7C0000U)
8594#define ENET_MMFR_RA_SHIFT (18U)
8595#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
8596#define ENET_MMFR_PA_MASK (0xF800000U)
8597#define ENET_MMFR_PA_SHIFT (23U)
8598#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
8599#define ENET_MMFR_OP_MASK (0x30000000U)
8600#define ENET_MMFR_OP_SHIFT (28U)
8607#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
8608#define ENET_MMFR_ST_MASK (0xC0000000U)
8609#define ENET_MMFR_ST_SHIFT (30U)
8610#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
8615#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
8616#define ENET_MSCR_MII_SPEED_SHIFT (1U)
8617#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
8618#define ENET_MSCR_DIS_PRE_MASK (0x80U)
8619#define ENET_MSCR_DIS_PRE_SHIFT (7U)
8624#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
8625#define ENET_MSCR_HOLDTIME_MASK (0x700U)
8626#define ENET_MSCR_HOLDTIME_SHIFT (8U)
8633#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
8638#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
8639#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
8640#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
8641#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
8642#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
8643#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
8644#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
8645#define ENET_MIBC_MIB_DIS_SHIFT (31U)
8646#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
8651#define ENET_RCR_LOOP_MASK (0x1U)
8652#define ENET_RCR_LOOP_SHIFT (0U)
8657#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
8658#define ENET_RCR_DRT_MASK (0x2U)
8659#define ENET_RCR_DRT_SHIFT (1U)
8664#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
8665#define ENET_RCR_MII_MODE_MASK (0x4U)
8666#define ENET_RCR_MII_MODE_SHIFT (2U)
8671#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
8672#define ENET_RCR_PROM_MASK (0x8U)
8673#define ENET_RCR_PROM_SHIFT (3U)
8678#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
8679#define ENET_RCR_BC_REJ_MASK (0x10U)
8680#define ENET_RCR_BC_REJ_SHIFT (4U)
8681#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
8682#define ENET_RCR_FCE_MASK (0x20U)
8683#define ENET_RCR_FCE_SHIFT (5U)
8684#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
8685#define ENET_RCR_RMII_MODE_MASK (0x100U)
8686#define ENET_RCR_RMII_MODE_SHIFT (8U)
8691#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
8692#define ENET_RCR_RMII_10T_MASK (0x200U)
8693#define ENET_RCR_RMII_10T_SHIFT (9U)
8698#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
8699#define ENET_RCR_PADEN_MASK (0x1000U)
8700#define ENET_RCR_PADEN_SHIFT (12U)
8705#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
8706#define ENET_RCR_PAUFWD_MASK (0x2000U)
8707#define ENET_RCR_PAUFWD_SHIFT (13U)
8712#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
8713#define ENET_RCR_CRCFWD_MASK (0x4000U)
8714#define ENET_RCR_CRCFWD_SHIFT (14U)
8719#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
8720#define ENET_RCR_CFEN_MASK (0x8000U)
8721#define ENET_RCR_CFEN_SHIFT (15U)
8726#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
8727#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
8728#define ENET_RCR_MAX_FL_SHIFT (16U)
8729#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
8730#define ENET_RCR_NLC_MASK (0x40000000U)
8731#define ENET_RCR_NLC_SHIFT (30U)
8736#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
8737#define ENET_RCR_GRS_MASK (0x80000000U)
8738#define ENET_RCR_GRS_SHIFT (31U)
8739#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
8744#define ENET_TCR_GTS_MASK (0x1U)
8745#define ENET_TCR_GTS_SHIFT (0U)
8746#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
8747#define ENET_TCR_FDEN_MASK (0x4U)
8748#define ENET_TCR_FDEN_SHIFT (2U)
8749#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
8750#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
8751#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
8756#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
8757#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
8758#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
8759#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
8760#define ENET_TCR_ADDSEL_MASK (0xE0U)
8761#define ENET_TCR_ADDSEL_SHIFT (5U)
8768#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
8769#define ENET_TCR_ADDINS_MASK (0x100U)
8770#define ENET_TCR_ADDINS_SHIFT (8U)
8775#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
8776#define ENET_TCR_CRCFWD_MASK (0x200U)
8777#define ENET_TCR_CRCFWD_SHIFT (9U)
8782#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
8787#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
8788#define ENET_PALR_PADDR1_SHIFT (0U)
8789#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
8794#define ENET_PAUR_TYPE_MASK (0xFFFFU)
8795#define ENET_PAUR_TYPE_SHIFT (0U)
8796#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
8797#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
8798#define ENET_PAUR_PADDR2_SHIFT (16U)
8799#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
8804#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
8805#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
8806#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
8807#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
8808#define ENET_OPD_OPCODE_SHIFT (16U)
8809#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
8814#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
8815#define ENET_IAUR_IADDR1_SHIFT (0U)
8816#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
8821#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
8822#define ENET_IALR_IADDR2_SHIFT (0U)
8823#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
8828#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
8829#define ENET_GAUR_GADDR1_SHIFT (0U)
8830#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
8835#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
8836#define ENET_GALR_GADDR2_SHIFT (0U)
8837#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
8842#define ENET_TFWR_TFWR_MASK (0x3FU)
8843#define ENET_TFWR_TFWR_SHIFT (0U)
8852#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
8853#define ENET_TFWR_STRFWD_MASK (0x100U)
8854#define ENET_TFWR_STRFWD_SHIFT (8U)
8859#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
8864#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
8865#define ENET_RDSR_R_DES_START_SHIFT (3U)
8866#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
8871#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
8872#define ENET_TDSR_X_DES_START_SHIFT (3U)
8873#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
8878#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
8879#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
8880#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
8885#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
8886#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
8887#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
8892#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
8893#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
8894#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
8895#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
8896#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
8897#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
8902#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
8903#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
8904#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
8909#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
8910#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
8911#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
8916#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
8917#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
8918#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
8923#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
8924#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
8925#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
8930#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
8931#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
8932#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
8937#define ENET_TIPG_IPG_MASK (0x1FU)
8938#define ENET_TIPG_IPG_SHIFT (0U)
8939#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
8944#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
8945#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
8946#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
8951#define ENET_TACC_SHIFT16_MASK (0x1U)
8952#define ENET_TACC_SHIFT16_SHIFT (0U)
8957#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
8958#define ENET_TACC_IPCHK_MASK (0x8U)
8959#define ENET_TACC_IPCHK_SHIFT (3U)
8964#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
8965#define ENET_TACC_PROCHK_MASK (0x10U)
8966#define ENET_TACC_PROCHK_SHIFT (4U)
8971#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
8976#define ENET_RACC_PADREM_MASK (0x1U)
8977#define ENET_RACC_PADREM_SHIFT (0U)
8982#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
8983#define ENET_RACC_IPDIS_MASK (0x2U)
8984#define ENET_RACC_IPDIS_SHIFT (1U)
8989#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
8990#define ENET_RACC_PRODIS_MASK (0x4U)
8991#define ENET_RACC_PRODIS_SHIFT (2U)
8996#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
8997#define ENET_RACC_LINEDIS_MASK (0x40U)
8998#define ENET_RACC_LINEDIS_SHIFT (6U)
9003#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
9004#define ENET_RACC_SHIFT16_MASK (0x80U)
9005#define ENET_RACC_SHIFT16_SHIFT (7U)
9010#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
9015#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
9016#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
9017#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
9022#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
9023#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
9024#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
9029#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
9030#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
9031#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
9036#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
9037#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
9038#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
9043#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
9044#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
9045#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
9050#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
9051#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
9052#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
9057#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
9058#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
9059#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
9064#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
9065#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
9066#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
9071#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
9072#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
9073#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
9078#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
9079#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
9080#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
9085#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
9086#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
9087#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
9092#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
9093#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
9094#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
9099#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
9100#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
9101#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
9106#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
9107#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
9108#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
9113#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
9114#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
9115#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
9120#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
9121#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
9122#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
9127#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
9128#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
9129#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
9134#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
9135#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
9136#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
9141#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
9142#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
9143#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
9148#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
9149#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
9150#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
9155#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
9156#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
9157#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
9162#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
9163#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
9164#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
9169#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
9170#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
9171#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
9176#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
9177#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
9178#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
9183#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
9184#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
9185#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
9190#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
9191#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
9192#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
9197#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
9198#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
9199#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
9204#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
9205#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
9206#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
9211#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
9212#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
9213#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
9218#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
9219#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
9220#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
9225#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
9226#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
9227#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
9232#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
9233#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
9234#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
9239#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
9240#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
9241#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
9246#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
9247#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
9248#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
9253#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
9254#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
9255#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
9260#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
9261#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
9262#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
9267#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
9268#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
9269#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
9274#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
9275#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
9276#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
9281#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
9282#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
9283#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
9288#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
9289#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
9290#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
9295#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
9296#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
9297#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
9302#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
9303#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
9304#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
9309#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
9310#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
9311#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
9316#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
9317#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
9318#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
9323#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
9324#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
9325#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
9330#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
9331#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
9332#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
9337#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
9338#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
9339#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
9344#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
9345#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
9346#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
9351#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
9352#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
9353#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
9358#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
9359#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
9360#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
9365#define ENET_ATCR_EN_MASK (0x1U)
9366#define ENET_ATCR_EN_SHIFT (0U)
9371#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
9372#define ENET_ATCR_OFFEN_MASK (0x4U)
9373#define ENET_ATCR_OFFEN_SHIFT (2U)
9378#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
9379#define ENET_ATCR_OFFRST_MASK (0x8U)
9380#define ENET_ATCR_OFFRST_SHIFT (3U)
9385#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
9386#define ENET_ATCR_PEREN_MASK (0x10U)
9387#define ENET_ATCR_PEREN_SHIFT (4U)
9392#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
9393#define ENET_ATCR_PINPER_MASK (0x80U)
9394#define ENET_ATCR_PINPER_SHIFT (7U)
9399#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
9400#define ENET_ATCR_RESTART_MASK (0x200U)
9401#define ENET_ATCR_RESTART_SHIFT (9U)
9402#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
9403#define ENET_ATCR_CAPTURE_MASK (0x800U)
9404#define ENET_ATCR_CAPTURE_SHIFT (11U)
9409#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
9410#define ENET_ATCR_SLAVE_MASK (0x2000U)
9411#define ENET_ATCR_SLAVE_SHIFT (13U)
9416#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
9421#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
9422#define ENET_ATVR_ATIME_SHIFT (0U)
9423#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
9428#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
9429#define ENET_ATOFF_OFFSET_SHIFT (0U)
9430#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
9435#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
9436#define ENET_ATPER_PERIOD_SHIFT (0U)
9437#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
9442#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
9443#define ENET_ATCOR_COR_SHIFT (0U)
9444#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
9449#define ENET_ATINC_INC_MASK (0x7FU)
9450#define ENET_ATINC_INC_SHIFT (0U)
9451#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
9452#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
9453#define ENET_ATINC_INC_CORR_SHIFT (8U)
9454#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
9459#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
9460#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
9461#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
9466#define ENET_TGSR_TF0_MASK (0x1U)
9467#define ENET_TGSR_TF0_SHIFT (0U)
9472#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
9473#define ENET_TGSR_TF1_MASK (0x2U)
9474#define ENET_TGSR_TF1_SHIFT (1U)
9479#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
9480#define ENET_TGSR_TF2_MASK (0x4U)
9481#define ENET_TGSR_TF2_SHIFT (2U)
9486#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
9487#define ENET_TGSR_TF3_MASK (0x8U)
9488#define ENET_TGSR_TF3_SHIFT (3U)
9493#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
9498#define ENET_TCSR_TDRE_MASK (0x1U)
9499#define ENET_TCSR_TDRE_SHIFT (0U)
9504#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
9505#define ENET_TCSR_TMODE_MASK (0x3CU)
9506#define ENET_TCSR_TMODE_SHIFT (2U)
9523#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
9524#define ENET_TCSR_TIE_MASK (0x40U)
9525#define ENET_TCSR_TIE_SHIFT (6U)
9530#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
9531#define ENET_TCSR_TF_MASK (0x80U)
9532#define ENET_TCSR_TF_SHIFT (7U)
9537#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
9540/* The count of ENET_TCSR */
9541#define ENET_TCSR_COUNT (4U)
9542
9545#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
9546#define ENET_TCCR_TCC_SHIFT (0U)
9547#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
9550/* The count of ENET_TCCR */
9551#define ENET_TCCR_COUNT (4U)
9552
9553
9556 /* end of group ENET_Register_Masks */
9557
9558
9559/* ENET - Peripheral instance base addresses */
9561#define ENET_BASE (0x400C0000u)
9563#define ENET ((ENET_Type *)ENET_BASE)
9565#define ENET_BASE_ADDRS { ENET_BASE }
9567#define ENET_BASE_PTRS { ENET }
9569#define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
9570#define ENET_Receive_IRQS { ENET_Receive_IRQn }
9571#define ENET_Error_IRQS { ENET_Error_IRQn }
9572#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
9573/* ENET Buffer Descriptor and Buffer Address Alignment. */
9574#define ENET_BUFF_ALIGNMENT (16U)
9575
9576
9579 /* end of group ENET_Peripheral_Access_Layer */
9580
9581
9582/* ----------------------------------------------------------------------------
9583 -- EWM Peripheral Access Layer
9584 ---------------------------------------------------------------------------- */
9585
9592typedef struct {
9593 __IO uint8_t CTRL;
9594 __O uint8_t SERV;
9595 __IO uint8_t CMPL;
9596 __IO uint8_t CMPH;
9597} EWM_Type;
9598
9599/* ----------------------------------------------------------------------------
9600 -- EWM Register Masks
9601 ---------------------------------------------------------------------------- */
9602
9610#define EWM_CTRL_EWMEN_MASK (0x1U)
9611#define EWM_CTRL_EWMEN_SHIFT (0U)
9612#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
9613#define EWM_CTRL_ASSIN_MASK (0x2U)
9614#define EWM_CTRL_ASSIN_SHIFT (1U)
9615#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
9616#define EWM_CTRL_INEN_MASK (0x4U)
9617#define EWM_CTRL_INEN_SHIFT (2U)
9618#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
9619#define EWM_CTRL_INTEN_MASK (0x8U)
9620#define EWM_CTRL_INTEN_SHIFT (3U)
9621#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
9626#define EWM_SERV_SERVICE_MASK (0xFFU)
9627#define EWM_SERV_SERVICE_SHIFT (0U)
9628#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
9633#define EWM_CMPL_COMPAREL_MASK (0xFFU)
9634#define EWM_CMPL_COMPAREL_SHIFT (0U)
9635#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
9640#define EWM_CMPH_COMPAREH_MASK (0xFFU)
9641#define EWM_CMPH_COMPAREH_SHIFT (0U)
9642#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
9648 /* end of group EWM_Register_Masks */
9649
9650
9651/* EWM - Peripheral instance base addresses */
9653#define EWM_BASE (0x40061000u)
9655#define EWM ((EWM_Type *)EWM_BASE)
9657#define EWM_BASE_ADDRS { EWM_BASE }
9659#define EWM_BASE_PTRS { EWM }
9661#define EWM_IRQS { WDOG_EWM_IRQn }
9662
9665 /* end of group EWM_Peripheral_Access_Layer */
9666
9667
9668/* ----------------------------------------------------------------------------
9669 -- FB Peripheral Access Layer
9670 ---------------------------------------------------------------------------- */
9671
9678typedef struct {
9679 struct { /* offset: 0x0, array step: 0xC */
9680 __IO uint32_t CSAR;
9681 __IO uint32_t CSMR;
9682 __IO uint32_t CSCR;
9683 } CS[6];
9684 uint8_t RESERVED_0[24];
9685 __IO uint32_t CSPMCR;
9686} FB_Type;
9687
9688/* ----------------------------------------------------------------------------
9689 -- FB Register Masks
9690 ---------------------------------------------------------------------------- */
9691
9699#define FB_CSAR_BA_MASK (0xFFFF0000U)
9700#define FB_CSAR_BA_SHIFT (16U)
9701#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
9704/* The count of FB_CSAR */
9705#define FB_CSAR_COUNT (6U)
9706
9709#define FB_CSMR_V_MASK (0x1U)
9710#define FB_CSMR_V_SHIFT (0U)
9715#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
9716#define FB_CSMR_WP_MASK (0x100U)
9717#define FB_CSMR_WP_SHIFT (8U)
9722#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
9723#define FB_CSMR_BAM_MASK (0xFFFF0000U)
9724#define FB_CSMR_BAM_SHIFT (16U)
9729#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
9732/* The count of FB_CSMR */
9733#define FB_CSMR_COUNT (6U)
9734
9737#define FB_CSCR_BSTW_MASK (0x8U)
9738#define FB_CSCR_BSTW_SHIFT (3U)
9743#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
9744#define FB_CSCR_BSTR_MASK (0x10U)
9745#define FB_CSCR_BSTR_SHIFT (4U)
9750#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
9751#define FB_CSCR_BEM_MASK (0x20U)
9752#define FB_CSCR_BEM_SHIFT (5U)
9757#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
9758#define FB_CSCR_PS_MASK (0xC0U)
9759#define FB_CSCR_PS_SHIFT (6U)
9765#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
9766#define FB_CSCR_AA_MASK (0x100U)
9767#define FB_CSCR_AA_SHIFT (8U)
9772#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
9773#define FB_CSCR_BLS_MASK (0x200U)
9774#define FB_CSCR_BLS_SHIFT (9U)
9779#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
9780#define FB_CSCR_WS_MASK (0xFC00U)
9781#define FB_CSCR_WS_SHIFT (10U)
9782#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
9783#define FB_CSCR_WRAH_MASK (0x30000U)
9784#define FB_CSCR_WRAH_SHIFT (16U)
9791#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
9792#define FB_CSCR_RDAH_MASK (0xC0000U)
9793#define FB_CSCR_RDAH_SHIFT (18U)
9800#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
9801#define FB_CSCR_ASET_MASK (0x300000U)
9802#define FB_CSCR_ASET_SHIFT (20U)
9809#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
9810#define FB_CSCR_EXTS_MASK (0x400000U)
9811#define FB_CSCR_EXTS_SHIFT (22U)
9816#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
9817#define FB_CSCR_SWSEN_MASK (0x800000U)
9818#define FB_CSCR_SWSEN_SHIFT (23U)
9823#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
9824#define FB_CSCR_SWS_MASK (0xFC000000U)
9825#define FB_CSCR_SWS_SHIFT (26U)
9826#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
9829/* The count of FB_CSCR */
9830#define FB_CSCR_COUNT (6U)
9831
9834#define FB_CSPMCR_GROUP5_MASK (0xF000U)
9835#define FB_CSPMCR_GROUP5_SHIFT (12U)
9841#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
9842#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
9843#define FB_CSPMCR_GROUP4_SHIFT (16U)
9849#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
9850#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
9851#define FB_CSPMCR_GROUP3_SHIFT (20U)
9857#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
9858#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
9859#define FB_CSPMCR_GROUP2_SHIFT (24U)
9865#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
9866#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
9867#define FB_CSPMCR_GROUP1_SHIFT (28U)
9873#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
9879 /* end of group FB_Register_Masks */
9880
9881
9882/* FB - Peripheral instance base addresses */
9884#define FB_BASE (0x4000C000u)
9886#define FB ((FB_Type *)FB_BASE)
9888#define FB_BASE_ADDRS { FB_BASE }
9890#define FB_BASE_PTRS { FB }
9891
9894 /* end of group FB_Peripheral_Access_Layer */
9895
9896
9897/* ----------------------------------------------------------------------------
9898 -- FMC Peripheral Access Layer
9899 ---------------------------------------------------------------------------- */
9900
9907typedef struct {
9908 __IO uint32_t PFAPR;
9909 __IO uint32_t PFB0CR;
9910 __IO uint32_t PFB1CR;
9911 uint8_t RESERVED_0[244];
9912 __IO uint32_t TAGVDW0S[4];
9913 __IO uint32_t TAGVDW1S[4];
9914 __IO uint32_t TAGVDW2S[4];
9915 __IO uint32_t TAGVDW3S[4];
9916 uint8_t RESERVED_1[192];
9917 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
9918 __IO uint32_t DATA_U;
9919 __IO uint32_t DATA_L;
9920 } SET[4][4];
9921} FMC_Type;
9922
9923/* ----------------------------------------------------------------------------
9924 -- FMC Register Masks
9925 ---------------------------------------------------------------------------- */
9926
9934#define FMC_PFAPR_M0AP_MASK (0x3U)
9935#define FMC_PFAPR_M0AP_SHIFT (0U)
9942#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
9943#define FMC_PFAPR_M1AP_MASK (0xCU)
9944#define FMC_PFAPR_M1AP_SHIFT (2U)
9951#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
9952#define FMC_PFAPR_M2AP_MASK (0x30U)
9953#define FMC_PFAPR_M2AP_SHIFT (4U)
9960#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
9961#define FMC_PFAPR_M3AP_MASK (0xC0U)
9962#define FMC_PFAPR_M3AP_SHIFT (6U)
9969#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
9970#define FMC_PFAPR_M4AP_MASK (0x300U)
9971#define FMC_PFAPR_M4AP_SHIFT (8U)
9978#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
9979#define FMC_PFAPR_M5AP_MASK (0xC00U)
9980#define FMC_PFAPR_M5AP_SHIFT (10U)
9987#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
9988#define FMC_PFAPR_M6AP_MASK (0x3000U)
9989#define FMC_PFAPR_M6AP_SHIFT (12U)
9996#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
9997#define FMC_PFAPR_M7AP_MASK (0xC000U)
9998#define FMC_PFAPR_M7AP_SHIFT (14U)
10005#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
10006#define FMC_PFAPR_M0PFD_MASK (0x10000U)
10007#define FMC_PFAPR_M0PFD_SHIFT (16U)
10012#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
10013#define FMC_PFAPR_M1PFD_MASK (0x20000U)
10014#define FMC_PFAPR_M1PFD_SHIFT (17U)
10019#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
10020#define FMC_PFAPR_M2PFD_MASK (0x40000U)
10021#define FMC_PFAPR_M2PFD_SHIFT (18U)
10026#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
10027#define FMC_PFAPR_M3PFD_MASK (0x80000U)
10028#define FMC_PFAPR_M3PFD_SHIFT (19U)
10033#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
10034#define FMC_PFAPR_M4PFD_MASK (0x100000U)
10035#define FMC_PFAPR_M4PFD_SHIFT (20U)
10040#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
10041#define FMC_PFAPR_M5PFD_MASK (0x200000U)
10042#define FMC_PFAPR_M5PFD_SHIFT (21U)
10047#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
10048#define FMC_PFAPR_M6PFD_MASK (0x400000U)
10049#define FMC_PFAPR_M6PFD_SHIFT (22U)
10054#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
10055#define FMC_PFAPR_M7PFD_MASK (0x800000U)
10056#define FMC_PFAPR_M7PFD_SHIFT (23U)
10061#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
10066#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
10067#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
10072#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
10073#define FMC_PFB0CR_B0IPE_MASK (0x2U)
10074#define FMC_PFB0CR_B0IPE_SHIFT (1U)
10079#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
10080#define FMC_PFB0CR_B0DPE_MASK (0x4U)
10081#define FMC_PFB0CR_B0DPE_SHIFT (2U)
10086#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
10087#define FMC_PFB0CR_B0ICE_MASK (0x8U)
10088#define FMC_PFB0CR_B0ICE_SHIFT (3U)
10093#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
10094#define FMC_PFB0CR_B0DCE_MASK (0x10U)
10095#define FMC_PFB0CR_B0DCE_SHIFT (4U)
10100#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
10101#define FMC_PFB0CR_CRC_MASK (0xE0U)
10102#define FMC_PFB0CR_CRC_SHIFT (5U)
10110#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
10111#define FMC_PFB0CR_B0MW_MASK (0x60000U)
10112#define FMC_PFB0CR_B0MW_SHIFT (17U)
10119#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
10120#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
10121#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
10126#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
10127#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
10128#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
10133#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
10134#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
10135#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
10140#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
10141#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
10142#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
10143#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
10148#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
10149#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
10154#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
10155#define FMC_PFB1CR_B1IPE_MASK (0x2U)
10156#define FMC_PFB1CR_B1IPE_SHIFT (1U)
10161#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
10162#define FMC_PFB1CR_B1DPE_MASK (0x4U)
10163#define FMC_PFB1CR_B1DPE_SHIFT (2U)
10168#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
10169#define FMC_PFB1CR_B1ICE_MASK (0x8U)
10170#define FMC_PFB1CR_B1ICE_SHIFT (3U)
10175#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
10176#define FMC_PFB1CR_B1DCE_MASK (0x10U)
10177#define FMC_PFB1CR_B1DCE_SHIFT (4U)
10182#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
10183#define FMC_PFB1CR_B1MW_MASK (0x60000U)
10184#define FMC_PFB1CR_B1MW_SHIFT (17U)
10191#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
10192#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
10193#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
10194#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
10199#define FMC_TAGVDW0S_valid_MASK (0x1U)
10200#define FMC_TAGVDW0S_valid_SHIFT (0U)
10201#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
10202#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
10203#define FMC_TAGVDW0S_tag_SHIFT (5U)
10204#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
10207/* The count of FMC_TAGVDW0S */
10208#define FMC_TAGVDW0S_COUNT (4U)
10209
10212#define FMC_TAGVDW1S_valid_MASK (0x1U)
10213#define FMC_TAGVDW1S_valid_SHIFT (0U)
10214#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
10215#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
10216#define FMC_TAGVDW1S_tag_SHIFT (5U)
10217#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
10220/* The count of FMC_TAGVDW1S */
10221#define FMC_TAGVDW1S_COUNT (4U)
10222
10225#define FMC_TAGVDW2S_valid_MASK (0x1U)
10226#define FMC_TAGVDW2S_valid_SHIFT (0U)
10227#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
10228#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
10229#define FMC_TAGVDW2S_tag_SHIFT (5U)
10230#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
10233/* The count of FMC_TAGVDW2S */
10234#define FMC_TAGVDW2S_COUNT (4U)
10235
10238#define FMC_TAGVDW3S_valid_MASK (0x1U)
10239#define FMC_TAGVDW3S_valid_SHIFT (0U)
10240#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
10241#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
10242#define FMC_TAGVDW3S_tag_SHIFT (5U)
10243#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
10246/* The count of FMC_TAGVDW3S */
10247#define FMC_TAGVDW3S_COUNT (4U)
10248
10251#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
10252#define FMC_DATA_U_data_SHIFT (0U)
10253#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
10256/* The count of FMC_DATA_U */
10257#define FMC_DATA_U_COUNT (4U)
10258
10259/* The count of FMC_DATA_U */
10260#define FMC_DATA_U_COUNT2 (4U)
10261
10264#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
10265#define FMC_DATA_L_data_SHIFT (0U)
10266#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
10269/* The count of FMC_DATA_L */
10270#define FMC_DATA_L_COUNT (4U)
10271
10272/* The count of FMC_DATA_L */
10273#define FMC_DATA_L_COUNT2 (4U)
10274
10275
10278 /* end of group FMC_Register_Masks */
10279
10280
10281/* FMC - Peripheral instance base addresses */
10283#define FMC_BASE (0x4001F000u)
10285#define FMC ((FMC_Type *)FMC_BASE)
10287#define FMC_BASE_ADDRS { FMC_BASE }
10289#define FMC_BASE_PTRS { FMC }
10290
10293 /* end of group FMC_Peripheral_Access_Layer */
10294
10295
10296/* ----------------------------------------------------------------------------
10297 -- FTFE Peripheral Access Layer
10298 ---------------------------------------------------------------------------- */
10299
10306typedef struct {
10307 __IO uint8_t FSTAT;
10308 __IO uint8_t FCNFG;
10309 __I uint8_t FSEC;
10310 __I uint8_t FOPT;
10311 __IO uint8_t FCCOB3;
10312 __IO uint8_t FCCOB2;
10313 __IO uint8_t FCCOB1;
10314 __IO uint8_t FCCOB0;
10315 __IO uint8_t FCCOB7;
10316 __IO uint8_t FCCOB6;
10317 __IO uint8_t FCCOB5;
10318 __IO uint8_t FCCOB4;
10319 __IO uint8_t FCCOBB;
10320 __IO uint8_t FCCOBA;
10321 __IO uint8_t FCCOB9;
10322 __IO uint8_t FCCOB8;
10323 __IO uint8_t FPROT3;
10324 __IO uint8_t FPROT2;
10325 __IO uint8_t FPROT1;
10326 __IO uint8_t FPROT0;
10327 uint8_t RESERVED_0[2];
10328 __IO uint8_t FEPROT;
10329 __IO uint8_t FDPROT;
10330} FTFE_Type;
10331
10332/* ----------------------------------------------------------------------------
10333 -- FTFE Register Masks
10334 ---------------------------------------------------------------------------- */
10335
10343#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
10344#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
10345#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
10346#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
10347#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
10352#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
10353#define FTFE_FSTAT_ACCERR_MASK (0x20U)
10354#define FTFE_FSTAT_ACCERR_SHIFT (5U)
10359#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
10360#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
10361#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
10366#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
10367#define FTFE_FSTAT_CCIF_MASK (0x80U)
10368#define FTFE_FSTAT_CCIF_SHIFT (7U)
10373#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
10378#define FTFE_FCNFG_EEERDY_MASK (0x1U)
10379#define FTFE_FCNFG_EEERDY_SHIFT (0U)
10384#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
10385#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
10386#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
10391#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
10392#define FTFE_FCNFG_PFLSH_MASK (0x4U)
10393#define FTFE_FCNFG_PFLSH_SHIFT (2U)
10398#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
10399#define FTFE_FCNFG_SWAP_MASK (0x8U)
10400#define FTFE_FCNFG_SWAP_SHIFT (3U)
10405#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
10406#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
10407#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
10412#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
10413#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
10414#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
10419#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
10420#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
10421#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
10426#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
10427#define FTFE_FCNFG_CCIE_MASK (0x80U)
10428#define FTFE_FCNFG_CCIE_SHIFT (7U)
10433#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
10438#define FTFE_FSEC_SEC_MASK (0x3U)
10439#define FTFE_FSEC_SEC_SHIFT (0U)
10446#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
10447#define FTFE_FSEC_FSLACC_MASK (0xCU)
10448#define FTFE_FSEC_FSLACC_SHIFT (2U)
10455#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
10456#define FTFE_FSEC_MEEN_MASK (0x30U)
10457#define FTFE_FSEC_MEEN_SHIFT (4U)
10464#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
10465#define FTFE_FSEC_KEYEN_MASK (0xC0U)
10466#define FTFE_FSEC_KEYEN_SHIFT (6U)
10473#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
10478#define FTFE_FOPT_OPT_MASK (0xFFU)
10479#define FTFE_FOPT_OPT_SHIFT (0U)
10480#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
10485#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
10486#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
10487#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
10492#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
10493#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
10494#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
10499#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
10500#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
10501#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
10506#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
10507#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
10508#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
10513#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
10514#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
10515#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
10520#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
10521#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
10522#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
10527#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
10528#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
10529#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
10534#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
10535#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
10536#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
10541#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
10542#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
10543#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
10548#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
10549#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
10550#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
10555#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
10556#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
10557#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
10562#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
10563#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
10564#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
10569#define FTFE_FPROT3_PROT_MASK (0xFFU)
10570#define FTFE_FPROT3_PROT_SHIFT (0U)
10575#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
10580#define FTFE_FPROT2_PROT_MASK (0xFFU)
10581#define FTFE_FPROT2_PROT_SHIFT (0U)
10586#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
10591#define FTFE_FPROT1_PROT_MASK (0xFFU)
10592#define FTFE_FPROT1_PROT_SHIFT (0U)
10597#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
10602#define FTFE_FPROT0_PROT_MASK (0xFFU)
10603#define FTFE_FPROT0_PROT_SHIFT (0U)
10608#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
10613#define FTFE_FEPROT_EPROT_MASK (0xFFU)
10614#define FTFE_FEPROT_EPROT_SHIFT (0U)
10619#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
10624#define FTFE_FDPROT_DPROT_MASK (0xFFU)
10625#define FTFE_FDPROT_DPROT_SHIFT (0U)
10630#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
10636 /* end of group FTFE_Register_Masks */
10637
10638
10639/* FTFE - Peripheral instance base addresses */
10641#define FTFE_BASE (0x40020000u)
10643#define FTFE ((FTFE_Type *)FTFE_BASE)
10645#define FTFE_BASE_ADDRS { FTFE_BASE }
10647#define FTFE_BASE_PTRS { FTFE }
10649#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
10650#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
10651
10654 /* end of group FTFE_Peripheral_Access_Layer */
10655
10656
10657/* ----------------------------------------------------------------------------
10658 -- FTM Peripheral Access Layer
10659 ---------------------------------------------------------------------------- */
10660
10667typedef struct {
10668 __IO uint32_t SC;
10669 __IO uint32_t CNT;
10670 __IO uint32_t MOD;
10671 struct { /* offset: 0xC, array step: 0x8 */
10672 __IO uint32_t CnSC;
10673 __IO uint32_t CnV;
10674 } CONTROLS[8];
10675 __IO uint32_t CNTIN;
10676 __IO uint32_t STATUS;
10677 __IO uint32_t MODE;
10678 __IO uint32_t SYNC;
10679 __IO uint32_t OUTINIT;
10680 __IO uint32_t OUTMASK;
10681 __IO uint32_t COMBINE;
10682 __IO uint32_t DEADTIME;
10683 __IO uint32_t EXTTRIG;
10684 __IO uint32_t POL;
10685 __IO uint32_t FMS;
10686 __IO uint32_t FILTER;
10687 __IO uint32_t FLTCTRL;
10688 __IO uint32_t QDCTRL;
10689 __IO uint32_t CONF;
10690 __IO uint32_t FLTPOL;
10691 __IO uint32_t SYNCONF;
10692 __IO uint32_t INVCTRL;
10693 __IO uint32_t SWOCTRL;
10694 __IO uint32_t PWMLOAD;
10695} FTM_Type;
10696
10697/* ----------------------------------------------------------------------------
10698 -- FTM Register Masks
10699 ---------------------------------------------------------------------------- */
10700
10708#define FTM_SC_PS_MASK (0x7U)
10709#define FTM_SC_PS_SHIFT (0U)
10720#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
10721#define FTM_SC_CLKS_MASK (0x18U)
10722#define FTM_SC_CLKS_SHIFT (3U)
10729#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
10730#define FTM_SC_CPWMS_MASK (0x20U)
10731#define FTM_SC_CPWMS_SHIFT (5U)
10736#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
10737#define FTM_SC_TOIE_MASK (0x40U)
10738#define FTM_SC_TOIE_SHIFT (6U)
10743#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
10744#define FTM_SC_TOF_MASK (0x80U)
10745#define FTM_SC_TOF_SHIFT (7U)
10750#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
10755#define FTM_CNT_COUNT_MASK (0xFFFFU)
10756#define FTM_CNT_COUNT_SHIFT (0U)
10757#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
10762#define FTM_MOD_MOD_MASK (0xFFFFU)
10763#define FTM_MOD_MOD_SHIFT (0U)
10764#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
10769#define FTM_CnSC_DMA_MASK (0x1U)
10770#define FTM_CnSC_DMA_SHIFT (0U)
10775#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
10776#define FTM_CnSC_ELSA_MASK (0x4U)
10777#define FTM_CnSC_ELSA_SHIFT (2U)
10778#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
10779#define FTM_CnSC_ELSB_MASK (0x8U)
10780#define FTM_CnSC_ELSB_SHIFT (3U)
10781#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
10782#define FTM_CnSC_MSA_MASK (0x10U)
10783#define FTM_CnSC_MSA_SHIFT (4U)
10784#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
10785#define FTM_CnSC_MSB_MASK (0x20U)
10786#define FTM_CnSC_MSB_SHIFT (5U)
10787#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
10788#define FTM_CnSC_CHIE_MASK (0x40U)
10789#define FTM_CnSC_CHIE_SHIFT (6U)
10794#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
10795#define FTM_CnSC_CHF_MASK (0x80U)
10796#define FTM_CnSC_CHF_SHIFT (7U)
10801#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
10804/* The count of FTM_CnSC */
10805#define FTM_CnSC_COUNT (8U)
10806
10809#define FTM_CnV_VAL_MASK (0xFFFFU)
10810#define FTM_CnV_VAL_SHIFT (0U)
10811#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
10814/* The count of FTM_CnV */
10815#define FTM_CnV_COUNT (8U)
10816
10819#define FTM_CNTIN_INIT_MASK (0xFFFFU)
10820#define FTM_CNTIN_INIT_SHIFT (0U)
10821#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
10826#define FTM_STATUS_CH0F_MASK (0x1U)
10827#define FTM_STATUS_CH0F_SHIFT (0U)
10832#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
10833#define FTM_STATUS_CH1F_MASK (0x2U)
10834#define FTM_STATUS_CH1F_SHIFT (1U)
10839#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
10840#define FTM_STATUS_CH2F_MASK (0x4U)
10841#define FTM_STATUS_CH2F_SHIFT (2U)
10846#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
10847#define FTM_STATUS_CH3F_MASK (0x8U)
10848#define FTM_STATUS_CH3F_SHIFT (3U)
10853#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
10854#define FTM_STATUS_CH4F_MASK (0x10U)
10855#define FTM_STATUS_CH4F_SHIFT (4U)
10860#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
10861#define FTM_STATUS_CH5F_MASK (0x20U)
10862#define FTM_STATUS_CH5F_SHIFT (5U)
10867#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
10868#define FTM_STATUS_CH6F_MASK (0x40U)
10869#define FTM_STATUS_CH6F_SHIFT (6U)
10874#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
10875#define FTM_STATUS_CH7F_MASK (0x80U)
10876#define FTM_STATUS_CH7F_SHIFT (7U)
10881#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
10886#define FTM_MODE_FTMEN_MASK (0x1U)
10887#define FTM_MODE_FTMEN_SHIFT (0U)
10892#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
10893#define FTM_MODE_INIT_MASK (0x2U)
10894#define FTM_MODE_INIT_SHIFT (1U)
10895#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
10896#define FTM_MODE_WPDIS_MASK (0x4U)
10897#define FTM_MODE_WPDIS_SHIFT (2U)
10902#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
10903#define FTM_MODE_PWMSYNC_MASK (0x8U)
10904#define FTM_MODE_PWMSYNC_SHIFT (3U)
10909#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
10910#define FTM_MODE_CAPTEST_MASK (0x10U)
10911#define FTM_MODE_CAPTEST_SHIFT (4U)
10916#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
10917#define FTM_MODE_FAULTM_MASK (0x60U)
10918#define FTM_MODE_FAULTM_SHIFT (5U)
10925#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
10926#define FTM_MODE_FAULTIE_MASK (0x80U)
10927#define FTM_MODE_FAULTIE_SHIFT (7U)
10932#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
10937#define FTM_SYNC_CNTMIN_MASK (0x1U)
10938#define FTM_SYNC_CNTMIN_SHIFT (0U)
10943#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
10944#define FTM_SYNC_CNTMAX_MASK (0x2U)
10945#define FTM_SYNC_CNTMAX_SHIFT (1U)
10950#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
10951#define FTM_SYNC_REINIT_MASK (0x4U)
10952#define FTM_SYNC_REINIT_SHIFT (2U)
10957#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
10958#define FTM_SYNC_SYNCHOM_MASK (0x8U)
10959#define FTM_SYNC_SYNCHOM_SHIFT (3U)
10964#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
10965#define FTM_SYNC_TRIG0_MASK (0x10U)
10966#define FTM_SYNC_TRIG0_SHIFT (4U)
10971#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
10972#define FTM_SYNC_TRIG1_MASK (0x20U)
10973#define FTM_SYNC_TRIG1_SHIFT (5U)
10978#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
10979#define FTM_SYNC_TRIG2_MASK (0x40U)
10980#define FTM_SYNC_TRIG2_SHIFT (6U)
10985#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
10986#define FTM_SYNC_SWSYNC_MASK (0x80U)
10987#define FTM_SYNC_SWSYNC_SHIFT (7U)
10992#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
10997#define FTM_OUTINIT_CH0OI_MASK (0x1U)
10998#define FTM_OUTINIT_CH0OI_SHIFT (0U)
11003#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
11004#define FTM_OUTINIT_CH1OI_MASK (0x2U)
11005#define FTM_OUTINIT_CH1OI_SHIFT (1U)
11010#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
11011#define FTM_OUTINIT_CH2OI_MASK (0x4U)
11012#define FTM_OUTINIT_CH2OI_SHIFT (2U)
11017#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
11018#define FTM_OUTINIT_CH3OI_MASK (0x8U)
11019#define FTM_OUTINIT_CH3OI_SHIFT (3U)
11024#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
11025#define FTM_OUTINIT_CH4OI_MASK (0x10U)
11026#define FTM_OUTINIT_CH4OI_SHIFT (4U)
11031#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
11032#define FTM_OUTINIT_CH5OI_MASK (0x20U)
11033#define FTM_OUTINIT_CH5OI_SHIFT (5U)
11038#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
11039#define FTM_OUTINIT_CH6OI_MASK (0x40U)
11040#define FTM_OUTINIT_CH6OI_SHIFT (6U)
11045#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
11046#define FTM_OUTINIT_CH7OI_MASK (0x80U)
11047#define FTM_OUTINIT_CH7OI_SHIFT (7U)
11052#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
11057#define FTM_OUTMASK_CH0OM_MASK (0x1U)
11058#define FTM_OUTMASK_CH0OM_SHIFT (0U)
11063#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
11064#define FTM_OUTMASK_CH1OM_MASK (0x2U)
11065#define FTM_OUTMASK_CH1OM_SHIFT (1U)
11070#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
11071#define FTM_OUTMASK_CH2OM_MASK (0x4U)
11072#define FTM_OUTMASK_CH2OM_SHIFT (2U)
11077#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
11078#define FTM_OUTMASK_CH3OM_MASK (0x8U)
11079#define FTM_OUTMASK_CH3OM_SHIFT (3U)
11084#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
11085#define FTM_OUTMASK_CH4OM_MASK (0x10U)
11086#define FTM_OUTMASK_CH4OM_SHIFT (4U)
11091#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
11092#define FTM_OUTMASK_CH5OM_MASK (0x20U)
11093#define FTM_OUTMASK_CH5OM_SHIFT (5U)
11098#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
11099#define FTM_OUTMASK_CH6OM_MASK (0x40U)
11100#define FTM_OUTMASK_CH6OM_SHIFT (6U)
11105#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
11106#define FTM_OUTMASK_CH7OM_MASK (0x80U)
11107#define FTM_OUTMASK_CH7OM_SHIFT (7U)
11112#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
11117#define FTM_COMBINE_COMBINE0_MASK (0x1U)
11118#define FTM_COMBINE_COMBINE0_SHIFT (0U)
11123#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
11124#define FTM_COMBINE_COMP0_MASK (0x2U)
11125#define FTM_COMBINE_COMP0_SHIFT (1U)
11130#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
11131#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
11132#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
11137#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
11138#define FTM_COMBINE_DECAP0_MASK (0x8U)
11139#define FTM_COMBINE_DECAP0_SHIFT (3U)
11144#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
11145#define FTM_COMBINE_DTEN0_MASK (0x10U)
11146#define FTM_COMBINE_DTEN0_SHIFT (4U)
11151#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
11152#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
11153#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
11158#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
11159#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
11160#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
11165#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
11166#define FTM_COMBINE_COMBINE1_MASK (0x100U)
11167#define FTM_COMBINE_COMBINE1_SHIFT (8U)
11172#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
11173#define FTM_COMBINE_COMP1_MASK (0x200U)
11174#define FTM_COMBINE_COMP1_SHIFT (9U)
11179#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
11180#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
11181#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
11186#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
11187#define FTM_COMBINE_DECAP1_MASK (0x800U)
11188#define FTM_COMBINE_DECAP1_SHIFT (11U)
11193#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
11194#define FTM_COMBINE_DTEN1_MASK (0x1000U)
11195#define FTM_COMBINE_DTEN1_SHIFT (12U)
11200#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
11201#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
11202#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
11207#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
11208#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
11209#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
11214#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
11215#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
11216#define FTM_COMBINE_COMBINE2_SHIFT (16U)
11221#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
11222#define FTM_COMBINE_COMP2_MASK (0x20000U)
11223#define FTM_COMBINE_COMP2_SHIFT (17U)
11228#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
11229#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
11230#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
11235#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
11236#define FTM_COMBINE_DECAP2_MASK (0x80000U)
11237#define FTM_COMBINE_DECAP2_SHIFT (19U)
11242#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
11243#define FTM_COMBINE_DTEN2_MASK (0x100000U)
11244#define FTM_COMBINE_DTEN2_SHIFT (20U)
11249#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
11250#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
11251#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
11256#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
11257#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
11258#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
11263#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
11264#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
11265#define FTM_COMBINE_COMBINE3_SHIFT (24U)
11270#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
11271#define FTM_COMBINE_COMP3_MASK (0x2000000U)
11272#define FTM_COMBINE_COMP3_SHIFT (25U)
11277#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
11278#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
11279#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
11284#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
11285#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
11286#define FTM_COMBINE_DECAP3_SHIFT (27U)
11291#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
11292#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
11293#define FTM_COMBINE_DTEN3_SHIFT (28U)
11298#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
11299#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
11300#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
11305#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
11306#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
11307#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
11312#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
11317#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
11318#define FTM_DEADTIME_DTVAL_SHIFT (0U)
11319#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
11320#define FTM_DEADTIME_DTPS_MASK (0xC0U)
11321#define FTM_DEADTIME_DTPS_SHIFT (6U)
11327#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
11332#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
11333#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
11338#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
11339#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
11340#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
11345#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
11346#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
11347#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
11352#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
11353#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
11354#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
11359#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
11360#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
11361#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
11366#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
11367#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
11368#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
11373#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
11374#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
11375#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
11380#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
11381#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
11382#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
11387#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
11392#define FTM_POL_POL0_MASK (0x1U)
11393#define FTM_POL_POL0_SHIFT (0U)
11398#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
11399#define FTM_POL_POL1_MASK (0x2U)
11400#define FTM_POL_POL1_SHIFT (1U)
11405#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
11406#define FTM_POL_POL2_MASK (0x4U)
11407#define FTM_POL_POL2_SHIFT (2U)
11412#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
11413#define FTM_POL_POL3_MASK (0x8U)
11414#define FTM_POL_POL3_SHIFT (3U)
11419#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
11420#define FTM_POL_POL4_MASK (0x10U)
11421#define FTM_POL_POL4_SHIFT (4U)
11426#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
11427#define FTM_POL_POL5_MASK (0x20U)
11428#define FTM_POL_POL5_SHIFT (5U)
11433#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
11434#define FTM_POL_POL6_MASK (0x40U)
11435#define FTM_POL_POL6_SHIFT (6U)
11440#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
11441#define FTM_POL_POL7_MASK (0x80U)
11442#define FTM_POL_POL7_SHIFT (7U)
11447#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
11452#define FTM_FMS_FAULTF0_MASK (0x1U)
11453#define FTM_FMS_FAULTF0_SHIFT (0U)
11458#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
11459#define FTM_FMS_FAULTF1_MASK (0x2U)
11460#define FTM_FMS_FAULTF1_SHIFT (1U)
11465#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
11466#define FTM_FMS_FAULTF2_MASK (0x4U)
11467#define FTM_FMS_FAULTF2_SHIFT (2U)
11472#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
11473#define FTM_FMS_FAULTF3_MASK (0x8U)
11474#define FTM_FMS_FAULTF3_SHIFT (3U)
11479#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
11480#define FTM_FMS_FAULTIN_MASK (0x20U)
11481#define FTM_FMS_FAULTIN_SHIFT (5U)
11486#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
11487#define FTM_FMS_WPEN_MASK (0x40U)
11488#define FTM_FMS_WPEN_SHIFT (6U)
11493#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
11494#define FTM_FMS_FAULTF_MASK (0x80U)
11495#define FTM_FMS_FAULTF_SHIFT (7U)
11500#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
11505#define FTM_FILTER_CH0FVAL_MASK (0xFU)
11506#define FTM_FILTER_CH0FVAL_SHIFT (0U)
11507#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
11508#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
11509#define FTM_FILTER_CH1FVAL_SHIFT (4U)
11510#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
11511#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
11512#define FTM_FILTER_CH2FVAL_SHIFT (8U)
11513#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
11514#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
11515#define FTM_FILTER_CH3FVAL_SHIFT (12U)
11516#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
11521#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
11522#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
11527#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
11528#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
11529#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
11534#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
11535#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
11536#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
11541#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
11542#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
11543#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
11548#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
11549#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
11550#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
11555#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
11556#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
11557#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
11562#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
11563#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
11564#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
11569#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
11570#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
11571#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
11576#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
11577#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
11578#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
11579#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
11584#define FTM_QDCTRL_QUADEN_MASK (0x1U)
11585#define FTM_QDCTRL_QUADEN_SHIFT (0U)
11590#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
11591#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
11592#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
11597#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
11598#define FTM_QDCTRL_QUADIR_MASK (0x4U)
11599#define FTM_QDCTRL_QUADIR_SHIFT (2U)
11604#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
11605#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
11606#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
11611#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
11612#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
11613#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
11618#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
11619#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
11620#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
11625#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
11626#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
11627#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
11632#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
11633#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
11634#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
11639#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
11644#define FTM_CONF_NUMTOF_MASK (0x1FU)
11645#define FTM_CONF_NUMTOF_SHIFT (0U)
11646#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
11647#define FTM_CONF_BDMMODE_MASK (0xC0U)
11648#define FTM_CONF_BDMMODE_SHIFT (6U)
11649#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
11650#define FTM_CONF_GTBEEN_MASK (0x200U)
11651#define FTM_CONF_GTBEEN_SHIFT (9U)
11656#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
11657#define FTM_CONF_GTBEOUT_MASK (0x400U)
11658#define FTM_CONF_GTBEOUT_SHIFT (10U)
11663#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
11668#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
11669#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
11674#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
11675#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
11676#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
11681#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
11682#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
11683#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
11688#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
11689#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
11690#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
11695#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
11700#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
11701#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
11706#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
11707#define FTM_SYNCONF_CNTINC_MASK (0x4U)
11708#define FTM_SYNCONF_CNTINC_SHIFT (2U)
11713#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
11714#define FTM_SYNCONF_INVC_MASK (0x10U)
11715#define FTM_SYNCONF_INVC_SHIFT (4U)
11720#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
11721#define FTM_SYNCONF_SWOC_MASK (0x20U)
11722#define FTM_SYNCONF_SWOC_SHIFT (5U)
11727#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
11728#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
11729#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
11734#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
11735#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
11736#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
11741#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
11742#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
11743#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
11748#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
11749#define FTM_SYNCONF_SWOM_MASK (0x400U)
11750#define FTM_SYNCONF_SWOM_SHIFT (10U)
11755#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
11756#define FTM_SYNCONF_SWINVC_MASK (0x800U)
11757#define FTM_SYNCONF_SWINVC_SHIFT (11U)
11762#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
11763#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
11764#define FTM_SYNCONF_SWSOC_SHIFT (12U)
11769#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
11770#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
11771#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
11776#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
11777#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
11778#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
11783#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
11784#define FTM_SYNCONF_HWOM_MASK (0x40000U)
11785#define FTM_SYNCONF_HWOM_SHIFT (18U)
11790#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
11791#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
11792#define FTM_SYNCONF_HWINVC_SHIFT (19U)
11797#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
11798#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
11799#define FTM_SYNCONF_HWSOC_SHIFT (20U)
11804#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
11809#define FTM_INVCTRL_INV0EN_MASK (0x1U)
11810#define FTM_INVCTRL_INV0EN_SHIFT (0U)
11815#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
11816#define FTM_INVCTRL_INV1EN_MASK (0x2U)
11817#define FTM_INVCTRL_INV1EN_SHIFT (1U)
11822#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
11823#define FTM_INVCTRL_INV2EN_MASK (0x4U)
11824#define FTM_INVCTRL_INV2EN_SHIFT (2U)
11829#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
11830#define FTM_INVCTRL_INV3EN_MASK (0x8U)
11831#define FTM_INVCTRL_INV3EN_SHIFT (3U)
11836#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
11841#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
11842#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
11847#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
11848#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
11849#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
11854#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
11855#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
11856#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
11861#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
11862#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
11863#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
11868#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
11869#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
11870#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
11875#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
11876#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
11877#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
11882#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
11883#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
11884#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
11889#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
11890#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
11891#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
11896#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
11897#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
11898#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
11903#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
11904#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
11905#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
11910#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
11911#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
11912#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
11917#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
11918#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
11919#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
11924#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
11925#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
11926#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
11931#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
11932#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
11933#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
11938#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
11939#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
11940#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
11945#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
11946#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
11947#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
11952#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
11957#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
11958#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
11963#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
11964#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
11965#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
11970#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
11971#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
11972#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
11977#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
11978#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
11979#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
11984#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
11985#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
11986#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
11991#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
11992#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
11993#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
11998#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
11999#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
12000#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
12005#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
12006#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
12007#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
12012#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
12013#define FTM_PWMLOAD_LDOK_MASK (0x200U)
12014#define FTM_PWMLOAD_LDOK_SHIFT (9U)
12019#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
12025 /* end of group FTM_Register_Masks */
12026
12027
12028/* FTM - Peripheral instance base addresses */
12030#define FTM0_BASE (0x40038000u)
12032#define FTM0 ((FTM_Type *)FTM0_BASE)
12034#define FTM1_BASE (0x40039000u)
12036#define FTM1 ((FTM_Type *)FTM1_BASE)
12038#define FTM2_BASE (0x4003A000u)
12040#define FTM2 ((FTM_Type *)FTM2_BASE)
12042#define FTM3_BASE (0x400B9000u)
12044#define FTM3 ((FTM_Type *)FTM3_BASE)
12046#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
12048#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
12050#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
12051
12054 /* end of group FTM_Peripheral_Access_Layer */
12055
12056
12057/* ----------------------------------------------------------------------------
12058 -- GPIO Peripheral Access Layer
12059 ---------------------------------------------------------------------------- */
12060
12067typedef struct {
12068 __IO uint32_t PDOR;
12069 __O uint32_t PSOR;
12070 __O uint32_t PCOR;
12071 __O uint32_t PTOR;
12072 __I uint32_t PDIR;
12073 __IO uint32_t PDDR;
12074} GPIO_Type;
12075
12076/* ----------------------------------------------------------------------------
12077 -- GPIO Register Masks
12078 ---------------------------------------------------------------------------- */
12079
12087#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
12088#define GPIO_PDOR_PDO_SHIFT (0U)
12093#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
12098#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
12099#define GPIO_PSOR_PTSO_SHIFT (0U)
12104#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
12109#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
12110#define GPIO_PCOR_PTCO_SHIFT (0U)
12115#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
12120#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
12121#define GPIO_PTOR_PTTO_SHIFT (0U)
12126#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
12131#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
12132#define GPIO_PDIR_PDI_SHIFT (0U)
12137#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
12142#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
12143#define GPIO_PDDR_PDD_SHIFT (0U)
12148#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
12154 /* end of group GPIO_Register_Masks */
12155
12156
12157/* GPIO - Peripheral instance base addresses */
12159#define GPIOA_BASE (0x400FF000u)
12161#define GPIOA ((GPIO_Type *)GPIOA_BASE)
12163#define GPIOB_BASE (0x400FF040u)
12165#define GPIOB ((GPIO_Type *)GPIOB_BASE)
12167#define GPIOC_BASE (0x400FF080u)
12169#define GPIOC ((GPIO_Type *)GPIOC_BASE)
12171#define GPIOD_BASE (0x400FF0C0u)
12173#define GPIOD ((GPIO_Type *)GPIOD_BASE)
12175#define GPIOE_BASE (0x400FF100u)
12177#define GPIOE ((GPIO_Type *)GPIOE_BASE)
12179#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
12181#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
12182
12185 /* end of group GPIO_Peripheral_Access_Layer */
12186
12187
12188/* ----------------------------------------------------------------------------
12189 -- I2C Peripheral Access Layer
12190 ---------------------------------------------------------------------------- */
12191
12198typedef struct {
12199 __IO uint8_t A1;
12200 __IO uint8_t F;
12201 __IO uint8_t C1;
12202 __IO uint8_t S;
12203 __IO uint8_t D;
12204 __IO uint8_t C2;
12205 __IO uint8_t FLT;
12206 __IO uint8_t RA;
12207 __IO uint8_t SMB;
12208 __IO uint8_t A2;
12209 __IO uint8_t SLTH;
12210 __IO uint8_t SLTL;
12211} I2C_Type;
12212
12213/* ----------------------------------------------------------------------------
12214 -- I2C Register Masks
12215 ---------------------------------------------------------------------------- */
12216
12224#define I2C_A1_AD_MASK (0xFEU)
12225#define I2C_A1_AD_SHIFT (1U)
12226#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
12231#define I2C_F_ICR_MASK (0x3FU)
12232#define I2C_F_ICR_SHIFT (0U)
12233#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
12234#define I2C_F_MULT_MASK (0xC0U)
12235#define I2C_F_MULT_SHIFT (6U)
12242#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
12247#define I2C_C1_DMAEN_MASK (0x1U)
12248#define I2C_C1_DMAEN_SHIFT (0U)
12253#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
12254#define I2C_C1_WUEN_MASK (0x2U)
12255#define I2C_C1_WUEN_SHIFT (1U)
12260#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
12261#define I2C_C1_RSTA_MASK (0x4U)
12262#define I2C_C1_RSTA_SHIFT (2U)
12263#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
12264#define I2C_C1_TXAK_MASK (0x8U)
12265#define I2C_C1_TXAK_SHIFT (3U)
12270#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
12271#define I2C_C1_TX_MASK (0x10U)
12272#define I2C_C1_TX_SHIFT (4U)
12277#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
12278#define I2C_C1_MST_MASK (0x20U)
12279#define I2C_C1_MST_SHIFT (5U)
12284#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
12285#define I2C_C1_IICIE_MASK (0x40U)
12286#define I2C_C1_IICIE_SHIFT (6U)
12291#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
12292#define I2C_C1_IICEN_MASK (0x80U)
12293#define I2C_C1_IICEN_SHIFT (7U)
12298#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
12303#define I2C_S_RXAK_MASK (0x1U)
12304#define I2C_S_RXAK_SHIFT (0U)
12309#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
12310#define I2C_S_IICIF_MASK (0x2U)
12311#define I2C_S_IICIF_SHIFT (1U)
12316#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
12317#define I2C_S_SRW_MASK (0x4U)
12318#define I2C_S_SRW_SHIFT (2U)
12323#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
12324#define I2C_S_RAM_MASK (0x8U)
12325#define I2C_S_RAM_SHIFT (3U)
12330#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
12331#define I2C_S_ARBL_MASK (0x10U)
12332#define I2C_S_ARBL_SHIFT (4U)
12337#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
12338#define I2C_S_BUSY_MASK (0x20U)
12339#define I2C_S_BUSY_SHIFT (5U)
12344#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
12345#define I2C_S_IAAS_MASK (0x40U)
12346#define I2C_S_IAAS_SHIFT (6U)
12351#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
12352#define I2C_S_TCF_MASK (0x80U)
12353#define I2C_S_TCF_SHIFT (7U)
12358#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
12363#define I2C_D_DATA_MASK (0xFFU)
12364#define I2C_D_DATA_SHIFT (0U)
12365#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
12370#define I2C_C2_AD_MASK (0x7U)
12371#define I2C_C2_AD_SHIFT (0U)
12372#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
12373#define I2C_C2_RMEN_MASK (0x8U)
12374#define I2C_C2_RMEN_SHIFT (3U)
12379#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
12380#define I2C_C2_SBRC_MASK (0x10U)
12381#define I2C_C2_SBRC_SHIFT (4U)
12386#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
12387#define I2C_C2_HDRS_MASK (0x20U)
12388#define I2C_C2_HDRS_SHIFT (5U)
12393#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
12394#define I2C_C2_ADEXT_MASK (0x40U)
12395#define I2C_C2_ADEXT_SHIFT (6U)
12400#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
12401#define I2C_C2_GCAEN_MASK (0x80U)
12402#define I2C_C2_GCAEN_SHIFT (7U)
12407#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
12412#define I2C_FLT_FLT_MASK (0xFU)
12413#define I2C_FLT_FLT_SHIFT (0U)
12417#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
12418#define I2C_FLT_STARTF_MASK (0x10U)
12419#define I2C_FLT_STARTF_SHIFT (4U)
12424#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
12425#define I2C_FLT_SSIE_MASK (0x20U)
12426#define I2C_FLT_SSIE_SHIFT (5U)
12431#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
12432#define I2C_FLT_STOPF_MASK (0x40U)
12433#define I2C_FLT_STOPF_SHIFT (6U)
12438#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
12439#define I2C_FLT_SHEN_MASK (0x80U)
12440#define I2C_FLT_SHEN_SHIFT (7U)
12445#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
12450#define I2C_RA_RAD_MASK (0xFEU)
12451#define I2C_RA_RAD_SHIFT (1U)
12452#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
12457#define I2C_SMB_SHTF2IE_MASK (0x1U)
12458#define I2C_SMB_SHTF2IE_SHIFT (0U)
12463#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
12464#define I2C_SMB_SHTF2_MASK (0x2U)
12465#define I2C_SMB_SHTF2_SHIFT (1U)
12470#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
12471#define I2C_SMB_SHTF1_MASK (0x4U)
12472#define I2C_SMB_SHTF1_SHIFT (2U)
12477#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
12478#define I2C_SMB_SLTF_MASK (0x8U)
12479#define I2C_SMB_SLTF_SHIFT (3U)
12484#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
12485#define I2C_SMB_TCKSEL_MASK (0x10U)
12486#define I2C_SMB_TCKSEL_SHIFT (4U)
12491#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
12492#define I2C_SMB_SIICAEN_MASK (0x20U)
12493#define I2C_SMB_SIICAEN_SHIFT (5U)
12498#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
12499#define I2C_SMB_ALERTEN_MASK (0x40U)
12500#define I2C_SMB_ALERTEN_SHIFT (6U)
12505#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
12506#define I2C_SMB_FACK_MASK (0x80U)
12507#define I2C_SMB_FACK_SHIFT (7U)
12512#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
12517#define I2C_A2_SAD_MASK (0xFEU)
12518#define I2C_A2_SAD_SHIFT (1U)
12519#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
12524#define I2C_SLTH_SSLT_MASK (0xFFU)
12525#define I2C_SLTH_SSLT_SHIFT (0U)
12526#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
12531#define I2C_SLTL_SSLT_MASK (0xFFU)
12532#define I2C_SLTL_SSLT_SHIFT (0U)
12533#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
12539 /* end of group I2C_Register_Masks */
12540
12541
12542/* I2C - Peripheral instance base addresses */
12544#define I2C0_BASE (0x40066000u)
12546#define I2C0 ((I2C_Type *)I2C0_BASE)
12548#define I2C1_BASE (0x40067000u)
12550#define I2C1 ((I2C_Type *)I2C1_BASE)
12552#define I2C2_BASE (0x400E6000u)
12554#define I2C2 ((I2C_Type *)I2C2_BASE)
12556#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
12558#define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
12560#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
12561
12564 /* end of group I2C_Peripheral_Access_Layer */
12565
12566
12567/* ----------------------------------------------------------------------------
12568 -- I2S Peripheral Access Layer
12569 ---------------------------------------------------------------------------- */
12570
12577typedef struct {
12578 __IO uint32_t TCSR;
12579 __IO uint32_t TCR1;
12580 __IO uint32_t TCR2;
12581 __IO uint32_t TCR3;
12582 __IO uint32_t TCR4;
12583 __IO uint32_t TCR5;
12584 uint8_t RESERVED_0[8];
12585 __O uint32_t TDR[2];
12586 uint8_t RESERVED_1[24];
12587 __I uint32_t TFR[2];
12588 uint8_t RESERVED_2[24];
12589 __IO uint32_t TMR;
12590 uint8_t RESERVED_3[28];
12591 __IO uint32_t RCSR;
12592 __IO uint32_t RCR1;
12593 __IO uint32_t RCR2;
12594 __IO uint32_t RCR3;
12595 __IO uint32_t RCR4;
12596 __IO uint32_t RCR5;
12597 uint8_t RESERVED_4[8];
12598 __I uint32_t RDR[2];
12599 uint8_t RESERVED_5[24];
12600 __I uint32_t RFR[2];
12601 uint8_t RESERVED_6[24];
12602 __IO uint32_t RMR;
12603 uint8_t RESERVED_7[28];
12604 __IO uint32_t MCR;
12605 __IO uint32_t MDR;
12606} I2S_Type;
12607
12608/* ----------------------------------------------------------------------------
12609 -- I2S Register Masks
12610 ---------------------------------------------------------------------------- */
12611
12619#define I2S_TCSR_FRDE_MASK (0x1U)
12620#define I2S_TCSR_FRDE_SHIFT (0U)
12625#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
12626#define I2S_TCSR_FWDE_MASK (0x2U)
12627#define I2S_TCSR_FWDE_SHIFT (1U)
12632#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
12633#define I2S_TCSR_FRIE_MASK (0x100U)
12634#define I2S_TCSR_FRIE_SHIFT (8U)
12639#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
12640#define I2S_TCSR_FWIE_MASK (0x200U)
12641#define I2S_TCSR_FWIE_SHIFT (9U)
12646#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
12647#define I2S_TCSR_FEIE_MASK (0x400U)
12648#define I2S_TCSR_FEIE_SHIFT (10U)
12653#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
12654#define I2S_TCSR_SEIE_MASK (0x800U)
12655#define I2S_TCSR_SEIE_SHIFT (11U)
12660#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
12661#define I2S_TCSR_WSIE_MASK (0x1000U)
12662#define I2S_TCSR_WSIE_SHIFT (12U)
12667#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
12668#define I2S_TCSR_FRF_MASK (0x10000U)
12669#define I2S_TCSR_FRF_SHIFT (16U)
12674#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
12675#define I2S_TCSR_FWF_MASK (0x20000U)
12676#define I2S_TCSR_FWF_SHIFT (17U)
12681#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
12682#define I2S_TCSR_FEF_MASK (0x40000U)
12683#define I2S_TCSR_FEF_SHIFT (18U)
12688#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
12689#define I2S_TCSR_SEF_MASK (0x80000U)
12690#define I2S_TCSR_SEF_SHIFT (19U)
12695#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
12696#define I2S_TCSR_WSF_MASK (0x100000U)
12697#define I2S_TCSR_WSF_SHIFT (20U)
12702#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
12703#define I2S_TCSR_SR_MASK (0x1000000U)
12704#define I2S_TCSR_SR_SHIFT (24U)
12709#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
12710#define I2S_TCSR_FR_MASK (0x2000000U)
12711#define I2S_TCSR_FR_SHIFT (25U)
12716#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
12717#define I2S_TCSR_BCE_MASK (0x10000000U)
12718#define I2S_TCSR_BCE_SHIFT (28U)
12723#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
12724#define I2S_TCSR_DBGE_MASK (0x20000000U)
12725#define I2S_TCSR_DBGE_SHIFT (29U)
12730#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
12731#define I2S_TCSR_STOPE_MASK (0x40000000U)
12732#define I2S_TCSR_STOPE_SHIFT (30U)
12737#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
12738#define I2S_TCSR_TE_MASK (0x80000000U)
12739#define I2S_TCSR_TE_SHIFT (31U)
12744#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
12749#define I2S_TCR1_TFW_MASK (0x7U)
12750#define I2S_TCR1_TFW_SHIFT (0U)
12751#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
12756#define I2S_TCR2_DIV_MASK (0xFFU)
12757#define I2S_TCR2_DIV_SHIFT (0U)
12758#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
12759#define I2S_TCR2_BCD_MASK (0x1000000U)
12760#define I2S_TCR2_BCD_SHIFT (24U)
12765#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
12766#define I2S_TCR2_BCP_MASK (0x2000000U)
12767#define I2S_TCR2_BCP_SHIFT (25U)
12772#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
12773#define I2S_TCR2_MSEL_MASK (0xC000000U)
12774#define I2S_TCR2_MSEL_SHIFT (26U)
12781#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
12782#define I2S_TCR2_BCI_MASK (0x10000000U)
12783#define I2S_TCR2_BCI_SHIFT (28U)
12788#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
12789#define I2S_TCR2_BCS_MASK (0x20000000U)
12790#define I2S_TCR2_BCS_SHIFT (29U)
12795#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
12796#define I2S_TCR2_SYNC_MASK (0xC0000000U)
12797#define I2S_TCR2_SYNC_SHIFT (30U)
12804#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
12809#define I2S_TCR3_WDFL_MASK (0x1FU)
12810#define I2S_TCR3_WDFL_SHIFT (0U)
12811#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
12812#define I2S_TCR3_TCE_MASK (0x30000U)
12813#define I2S_TCR3_TCE_SHIFT (16U)
12818#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
12823#define I2S_TCR4_FSD_MASK (0x1U)
12824#define I2S_TCR4_FSD_SHIFT (0U)
12829#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
12830#define I2S_TCR4_FSP_MASK (0x2U)
12831#define I2S_TCR4_FSP_SHIFT (1U)
12836#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
12837#define I2S_TCR4_FSE_MASK (0x8U)
12838#define I2S_TCR4_FSE_SHIFT (3U)
12843#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
12844#define I2S_TCR4_MF_MASK (0x10U)
12845#define I2S_TCR4_MF_SHIFT (4U)
12850#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
12851#define I2S_TCR4_SYWD_MASK (0x1F00U)
12852#define I2S_TCR4_SYWD_SHIFT (8U)
12853#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
12854#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
12855#define I2S_TCR4_FRSZ_SHIFT (16U)
12856#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
12861#define I2S_TCR5_FBT_MASK (0x1F00U)
12862#define I2S_TCR5_FBT_SHIFT (8U)
12863#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
12864#define I2S_TCR5_W0W_MASK (0x1F0000U)
12865#define I2S_TCR5_W0W_SHIFT (16U)
12866#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
12867#define I2S_TCR5_WNW_MASK (0x1F000000U)
12868#define I2S_TCR5_WNW_SHIFT (24U)
12869#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
12874#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
12875#define I2S_TDR_TDR_SHIFT (0U)
12876#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
12879/* The count of I2S_TDR */
12880#define I2S_TDR_COUNT (2U)
12881
12884#define I2S_TFR_RFP_MASK (0xFU)
12885#define I2S_TFR_RFP_SHIFT (0U)
12886#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
12887#define I2S_TFR_WFP_MASK (0xF0000U)
12888#define I2S_TFR_WFP_SHIFT (16U)
12889#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
12892/* The count of I2S_TFR */
12893#define I2S_TFR_COUNT (2U)
12894
12897#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
12898#define I2S_TMR_TWM_SHIFT (0U)
12903#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
12908#define I2S_RCSR_FRDE_MASK (0x1U)
12909#define I2S_RCSR_FRDE_SHIFT (0U)
12914#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
12915#define I2S_RCSR_FWDE_MASK (0x2U)
12916#define I2S_RCSR_FWDE_SHIFT (1U)
12921#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
12922#define I2S_RCSR_FRIE_MASK (0x100U)
12923#define I2S_RCSR_FRIE_SHIFT (8U)
12928#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
12929#define I2S_RCSR_FWIE_MASK (0x200U)
12930#define I2S_RCSR_FWIE_SHIFT (9U)
12935#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
12936#define I2S_RCSR_FEIE_MASK (0x400U)
12937#define I2S_RCSR_FEIE_SHIFT (10U)
12942#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
12943#define I2S_RCSR_SEIE_MASK (0x800U)
12944#define I2S_RCSR_SEIE_SHIFT (11U)
12949#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
12950#define I2S_RCSR_WSIE_MASK (0x1000U)
12951#define I2S_RCSR_WSIE_SHIFT (12U)
12956#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
12957#define I2S_RCSR_FRF_MASK (0x10000U)
12958#define I2S_RCSR_FRF_SHIFT (16U)
12963#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
12964#define I2S_RCSR_FWF_MASK (0x20000U)
12965#define I2S_RCSR_FWF_SHIFT (17U)
12970#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
12971#define I2S_RCSR_FEF_MASK (0x40000U)
12972#define I2S_RCSR_FEF_SHIFT (18U)
12977#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
12978#define I2S_RCSR_SEF_MASK (0x80000U)
12979#define I2S_RCSR_SEF_SHIFT (19U)
12984#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
12985#define I2S_RCSR_WSF_MASK (0x100000U)
12986#define I2S_RCSR_WSF_SHIFT (20U)
12991#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
12992#define I2S_RCSR_SR_MASK (0x1000000U)
12993#define I2S_RCSR_SR_SHIFT (24U)
12998#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
12999#define I2S_RCSR_FR_MASK (0x2000000U)
13000#define I2S_RCSR_FR_SHIFT (25U)
13005#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
13006#define I2S_RCSR_BCE_MASK (0x10000000U)
13007#define I2S_RCSR_BCE_SHIFT (28U)
13012#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
13013#define I2S_RCSR_DBGE_MASK (0x20000000U)
13014#define I2S_RCSR_DBGE_SHIFT (29U)
13019#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
13020#define I2S_RCSR_STOPE_MASK (0x40000000U)
13021#define I2S_RCSR_STOPE_SHIFT (30U)
13026#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
13027#define I2S_RCSR_RE_MASK (0x80000000U)
13028#define I2S_RCSR_RE_SHIFT (31U)
13033#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
13038#define I2S_RCR1_RFW_MASK (0x7U)
13039#define I2S_RCR1_RFW_SHIFT (0U)
13040#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
13045#define I2S_RCR2_DIV_MASK (0xFFU)
13046#define I2S_RCR2_DIV_SHIFT (0U)
13047#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
13048#define I2S_RCR2_BCD_MASK (0x1000000U)
13049#define I2S_RCR2_BCD_SHIFT (24U)
13054#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
13055#define I2S_RCR2_BCP_MASK (0x2000000U)
13056#define I2S_RCR2_BCP_SHIFT (25U)
13061#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
13062#define I2S_RCR2_MSEL_MASK (0xC000000U)
13063#define I2S_RCR2_MSEL_SHIFT (26U)
13070#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
13071#define I2S_RCR2_BCI_MASK (0x10000000U)
13072#define I2S_RCR2_BCI_SHIFT (28U)
13077#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
13078#define I2S_RCR2_BCS_MASK (0x20000000U)
13079#define I2S_RCR2_BCS_SHIFT (29U)
13084#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
13085#define I2S_RCR2_SYNC_MASK (0xC0000000U)
13086#define I2S_RCR2_SYNC_SHIFT (30U)
13093#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
13098#define I2S_RCR3_WDFL_MASK (0x1FU)
13099#define I2S_RCR3_WDFL_SHIFT (0U)
13100#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
13101#define I2S_RCR3_RCE_MASK (0x30000U)
13102#define I2S_RCR3_RCE_SHIFT (16U)
13107#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
13112#define I2S_RCR4_FSD_MASK (0x1U)
13113#define I2S_RCR4_FSD_SHIFT (0U)
13118#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
13119#define I2S_RCR4_FSP_MASK (0x2U)
13120#define I2S_RCR4_FSP_SHIFT (1U)
13125#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
13126#define I2S_RCR4_FSE_MASK (0x8U)
13127#define I2S_RCR4_FSE_SHIFT (3U)
13132#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
13133#define I2S_RCR4_MF_MASK (0x10U)
13134#define I2S_RCR4_MF_SHIFT (4U)
13139#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
13140#define I2S_RCR4_SYWD_MASK (0x1F00U)
13141#define I2S_RCR4_SYWD_SHIFT (8U)
13142#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
13143#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
13144#define I2S_RCR4_FRSZ_SHIFT (16U)
13145#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
13150#define I2S_RCR5_FBT_MASK (0x1F00U)
13151#define I2S_RCR5_FBT_SHIFT (8U)
13152#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
13153#define I2S_RCR5_W0W_MASK (0x1F0000U)
13154#define I2S_RCR5_W0W_SHIFT (16U)
13155#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
13156#define I2S_RCR5_WNW_MASK (0x1F000000U)
13157#define I2S_RCR5_WNW_SHIFT (24U)
13158#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
13163#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
13164#define I2S_RDR_RDR_SHIFT (0U)
13165#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
13168/* The count of I2S_RDR */
13169#define I2S_RDR_COUNT (2U)
13170
13173#define I2S_RFR_RFP_MASK (0xFU)
13174#define I2S_RFR_RFP_SHIFT (0U)
13175#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
13176#define I2S_RFR_WFP_MASK (0xF0000U)
13177#define I2S_RFR_WFP_SHIFT (16U)
13178#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
13181/* The count of I2S_RFR */
13182#define I2S_RFR_COUNT (2U)
13183
13186#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
13187#define I2S_RMR_RWM_SHIFT (0U)
13192#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
13197#define I2S_MCR_MICS_MASK (0x3000000U)
13198#define I2S_MCR_MICS_SHIFT (24U)
13205#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
13206#define I2S_MCR_MOE_MASK (0x40000000U)
13207#define I2S_MCR_MOE_SHIFT (30U)
13212#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
13213#define I2S_MCR_DUF_MASK (0x80000000U)
13214#define I2S_MCR_DUF_SHIFT (31U)
13219#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
13224#define I2S_MDR_DIVIDE_MASK (0xFFFU)
13225#define I2S_MDR_DIVIDE_SHIFT (0U)
13226#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
13227#define I2S_MDR_FRACT_MASK (0xFF000U)
13228#define I2S_MDR_FRACT_SHIFT (12U)
13229#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
13235 /* end of group I2S_Register_Masks */
13236
13237
13238/* I2S - Peripheral instance base addresses */
13240#define I2S0_BASE (0x4002F000u)
13242#define I2S0 ((I2S_Type *)I2S0_BASE)
13244#define I2S_BASE_ADDRS { I2S0_BASE }
13246#define I2S_BASE_PTRS { I2S0 }
13248#define I2S_RX_IRQS { I2S0_Rx_IRQn }
13249#define I2S_TX_IRQS { I2S0_Tx_IRQn }
13250
13253 /* end of group I2S_Peripheral_Access_Layer */
13254
13255
13256/* ----------------------------------------------------------------------------
13257 -- LLWU Peripheral Access Layer
13258 ---------------------------------------------------------------------------- */
13259
13266typedef struct {
13267 __IO uint8_t PE1;
13268 __IO uint8_t PE2;
13269 __IO uint8_t PE3;
13270 __IO uint8_t PE4;
13271 __IO uint8_t ME;
13272 __IO uint8_t F1;
13273 __IO uint8_t F2;
13274 __I uint8_t F3;
13275 __IO uint8_t FILT1;
13276 __IO uint8_t FILT2;
13277 __IO uint8_t RST;
13278} LLWU_Type;
13279
13280/* ----------------------------------------------------------------------------
13281 -- LLWU Register Masks
13282 ---------------------------------------------------------------------------- */
13283
13291#define LLWU_PE1_WUPE0_MASK (0x3U)
13292#define LLWU_PE1_WUPE0_SHIFT (0U)
13299#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
13300#define LLWU_PE1_WUPE1_MASK (0xCU)
13301#define LLWU_PE1_WUPE1_SHIFT (2U)
13308#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
13309#define LLWU_PE1_WUPE2_MASK (0x30U)
13310#define LLWU_PE1_WUPE2_SHIFT (4U)
13317#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
13318#define LLWU_PE1_WUPE3_MASK (0xC0U)
13319#define LLWU_PE1_WUPE3_SHIFT (6U)
13326#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
13331#define LLWU_PE2_WUPE4_MASK (0x3U)
13332#define LLWU_PE2_WUPE4_SHIFT (0U)
13339#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
13340#define LLWU_PE2_WUPE5_MASK (0xCU)
13341#define LLWU_PE2_WUPE5_SHIFT (2U)
13348#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
13349#define LLWU_PE2_WUPE6_MASK (0x30U)
13350#define LLWU_PE2_WUPE6_SHIFT (4U)
13357#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
13358#define LLWU_PE2_WUPE7_MASK (0xC0U)
13359#define LLWU_PE2_WUPE7_SHIFT (6U)
13366#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
13371#define LLWU_PE3_WUPE8_MASK (0x3U)
13372#define LLWU_PE3_WUPE8_SHIFT (0U)
13379#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
13380#define LLWU_PE3_WUPE9_MASK (0xCU)
13381#define LLWU_PE3_WUPE9_SHIFT (2U)
13388#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
13389#define LLWU_PE3_WUPE10_MASK (0x30U)
13390#define LLWU_PE3_WUPE10_SHIFT (4U)
13397#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
13398#define LLWU_PE3_WUPE11_MASK (0xC0U)
13399#define LLWU_PE3_WUPE11_SHIFT (6U)
13406#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
13411#define LLWU_PE4_WUPE12_MASK (0x3U)
13412#define LLWU_PE4_WUPE12_SHIFT (0U)
13419#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
13420#define LLWU_PE4_WUPE13_MASK (0xCU)
13421#define LLWU_PE4_WUPE13_SHIFT (2U)
13428#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
13429#define LLWU_PE4_WUPE14_MASK (0x30U)
13430#define LLWU_PE4_WUPE14_SHIFT (4U)
13437#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
13438#define LLWU_PE4_WUPE15_MASK (0xC0U)
13439#define LLWU_PE4_WUPE15_SHIFT (6U)
13446#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
13451#define LLWU_ME_WUME0_MASK (0x1U)
13452#define LLWU_ME_WUME0_SHIFT (0U)
13457#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
13458#define LLWU_ME_WUME1_MASK (0x2U)
13459#define LLWU_ME_WUME1_SHIFT (1U)
13464#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
13465#define LLWU_ME_WUME2_MASK (0x4U)
13466#define LLWU_ME_WUME2_SHIFT (2U)
13471#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
13472#define LLWU_ME_WUME3_MASK (0x8U)
13473#define LLWU_ME_WUME3_SHIFT (3U)
13478#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
13479#define LLWU_ME_WUME4_MASK (0x10U)
13480#define LLWU_ME_WUME4_SHIFT (4U)
13485#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
13486#define LLWU_ME_WUME5_MASK (0x20U)
13487#define LLWU_ME_WUME5_SHIFT (5U)
13492#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
13493#define LLWU_ME_WUME6_MASK (0x40U)
13494#define LLWU_ME_WUME6_SHIFT (6U)
13499#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
13500#define LLWU_ME_WUME7_MASK (0x80U)
13501#define LLWU_ME_WUME7_SHIFT (7U)
13506#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
13511#define LLWU_F1_WUF0_MASK (0x1U)
13512#define LLWU_F1_WUF0_SHIFT (0U)
13517#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
13518#define LLWU_F1_WUF1_MASK (0x2U)
13519#define LLWU_F1_WUF1_SHIFT (1U)
13524#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
13525#define LLWU_F1_WUF2_MASK (0x4U)
13526#define LLWU_F1_WUF2_SHIFT (2U)
13531#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
13532#define LLWU_F1_WUF3_MASK (0x8U)
13533#define LLWU_F1_WUF3_SHIFT (3U)
13538#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
13539#define LLWU_F1_WUF4_MASK (0x10U)
13540#define LLWU_F1_WUF4_SHIFT (4U)
13545#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
13546#define LLWU_F1_WUF5_MASK (0x20U)
13547#define LLWU_F1_WUF5_SHIFT (5U)
13552#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
13553#define LLWU_F1_WUF6_MASK (0x40U)
13554#define LLWU_F1_WUF6_SHIFT (6U)
13559#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
13560#define LLWU_F1_WUF7_MASK (0x80U)
13561#define LLWU_F1_WUF7_SHIFT (7U)
13566#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
13571#define LLWU_F2_WUF8_MASK (0x1U)
13572#define LLWU_F2_WUF8_SHIFT (0U)
13577#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
13578#define LLWU_F2_WUF9_MASK (0x2U)
13579#define LLWU_F2_WUF9_SHIFT (1U)
13584#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
13585#define LLWU_F2_WUF10_MASK (0x4U)
13586#define LLWU_F2_WUF10_SHIFT (2U)
13591#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
13592#define LLWU_F2_WUF11_MASK (0x8U)
13593#define LLWU_F2_WUF11_SHIFT (3U)
13598#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
13599#define LLWU_F2_WUF12_MASK (0x10U)
13600#define LLWU_F2_WUF12_SHIFT (4U)
13605#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
13606#define LLWU_F2_WUF13_MASK (0x20U)
13607#define LLWU_F2_WUF13_SHIFT (5U)
13612#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
13613#define LLWU_F2_WUF14_MASK (0x40U)
13614#define LLWU_F2_WUF14_SHIFT (6U)
13619#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
13620#define LLWU_F2_WUF15_MASK (0x80U)
13621#define LLWU_F2_WUF15_SHIFT (7U)
13626#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
13631#define LLWU_F3_MWUF0_MASK (0x1U)
13632#define LLWU_F3_MWUF0_SHIFT (0U)
13637#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
13638#define LLWU_F3_MWUF1_MASK (0x2U)
13639#define LLWU_F3_MWUF1_SHIFT (1U)
13644#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
13645#define LLWU_F3_MWUF2_MASK (0x4U)
13646#define LLWU_F3_MWUF2_SHIFT (2U)
13651#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
13652#define LLWU_F3_MWUF3_MASK (0x8U)
13653#define LLWU_F3_MWUF3_SHIFT (3U)
13658#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
13659#define LLWU_F3_MWUF4_MASK (0x10U)
13660#define LLWU_F3_MWUF4_SHIFT (4U)
13665#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
13666#define LLWU_F3_MWUF5_MASK (0x20U)
13667#define LLWU_F3_MWUF5_SHIFT (5U)
13672#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
13673#define LLWU_F3_MWUF6_MASK (0x40U)
13674#define LLWU_F3_MWUF6_SHIFT (6U)
13679#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
13680#define LLWU_F3_MWUF7_MASK (0x80U)
13681#define LLWU_F3_MWUF7_SHIFT (7U)
13686#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
13691#define LLWU_FILT1_FILTSEL_MASK (0xFU)
13692#define LLWU_FILT1_FILTSEL_SHIFT (0U)
13697#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
13698#define LLWU_FILT1_FILTE_MASK (0x60U)
13699#define LLWU_FILT1_FILTE_SHIFT (5U)
13706#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
13707#define LLWU_FILT1_FILTF_MASK (0x80U)
13708#define LLWU_FILT1_FILTF_SHIFT (7U)
13713#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
13718#define LLWU_FILT2_FILTSEL_MASK (0xFU)
13719#define LLWU_FILT2_FILTSEL_SHIFT (0U)
13724#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
13725#define LLWU_FILT2_FILTE_MASK (0x60U)
13726#define LLWU_FILT2_FILTE_SHIFT (5U)
13733#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
13734#define LLWU_FILT2_FILTF_MASK (0x80U)
13735#define LLWU_FILT2_FILTF_SHIFT (7U)
13740#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
13745#define LLWU_RST_RSTFILT_MASK (0x1U)
13746#define LLWU_RST_RSTFILT_SHIFT (0U)
13751#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
13752#define LLWU_RST_LLRSTE_MASK (0x2U)
13753#define LLWU_RST_LLRSTE_SHIFT (1U)
13758#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
13764 /* end of group LLWU_Register_Masks */
13765
13766
13767/* LLWU - Peripheral instance base addresses */
13769#define LLWU_BASE (0x4007C000u)
13771#define LLWU ((LLWU_Type *)LLWU_BASE)
13773#define LLWU_BASE_ADDRS { LLWU_BASE }
13775#define LLWU_BASE_PTRS { LLWU }
13777#define LLWU_IRQS { LLWU_IRQn }
13778
13781 /* end of group LLWU_Peripheral_Access_Layer */
13782
13783
13784/* ----------------------------------------------------------------------------
13785 -- LPTMR Peripheral Access Layer
13786 ---------------------------------------------------------------------------- */
13787
13794typedef struct {
13795 __IO uint32_t CSR;
13796 __IO uint32_t PSR;
13797 __IO uint32_t CMR;
13798 __IO uint32_t CNR;
13799} LPTMR_Type;
13800
13801/* ----------------------------------------------------------------------------
13802 -- LPTMR Register Masks
13803 ---------------------------------------------------------------------------- */
13804
13812#define LPTMR_CSR_TEN_MASK (0x1U)
13813#define LPTMR_CSR_TEN_SHIFT (0U)
13818#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
13819#define LPTMR_CSR_TMS_MASK (0x2U)
13820#define LPTMR_CSR_TMS_SHIFT (1U)
13825#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
13826#define LPTMR_CSR_TFC_MASK (0x4U)
13827#define LPTMR_CSR_TFC_SHIFT (2U)
13832#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
13833#define LPTMR_CSR_TPP_MASK (0x8U)
13834#define LPTMR_CSR_TPP_SHIFT (3U)
13839#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
13840#define LPTMR_CSR_TPS_MASK (0x30U)
13841#define LPTMR_CSR_TPS_SHIFT (4U)
13848#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
13849#define LPTMR_CSR_TIE_MASK (0x40U)
13850#define LPTMR_CSR_TIE_SHIFT (6U)
13855#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
13856#define LPTMR_CSR_TCF_MASK (0x80U)
13857#define LPTMR_CSR_TCF_SHIFT (7U)
13862#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
13867#define LPTMR_PSR_PCS_MASK (0x3U)
13868#define LPTMR_PSR_PCS_SHIFT (0U)
13875#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
13876#define LPTMR_PSR_PBYP_MASK (0x4U)
13877#define LPTMR_PSR_PBYP_SHIFT (2U)
13882#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
13883#define LPTMR_PSR_PRESCALE_MASK (0x78U)
13884#define LPTMR_PSR_PRESCALE_SHIFT (3U)
13903#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
13908#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
13909#define LPTMR_CMR_COMPARE_SHIFT (0U)
13910#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
13915#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
13916#define LPTMR_CNR_COUNTER_SHIFT (0U)
13917#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
13923 /* end of group LPTMR_Register_Masks */
13924
13925
13926/* LPTMR - Peripheral instance base addresses */
13928#define LPTMR0_BASE (0x40040000u)
13930#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
13932#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
13934#define LPTMR_BASE_PTRS { LPTMR0 }
13936#define LPTMR_IRQS { LPTMR0_IRQn }
13937
13940 /* end of group LPTMR_Peripheral_Access_Layer */
13941
13942
13943/* ----------------------------------------------------------------------------
13944 -- MCG Peripheral Access Layer
13945 ---------------------------------------------------------------------------- */
13946
13953typedef struct {
13954 __IO uint8_t C1;
13955 __IO uint8_t C2;
13956 __IO uint8_t C3;
13957 __IO uint8_t C4;
13958 __IO uint8_t C5;
13959 __IO uint8_t C6;
13960 __IO uint8_t S;
13961 uint8_t RESERVED_0[1];
13962 __IO uint8_t SC;
13963 uint8_t RESERVED_1[1];
13964 __IO uint8_t ATCVH;
13965 __IO uint8_t ATCVL;
13966 __IO uint8_t C7;
13967 __IO uint8_t C8;
13968} MCG_Type;
13969
13970/* ----------------------------------------------------------------------------
13971 -- MCG Register Masks
13972 ---------------------------------------------------------------------------- */
13973
13981#define MCG_C1_IREFSTEN_MASK (0x1U)
13982#define MCG_C1_IREFSTEN_SHIFT (0U)
13987#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
13988#define MCG_C1_IRCLKEN_MASK (0x2U)
13989#define MCG_C1_IRCLKEN_SHIFT (1U)
13994#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
13995#define MCG_C1_IREFS_MASK (0x4U)
13996#define MCG_C1_IREFS_SHIFT (2U)
14001#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
14002#define MCG_C1_FRDIV_MASK (0x38U)
14003#define MCG_C1_FRDIV_SHIFT (3U)
14014#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
14015#define MCG_C1_CLKS_MASK (0xC0U)
14016#define MCG_C1_CLKS_SHIFT (6U)
14023#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
14028#define MCG_C2_IRCS_MASK (0x1U)
14029#define MCG_C2_IRCS_SHIFT (0U)
14034#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
14035#define MCG_C2_LP_MASK (0x2U)
14036#define MCG_C2_LP_SHIFT (1U)
14041#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
14042#define MCG_C2_EREFS_MASK (0x4U)
14043#define MCG_C2_EREFS_SHIFT (2U)
14048#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
14049#define MCG_C2_HGO_MASK (0x8U)
14050#define MCG_C2_HGO_SHIFT (3U)
14055#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
14056#define MCG_C2_RANGE_MASK (0x30U)
14057#define MCG_C2_RANGE_SHIFT (4U)
14063#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
14064#define MCG_C2_FCFTRIM_MASK (0x40U)
14065#define MCG_C2_FCFTRIM_SHIFT (6U)
14066#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
14067#define MCG_C2_LOCRE0_MASK (0x80U)
14068#define MCG_C2_LOCRE0_SHIFT (7U)
14073#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
14078#define MCG_C3_SCTRIM_MASK (0xFFU)
14079#define MCG_C3_SCTRIM_SHIFT (0U)
14080#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
14085#define MCG_C4_SCFTRIM_MASK (0x1U)
14086#define MCG_C4_SCFTRIM_SHIFT (0U)
14087#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
14088#define MCG_C4_FCTRIM_MASK (0x1EU)
14089#define MCG_C4_FCTRIM_SHIFT (1U)
14090#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
14091#define MCG_C4_DRST_DRS_MASK (0x60U)
14092#define MCG_C4_DRST_DRS_SHIFT (5U)
14099#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
14100#define MCG_C4_DMX32_MASK (0x80U)
14101#define MCG_C4_DMX32_SHIFT (7U)
14106#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
14111#define MCG_C5_PRDIV0_MASK (0x1FU)
14112#define MCG_C5_PRDIV0_SHIFT (0U)
14147#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
14148#define MCG_C5_PLLSTEN0_MASK (0x20U)
14149#define MCG_C5_PLLSTEN0_SHIFT (5U)
14154#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
14155#define MCG_C5_PLLCLKEN0_MASK (0x40U)
14156#define MCG_C5_PLLCLKEN0_SHIFT (6U)
14161#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
14166#define MCG_C6_VDIV0_MASK (0x1FU)
14167#define MCG_C6_VDIV0_SHIFT (0U)
14202#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
14203#define MCG_C6_CME0_MASK (0x20U)
14204#define MCG_C6_CME0_SHIFT (5U)
14209#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
14210#define MCG_C6_PLLS_MASK (0x40U)
14211#define MCG_C6_PLLS_SHIFT (6U)
14216#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
14217#define MCG_C6_LOLIE0_MASK (0x80U)
14218#define MCG_C6_LOLIE0_SHIFT (7U)
14223#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
14228#define MCG_S_IRCST_MASK (0x1U)
14229#define MCG_S_IRCST_SHIFT (0U)
14234#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
14235#define MCG_S_OSCINIT0_MASK (0x2U)
14236#define MCG_S_OSCINIT0_SHIFT (1U)
14237#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
14238#define MCG_S_CLKST_MASK (0xCU)
14239#define MCG_S_CLKST_SHIFT (2U)
14246#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
14247#define MCG_S_IREFST_MASK (0x10U)
14248#define MCG_S_IREFST_SHIFT (4U)
14253#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
14254#define MCG_S_PLLST_MASK (0x20U)
14255#define MCG_S_PLLST_SHIFT (5U)
14260#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
14261#define MCG_S_LOCK0_MASK (0x40U)
14262#define MCG_S_LOCK0_SHIFT (6U)
14267#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
14268#define MCG_S_LOLS0_MASK (0x80U)
14269#define MCG_S_LOLS0_SHIFT (7U)
14274#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
14279#define MCG_SC_LOCS0_MASK (0x1U)
14280#define MCG_SC_LOCS0_SHIFT (0U)
14285#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
14286#define MCG_SC_FCRDIV_MASK (0xEU)
14287#define MCG_SC_FCRDIV_SHIFT (1U)
14298#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
14299#define MCG_SC_FLTPRSRV_MASK (0x10U)
14300#define MCG_SC_FLTPRSRV_SHIFT (4U)
14305#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
14306#define MCG_SC_ATMF_MASK (0x20U)
14307#define MCG_SC_ATMF_SHIFT (5U)
14312#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
14313#define MCG_SC_ATMS_MASK (0x40U)
14314#define MCG_SC_ATMS_SHIFT (6U)
14319#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
14320#define MCG_SC_ATME_MASK (0x80U)
14321#define MCG_SC_ATME_SHIFT (7U)
14326#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
14331#define MCG_ATCVH_ATCVH_MASK (0xFFU)
14332#define MCG_ATCVH_ATCVH_SHIFT (0U)
14333#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
14338#define MCG_ATCVL_ATCVL_MASK (0xFFU)
14339#define MCG_ATCVL_ATCVL_SHIFT (0U)
14340#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
14345#define MCG_C7_OSCSEL_MASK (0x3U)
14346#define MCG_C7_OSCSEL_SHIFT (0U)
14353#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
14358#define MCG_C8_LOCS1_MASK (0x1U)
14359#define MCG_C8_LOCS1_SHIFT (0U)
14364#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
14365#define MCG_C8_CME1_MASK (0x20U)
14366#define MCG_C8_CME1_SHIFT (5U)
14371#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
14372#define MCG_C8_LOLRE_MASK (0x40U)
14373#define MCG_C8_LOLRE_SHIFT (6U)
14378#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
14379#define MCG_C8_LOCRE1_MASK (0x80U)
14380#define MCG_C8_LOCRE1_SHIFT (7U)
14385#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
14391 /* end of group MCG_Register_Masks */
14392
14393
14394/* MCG - Peripheral instance base addresses */
14396#define MCG_BASE (0x40064000u)
14398#define MCG ((MCG_Type *)MCG_BASE)
14400#define MCG_BASE_ADDRS { MCG_BASE }
14402#define MCG_BASE_PTRS { MCG }
14403
14406 /* end of group MCG_Peripheral_Access_Layer */
14407
14408
14409/* ----------------------------------------------------------------------------
14410 -- MCM Peripheral Access Layer
14411 ---------------------------------------------------------------------------- */
14412
14419typedef struct {
14420 uint8_t RESERVED_0[8];
14421 __I uint16_t PLASC;
14422 __I uint16_t PLAMC;
14423 __IO uint32_t CR;
14424 __IO uint32_t ISCR;
14425 __IO uint32_t ETBCC;
14426 __IO uint32_t ETBRL;
14427 __I uint32_t ETBCNT;
14428 uint8_t RESERVED_1[16];
14429 __IO uint32_t PID;
14430} MCM_Type;
14431
14432/* ----------------------------------------------------------------------------
14433 -- MCM Register Masks
14434 ---------------------------------------------------------------------------- */
14435
14443#define MCM_PLASC_ASC_MASK (0xFFU)
14444#define MCM_PLASC_ASC_SHIFT (0U)
14449#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
14454#define MCM_PLAMC_AMC_MASK (0xFFU)
14455#define MCM_PLAMC_AMC_SHIFT (0U)
14460#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
14465#define MCM_CR_SRAMUAP_MASK (0x3000000U)
14466#define MCM_CR_SRAMUAP_SHIFT (24U)
14473#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
14474#define MCM_CR_SRAMUWP_MASK (0x4000000U)
14475#define MCM_CR_SRAMUWP_SHIFT (26U)
14476#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
14477#define MCM_CR_SRAMLAP_MASK (0x30000000U)
14478#define MCM_CR_SRAMLAP_SHIFT (28U)
14485#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
14486#define MCM_CR_SRAMLWP_MASK (0x40000000U)
14487#define MCM_CR_SRAMLWP_SHIFT (30U)
14488#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
14493#define MCM_ISCR_IRQ_MASK (0x2U)
14494#define MCM_ISCR_IRQ_SHIFT (1U)
14499#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
14500#define MCM_ISCR_NMI_MASK (0x4U)
14501#define MCM_ISCR_NMI_SHIFT (2U)
14506#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
14507#define MCM_ISCR_DHREQ_MASK (0x8U)
14508#define MCM_ISCR_DHREQ_SHIFT (3U)
14513#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
14514#define MCM_ISCR_FIOC_MASK (0x100U)
14515#define MCM_ISCR_FIOC_SHIFT (8U)
14520#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
14521#define MCM_ISCR_FDZC_MASK (0x200U)
14522#define MCM_ISCR_FDZC_SHIFT (9U)
14527#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
14528#define MCM_ISCR_FOFC_MASK (0x400U)
14529#define MCM_ISCR_FOFC_SHIFT (10U)
14534#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
14535#define MCM_ISCR_FUFC_MASK (0x800U)
14536#define MCM_ISCR_FUFC_SHIFT (11U)
14541#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
14542#define MCM_ISCR_FIXC_MASK (0x1000U)
14543#define MCM_ISCR_FIXC_SHIFT (12U)
14548#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
14549#define MCM_ISCR_FIDC_MASK (0x8000U)
14550#define MCM_ISCR_FIDC_SHIFT (15U)
14555#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
14556#define MCM_ISCR_FIOCE_MASK (0x1000000U)
14557#define MCM_ISCR_FIOCE_SHIFT (24U)
14562#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
14563#define MCM_ISCR_FDZCE_MASK (0x2000000U)
14564#define MCM_ISCR_FDZCE_SHIFT (25U)
14569#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
14570#define MCM_ISCR_FOFCE_MASK (0x4000000U)
14571#define MCM_ISCR_FOFCE_SHIFT (26U)
14576#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
14577#define MCM_ISCR_FUFCE_MASK (0x8000000U)
14578#define MCM_ISCR_FUFCE_SHIFT (27U)
14583#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
14584#define MCM_ISCR_FIXCE_MASK (0x10000000U)
14585#define MCM_ISCR_FIXCE_SHIFT (28U)
14590#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
14591#define MCM_ISCR_FIDCE_MASK (0x80000000U)
14592#define MCM_ISCR_FIDCE_SHIFT (31U)
14597#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
14602#define MCM_ETBCC_CNTEN_MASK (0x1U)
14603#define MCM_ETBCC_CNTEN_SHIFT (0U)
14608#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
14609#define MCM_ETBCC_RSPT_MASK (0x6U)
14610#define MCM_ETBCC_RSPT_SHIFT (1U)
14617#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
14618#define MCM_ETBCC_RLRQ_MASK (0x8U)
14619#define MCM_ETBCC_RLRQ_SHIFT (3U)
14624#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
14625#define MCM_ETBCC_ETDIS_MASK (0x10U)
14626#define MCM_ETBCC_ETDIS_SHIFT (4U)
14631#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
14632#define MCM_ETBCC_ITDIS_MASK (0x20U)
14633#define MCM_ETBCC_ITDIS_SHIFT (5U)
14638#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
14643#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
14644#define MCM_ETBRL_RELOAD_SHIFT (0U)
14645#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
14650#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
14651#define MCM_ETBCNT_COUNTER_SHIFT (0U)
14652#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
14657#define MCM_PID_PID_MASK (0xFFU)
14658#define MCM_PID_PID_SHIFT (0U)
14659#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
14665 /* end of group MCM_Register_Masks */
14666
14667
14668/* MCM - Peripheral instance base addresses */
14670#define MCM_BASE (0xE0080000u)
14672#define MCM ((MCM_Type *)MCM_BASE)
14674#define MCM_BASE_ADDRS { MCM_BASE }
14676#define MCM_BASE_PTRS { MCM }
14678#define MCM_IRQS { MCM_IRQn }
14679
14682 /* end of group MCM_Peripheral_Access_Layer */
14683
14684
14685/* ----------------------------------------------------------------------------
14686 -- NV Peripheral Access Layer
14687 ---------------------------------------------------------------------------- */
14688
14695typedef struct {
14696 __I uint8_t BACKKEY3;
14697 __I uint8_t BACKKEY2;
14698 __I uint8_t BACKKEY1;
14699 __I uint8_t BACKKEY0;
14700 __I uint8_t BACKKEY7;
14701 __I uint8_t BACKKEY6;
14702 __I uint8_t BACKKEY5;
14703 __I uint8_t BACKKEY4;
14704 __I uint8_t FPROT3;
14705 __I uint8_t FPROT2;
14706 __I uint8_t FPROT1;
14707 __I uint8_t FPROT0;
14708 __I uint8_t FSEC;
14709 __I uint8_t FOPT;
14710 __I uint8_t FEPROT;
14711 __I uint8_t FDPROT;
14712} NV_Type;
14713
14714/* ----------------------------------------------------------------------------
14715 -- NV Register Masks
14716 ---------------------------------------------------------------------------- */
14717
14725#define NV_BACKKEY3_KEY_MASK (0xFFU)
14726#define NV_BACKKEY3_KEY_SHIFT (0U)
14727#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
14732#define NV_BACKKEY2_KEY_MASK (0xFFU)
14733#define NV_BACKKEY2_KEY_SHIFT (0U)
14734#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
14739#define NV_BACKKEY1_KEY_MASK (0xFFU)
14740#define NV_BACKKEY1_KEY_SHIFT (0U)
14741#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
14746#define NV_BACKKEY0_KEY_MASK (0xFFU)
14747#define NV_BACKKEY0_KEY_SHIFT (0U)
14748#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
14753#define NV_BACKKEY7_KEY_MASK (0xFFU)
14754#define NV_BACKKEY7_KEY_SHIFT (0U)
14755#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
14760#define NV_BACKKEY6_KEY_MASK (0xFFU)
14761#define NV_BACKKEY6_KEY_SHIFT (0U)
14762#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
14767#define NV_BACKKEY5_KEY_MASK (0xFFU)
14768#define NV_BACKKEY5_KEY_SHIFT (0U)
14769#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
14774#define NV_BACKKEY4_KEY_MASK (0xFFU)
14775#define NV_BACKKEY4_KEY_SHIFT (0U)
14776#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
14781#define NV_FPROT3_PROT_MASK (0xFFU)
14782#define NV_FPROT3_PROT_SHIFT (0U)
14783#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
14788#define NV_FPROT2_PROT_MASK (0xFFU)
14789#define NV_FPROT2_PROT_SHIFT (0U)
14790#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
14795#define NV_FPROT1_PROT_MASK (0xFFU)
14796#define NV_FPROT1_PROT_SHIFT (0U)
14797#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
14802#define NV_FPROT0_PROT_MASK (0xFFU)
14803#define NV_FPROT0_PROT_SHIFT (0U)
14804#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
14809#define NV_FSEC_SEC_MASK (0x3U)
14810#define NV_FSEC_SEC_SHIFT (0U)
14815#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
14816#define NV_FSEC_FSLACC_MASK (0xCU)
14817#define NV_FSEC_FSLACC_SHIFT (2U)
14822#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
14823#define NV_FSEC_MEEN_MASK (0x30U)
14824#define NV_FSEC_MEEN_SHIFT (4U)
14829#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
14830#define NV_FSEC_KEYEN_MASK (0xC0U)
14831#define NV_FSEC_KEYEN_SHIFT (6U)
14836#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
14841#define NV_FOPT_LPBOOT_MASK (0x1U)
14842#define NV_FOPT_LPBOOT_SHIFT (0U)
14847#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
14848#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
14849#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
14854#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
14859#define NV_FEPROT_EPROT_MASK (0xFFU)
14860#define NV_FEPROT_EPROT_SHIFT (0U)
14861#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
14866#define NV_FDPROT_DPROT_MASK (0xFFU)
14867#define NV_FDPROT_DPROT_SHIFT (0U)
14868#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
14874 /* end of group NV_Register_Masks */
14875
14876
14877/* NV - Peripheral instance base addresses */
14879#define FTFE_FlashConfig_BASE (0x400u)
14881#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
14883#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
14885#define NV_BASE_PTRS { FTFE_FlashConfig }
14886
14889 /* end of group NV_Peripheral_Access_Layer */
14890
14891
14892/* ----------------------------------------------------------------------------
14893 -- OSC Peripheral Access Layer
14894 ---------------------------------------------------------------------------- */
14895
14902typedef struct {
14903 __IO uint8_t CR;
14904} OSC_Type;
14905
14906/* ----------------------------------------------------------------------------
14907 -- OSC Register Masks
14908 ---------------------------------------------------------------------------- */
14909
14917#define OSC_CR_SC16P_MASK (0x1U)
14918#define OSC_CR_SC16P_SHIFT (0U)
14923#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
14924#define OSC_CR_SC8P_MASK (0x2U)
14925#define OSC_CR_SC8P_SHIFT (1U)
14930#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
14931#define OSC_CR_SC4P_MASK (0x4U)
14932#define OSC_CR_SC4P_SHIFT (2U)
14937#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
14938#define OSC_CR_SC2P_MASK (0x8U)
14939#define OSC_CR_SC2P_SHIFT (3U)
14944#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
14945#define OSC_CR_EREFSTEN_MASK (0x20U)
14946#define OSC_CR_EREFSTEN_SHIFT (5U)
14951#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
14952#define OSC_CR_ERCLKEN_MASK (0x80U)
14953#define OSC_CR_ERCLKEN_SHIFT (7U)
14958#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
14964 /* end of group OSC_Register_Masks */
14965
14966
14967/* OSC - Peripheral instance base addresses */
14969#define OSC_BASE (0x40065000u)
14971#define OSC ((OSC_Type *)OSC_BASE)
14973#define OSC_BASE_ADDRS { OSC_BASE }
14975#define OSC_BASE_PTRS { OSC }
14976
14979 /* end of group OSC_Peripheral_Access_Layer */
14980
14981
14982/* ----------------------------------------------------------------------------
14983 -- PDB Peripheral Access Layer
14984 ---------------------------------------------------------------------------- */
14985
14992typedef struct {
14993 __IO uint32_t SC;
14994 __IO uint32_t MOD;
14995 __I uint32_t CNT;
14996 __IO uint32_t IDLY;
14997 struct { /* offset: 0x10, array step: 0x28 */
14998 __IO uint32_t C1;
14999 __IO uint32_t S;
15000 __IO uint32_t DLY[2];
15001 uint8_t RESERVED_0[24];
15002 } CH[2];
15003 uint8_t RESERVED_0[240];
15004 struct { /* offset: 0x150, array step: 0x8 */
15005 __IO uint32_t INTC;
15006 __IO uint32_t INT;
15007 } DAC[2];
15008 uint8_t RESERVED_1[48];
15009 __IO uint32_t POEN;
15010 __IO uint32_t PODLY[3];
15011} PDB_Type;
15012
15013/* ----------------------------------------------------------------------------
15014 -- PDB Register Masks
15015 ---------------------------------------------------------------------------- */
15016
15024#define PDB_SC_LDOK_MASK (0x1U)
15025#define PDB_SC_LDOK_SHIFT (0U)
15026#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
15027#define PDB_SC_CONT_MASK (0x2U)
15028#define PDB_SC_CONT_SHIFT (1U)
15033#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
15034#define PDB_SC_MULT_MASK (0xCU)
15035#define PDB_SC_MULT_SHIFT (2U)
15042#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
15043#define PDB_SC_PDBIE_MASK (0x20U)
15044#define PDB_SC_PDBIE_SHIFT (5U)
15049#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
15050#define PDB_SC_PDBIF_MASK (0x40U)
15051#define PDB_SC_PDBIF_SHIFT (6U)
15052#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
15053#define PDB_SC_PDBEN_MASK (0x80U)
15054#define PDB_SC_PDBEN_SHIFT (7U)
15059#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
15060#define PDB_SC_TRGSEL_MASK (0xF00U)
15061#define PDB_SC_TRGSEL_SHIFT (8U)
15080#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
15081#define PDB_SC_PRESCALER_MASK (0x7000U)
15082#define PDB_SC_PRESCALER_SHIFT (12U)
15093#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
15094#define PDB_SC_DMAEN_MASK (0x8000U)
15095#define PDB_SC_DMAEN_SHIFT (15U)
15100#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
15101#define PDB_SC_SWTRIG_MASK (0x10000U)
15102#define PDB_SC_SWTRIG_SHIFT (16U)
15103#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
15104#define PDB_SC_PDBEIE_MASK (0x20000U)
15105#define PDB_SC_PDBEIE_SHIFT (17U)
15110#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
15111#define PDB_SC_LDMOD_MASK (0xC0000U)
15112#define PDB_SC_LDMOD_SHIFT (18U)
15119#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
15124#define PDB_MOD_MOD_MASK (0xFFFFU)
15125#define PDB_MOD_MOD_SHIFT (0U)
15126#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
15131#define PDB_CNT_CNT_MASK (0xFFFFU)
15132#define PDB_CNT_CNT_SHIFT (0U)
15133#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
15138#define PDB_IDLY_IDLY_MASK (0xFFFFU)
15139#define PDB_IDLY_IDLY_SHIFT (0U)
15140#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
15145#define PDB_C1_EN_MASK (0xFFU)
15146#define PDB_C1_EN_SHIFT (0U)
15151#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
15152#define PDB_C1_TOS_MASK (0xFF00U)
15153#define PDB_C1_TOS_SHIFT (8U)
15158#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
15159#define PDB_C1_BB_MASK (0xFF0000U)
15160#define PDB_C1_BB_SHIFT (16U)
15165#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
15168/* The count of PDB_C1 */
15169#define PDB_C1_COUNT (2U)
15170
15173#define PDB_S_ERR_MASK (0xFFU)
15174#define PDB_S_ERR_SHIFT (0U)
15179#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
15180#define PDB_S_CF_MASK (0xFF0000U)
15181#define PDB_S_CF_SHIFT (16U)
15182#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
15185/* The count of PDB_S */
15186#define PDB_S_COUNT (2U)
15187
15190#define PDB_DLY_DLY_MASK (0xFFFFU)
15191#define PDB_DLY_DLY_SHIFT (0U)
15192#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
15195/* The count of PDB_DLY */
15196#define PDB_DLY_COUNT (2U)
15197
15198/* The count of PDB_DLY */
15199#define PDB_DLY_COUNT2 (2U)
15200
15203#define PDB_INTC_TOE_MASK (0x1U)
15204#define PDB_INTC_TOE_SHIFT (0U)
15209#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
15210#define PDB_INTC_EXT_MASK (0x2U)
15211#define PDB_INTC_EXT_SHIFT (1U)
15216#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
15219/* The count of PDB_INTC */
15220#define PDB_INTC_COUNT (2U)
15221
15224#define PDB_INT_INT_MASK (0xFFFFU)
15225#define PDB_INT_INT_SHIFT (0U)
15226#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
15229/* The count of PDB_INT */
15230#define PDB_INT_COUNT (2U)
15231
15234#define PDB_POEN_POEN_MASK (0xFFU)
15235#define PDB_POEN_POEN_SHIFT (0U)
15240#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
15245#define PDB_PODLY_DLY2_MASK (0xFFFFU)
15246#define PDB_PODLY_DLY2_SHIFT (0U)
15247#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
15248#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
15249#define PDB_PODLY_DLY1_SHIFT (16U)
15250#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
15253/* The count of PDB_PODLY */
15254#define PDB_PODLY_COUNT (3U)
15255
15256
15259 /* end of group PDB_Register_Masks */
15260
15261
15262/* PDB - Peripheral instance base addresses */
15264#define PDB0_BASE (0x40036000u)
15266#define PDB0 ((PDB_Type *)PDB0_BASE)
15268#define PDB_BASE_ADDRS { PDB0_BASE }
15270#define PDB_BASE_PTRS { PDB0 }
15272#define PDB_IRQS { PDB0_IRQn }
15273
15276 /* end of group PDB_Peripheral_Access_Layer */
15277
15278
15279/* ----------------------------------------------------------------------------
15280 -- PIT Peripheral Access Layer
15281 ---------------------------------------------------------------------------- */
15282
15289typedef struct {
15290 __IO uint32_t MCR;
15291 uint8_t RESERVED_0[252];
15292 struct { /* offset: 0x100, array step: 0x10 */
15293 __IO uint32_t LDVAL;
15294 __I uint32_t CVAL;
15295 __IO uint32_t TCTRL;
15296 __IO uint32_t TFLG;
15297 } CHANNEL[4];
15298} PIT_Type;
15299
15300/* ----------------------------------------------------------------------------
15301 -- PIT Register Masks
15302 ---------------------------------------------------------------------------- */
15303
15311#define PIT_MCR_FRZ_MASK (0x1U)
15312#define PIT_MCR_FRZ_SHIFT (0U)
15317#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
15318#define PIT_MCR_MDIS_MASK (0x2U)
15319#define PIT_MCR_MDIS_SHIFT (1U)
15324#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
15329#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
15330#define PIT_LDVAL_TSV_SHIFT (0U)
15331#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
15334/* The count of PIT_LDVAL */
15335#define PIT_LDVAL_COUNT (4U)
15336
15339#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
15340#define PIT_CVAL_TVL_SHIFT (0U)
15341#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
15344/* The count of PIT_CVAL */
15345#define PIT_CVAL_COUNT (4U)
15346
15349#define PIT_TCTRL_TEN_MASK (0x1U)
15350#define PIT_TCTRL_TEN_SHIFT (0U)
15355#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
15356#define PIT_TCTRL_TIE_MASK (0x2U)
15357#define PIT_TCTRL_TIE_SHIFT (1U)
15362#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
15363#define PIT_TCTRL_CHN_MASK (0x4U)
15364#define PIT_TCTRL_CHN_SHIFT (2U)
15369#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
15372/* The count of PIT_TCTRL */
15373#define PIT_TCTRL_COUNT (4U)
15374
15377#define PIT_TFLG_TIF_MASK (0x1U)
15378#define PIT_TFLG_TIF_SHIFT (0U)
15383#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
15386/* The count of PIT_TFLG */
15387#define PIT_TFLG_COUNT (4U)
15388
15389
15392 /* end of group PIT_Register_Masks */
15393
15394
15395/* PIT - Peripheral instance base addresses */
15397#define PIT_BASE (0x40037000u)
15399#define PIT ((PIT_Type *)PIT_BASE)
15401#define PIT_BASE_ADDRS { PIT_BASE }
15403#define PIT_BASE_PTRS { PIT }
15405#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
15406
15409 /* end of group PIT_Peripheral_Access_Layer */
15410
15411
15412/* ----------------------------------------------------------------------------
15413 -- PMC Peripheral Access Layer
15414 ---------------------------------------------------------------------------- */
15415
15422typedef struct {
15423 __IO uint8_t LVDSC1;
15424 __IO uint8_t LVDSC2;
15425 __IO uint8_t REGSC;
15426} PMC_Type;
15427
15428/* ----------------------------------------------------------------------------
15429 -- PMC Register Masks
15430 ---------------------------------------------------------------------------- */
15431
15439#define PMC_LVDSC1_LVDV_MASK (0x3U)
15440#define PMC_LVDSC1_LVDV_SHIFT (0U)
15447#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
15448#define PMC_LVDSC1_LVDRE_MASK (0x10U)
15449#define PMC_LVDSC1_LVDRE_SHIFT (4U)
15454#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
15455#define PMC_LVDSC1_LVDIE_MASK (0x20U)
15456#define PMC_LVDSC1_LVDIE_SHIFT (5U)
15461#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
15462#define PMC_LVDSC1_LVDACK_MASK (0x40U)
15463#define PMC_LVDSC1_LVDACK_SHIFT (6U)
15464#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
15465#define PMC_LVDSC1_LVDF_MASK (0x80U)
15466#define PMC_LVDSC1_LVDF_SHIFT (7U)
15471#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
15476#define PMC_LVDSC2_LVWV_MASK (0x3U)
15477#define PMC_LVDSC2_LVWV_SHIFT (0U)
15484#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
15485#define PMC_LVDSC2_LVWIE_MASK (0x20U)
15486#define PMC_LVDSC2_LVWIE_SHIFT (5U)
15491#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
15492#define PMC_LVDSC2_LVWACK_MASK (0x40U)
15493#define PMC_LVDSC2_LVWACK_SHIFT (6U)
15494#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
15495#define PMC_LVDSC2_LVWF_MASK (0x80U)
15496#define PMC_LVDSC2_LVWF_SHIFT (7U)
15501#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
15506#define PMC_REGSC_BGBE_MASK (0x1U)
15507#define PMC_REGSC_BGBE_SHIFT (0U)
15512#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
15513#define PMC_REGSC_REGONS_MASK (0x4U)
15514#define PMC_REGSC_REGONS_SHIFT (2U)
15519#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
15520#define PMC_REGSC_ACKISO_MASK (0x8U)
15521#define PMC_REGSC_ACKISO_SHIFT (3U)
15526#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
15527#define PMC_REGSC_BGEN_MASK (0x10U)
15528#define PMC_REGSC_BGEN_SHIFT (4U)
15533#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
15539 /* end of group PMC_Register_Masks */
15540
15541
15542/* PMC - Peripheral instance base addresses */
15544#define PMC_BASE (0x4007D000u)
15546#define PMC ((PMC_Type *)PMC_BASE)
15548#define PMC_BASE_ADDRS { PMC_BASE }
15550#define PMC_BASE_PTRS { PMC }
15552#define PMC_IRQS { LVD_LVW_IRQn }
15553
15556 /* end of group PMC_Peripheral_Access_Layer */
15557
15558
15559/* ----------------------------------------------------------------------------
15560 -- PORT Peripheral Access Layer
15561 ---------------------------------------------------------------------------- */
15562
15569typedef struct {
15570 __IO uint32_t PCR[32];
15571 __O uint32_t GPCLR;
15572 __O uint32_t GPCHR;
15573 uint8_t RESERVED_0[24];
15574 __IO uint32_t ISFR;
15575 uint8_t RESERVED_1[28];
15576 __IO uint32_t DFER;
15577 __IO uint32_t DFCR;
15578 __IO uint32_t DFWR;
15579} PORT_Type;
15580
15581/* ----------------------------------------------------------------------------
15582 -- PORT Register Masks
15583 ---------------------------------------------------------------------------- */
15584
15592#define PORT_PCR_PS_MASK (0x1U)
15593#define PORT_PCR_PS_SHIFT (0U)
15598#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
15599#define PORT_PCR_PE_MASK (0x2U)
15600#define PORT_PCR_PE_SHIFT (1U)
15605#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
15606#define PORT_PCR_SRE_MASK (0x4U)
15607#define PORT_PCR_SRE_SHIFT (2U)
15612#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
15613#define PORT_PCR_PFE_MASK (0x10U)
15614#define PORT_PCR_PFE_SHIFT (4U)
15619#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
15620#define PORT_PCR_ODE_MASK (0x20U)
15621#define PORT_PCR_ODE_SHIFT (5U)
15626#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
15627#define PORT_PCR_DSE_MASK (0x40U)
15628#define PORT_PCR_DSE_SHIFT (6U)
15633#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
15634#define PORT_PCR_MUX_MASK (0x700U)
15635#define PORT_PCR_MUX_SHIFT (8U)
15646#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
15647#define PORT_PCR_LK_MASK (0x8000U)
15648#define PORT_PCR_LK_SHIFT (15U)
15653#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
15654#define PORT_PCR_IRQC_MASK (0xF0000U)
15655#define PORT_PCR_IRQC_SHIFT (16U)
15667#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
15668#define PORT_PCR_ISF_MASK (0x1000000U)
15669#define PORT_PCR_ISF_SHIFT (24U)
15674#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
15677/* The count of PORT_PCR */
15678#define PORT_PCR_COUNT (32U)
15679
15682#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
15683#define PORT_GPCLR_GPWD_SHIFT (0U)
15684#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
15685#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
15686#define PORT_GPCLR_GPWE_SHIFT (16U)
15691#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
15696#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
15697#define PORT_GPCHR_GPWD_SHIFT (0U)
15698#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
15699#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
15700#define PORT_GPCHR_GPWE_SHIFT (16U)
15705#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
15710#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
15711#define PORT_ISFR_ISF_SHIFT (0U)
15716#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
15721#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
15722#define PORT_DFER_DFE_SHIFT (0U)
15727#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
15732#define PORT_DFCR_CS_MASK (0x1U)
15733#define PORT_DFCR_CS_SHIFT (0U)
15738#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
15743#define PORT_DFWR_FILT_MASK (0x1FU)
15744#define PORT_DFWR_FILT_SHIFT (0U)
15745#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
15751 /* end of group PORT_Register_Masks */
15752
15753
15754/* PORT - Peripheral instance base addresses */
15756#define PORTA_BASE (0x40049000u)
15758#define PORTA ((PORT_Type *)PORTA_BASE)
15760#define PORTB_BASE (0x4004A000u)
15762#define PORTB ((PORT_Type *)PORTB_BASE)
15764#define PORTC_BASE (0x4004B000u)
15766#define PORTC ((PORT_Type *)PORTC_BASE)
15768#define PORTD_BASE (0x4004C000u)
15770#define PORTD ((PORT_Type *)PORTD_BASE)
15772#define PORTE_BASE (0x4004D000u)
15774#define PORTE ((PORT_Type *)PORTE_BASE)
15776#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
15778#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
15780#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
15781
15784 /* end of group PORT_Peripheral_Access_Layer */
15785
15786
15787/* ----------------------------------------------------------------------------
15788 -- RCM Peripheral Access Layer
15789 ---------------------------------------------------------------------------- */
15790
15797typedef struct {
15798 __I uint8_t SRS0;
15799 __I uint8_t SRS1;
15800 uint8_t RESERVED_0[2];
15801 __IO uint8_t RPFC;
15802 __IO uint8_t RPFW;
15803 uint8_t RESERVED_1[1];
15804 __I uint8_t MR;
15805} RCM_Type;
15806
15807/* ----------------------------------------------------------------------------
15808 -- RCM Register Masks
15809 ---------------------------------------------------------------------------- */
15810
15818#define RCM_SRS0_WAKEUP_MASK (0x1U)
15819#define RCM_SRS0_WAKEUP_SHIFT (0U)
15824#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
15825#define RCM_SRS0_LVD_MASK (0x2U)
15826#define RCM_SRS0_LVD_SHIFT (1U)
15831#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
15832#define RCM_SRS0_LOC_MASK (0x4U)
15833#define RCM_SRS0_LOC_SHIFT (2U)
15838#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
15839#define RCM_SRS0_LOL_MASK (0x8U)
15840#define RCM_SRS0_LOL_SHIFT (3U)
15845#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
15846#define RCM_SRS0_WDOG_MASK (0x20U)
15847#define RCM_SRS0_WDOG_SHIFT (5U)
15852#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
15853#define RCM_SRS0_PIN_MASK (0x40U)
15854#define RCM_SRS0_PIN_SHIFT (6U)
15859#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
15860#define RCM_SRS0_POR_MASK (0x80U)
15861#define RCM_SRS0_POR_SHIFT (7U)
15866#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
15871#define RCM_SRS1_JTAG_MASK (0x1U)
15872#define RCM_SRS1_JTAG_SHIFT (0U)
15877#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
15878#define RCM_SRS1_LOCKUP_MASK (0x2U)
15879#define RCM_SRS1_LOCKUP_SHIFT (1U)
15884#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
15885#define RCM_SRS1_SW_MASK (0x4U)
15886#define RCM_SRS1_SW_SHIFT (2U)
15891#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
15892#define RCM_SRS1_MDM_AP_MASK (0x8U)
15893#define RCM_SRS1_MDM_AP_SHIFT (3U)
15898#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
15899#define RCM_SRS1_EZPT_MASK (0x10U)
15900#define RCM_SRS1_EZPT_SHIFT (4U)
15905#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
15906#define RCM_SRS1_SACKERR_MASK (0x20U)
15907#define RCM_SRS1_SACKERR_SHIFT (5U)
15912#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
15917#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
15918#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
15925#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
15926#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
15927#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
15932#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
15937#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
15938#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
15973#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
15978#define RCM_MR_EZP_MS_MASK (0x2U)
15979#define RCM_MR_EZP_MS_SHIFT (1U)
15984#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
15990 /* end of group RCM_Register_Masks */
15991
15992
15993/* RCM - Peripheral instance base addresses */
15995#define RCM_BASE (0x4007F000u)
15997#define RCM ((RCM_Type *)RCM_BASE)
15999#define RCM_BASE_ADDRS { RCM_BASE }
16001#define RCM_BASE_PTRS { RCM }
16002
16005 /* end of group RCM_Peripheral_Access_Layer */
16006
16007
16008/* ----------------------------------------------------------------------------
16009 -- RFSYS Peripheral Access Layer
16010 ---------------------------------------------------------------------------- */
16011
16018typedef struct {
16019 __IO uint32_t REG[8];
16020} RFSYS_Type;
16021
16022/* ----------------------------------------------------------------------------
16023 -- RFSYS Register Masks
16024 ---------------------------------------------------------------------------- */
16025
16033#define RFSYS_REG_LL_MASK (0xFFU)
16034#define RFSYS_REG_LL_SHIFT (0U)
16035#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
16036#define RFSYS_REG_LH_MASK (0xFF00U)
16037#define RFSYS_REG_LH_SHIFT (8U)
16038#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
16039#define RFSYS_REG_HL_MASK (0xFF0000U)
16040#define RFSYS_REG_HL_SHIFT (16U)
16041#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
16042#define RFSYS_REG_HH_MASK (0xFF000000U)
16043#define RFSYS_REG_HH_SHIFT (24U)
16044#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
16047/* The count of RFSYS_REG */
16048#define RFSYS_REG_COUNT (8U)
16049
16050
16053 /* end of group RFSYS_Register_Masks */
16054
16055
16056/* RFSYS - Peripheral instance base addresses */
16058#define RFSYS_BASE (0x40041000u)
16060#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
16062#define RFSYS_BASE_ADDRS { RFSYS_BASE }
16064#define RFSYS_BASE_PTRS { RFSYS }
16065
16068 /* end of group RFSYS_Peripheral_Access_Layer */
16069
16070
16071/* ----------------------------------------------------------------------------
16072 -- RFVBAT Peripheral Access Layer
16073 ---------------------------------------------------------------------------- */
16074
16081typedef struct {
16082 __IO uint32_t REG[8];
16083} RFVBAT_Type;
16084
16085/* ----------------------------------------------------------------------------
16086 -- RFVBAT Register Masks
16087 ---------------------------------------------------------------------------- */
16088
16096#define RFVBAT_REG_LL_MASK (0xFFU)
16097#define RFVBAT_REG_LL_SHIFT (0U)
16098#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
16099#define RFVBAT_REG_LH_MASK (0xFF00U)
16100#define RFVBAT_REG_LH_SHIFT (8U)
16101#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
16102#define RFVBAT_REG_HL_MASK (0xFF0000U)
16103#define RFVBAT_REG_HL_SHIFT (16U)
16104#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
16105#define RFVBAT_REG_HH_MASK (0xFF000000U)
16106#define RFVBAT_REG_HH_SHIFT (24U)
16107#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
16110/* The count of RFVBAT_REG */
16111#define RFVBAT_REG_COUNT (8U)
16112
16113
16116 /* end of group RFVBAT_Register_Masks */
16117
16118
16119/* RFVBAT - Peripheral instance base addresses */
16121#define RFVBAT_BASE (0x4003E000u)
16123#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
16125#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
16127#define RFVBAT_BASE_PTRS { RFVBAT }
16128
16131 /* end of group RFVBAT_Peripheral_Access_Layer */
16132
16133
16134/* ----------------------------------------------------------------------------
16135 -- RNG Peripheral Access Layer
16136 ---------------------------------------------------------------------------- */
16137
16144typedef struct {
16145 __IO uint32_t CR;
16146 __I uint32_t SR;
16147 __O uint32_t ER;
16148 __I uint32_t OR;
16149} RNG_Type;
16150
16151/* ----------------------------------------------------------------------------
16152 -- RNG Register Masks
16153 ---------------------------------------------------------------------------- */
16154
16162#define RNG_CR_GO_MASK (0x1U)
16163#define RNG_CR_GO_SHIFT (0U)
16168#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
16169#define RNG_CR_HA_MASK (0x2U)
16170#define RNG_CR_HA_SHIFT (1U)
16175#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
16176#define RNG_CR_INTM_MASK (0x4U)
16177#define RNG_CR_INTM_SHIFT (2U)
16182#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
16183#define RNG_CR_CLRI_MASK (0x8U)
16184#define RNG_CR_CLRI_SHIFT (3U)
16189#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
16190#define RNG_CR_SLP_MASK (0x10U)
16191#define RNG_CR_SLP_SHIFT (4U)
16196#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
16201#define RNG_SR_SECV_MASK (0x1U)
16202#define RNG_SR_SECV_SHIFT (0U)
16207#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
16208#define RNG_SR_LRS_MASK (0x2U)
16209#define RNG_SR_LRS_SHIFT (1U)
16214#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
16215#define RNG_SR_ORU_MASK (0x4U)
16216#define RNG_SR_ORU_SHIFT (2U)
16221#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
16222#define RNG_SR_ERRI_MASK (0x8U)
16223#define RNG_SR_ERRI_SHIFT (3U)
16228#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
16229#define RNG_SR_SLP_MASK (0x10U)
16230#define RNG_SR_SLP_SHIFT (4U)
16235#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
16236#define RNG_SR_OREG_LVL_MASK (0xFF00U)
16237#define RNG_SR_OREG_LVL_SHIFT (8U)
16242#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
16243#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
16244#define RNG_SR_OREG_SIZE_SHIFT (16U)
16248#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
16253#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
16254#define RNG_ER_EXT_ENT_SHIFT (0U)
16255#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
16260#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
16261#define RNG_OR_RANDOUT_SHIFT (0U)
16265#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
16271 /* end of group RNG_Register_Masks */
16272
16273
16274/* RNG - Peripheral instance base addresses */
16276#define RNG_BASE (0x40029000u)
16278#define RNG ((RNG_Type *)RNG_BASE)
16280#define RNG_BASE_ADDRS { RNG_BASE }
16282#define RNG_BASE_PTRS { RNG }
16284#define RNG_IRQS { RNG_IRQn }
16285
16288 /* end of group RNG_Peripheral_Access_Layer */
16289
16290
16291/* ----------------------------------------------------------------------------
16292 -- RTC Peripheral Access Layer
16293 ---------------------------------------------------------------------------- */
16294
16301typedef struct {
16302 __IO uint32_t TSR;
16303 __IO uint32_t TPR;
16304 __IO uint32_t TAR;
16305 __IO uint32_t TCR;
16306 __IO uint32_t CR;
16307 __IO uint32_t SR;
16308 __IO uint32_t LR;
16309 __IO uint32_t IER;
16310 uint8_t RESERVED_0[2016];
16311 __IO uint32_t WAR;
16312 __IO uint32_t RAR;
16313} RTC_Type;
16314
16315/* ----------------------------------------------------------------------------
16316 -- RTC Register Masks
16317 ---------------------------------------------------------------------------- */
16318
16326#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
16327#define RTC_TSR_TSR_SHIFT (0U)
16328#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
16333#define RTC_TPR_TPR_MASK (0xFFFFU)
16334#define RTC_TPR_TPR_SHIFT (0U)
16335#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
16340#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
16341#define RTC_TAR_TAR_SHIFT (0U)
16342#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
16347#define RTC_TCR_TCR_MASK (0xFFU)
16348#define RTC_TCR_TCR_SHIFT (0U)
16356#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
16357#define RTC_TCR_CIR_MASK (0xFF00U)
16358#define RTC_TCR_CIR_SHIFT (8U)
16359#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
16360#define RTC_TCR_TCV_MASK (0xFF0000U)
16361#define RTC_TCR_TCV_SHIFT (16U)
16362#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
16363#define RTC_TCR_CIC_MASK (0xFF000000U)
16364#define RTC_TCR_CIC_SHIFT (24U)
16365#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
16370#define RTC_CR_SWR_MASK (0x1U)
16371#define RTC_CR_SWR_SHIFT (0U)
16376#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
16377#define RTC_CR_WPE_MASK (0x2U)
16378#define RTC_CR_WPE_SHIFT (1U)
16383#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
16384#define RTC_CR_SUP_MASK (0x4U)
16385#define RTC_CR_SUP_SHIFT (2U)
16390#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
16391#define RTC_CR_UM_MASK (0x8U)
16392#define RTC_CR_UM_SHIFT (3U)
16397#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
16398#define RTC_CR_WPS_MASK (0x10U)
16399#define RTC_CR_WPS_SHIFT (4U)
16404#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
16405#define RTC_CR_OSCE_MASK (0x100U)
16406#define RTC_CR_OSCE_SHIFT (8U)
16411#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
16412#define RTC_CR_CLKO_MASK (0x200U)
16413#define RTC_CR_CLKO_SHIFT (9U)
16418#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
16419#define RTC_CR_SC16P_MASK (0x400U)
16420#define RTC_CR_SC16P_SHIFT (10U)
16425#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
16426#define RTC_CR_SC8P_MASK (0x800U)
16427#define RTC_CR_SC8P_SHIFT (11U)
16432#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
16433#define RTC_CR_SC4P_MASK (0x1000U)
16434#define RTC_CR_SC4P_SHIFT (12U)
16439#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
16440#define RTC_CR_SC2P_MASK (0x2000U)
16441#define RTC_CR_SC2P_SHIFT (13U)
16446#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
16451#define RTC_SR_TIF_MASK (0x1U)
16452#define RTC_SR_TIF_SHIFT (0U)
16457#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
16458#define RTC_SR_TOF_MASK (0x2U)
16459#define RTC_SR_TOF_SHIFT (1U)
16464#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
16465#define RTC_SR_TAF_MASK (0x4U)
16466#define RTC_SR_TAF_SHIFT (2U)
16471#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
16472#define RTC_SR_TCE_MASK (0x10U)
16473#define RTC_SR_TCE_SHIFT (4U)
16478#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
16483#define RTC_LR_TCL_MASK (0x8U)
16484#define RTC_LR_TCL_SHIFT (3U)
16489#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
16490#define RTC_LR_CRL_MASK (0x10U)
16491#define RTC_LR_CRL_SHIFT (4U)
16496#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
16497#define RTC_LR_SRL_MASK (0x20U)
16498#define RTC_LR_SRL_SHIFT (5U)
16503#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
16504#define RTC_LR_LRL_MASK (0x40U)
16505#define RTC_LR_LRL_SHIFT (6U)
16510#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
16515#define RTC_IER_TIIE_MASK (0x1U)
16516#define RTC_IER_TIIE_SHIFT (0U)
16521#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
16522#define RTC_IER_TOIE_MASK (0x2U)
16523#define RTC_IER_TOIE_SHIFT (1U)
16528#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
16529#define RTC_IER_TAIE_MASK (0x4U)
16530#define RTC_IER_TAIE_SHIFT (2U)
16535#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
16536#define RTC_IER_TSIE_MASK (0x10U)
16537#define RTC_IER_TSIE_SHIFT (4U)
16542#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
16543#define RTC_IER_WPON_MASK (0x80U)
16544#define RTC_IER_WPON_SHIFT (7U)
16549#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
16554#define RTC_WAR_TSRW_MASK (0x1U)
16555#define RTC_WAR_TSRW_SHIFT (0U)
16560#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
16561#define RTC_WAR_TPRW_MASK (0x2U)
16562#define RTC_WAR_TPRW_SHIFT (1U)
16567#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
16568#define RTC_WAR_TARW_MASK (0x4U)
16569#define RTC_WAR_TARW_SHIFT (2U)
16574#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
16575#define RTC_WAR_TCRW_MASK (0x8U)
16576#define RTC_WAR_TCRW_SHIFT (3U)
16581#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
16582#define RTC_WAR_CRW_MASK (0x10U)
16583#define RTC_WAR_CRW_SHIFT (4U)
16588#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
16589#define RTC_WAR_SRW_MASK (0x20U)
16590#define RTC_WAR_SRW_SHIFT (5U)
16595#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
16596#define RTC_WAR_LRW_MASK (0x40U)
16597#define RTC_WAR_LRW_SHIFT (6U)
16602#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
16603#define RTC_WAR_IERW_MASK (0x80U)
16604#define RTC_WAR_IERW_SHIFT (7U)
16609#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
16614#define RTC_RAR_TSRR_MASK (0x1U)
16615#define RTC_RAR_TSRR_SHIFT (0U)
16620#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
16621#define RTC_RAR_TPRR_MASK (0x2U)
16622#define RTC_RAR_TPRR_SHIFT (1U)
16627#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
16628#define RTC_RAR_TARR_MASK (0x4U)
16629#define RTC_RAR_TARR_SHIFT (2U)
16634#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
16635#define RTC_RAR_TCRR_MASK (0x8U)
16636#define RTC_RAR_TCRR_SHIFT (3U)
16641#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
16642#define RTC_RAR_CRR_MASK (0x10U)
16643#define RTC_RAR_CRR_SHIFT (4U)
16648#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
16649#define RTC_RAR_SRR_MASK (0x20U)
16650#define RTC_RAR_SRR_SHIFT (5U)
16655#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
16656#define RTC_RAR_LRR_MASK (0x40U)
16657#define RTC_RAR_LRR_SHIFT (6U)
16662#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
16663#define RTC_RAR_IERR_MASK (0x80U)
16664#define RTC_RAR_IERR_SHIFT (7U)
16669#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
16675 /* end of group RTC_Register_Masks */
16676
16677
16678/* RTC - Peripheral instance base addresses */
16680#define RTC_BASE (0x4003D000u)
16682#define RTC ((RTC_Type *)RTC_BASE)
16684#define RTC_BASE_ADDRS { RTC_BASE }
16686#define RTC_BASE_PTRS { RTC }
16688#define RTC_IRQS { RTC_IRQn }
16689#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
16690
16693 /* end of group RTC_Peripheral_Access_Layer */
16694
16695
16696/* ----------------------------------------------------------------------------
16697 -- SDHC Peripheral Access Layer
16698 ---------------------------------------------------------------------------- */
16699
16706typedef struct {
16707 __IO uint32_t DSADDR;
16708 __IO uint32_t BLKATTR;
16709 __IO uint32_t CMDARG;
16710 __IO uint32_t XFERTYP;
16711 __I uint32_t CMDRSP[4];
16712 __IO uint32_t DATPORT;
16713 __I uint32_t PRSSTAT;
16714 __IO uint32_t PROCTL;
16715 __IO uint32_t SYSCTL;
16716 __IO uint32_t IRQSTAT;
16717 __IO uint32_t IRQSTATEN;
16718 __IO uint32_t IRQSIGEN;
16719 __I uint32_t AC12ERR;
16720 __I uint32_t HTCAPBLT;
16721 __IO uint32_t WML;
16722 uint8_t RESERVED_0[8];
16723 __O uint32_t FEVT;
16724 __I uint32_t ADMAES;
16725 __IO uint32_t ADSADDR;
16726 uint8_t RESERVED_1[100];
16727 __IO uint32_t VENDOR;
16728 __IO uint32_t MMCBOOT;
16729 uint8_t RESERVED_2[52];
16730 __I uint32_t HOSTVER;
16731} SDHC_Type;
16732
16733/* ----------------------------------------------------------------------------
16734 -- SDHC Register Masks
16735 ---------------------------------------------------------------------------- */
16736
16744#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
16745#define SDHC_DSADDR_DSADDR_SHIFT (2U)
16746#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
16751#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
16752#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
16764#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
16765#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
16766#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
16773#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
16778#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
16779#define SDHC_CMDARG_CMDARG_SHIFT (0U)
16780#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
16785#define SDHC_XFERTYP_DMAEN_MASK (0x1U)
16786#define SDHC_XFERTYP_DMAEN_SHIFT (0U)
16791#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
16792#define SDHC_XFERTYP_BCEN_MASK (0x2U)
16793#define SDHC_XFERTYP_BCEN_SHIFT (1U)
16798#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
16799#define SDHC_XFERTYP_AC12EN_MASK (0x4U)
16800#define SDHC_XFERTYP_AC12EN_SHIFT (2U)
16805#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
16806#define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
16807#define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
16812#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
16813#define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
16814#define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
16819#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
16820#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
16821#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
16828#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
16829#define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
16830#define SDHC_XFERTYP_CCCEN_SHIFT (19U)
16835#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
16836#define SDHC_XFERTYP_CICEN_MASK (0x100000U)
16837#define SDHC_XFERTYP_CICEN_SHIFT (20U)
16842#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
16843#define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
16844#define SDHC_XFERTYP_DPSEL_SHIFT (21U)
16849#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
16850#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
16851#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
16858#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
16859#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
16860#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
16861#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
16866#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
16867#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
16868#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
16869#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
16870#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
16871#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
16872#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
16873#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
16874#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
16875#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
16876#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
16877#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
16880/* The count of SDHC_CMDRSP */
16881#define SDHC_CMDRSP_COUNT (4U)
16882
16885#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
16886#define SDHC_DATPORT_DATCONT_SHIFT (0U)
16887#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
16892#define SDHC_PRSSTAT_CIHB_MASK (0x1U)
16893#define SDHC_PRSSTAT_CIHB_SHIFT (0U)
16898#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
16899#define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
16900#define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
16905#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
16906#define SDHC_PRSSTAT_DLA_MASK (0x4U)
16907#define SDHC_PRSSTAT_DLA_SHIFT (2U)
16912#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
16913#define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
16914#define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
16919#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
16920#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
16921#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
16926#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
16927#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
16928#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
16933#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
16934#define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
16935#define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
16940#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
16941#define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
16942#define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
16947#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
16948#define SDHC_PRSSTAT_WTA_MASK (0x100U)
16949#define SDHC_PRSSTAT_WTA_SHIFT (8U)
16954#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
16955#define SDHC_PRSSTAT_RTA_MASK (0x200U)
16956#define SDHC_PRSSTAT_RTA_SHIFT (9U)
16961#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
16962#define SDHC_PRSSTAT_BWEN_MASK (0x400U)
16963#define SDHC_PRSSTAT_BWEN_SHIFT (10U)
16968#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
16969#define SDHC_PRSSTAT_BREN_MASK (0x800U)
16970#define SDHC_PRSSTAT_BREN_SHIFT (11U)
16975#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
16976#define SDHC_PRSSTAT_CINS_MASK (0x10000U)
16977#define SDHC_PRSSTAT_CINS_SHIFT (16U)
16982#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
16983#define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
16984#define SDHC_PRSSTAT_CLSL_SHIFT (23U)
16985#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
16986#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
16987#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
16988#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
16993#define SDHC_PROCTL_LCTL_MASK (0x1U)
16994#define SDHC_PROCTL_LCTL_SHIFT (0U)
16999#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
17000#define SDHC_PROCTL_DTW_MASK (0x6U)
17001#define SDHC_PROCTL_DTW_SHIFT (1U)
17008#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
17009#define SDHC_PROCTL_D3CD_MASK (0x8U)
17010#define SDHC_PROCTL_D3CD_SHIFT (3U)
17015#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
17016#define SDHC_PROCTL_EMODE_MASK (0x30U)
17017#define SDHC_PROCTL_EMODE_SHIFT (4U)
17024#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
17025#define SDHC_PROCTL_CDTL_MASK (0x40U)
17026#define SDHC_PROCTL_CDTL_SHIFT (6U)
17031#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
17032#define SDHC_PROCTL_CDSS_MASK (0x80U)
17033#define SDHC_PROCTL_CDSS_SHIFT (7U)
17038#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
17039#define SDHC_PROCTL_DMAS_MASK (0x300U)
17040#define SDHC_PROCTL_DMAS_SHIFT (8U)
17047#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
17048#define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
17049#define SDHC_PROCTL_SABGREQ_SHIFT (16U)
17054#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
17055#define SDHC_PROCTL_CREQ_MASK (0x20000U)
17056#define SDHC_PROCTL_CREQ_SHIFT (17U)
17061#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
17062#define SDHC_PROCTL_RWCTL_MASK (0x40000U)
17063#define SDHC_PROCTL_RWCTL_SHIFT (18U)
17068#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
17069#define SDHC_PROCTL_IABG_MASK (0x80000U)
17070#define SDHC_PROCTL_IABG_SHIFT (19U)
17075#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
17076#define SDHC_PROCTL_WECINT_MASK (0x1000000U)
17077#define SDHC_PROCTL_WECINT_SHIFT (24U)
17082#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
17083#define SDHC_PROCTL_WECINS_MASK (0x2000000U)
17084#define SDHC_PROCTL_WECINS_SHIFT (25U)
17089#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
17090#define SDHC_PROCTL_WECRM_MASK (0x4000000U)
17091#define SDHC_PROCTL_WECRM_SHIFT (26U)
17096#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
17101#define SDHC_SYSCTL_IPGEN_MASK (0x1U)
17102#define SDHC_SYSCTL_IPGEN_SHIFT (0U)
17107#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
17108#define SDHC_SYSCTL_HCKEN_MASK (0x2U)
17109#define SDHC_SYSCTL_HCKEN_SHIFT (1U)
17114#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
17115#define SDHC_SYSCTL_PEREN_MASK (0x4U)
17116#define SDHC_SYSCTL_PEREN_SHIFT (2U)
17121#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
17122#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
17123#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
17124#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
17125#define SDHC_SYSCTL_DVS_MASK (0xF0U)
17126#define SDHC_SYSCTL_DVS_SHIFT (4U)
17133#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
17134#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
17135#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
17146#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
17147#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
17148#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
17155#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
17156#define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
17157#define SDHC_SYSCTL_RSTA_SHIFT (24U)
17162#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
17163#define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
17164#define SDHC_SYSCTL_RSTC_SHIFT (25U)
17169#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
17170#define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
17171#define SDHC_SYSCTL_RSTD_SHIFT (26U)
17176#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
17177#define SDHC_SYSCTL_INITA_MASK (0x8000000U)
17178#define SDHC_SYSCTL_INITA_SHIFT (27U)
17179#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
17184#define SDHC_IRQSTAT_CC_MASK (0x1U)
17185#define SDHC_IRQSTAT_CC_SHIFT (0U)
17190#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
17191#define SDHC_IRQSTAT_TC_MASK (0x2U)
17192#define SDHC_IRQSTAT_TC_SHIFT (1U)
17197#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
17198#define SDHC_IRQSTAT_BGE_MASK (0x4U)
17199#define SDHC_IRQSTAT_BGE_SHIFT (2U)
17204#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
17205#define SDHC_IRQSTAT_DINT_MASK (0x8U)
17206#define SDHC_IRQSTAT_DINT_SHIFT (3U)
17211#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
17212#define SDHC_IRQSTAT_BWR_MASK (0x10U)
17213#define SDHC_IRQSTAT_BWR_SHIFT (4U)
17218#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
17219#define SDHC_IRQSTAT_BRR_MASK (0x20U)
17220#define SDHC_IRQSTAT_BRR_SHIFT (5U)
17225#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
17226#define SDHC_IRQSTAT_CINS_MASK (0x40U)
17227#define SDHC_IRQSTAT_CINS_SHIFT (6U)
17232#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
17233#define SDHC_IRQSTAT_CRM_MASK (0x80U)
17234#define SDHC_IRQSTAT_CRM_SHIFT (7U)
17239#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
17240#define SDHC_IRQSTAT_CINT_MASK (0x100U)
17241#define SDHC_IRQSTAT_CINT_SHIFT (8U)
17246#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
17247#define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
17248#define SDHC_IRQSTAT_CTOE_SHIFT (16U)
17253#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
17254#define SDHC_IRQSTAT_CCE_MASK (0x20000U)
17255#define SDHC_IRQSTAT_CCE_SHIFT (17U)
17260#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
17261#define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
17262#define SDHC_IRQSTAT_CEBE_SHIFT (18U)
17267#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
17268#define SDHC_IRQSTAT_CIE_MASK (0x80000U)
17269#define SDHC_IRQSTAT_CIE_SHIFT (19U)
17274#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
17275#define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
17276#define SDHC_IRQSTAT_DTOE_SHIFT (20U)
17281#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
17282#define SDHC_IRQSTAT_DCE_MASK (0x200000U)
17283#define SDHC_IRQSTAT_DCE_SHIFT (21U)
17288#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
17289#define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
17290#define SDHC_IRQSTAT_DEBE_SHIFT (22U)
17295#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
17296#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
17297#define SDHC_IRQSTAT_AC12E_SHIFT (24U)
17302#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
17303#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
17304#define SDHC_IRQSTAT_DMAE_SHIFT (28U)
17309#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
17314#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
17315#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
17320#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
17321#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
17322#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
17327#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
17328#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
17329#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
17334#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
17335#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
17336#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
17341#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
17342#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
17343#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
17348#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
17349#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
17350#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
17355#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
17356#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
17357#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
17362#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
17363#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
17364#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
17369#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
17370#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
17371#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
17376#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
17377#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
17378#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
17383#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
17384#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
17385#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
17390#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
17391#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
17392#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
17397#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
17398#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
17399#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
17404#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
17405#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
17406#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
17411#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
17412#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
17413#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
17418#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
17419#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
17420#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
17425#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
17426#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
17427#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
17432#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
17433#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
17434#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
17439#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
17444#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
17445#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
17450#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
17451#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
17452#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
17457#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
17458#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
17459#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
17464#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
17465#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
17466#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
17471#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
17472#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
17473#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
17478#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
17479#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
17480#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
17485#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
17486#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
17487#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
17492#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
17493#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
17494#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
17499#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
17500#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
17501#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
17506#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
17507#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
17508#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
17513#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
17514#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
17515#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
17520#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
17521#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
17522#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
17527#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
17528#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
17529#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
17534#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
17535#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
17536#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
17541#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
17542#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
17543#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
17548#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
17549#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
17550#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
17555#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
17556#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
17557#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
17562#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
17563#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
17564#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
17569#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
17574#define SDHC_AC12ERR_AC12NE_MASK (0x1U)
17575#define SDHC_AC12ERR_AC12NE_SHIFT (0U)
17580#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
17581#define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
17582#define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
17587#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
17588#define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
17589#define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
17594#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
17595#define SDHC_AC12ERR_AC12CE_MASK (0x8U)
17596#define SDHC_AC12ERR_AC12CE_SHIFT (3U)
17601#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
17602#define SDHC_AC12ERR_AC12IE_MASK (0x10U)
17603#define SDHC_AC12ERR_AC12IE_SHIFT (4U)
17608#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
17609#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
17610#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
17615#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
17620#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
17621#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
17628#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
17629#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
17630#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
17635#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
17636#define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
17637#define SDHC_HTCAPBLT_HSS_SHIFT (21U)
17642#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
17643#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
17644#define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
17649#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
17650#define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
17651#define SDHC_HTCAPBLT_SRS_SHIFT (23U)
17656#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
17657#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
17658#define SDHC_HTCAPBLT_VS33_SHIFT (24U)
17663#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
17668#define SDHC_WML_RDWML_MASK (0xFFU)
17669#define SDHC_WML_RDWML_SHIFT (0U)
17670#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
17671#define SDHC_WML_WRWML_MASK (0xFF0000U)
17672#define SDHC_WML_WRWML_SHIFT (16U)
17673#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
17678#define SDHC_FEVT_AC12NE_MASK (0x1U)
17679#define SDHC_FEVT_AC12NE_SHIFT (0U)
17680#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
17681#define SDHC_FEVT_AC12TOE_MASK (0x2U)
17682#define SDHC_FEVT_AC12TOE_SHIFT (1U)
17683#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
17684#define SDHC_FEVT_AC12CE_MASK (0x4U)
17685#define SDHC_FEVT_AC12CE_SHIFT (2U)
17686#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
17687#define SDHC_FEVT_AC12EBE_MASK (0x8U)
17688#define SDHC_FEVT_AC12EBE_SHIFT (3U)
17689#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
17690#define SDHC_FEVT_AC12IE_MASK (0x10U)
17691#define SDHC_FEVT_AC12IE_SHIFT (4U)
17692#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
17693#define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
17694#define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
17695#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
17696#define SDHC_FEVT_CTOE_MASK (0x10000U)
17697#define SDHC_FEVT_CTOE_SHIFT (16U)
17698#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
17699#define SDHC_FEVT_CCE_MASK (0x20000U)
17700#define SDHC_FEVT_CCE_SHIFT (17U)
17701#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
17702#define SDHC_FEVT_CEBE_MASK (0x40000U)
17703#define SDHC_FEVT_CEBE_SHIFT (18U)
17704#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
17705#define SDHC_FEVT_CIE_MASK (0x80000U)
17706#define SDHC_FEVT_CIE_SHIFT (19U)
17707#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
17708#define SDHC_FEVT_DTOE_MASK (0x100000U)
17709#define SDHC_FEVT_DTOE_SHIFT (20U)
17710#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
17711#define SDHC_FEVT_DCE_MASK (0x200000U)
17712#define SDHC_FEVT_DCE_SHIFT (21U)
17713#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
17714#define SDHC_FEVT_DEBE_MASK (0x400000U)
17715#define SDHC_FEVT_DEBE_SHIFT (22U)
17716#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
17717#define SDHC_FEVT_AC12E_MASK (0x1000000U)
17718#define SDHC_FEVT_AC12E_SHIFT (24U)
17719#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
17720#define SDHC_FEVT_DMAE_MASK (0x10000000U)
17721#define SDHC_FEVT_DMAE_SHIFT (28U)
17722#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
17723#define SDHC_FEVT_CINT_MASK (0x80000000U)
17724#define SDHC_FEVT_CINT_SHIFT (31U)
17725#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
17730#define SDHC_ADMAES_ADMAES_MASK (0x3U)
17731#define SDHC_ADMAES_ADMAES_SHIFT (0U)
17732#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
17733#define SDHC_ADMAES_ADMALME_MASK (0x4U)
17734#define SDHC_ADMAES_ADMALME_SHIFT (2U)
17739#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
17740#define SDHC_ADMAES_ADMADCE_MASK (0x8U)
17741#define SDHC_ADMAES_ADMADCE_SHIFT (3U)
17746#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
17751#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
17752#define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
17753#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
17758#define SDHC_VENDOR_EXTDMAEN_MASK (0x1U)
17759#define SDHC_VENDOR_EXTDMAEN_SHIFT (0U)
17764#define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
17765#define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
17766#define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
17771#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
17772#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
17773#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
17774#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
17779#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
17780#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
17793#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
17794#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
17795#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
17800#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
17801#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
17802#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
17807#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
17808#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
17809#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
17814#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
17815#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
17816#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
17817#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
17818#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
17819#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
17820#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
17825#define SDHC_HOSTVER_SVN_MASK (0xFFU)
17826#define SDHC_HOSTVER_SVN_SHIFT (0U)
17830#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
17831#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
17832#define SDHC_HOSTVER_VVN_SHIFT (8U)
17839#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
17845 /* end of group SDHC_Register_Masks */
17846
17847
17848/* SDHC - Peripheral instance base addresses */
17850#define SDHC_BASE (0x400B1000u)
17852#define SDHC ((SDHC_Type *)SDHC_BASE)
17854#define SDHC_BASE_ADDRS { SDHC_BASE }
17856#define SDHC_BASE_PTRS { SDHC }
17858#define SDHC_IRQS { SDHC_IRQn }
17859
17862 /* end of group SDHC_Peripheral_Access_Layer */
17863
17864
17865/* ----------------------------------------------------------------------------
17866 -- SIM Peripheral Access Layer
17867 ---------------------------------------------------------------------------- */
17868
17875typedef struct {
17876 __IO uint32_t SOPT1;
17877 __IO uint32_t SOPT1CFG;
17878 uint8_t RESERVED_0[4092];
17879 __IO uint32_t SOPT2;
17880 uint8_t RESERVED_1[4];
17881 __IO uint32_t SOPT4;
17882 __IO uint32_t SOPT5;
17883 uint8_t RESERVED_2[4];
17884 __IO uint32_t SOPT7;
17885 uint8_t RESERVED_3[8];
17886 __I uint32_t SDID;
17887 __IO uint32_t SCGC1;
17888 __IO uint32_t SCGC2;
17889 __IO uint32_t SCGC3;
17890 __IO uint32_t SCGC4;
17891 __IO uint32_t SCGC5;
17892 __IO uint32_t SCGC6;
17893 __IO uint32_t SCGC7;
17894 __IO uint32_t CLKDIV1;
17895 __IO uint32_t CLKDIV2;
17896 __IO uint32_t FCFG1;
17897 __I uint32_t FCFG2;
17898 __I uint32_t UIDH;
17899 __I uint32_t UIDMH;
17900 __I uint32_t UIDML;
17901 __I uint32_t UIDL;
17902} SIM_Type;
17903
17904/* ----------------------------------------------------------------------------
17905 -- SIM Register Masks
17906 ---------------------------------------------------------------------------- */
17907
17915#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
17916#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
17928#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
17929#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
17930#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
17937#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
17938#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
17939#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
17944#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
17945#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
17946#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
17951#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
17952#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
17953#define SIM_SOPT1_USBREGEN_SHIFT (31U)
17958#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
17963#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
17964#define SIM_SOPT1CFG_URWE_SHIFT (24U)
17969#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
17970#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
17971#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
17976#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
17977#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
17978#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
17983#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
17988#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
17989#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
17994#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
17995#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
17996#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
18007#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
18008#define SIM_SOPT2_FBSL_MASK (0x300U)
18009#define SIM_SOPT2_FBSL_SHIFT (8U)
18016#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
18017#define SIM_SOPT2_PTD7PAD_MASK (0x800U)
18018#define SIM_SOPT2_PTD7PAD_SHIFT (11U)
18023#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
18024#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
18025#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
18030#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
18031#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
18032#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
18039#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
18040#define SIM_SOPT2_USBSRC_MASK (0x40000U)
18041#define SIM_SOPT2_USBSRC_SHIFT (18U)
18046#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
18047#define SIM_SOPT2_RMIISRC_MASK (0x80000U)
18048#define SIM_SOPT2_RMIISRC_SHIFT (19U)
18053#define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
18054#define SIM_SOPT2_TIMESRC_MASK (0x300000U)
18055#define SIM_SOPT2_TIMESRC_SHIFT (20U)
18062#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
18063#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
18064#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
18071#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
18076#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
18077#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
18082#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
18083#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
18084#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
18089#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
18090#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
18091#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
18096#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
18097#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
18098#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
18103#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
18104#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
18105#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
18110#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
18111#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
18112#define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
18117#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
18118#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
18119#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
18126#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
18127#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
18128#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
18135#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
18136#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
18137#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
18142#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
18143#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
18144#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
18149#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
18150#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
18151#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
18156#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
18157#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
18158#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
18163#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
18164#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
18165#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
18170#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
18171#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
18172#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
18177#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
18178#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
18179#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
18184#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
18185#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
18186#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
18191#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
18196#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
18197#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
18204#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
18205#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
18206#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
18213#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
18214#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
18215#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
18222#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
18223#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
18224#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
18231#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
18236#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
18237#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
18256#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
18257#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
18258#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
18263#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
18264#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
18265#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
18270#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
18271#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
18272#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
18291#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
18292#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
18293#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
18298#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
18299#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
18300#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
18305#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
18310#define SIM_SDID_PINID_MASK (0xFU)
18311#define SIM_SDID_PINID_SHIFT (0U)
18330#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
18331#define SIM_SDID_FAMID_MASK (0x70U)
18332#define SIM_SDID_FAMID_SHIFT (4U)
18343#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
18344#define SIM_SDID_DIEID_MASK (0xF80U)
18345#define SIM_SDID_DIEID_SHIFT (7U)
18346#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
18347#define SIM_SDID_REVID_MASK (0xF000U)
18348#define SIM_SDID_REVID_SHIFT (12U)
18349#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
18350#define SIM_SDID_SERIESID_MASK (0xF00000U)
18351#define SIM_SDID_SERIESID_SHIFT (20U)
18358#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
18359#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
18360#define SIM_SDID_SUBFAMID_SHIFT (24U)
18370#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
18371#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
18372#define SIM_SDID_FAMILYID_SHIFT (28U)
18381#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
18386#define SIM_SCGC1_I2C2_MASK (0x40U)
18387#define SIM_SCGC1_I2C2_SHIFT (6U)
18392#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
18393#define SIM_SCGC1_UART4_MASK (0x400U)
18394#define SIM_SCGC1_UART4_SHIFT (10U)
18399#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
18400#define SIM_SCGC1_UART5_MASK (0x800U)
18401#define SIM_SCGC1_UART5_SHIFT (11U)
18406#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
18411#define SIM_SCGC2_ENET_MASK (0x1U)
18412#define SIM_SCGC2_ENET_SHIFT (0U)
18417#define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
18418#define SIM_SCGC2_DAC0_MASK (0x1000U)
18419#define SIM_SCGC2_DAC0_SHIFT (12U)
18424#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
18425#define SIM_SCGC2_DAC1_MASK (0x2000U)
18426#define SIM_SCGC2_DAC1_SHIFT (13U)
18431#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
18436#define SIM_SCGC3_RNGA_MASK (0x1U)
18437#define SIM_SCGC3_RNGA_SHIFT (0U)
18442#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
18443#define SIM_SCGC3_SPI2_MASK (0x1000U)
18444#define SIM_SCGC3_SPI2_SHIFT (12U)
18449#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
18450#define SIM_SCGC3_SDHC_MASK (0x20000U)
18451#define SIM_SCGC3_SDHC_SHIFT (17U)
18456#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
18457#define SIM_SCGC3_FTM2_MASK (0x1000000U)
18458#define SIM_SCGC3_FTM2_SHIFT (24U)
18463#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
18464#define SIM_SCGC3_FTM3_MASK (0x2000000U)
18465#define SIM_SCGC3_FTM3_SHIFT (25U)
18470#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
18471#define SIM_SCGC3_ADC1_MASK (0x8000000U)
18472#define SIM_SCGC3_ADC1_SHIFT (27U)
18477#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
18482#define SIM_SCGC4_EWM_MASK (0x2U)
18483#define SIM_SCGC4_EWM_SHIFT (1U)
18488#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
18489#define SIM_SCGC4_CMT_MASK (0x4U)
18490#define SIM_SCGC4_CMT_SHIFT (2U)
18495#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
18496#define SIM_SCGC4_I2C0_MASK (0x40U)
18497#define SIM_SCGC4_I2C0_SHIFT (6U)
18502#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
18503#define SIM_SCGC4_I2C1_MASK (0x80U)
18504#define SIM_SCGC4_I2C1_SHIFT (7U)
18509#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
18510#define SIM_SCGC4_UART0_MASK (0x400U)
18511#define SIM_SCGC4_UART0_SHIFT (10U)
18516#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
18517#define SIM_SCGC4_UART1_MASK (0x800U)
18518#define SIM_SCGC4_UART1_SHIFT (11U)
18523#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
18524#define SIM_SCGC4_UART2_MASK (0x1000U)
18525#define SIM_SCGC4_UART2_SHIFT (12U)
18530#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
18531#define SIM_SCGC4_UART3_MASK (0x2000U)
18532#define SIM_SCGC4_UART3_SHIFT (13U)
18537#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
18538#define SIM_SCGC4_USBOTG_MASK (0x40000U)
18539#define SIM_SCGC4_USBOTG_SHIFT (18U)
18544#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
18545#define SIM_SCGC4_CMP_MASK (0x80000U)
18546#define SIM_SCGC4_CMP_SHIFT (19U)
18551#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
18552#define SIM_SCGC4_VREF_MASK (0x100000U)
18553#define SIM_SCGC4_VREF_SHIFT (20U)
18558#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
18563#define SIM_SCGC5_LPTMR_MASK (0x1U)
18564#define SIM_SCGC5_LPTMR_SHIFT (0U)
18569#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
18570#define SIM_SCGC5_PORTA_MASK (0x200U)
18571#define SIM_SCGC5_PORTA_SHIFT (9U)
18576#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
18577#define SIM_SCGC5_PORTB_MASK (0x400U)
18578#define SIM_SCGC5_PORTB_SHIFT (10U)
18583#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
18584#define SIM_SCGC5_PORTC_MASK (0x800U)
18585#define SIM_SCGC5_PORTC_SHIFT (11U)
18590#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
18591#define SIM_SCGC5_PORTD_MASK (0x1000U)
18592#define SIM_SCGC5_PORTD_SHIFT (12U)
18597#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
18598#define SIM_SCGC5_PORTE_MASK (0x2000U)
18599#define SIM_SCGC5_PORTE_SHIFT (13U)
18604#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
18609#define SIM_SCGC6_FTF_MASK (0x1U)
18610#define SIM_SCGC6_FTF_SHIFT (0U)
18615#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
18616#define SIM_SCGC6_DMAMUX_MASK (0x2U)
18617#define SIM_SCGC6_DMAMUX_SHIFT (1U)
18622#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
18623#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
18624#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
18629#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
18630#define SIM_SCGC6_RNGA_MASK (0x200U)
18631#define SIM_SCGC6_RNGA_SHIFT (9U)
18632#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
18633#define SIM_SCGC6_SPI0_MASK (0x1000U)
18634#define SIM_SCGC6_SPI0_SHIFT (12U)
18639#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
18640#define SIM_SCGC6_SPI1_MASK (0x2000U)
18641#define SIM_SCGC6_SPI1_SHIFT (13U)
18646#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
18647#define SIM_SCGC6_I2S_MASK (0x8000U)
18648#define SIM_SCGC6_I2S_SHIFT (15U)
18653#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
18654#define SIM_SCGC6_CRC_MASK (0x40000U)
18655#define SIM_SCGC6_CRC_SHIFT (18U)
18660#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
18661#define SIM_SCGC6_USBDCD_MASK (0x200000U)
18662#define SIM_SCGC6_USBDCD_SHIFT (21U)
18667#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
18668#define SIM_SCGC6_PDB_MASK (0x400000U)
18669#define SIM_SCGC6_PDB_SHIFT (22U)
18674#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
18675#define SIM_SCGC6_PIT_MASK (0x800000U)
18676#define SIM_SCGC6_PIT_SHIFT (23U)
18681#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
18682#define SIM_SCGC6_FTM0_MASK (0x1000000U)
18683#define SIM_SCGC6_FTM0_SHIFT (24U)
18688#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
18689#define SIM_SCGC6_FTM1_MASK (0x2000000U)
18690#define SIM_SCGC6_FTM1_SHIFT (25U)
18695#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
18696#define SIM_SCGC6_FTM2_MASK (0x4000000U)
18697#define SIM_SCGC6_FTM2_SHIFT (26U)
18702#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
18703#define SIM_SCGC6_ADC0_MASK (0x8000000U)
18704#define SIM_SCGC6_ADC0_SHIFT (27U)
18709#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
18710#define SIM_SCGC6_RTC_MASK (0x20000000U)
18711#define SIM_SCGC6_RTC_SHIFT (29U)
18716#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
18717#define SIM_SCGC6_DAC0_MASK (0x80000000U)
18718#define SIM_SCGC6_DAC0_SHIFT (31U)
18723#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
18728#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
18729#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
18734#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
18735#define SIM_SCGC7_DMA_MASK (0x2U)
18736#define SIM_SCGC7_DMA_SHIFT (1U)
18741#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
18742#define SIM_SCGC7_MPU_MASK (0x4U)
18743#define SIM_SCGC7_MPU_SHIFT (2U)
18748#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
18753#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
18754#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
18773#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
18774#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
18775#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
18794#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
18795#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
18796#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
18815#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
18816#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
18817#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
18836#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
18841#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
18842#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
18843#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
18844#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
18845#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
18846#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
18851#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
18852#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
18857#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
18858#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
18859#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
18864#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
18865#define SIM_FCFG1_DEPART_MASK (0xF00U)
18866#define SIM_FCFG1_DEPART_SHIFT (8U)
18867#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
18868#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
18869#define SIM_FCFG1_EESIZE_SHIFT (16U)
18883#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
18884#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
18885#define SIM_FCFG1_PFSIZE_SHIFT (24U)
18895#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
18896#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
18897#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
18907#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
18912#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
18913#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
18914#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
18915#define SIM_FCFG2_PFLSH_MASK (0x800000U)
18916#define SIM_FCFG2_PFLSH_SHIFT (23U)
18921#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
18922#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
18923#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
18924#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
18929#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
18930#define SIM_UIDH_UID_SHIFT (0U)
18931#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
18936#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
18937#define SIM_UIDMH_UID_SHIFT (0U)
18938#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
18943#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
18944#define SIM_UIDML_UID_SHIFT (0U)
18945#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
18950#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
18951#define SIM_UIDL_UID_SHIFT (0U)
18952#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
18958 /* end of group SIM_Register_Masks */
18959
18960
18961/* SIM - Peripheral instance base addresses */
18963#define SIM_BASE (0x40047000u)
18965#define SIM ((SIM_Type *)SIM_BASE)
18967#define SIM_BASE_ADDRS { SIM_BASE }
18969#define SIM_BASE_PTRS { SIM }
18970
18973 /* end of group SIM_Peripheral_Access_Layer */
18974
18975
18976/* ----------------------------------------------------------------------------
18977 -- SMC Peripheral Access Layer
18978 ---------------------------------------------------------------------------- */
18979
18986typedef struct {
18987 __IO uint8_t PMPROT;
18988 __IO uint8_t PMCTRL;
18989 __IO uint8_t VLLSCTRL;
18990 __I uint8_t PMSTAT;
18991} SMC_Type;
18992
18993/* ----------------------------------------------------------------------------
18994 -- SMC Register Masks
18995 ---------------------------------------------------------------------------- */
18996
19004#define SMC_PMPROT_AVLLS_MASK (0x2U)
19005#define SMC_PMPROT_AVLLS_SHIFT (1U)
19010#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
19011#define SMC_PMPROT_ALLS_MASK (0x8U)
19012#define SMC_PMPROT_ALLS_SHIFT (3U)
19017#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
19018#define SMC_PMPROT_AVLP_MASK (0x20U)
19019#define SMC_PMPROT_AVLP_SHIFT (5U)
19024#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
19029#define SMC_PMCTRL_STOPM_MASK (0x7U)
19030#define SMC_PMCTRL_STOPM_SHIFT (0U)
19041#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
19042#define SMC_PMCTRL_STOPA_MASK (0x8U)
19043#define SMC_PMCTRL_STOPA_SHIFT (3U)
19048#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
19049#define SMC_PMCTRL_RUNM_MASK (0x60U)
19050#define SMC_PMCTRL_RUNM_SHIFT (5U)
19057#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
19058#define SMC_PMCTRL_LPWUI_MASK (0x80U)
19059#define SMC_PMCTRL_LPWUI_SHIFT (7U)
19064#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
19069#define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
19070#define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
19081#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
19082#define SMC_VLLSCTRL_PORPO_MASK (0x20U)
19083#define SMC_VLLSCTRL_PORPO_SHIFT (5U)
19088#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
19093#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
19094#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
19095#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
19101 /* end of group SMC_Register_Masks */
19102
19103
19104/* SMC - Peripheral instance base addresses */
19106#define SMC_BASE (0x4007E000u)
19108#define SMC ((SMC_Type *)SMC_BASE)
19110#define SMC_BASE_ADDRS { SMC_BASE }
19112#define SMC_BASE_PTRS { SMC }
19113
19116 /* end of group SMC_Peripheral_Access_Layer */
19117
19118
19119/* ----------------------------------------------------------------------------
19120 -- SPI Peripheral Access Layer
19121 ---------------------------------------------------------------------------- */
19122
19129typedef struct {
19130 __IO uint32_t MCR;
19131 uint8_t RESERVED_0[4];
19132 __IO uint32_t TCR;
19133 union { /* offset: 0xC */
19134 __IO uint32_t CTAR[2];
19135 __IO uint32_t CTAR_SLAVE[1];
19136 };
19137 uint8_t RESERVED_1[24];
19138 __IO uint32_t SR;
19139 __IO uint32_t RSER;
19140 union { /* offset: 0x34 */
19141 __IO uint32_t PUSHR;
19142 __IO uint32_t PUSHR_SLAVE;
19143 };
19144 __I uint32_t POPR;
19145 __I uint32_t TXFR0;
19146 __I uint32_t TXFR1;
19147 __I uint32_t TXFR2;
19148 __I uint32_t TXFR3;
19149 uint8_t RESERVED_2[48];
19150 __I uint32_t RXFR0;
19151 __I uint32_t RXFR1;
19152 __I uint32_t RXFR2;
19153 __I uint32_t RXFR3;
19154} SPI_Type;
19155
19156/* ----------------------------------------------------------------------------
19157 -- SPI Register Masks
19158 ---------------------------------------------------------------------------- */
19159
19167#define SPI_MCR_HALT_MASK (0x1U)
19168#define SPI_MCR_HALT_SHIFT (0U)
19173#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
19174#define SPI_MCR_SMPL_PT_MASK (0x300U)
19175#define SPI_MCR_SMPL_PT_SHIFT (8U)
19182#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
19183#define SPI_MCR_CLR_RXF_MASK (0x400U)
19184#define SPI_MCR_CLR_RXF_SHIFT (10U)
19189#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
19190#define SPI_MCR_CLR_TXF_MASK (0x800U)
19191#define SPI_MCR_CLR_TXF_SHIFT (11U)
19196#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
19197#define SPI_MCR_DIS_RXF_MASK (0x1000U)
19198#define SPI_MCR_DIS_RXF_SHIFT (12U)
19203#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
19204#define SPI_MCR_DIS_TXF_MASK (0x2000U)
19205#define SPI_MCR_DIS_TXF_SHIFT (13U)
19210#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
19211#define SPI_MCR_MDIS_MASK (0x4000U)
19212#define SPI_MCR_MDIS_SHIFT (14U)
19217#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
19218#define SPI_MCR_DOZE_MASK (0x8000U)
19219#define SPI_MCR_DOZE_SHIFT (15U)
19224#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
19225#define SPI_MCR_PCSIS_MASK (0x3F0000U)
19226#define SPI_MCR_PCSIS_SHIFT (16U)
19231#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
19232#define SPI_MCR_ROOE_MASK (0x1000000U)
19233#define SPI_MCR_ROOE_SHIFT (24U)
19238#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
19239#define SPI_MCR_PCSSE_MASK (0x2000000U)
19240#define SPI_MCR_PCSSE_SHIFT (25U)
19245#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
19246#define SPI_MCR_MTFE_MASK (0x4000000U)
19247#define SPI_MCR_MTFE_SHIFT (26U)
19252#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
19253#define SPI_MCR_FRZ_MASK (0x8000000U)
19254#define SPI_MCR_FRZ_SHIFT (27U)
19259#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
19260#define SPI_MCR_DCONF_MASK (0x30000000U)
19261#define SPI_MCR_DCONF_SHIFT (28U)
19268#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
19269#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
19270#define SPI_MCR_CONT_SCKE_SHIFT (30U)
19275#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
19276#define SPI_MCR_MSTR_MASK (0x80000000U)
19277#define SPI_MCR_MSTR_SHIFT (31U)
19282#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
19287#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
19288#define SPI_TCR_SPI_TCNT_SHIFT (16U)
19289#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
19294#define SPI_CTAR_BR_MASK (0xFU)
19295#define SPI_CTAR_BR_SHIFT (0U)
19296#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
19297#define SPI_CTAR_DT_MASK (0xF0U)
19298#define SPI_CTAR_DT_SHIFT (4U)
19299#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
19300#define SPI_CTAR_ASC_MASK (0xF00U)
19301#define SPI_CTAR_ASC_SHIFT (8U)
19302#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
19303#define SPI_CTAR_CSSCK_MASK (0xF000U)
19304#define SPI_CTAR_CSSCK_SHIFT (12U)
19305#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
19306#define SPI_CTAR_PBR_MASK (0x30000U)
19307#define SPI_CTAR_PBR_SHIFT (16U)
19314#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
19315#define SPI_CTAR_PDT_MASK (0xC0000U)
19316#define SPI_CTAR_PDT_SHIFT (18U)
19323#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
19324#define SPI_CTAR_PASC_MASK (0x300000U)
19325#define SPI_CTAR_PASC_SHIFT (20U)
19332#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
19333#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
19334#define SPI_CTAR_PCSSCK_SHIFT (22U)
19341#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
19342#define SPI_CTAR_LSBFE_MASK (0x1000000U)
19343#define SPI_CTAR_LSBFE_SHIFT (24U)
19348#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
19349#define SPI_CTAR_CPHA_MASK (0x2000000U)
19350#define SPI_CTAR_CPHA_SHIFT (25U)
19355#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
19356#define SPI_CTAR_CPOL_MASK (0x4000000U)
19357#define SPI_CTAR_CPOL_SHIFT (26U)
19362#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
19363#define SPI_CTAR_FMSZ_MASK (0x78000000U)
19364#define SPI_CTAR_FMSZ_SHIFT (27U)
19365#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
19366#define SPI_CTAR_DBR_MASK (0x80000000U)
19367#define SPI_CTAR_DBR_SHIFT (31U)
19372#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
19375/* The count of SPI_CTAR */
19376#define SPI_CTAR_COUNT (2U)
19377
19380#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
19381#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
19386#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
19387#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
19388#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
19393#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
19394#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
19395#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
19396#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
19399/* The count of SPI_CTAR_SLAVE */
19400#define SPI_CTAR_SLAVE_COUNT (1U)
19401
19404#define SPI_SR_POPNXTPTR_MASK (0xFU)
19405#define SPI_SR_POPNXTPTR_SHIFT (0U)
19406#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
19407#define SPI_SR_RXCTR_MASK (0xF0U)
19408#define SPI_SR_RXCTR_SHIFT (4U)
19409#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
19410#define SPI_SR_TXNXTPTR_MASK (0xF00U)
19411#define SPI_SR_TXNXTPTR_SHIFT (8U)
19412#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
19413#define SPI_SR_TXCTR_MASK (0xF000U)
19414#define SPI_SR_TXCTR_SHIFT (12U)
19415#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
19416#define SPI_SR_RFDF_MASK (0x20000U)
19417#define SPI_SR_RFDF_SHIFT (17U)
19422#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
19423#define SPI_SR_RFOF_MASK (0x80000U)
19424#define SPI_SR_RFOF_SHIFT (19U)
19429#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
19430#define SPI_SR_TFFF_MASK (0x2000000U)
19431#define SPI_SR_TFFF_SHIFT (25U)
19436#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
19437#define SPI_SR_TFUF_MASK (0x8000000U)
19438#define SPI_SR_TFUF_SHIFT (27U)
19443#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
19444#define SPI_SR_EOQF_MASK (0x10000000U)
19445#define SPI_SR_EOQF_SHIFT (28U)
19450#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
19451#define SPI_SR_TXRXS_MASK (0x40000000U)
19452#define SPI_SR_TXRXS_SHIFT (30U)
19457#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
19458#define SPI_SR_TCF_MASK (0x80000000U)
19459#define SPI_SR_TCF_SHIFT (31U)
19464#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
19469#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
19470#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
19475#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
19476#define SPI_RSER_RFDF_RE_MASK (0x20000U)
19477#define SPI_RSER_RFDF_RE_SHIFT (17U)
19482#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
19483#define SPI_RSER_RFOF_RE_MASK (0x80000U)
19484#define SPI_RSER_RFOF_RE_SHIFT (19U)
19489#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
19490#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
19491#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
19496#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
19497#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
19498#define SPI_RSER_TFFF_RE_SHIFT (25U)
19503#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
19504#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
19505#define SPI_RSER_TFUF_RE_SHIFT (27U)
19510#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
19511#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
19512#define SPI_RSER_EOQF_RE_SHIFT (28U)
19517#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
19518#define SPI_RSER_TCF_RE_MASK (0x80000000U)
19519#define SPI_RSER_TCF_RE_SHIFT (31U)
19524#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
19529#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
19530#define SPI_PUSHR_TXDATA_SHIFT (0U)
19531#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
19532#define SPI_PUSHR_PCS_MASK (0x3F0000U)
19533#define SPI_PUSHR_PCS_SHIFT (16U)
19538#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
19539#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
19540#define SPI_PUSHR_CTCNT_SHIFT (26U)
19545#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
19546#define SPI_PUSHR_EOQ_MASK (0x8000000U)
19547#define SPI_PUSHR_EOQ_SHIFT (27U)
19552#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
19553#define SPI_PUSHR_CTAS_MASK (0x70000000U)
19554#define SPI_PUSHR_CTAS_SHIFT (28U)
19565#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
19566#define SPI_PUSHR_CONT_MASK (0x80000000U)
19567#define SPI_PUSHR_CONT_SHIFT (31U)
19572#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
19577#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
19578#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
19579#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
19584#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
19585#define SPI_POPR_RXDATA_SHIFT (0U)
19586#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
19591#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
19592#define SPI_TXFR0_TXDATA_SHIFT (0U)
19593#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
19594#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
19595#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
19596#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
19601#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
19602#define SPI_TXFR1_TXDATA_SHIFT (0U)
19603#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
19604#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
19605#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
19606#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
19611#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
19612#define SPI_TXFR2_TXDATA_SHIFT (0U)
19613#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
19614#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
19615#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
19616#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
19621#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
19622#define SPI_TXFR3_TXDATA_SHIFT (0U)
19623#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
19624#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
19625#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
19626#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
19631#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
19632#define SPI_RXFR0_RXDATA_SHIFT (0U)
19633#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
19638#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
19639#define SPI_RXFR1_RXDATA_SHIFT (0U)
19640#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
19645#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
19646#define SPI_RXFR2_RXDATA_SHIFT (0U)
19647#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
19652#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
19653#define SPI_RXFR3_RXDATA_SHIFT (0U)
19654#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
19660 /* end of group SPI_Register_Masks */
19661
19662
19663/* SPI - Peripheral instance base addresses */
19665#define SPI0_BASE (0x4002C000u)
19667#define SPI0 ((SPI_Type *)SPI0_BASE)
19669#define SPI1_BASE (0x4002D000u)
19671#define SPI1 ((SPI_Type *)SPI1_BASE)
19673#define SPI2_BASE (0x400AC000u)
19675#define SPI2 ((SPI_Type *)SPI2_BASE)
19677#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
19679#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
19681#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
19682
19685 /* end of group SPI_Peripheral_Access_Layer */
19686
19687
19688/* ----------------------------------------------------------------------------
19689 -- SYSMPU Peripheral Access Layer
19690 ---------------------------------------------------------------------------- */
19691
19698typedef struct {
19699 __IO uint32_t CESR;
19700 uint8_t RESERVED_0[12];
19701 struct { /* offset: 0x10, array step: 0x8 */
19702 __I uint32_t EAR;
19703 __I uint32_t EDR;
19704 } SP[5];
19705 uint8_t RESERVED_1[968];
19706 __IO uint32_t WORD[12][4];
19707 uint8_t RESERVED_2[832];
19708 __IO uint32_t RGDAAC[12];
19709} SYSMPU_Type;
19710
19711/* ----------------------------------------------------------------------------
19712 -- SYSMPU Register Masks
19713 ---------------------------------------------------------------------------- */
19714
19722#define SYSMPU_CESR_VLD_MASK (0x1U)
19723#define SYSMPU_CESR_VLD_SHIFT (0U)
19728#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
19729#define SYSMPU_CESR_NRGD_MASK (0xF00U)
19730#define SYSMPU_CESR_NRGD_SHIFT (8U)
19736#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
19737#define SYSMPU_CESR_NSP_MASK (0xF000U)
19738#define SYSMPU_CESR_NSP_SHIFT (12U)
19739#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
19740#define SYSMPU_CESR_HRL_MASK (0xF0000U)
19741#define SYSMPU_CESR_HRL_SHIFT (16U)
19742#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
19743#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
19744#define SYSMPU_CESR_SPERR_SHIFT (27U)
19749#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
19754#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
19755#define SYSMPU_EAR_EADDR_SHIFT (0U)
19756#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
19759/* The count of SYSMPU_EAR */
19760#define SYSMPU_EAR_COUNT (5U)
19761
19764#define SYSMPU_EDR_ERW_MASK (0x1U)
19765#define SYSMPU_EDR_ERW_SHIFT (0U)
19770#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
19771#define SYSMPU_EDR_EATTR_MASK (0xEU)
19772#define SYSMPU_EDR_EATTR_SHIFT (1U)
19779#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
19780#define SYSMPU_EDR_EMN_MASK (0xF0U)
19781#define SYSMPU_EDR_EMN_SHIFT (4U)
19782#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
19783#define SYSMPU_EDR_EPID_MASK (0xFF00U)
19784#define SYSMPU_EDR_EPID_SHIFT (8U)
19785#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
19786#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
19787#define SYSMPU_EDR_EACD_SHIFT (16U)
19788#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
19791/* The count of SYSMPU_EDR */
19792#define SYSMPU_EDR_COUNT (5U)
19793
19796#define SYSMPU_WORD_M0UM_MASK (0x7U)
19797#define SYSMPU_WORD_M0UM_SHIFT (0U)
19798#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
19799#define SYSMPU_WORD_VLD_MASK (0x1U)
19800#define SYSMPU_WORD_VLD_SHIFT (0U)
19805#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
19806#define SYSMPU_WORD_M0SM_MASK (0x18U)
19807#define SYSMPU_WORD_M0SM_SHIFT (3U)
19808#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
19809#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
19810#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
19811#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
19812#define SYSMPU_WORD_M0PE_MASK (0x20U)
19813#define SYSMPU_WORD_M0PE_SHIFT (5U)
19814#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
19815#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
19816#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
19817#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
19818#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
19819#define SYSMPU_WORD_M1UM_SHIFT (6U)
19820#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
19821#define SYSMPU_WORD_M1SM_MASK (0x600U)
19822#define SYSMPU_WORD_M1SM_SHIFT (9U)
19823#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
19824#define SYSMPU_WORD_M1PE_MASK (0x800U)
19825#define SYSMPU_WORD_M1PE_SHIFT (11U)
19826#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
19827#define SYSMPU_WORD_M2UM_MASK (0x7000U)
19828#define SYSMPU_WORD_M2UM_SHIFT (12U)
19829#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
19830#define SYSMPU_WORD_M2SM_MASK (0x18000U)
19831#define SYSMPU_WORD_M2SM_SHIFT (15U)
19832#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
19833#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
19834#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
19835#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
19836#define SYSMPU_WORD_M2PE_MASK (0x20000U)
19837#define SYSMPU_WORD_M2PE_SHIFT (17U)
19838#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
19839#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
19840#define SYSMPU_WORD_M3UM_SHIFT (18U)
19845#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
19846#define SYSMPU_WORD_M3SM_MASK (0x600000U)
19847#define SYSMPU_WORD_M3SM_SHIFT (21U)
19854#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
19855#define SYSMPU_WORD_M3PE_MASK (0x800000U)
19856#define SYSMPU_WORD_M3PE_SHIFT (23U)
19861#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
19862#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
19863#define SYSMPU_WORD_M4WE_SHIFT (24U)
19868#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
19869#define SYSMPU_WORD_PID_MASK (0xFF000000U)
19870#define SYSMPU_WORD_PID_SHIFT (24U)
19871#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
19872#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
19873#define SYSMPU_WORD_M4RE_SHIFT (25U)
19878#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
19879#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
19880#define SYSMPU_WORD_M5WE_SHIFT (26U)
19885#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
19886#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
19887#define SYSMPU_WORD_M5RE_SHIFT (27U)
19892#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
19893#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
19894#define SYSMPU_WORD_M6WE_SHIFT (28U)
19899#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
19900#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
19901#define SYSMPU_WORD_M6RE_SHIFT (29U)
19906#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
19907#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
19908#define SYSMPU_WORD_M7WE_SHIFT (30U)
19913#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
19914#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
19915#define SYSMPU_WORD_M7RE_SHIFT (31U)
19920#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
19923/* The count of SYSMPU_WORD */
19924#define SYSMPU_WORD_COUNT (12U)
19925
19926/* The count of SYSMPU_WORD */
19927#define SYSMPU_WORD_COUNT2 (4U)
19928
19931#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
19932#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
19933#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
19934#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
19935#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
19936#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
19937#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
19938#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
19939#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
19940#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
19941#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
19942#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
19943#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
19944#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
19945#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
19946#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
19947#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
19948#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
19949#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
19950#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
19951#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
19952#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
19953#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
19954#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
19955#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
19956#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
19957#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
19958#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
19959#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
19964#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
19965#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
19966#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
19973#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
19974#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
19975#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
19980#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
19981#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
19982#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
19987#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
19988#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
19989#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
19994#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
19995#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
19996#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
20001#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
20002#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
20003#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
20008#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
20009#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
20010#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
20015#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
20016#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
20017#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
20022#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
20023#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
20024#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
20029#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
20030#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
20031#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
20036#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
20039/* The count of SYSMPU_RGDAAC */
20040#define SYSMPU_RGDAAC_COUNT (12U)
20041
20042
20045 /* end of group SYSMPU_Register_Masks */
20046
20047
20048/* SYSMPU - Peripheral instance base addresses */
20050#define SYSMPU_BASE (0x4000D000u)
20052#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
20054#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
20056#define SYSMPU_BASE_PTRS { SYSMPU }
20057
20060 /* end of group SYSMPU_Peripheral_Access_Layer */
20061
20062
20063/* ----------------------------------------------------------------------------
20064 -- UART Peripheral Access Layer
20065 ---------------------------------------------------------------------------- */
20066
20073typedef struct {
20074 __IO uint8_t BDH;
20075 __IO uint8_t BDL;
20076 __IO uint8_t C1;
20077 __IO uint8_t C2;
20078 __I uint8_t S1;
20079 __IO uint8_t S2;
20080 __IO uint8_t C3;
20081 __IO uint8_t D;
20082 __IO uint8_t MA1;
20083 __IO uint8_t MA2;
20084 __IO uint8_t C4;
20085 __IO uint8_t C5;
20086 __I uint8_t ED;
20087 __IO uint8_t MODEM;
20088 __IO uint8_t IR;
20089 uint8_t RESERVED_0[1];
20090 __IO uint8_t PFIFO;
20091 __IO uint8_t CFIFO;
20092 __IO uint8_t SFIFO;
20093 __IO uint8_t TWFIFO;
20094 __I uint8_t TCFIFO;
20095 __IO uint8_t RWFIFO;
20096 __I uint8_t RCFIFO;
20097 uint8_t RESERVED_1[1];
20098 __IO uint8_t C7816;
20099 __IO uint8_t IE7816;
20100 __IO uint8_t IS7816;
20101 union { /* offset: 0x1B */
20102 __IO uint8_t WP7816T0;
20103 __IO uint8_t WP7816T1;
20104 };
20105 __IO uint8_t WN7816;
20106 __IO uint8_t WF7816;
20107 __IO uint8_t ET7816;
20108 __IO uint8_t TL7816;
20109} UART_Type;
20110
20111/* ----------------------------------------------------------------------------
20112 -- UART Register Masks
20113 ---------------------------------------------------------------------------- */
20114
20122#define UART_BDH_SBR_MASK (0x1FU)
20123#define UART_BDH_SBR_SHIFT (0U)
20124#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
20125#define UART_BDH_SBNS_MASK (0x20U)
20126#define UART_BDH_SBNS_SHIFT (5U)
20131#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
20132#define UART_BDH_RXEDGIE_MASK (0x40U)
20133#define UART_BDH_RXEDGIE_SHIFT (6U)
20138#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
20139#define UART_BDH_LBKDIE_MASK (0x80U)
20140#define UART_BDH_LBKDIE_SHIFT (7U)
20145#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
20150#define UART_BDL_SBR_MASK (0xFFU)
20151#define UART_BDL_SBR_SHIFT (0U)
20152#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
20157#define UART_C1_PT_MASK (0x1U)
20158#define UART_C1_PT_SHIFT (0U)
20163#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
20164#define UART_C1_PE_MASK (0x2U)
20165#define UART_C1_PE_SHIFT (1U)
20170#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
20171#define UART_C1_ILT_MASK (0x4U)
20172#define UART_C1_ILT_SHIFT (2U)
20177#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
20178#define UART_C1_WAKE_MASK (0x8U)
20179#define UART_C1_WAKE_SHIFT (3U)
20184#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
20185#define UART_C1_M_MASK (0x10U)
20186#define UART_C1_M_SHIFT (4U)
20191#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
20192#define UART_C1_RSRC_MASK (0x20U)
20193#define UART_C1_RSRC_SHIFT (5U)
20198#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
20199#define UART_C1_UARTSWAI_MASK (0x40U)
20200#define UART_C1_UARTSWAI_SHIFT (6U)
20205#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
20206#define UART_C1_LOOPS_MASK (0x80U)
20207#define UART_C1_LOOPS_SHIFT (7U)
20212#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
20217#define UART_C2_SBK_MASK (0x1U)
20218#define UART_C2_SBK_SHIFT (0U)
20223#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
20224#define UART_C2_RWU_MASK (0x2U)
20225#define UART_C2_RWU_SHIFT (1U)
20230#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
20231#define UART_C2_RE_MASK (0x4U)
20232#define UART_C2_RE_SHIFT (2U)
20237#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
20238#define UART_C2_TE_MASK (0x8U)
20239#define UART_C2_TE_SHIFT (3U)
20244#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
20245#define UART_C2_ILIE_MASK (0x10U)
20246#define UART_C2_ILIE_SHIFT (4U)
20251#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
20252#define UART_C2_RIE_MASK (0x20U)
20253#define UART_C2_RIE_SHIFT (5U)
20258#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
20259#define UART_C2_TCIE_MASK (0x40U)
20260#define UART_C2_TCIE_SHIFT (6U)
20265#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
20266#define UART_C2_TIE_MASK (0x80U)
20267#define UART_C2_TIE_SHIFT (7U)
20272#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
20277#define UART_S1_PF_MASK (0x1U)
20278#define UART_S1_PF_SHIFT (0U)
20283#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
20284#define UART_S1_FE_MASK (0x2U)
20285#define UART_S1_FE_SHIFT (1U)
20290#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
20291#define UART_S1_NF_MASK (0x4U)
20292#define UART_S1_NF_SHIFT (2U)
20297#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
20298#define UART_S1_OR_MASK (0x8U)
20299#define UART_S1_OR_SHIFT (3U)
20304#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
20305#define UART_S1_IDLE_MASK (0x10U)
20306#define UART_S1_IDLE_SHIFT (4U)
20311#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
20312#define UART_S1_RDRF_MASK (0x20U)
20313#define UART_S1_RDRF_SHIFT (5U)
20318#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
20319#define UART_S1_TC_MASK (0x40U)
20320#define UART_S1_TC_SHIFT (6U)
20325#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
20326#define UART_S1_TDRE_MASK (0x80U)
20327#define UART_S1_TDRE_SHIFT (7U)
20332#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
20337#define UART_S2_RAF_MASK (0x1U)
20338#define UART_S2_RAF_SHIFT (0U)
20343#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
20344#define UART_S2_LBKDE_MASK (0x2U)
20345#define UART_S2_LBKDE_SHIFT (1U)
20350#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
20351#define UART_S2_BRK13_MASK (0x4U)
20352#define UART_S2_BRK13_SHIFT (2U)
20357#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
20358#define UART_S2_RWUID_MASK (0x8U)
20359#define UART_S2_RWUID_SHIFT (3U)
20364#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
20365#define UART_S2_RXINV_MASK (0x10U)
20366#define UART_S2_RXINV_SHIFT (4U)
20371#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
20372#define UART_S2_MSBF_MASK (0x20U)
20373#define UART_S2_MSBF_SHIFT (5U)
20378#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
20379#define UART_S2_RXEDGIF_MASK (0x40U)
20380#define UART_S2_RXEDGIF_SHIFT (6U)
20385#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
20386#define UART_S2_LBKDIF_MASK (0x80U)
20387#define UART_S2_LBKDIF_SHIFT (7U)
20392#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
20397#define UART_C3_PEIE_MASK (0x1U)
20398#define UART_C3_PEIE_SHIFT (0U)
20403#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
20404#define UART_C3_FEIE_MASK (0x2U)
20405#define UART_C3_FEIE_SHIFT (1U)
20410#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
20411#define UART_C3_NEIE_MASK (0x4U)
20412#define UART_C3_NEIE_SHIFT (2U)
20417#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
20418#define UART_C3_ORIE_MASK (0x8U)
20419#define UART_C3_ORIE_SHIFT (3U)
20424#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
20425#define UART_C3_TXINV_MASK (0x10U)
20426#define UART_C3_TXINV_SHIFT (4U)
20431#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
20432#define UART_C3_TXDIR_MASK (0x20U)
20433#define UART_C3_TXDIR_SHIFT (5U)
20438#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
20439#define UART_C3_T8_MASK (0x40U)
20440#define UART_C3_T8_SHIFT (6U)
20441#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
20442#define UART_C3_R8_MASK (0x80U)
20443#define UART_C3_R8_SHIFT (7U)
20444#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
20449#define UART_D_RT_MASK (0xFFU)
20450#define UART_D_RT_SHIFT (0U)
20451#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
20456#define UART_MA1_MA_MASK (0xFFU)
20457#define UART_MA1_MA_SHIFT (0U)
20458#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
20463#define UART_MA2_MA_MASK (0xFFU)
20464#define UART_MA2_MA_SHIFT (0U)
20465#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
20470#define UART_C4_BRFA_MASK (0x1FU)
20471#define UART_C4_BRFA_SHIFT (0U)
20472#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
20473#define UART_C4_M10_MASK (0x20U)
20474#define UART_C4_M10_SHIFT (5U)
20479#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
20480#define UART_C4_MAEN2_MASK (0x40U)
20481#define UART_C4_MAEN2_SHIFT (6U)
20486#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
20487#define UART_C4_MAEN1_MASK (0x80U)
20488#define UART_C4_MAEN1_SHIFT (7U)
20493#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
20498#define UART_C5_LBKDDMAS_MASK (0x8U)
20499#define UART_C5_LBKDDMAS_SHIFT (3U)
20504#define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK)
20505#define UART_C5_ILDMAS_MASK (0x10U)
20506#define UART_C5_ILDMAS_SHIFT (4U)
20511#define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK)
20512#define UART_C5_RDMAS_MASK (0x20U)
20513#define UART_C5_RDMAS_SHIFT (5U)
20518#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
20519#define UART_C5_TCDMAS_MASK (0x40U)
20520#define UART_C5_TCDMAS_SHIFT (6U)
20525#define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK)
20526#define UART_C5_TDMAS_MASK (0x80U)
20527#define UART_C5_TDMAS_SHIFT (7U)
20532#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
20537#define UART_ED_PARITYE_MASK (0x40U)
20538#define UART_ED_PARITYE_SHIFT (6U)
20543#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
20544#define UART_ED_NOISY_MASK (0x80U)
20545#define UART_ED_NOISY_SHIFT (7U)
20550#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
20555#define UART_MODEM_TXCTSE_MASK (0x1U)
20556#define UART_MODEM_TXCTSE_SHIFT (0U)
20561#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
20562#define UART_MODEM_TXRTSE_MASK (0x2U)
20563#define UART_MODEM_TXRTSE_SHIFT (1U)
20568#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
20569#define UART_MODEM_TXRTSPOL_MASK (0x4U)
20570#define UART_MODEM_TXRTSPOL_SHIFT (2U)
20575#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
20576#define UART_MODEM_RXRTSE_MASK (0x8U)
20577#define UART_MODEM_RXRTSE_SHIFT (3U)
20582#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
20587#define UART_IR_TNP_MASK (0x3U)
20588#define UART_IR_TNP_SHIFT (0U)
20595#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
20596#define UART_IR_IREN_MASK (0x4U)
20597#define UART_IR_IREN_SHIFT (2U)
20602#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
20607#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
20608#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
20619#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
20620#define UART_PFIFO_RXFE_MASK (0x8U)
20621#define UART_PFIFO_RXFE_SHIFT (3U)
20626#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
20627#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
20628#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
20639#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
20640#define UART_PFIFO_TXFE_MASK (0x80U)
20641#define UART_PFIFO_TXFE_SHIFT (7U)
20646#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
20651#define UART_CFIFO_RXUFE_MASK (0x1U)
20652#define UART_CFIFO_RXUFE_SHIFT (0U)
20657#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
20658#define UART_CFIFO_TXOFE_MASK (0x2U)
20659#define UART_CFIFO_TXOFE_SHIFT (1U)
20664#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
20665#define UART_CFIFO_RXOFE_MASK (0x4U)
20666#define UART_CFIFO_RXOFE_SHIFT (2U)
20671#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
20672#define UART_CFIFO_RXFLUSH_MASK (0x40U)
20673#define UART_CFIFO_RXFLUSH_SHIFT (6U)
20678#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
20679#define UART_CFIFO_TXFLUSH_MASK (0x80U)
20680#define UART_CFIFO_TXFLUSH_SHIFT (7U)
20685#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
20690#define UART_SFIFO_RXUF_MASK (0x1U)
20691#define UART_SFIFO_RXUF_SHIFT (0U)
20696#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
20697#define UART_SFIFO_TXOF_MASK (0x2U)
20698#define UART_SFIFO_TXOF_SHIFT (1U)
20703#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
20704#define UART_SFIFO_RXOF_MASK (0x4U)
20705#define UART_SFIFO_RXOF_SHIFT (2U)
20710#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
20711#define UART_SFIFO_RXEMPT_MASK (0x40U)
20712#define UART_SFIFO_RXEMPT_SHIFT (6U)
20717#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
20718#define UART_SFIFO_TXEMPT_MASK (0x80U)
20719#define UART_SFIFO_TXEMPT_SHIFT (7U)
20724#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
20729#define UART_TWFIFO_TXWATER_MASK (0xFFU)
20730#define UART_TWFIFO_TXWATER_SHIFT (0U)
20731#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
20736#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
20737#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
20738#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
20743#define UART_RWFIFO_RXWATER_MASK (0xFFU)
20744#define UART_RWFIFO_RXWATER_SHIFT (0U)
20745#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
20750#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
20751#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
20752#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
20757#define UART_C7816_ISO_7816E_MASK (0x1U)
20758#define UART_C7816_ISO_7816E_SHIFT (0U)
20763#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
20764#define UART_C7816_TTYPE_MASK (0x2U)
20765#define UART_C7816_TTYPE_SHIFT (1U)
20770#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
20771#define UART_C7816_INIT_MASK (0x4U)
20772#define UART_C7816_INIT_SHIFT (2U)
20777#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
20778#define UART_C7816_ANACK_MASK (0x8U)
20779#define UART_C7816_ANACK_SHIFT (3U)
20784#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
20785#define UART_C7816_ONACK_MASK (0x10U)
20786#define UART_C7816_ONACK_SHIFT (4U)
20791#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
20796#define UART_IE7816_RXTE_MASK (0x1U)
20797#define UART_IE7816_RXTE_SHIFT (0U)
20802#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
20803#define UART_IE7816_TXTE_MASK (0x2U)
20804#define UART_IE7816_TXTE_SHIFT (1U)
20809#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
20810#define UART_IE7816_GTVE_MASK (0x4U)
20811#define UART_IE7816_GTVE_SHIFT (2U)
20816#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
20817#define UART_IE7816_INITDE_MASK (0x10U)
20818#define UART_IE7816_INITDE_SHIFT (4U)
20823#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
20824#define UART_IE7816_BWTE_MASK (0x20U)
20825#define UART_IE7816_BWTE_SHIFT (5U)
20830#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
20831#define UART_IE7816_CWTE_MASK (0x40U)
20832#define UART_IE7816_CWTE_SHIFT (6U)
20837#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
20838#define UART_IE7816_WTE_MASK (0x80U)
20839#define UART_IE7816_WTE_SHIFT (7U)
20844#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
20849#define UART_IS7816_RXT_MASK (0x1U)
20850#define UART_IS7816_RXT_SHIFT (0U)
20855#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
20856#define UART_IS7816_TXT_MASK (0x2U)
20857#define UART_IS7816_TXT_SHIFT (1U)
20862#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
20863#define UART_IS7816_GTV_MASK (0x4U)
20864#define UART_IS7816_GTV_SHIFT (2U)
20869#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
20870#define UART_IS7816_INITD_MASK (0x10U)
20871#define UART_IS7816_INITD_SHIFT (4U)
20876#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
20877#define UART_IS7816_BWT_MASK (0x20U)
20878#define UART_IS7816_BWT_SHIFT (5U)
20883#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
20884#define UART_IS7816_CWT_MASK (0x40U)
20885#define UART_IS7816_CWT_SHIFT (6U)
20890#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
20891#define UART_IS7816_WT_MASK (0x80U)
20892#define UART_IS7816_WT_SHIFT (7U)
20897#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
20902#define UART_WP7816T0_WI_MASK (0xFFU)
20903#define UART_WP7816T0_WI_SHIFT (0U)
20904#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
20909#define UART_WP7816T1_BWI_MASK (0xFU)
20910#define UART_WP7816T1_BWI_SHIFT (0U)
20911#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
20912#define UART_WP7816T1_CWI_MASK (0xF0U)
20913#define UART_WP7816T1_CWI_SHIFT (4U)
20914#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
20919#define UART_WN7816_GTN_MASK (0xFFU)
20920#define UART_WN7816_GTN_SHIFT (0U)
20921#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
20926#define UART_WF7816_GTFD_MASK (0xFFU)
20927#define UART_WF7816_GTFD_SHIFT (0U)
20928#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
20933#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
20934#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
20935#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
20936#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
20937#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
20942#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
20947#define UART_TL7816_TLEN_MASK (0xFFU)
20948#define UART_TL7816_TLEN_SHIFT (0U)
20949#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
20955 /* end of group UART_Register_Masks */
20956
20957
20958/* UART - Peripheral instance base addresses */
20960#define UART0_BASE (0x4006A000u)
20962#define UART0 ((UART_Type *)UART0_BASE)
20964#define UART1_BASE (0x4006B000u)
20966#define UART1 ((UART_Type *)UART1_BASE)
20968#define UART2_BASE (0x4006C000u)
20970#define UART2 ((UART_Type *)UART2_BASE)
20972#define UART3_BASE (0x4006D000u)
20974#define UART3 ((UART_Type *)UART3_BASE)
20976#define UART4_BASE (0x400EA000u)
20978#define UART4 ((UART_Type *)UART4_BASE)
20980#define UART5_BASE (0x400EB000u)
20982#define UART5 ((UART_Type *)UART5_BASE)
20984#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
20986#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
20988#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
20989#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
20990#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
20991
20994 /* end of group UART_Peripheral_Access_Layer */
20995
20996
20997/* ----------------------------------------------------------------------------
20998 -- USB Peripheral Access Layer
20999 ---------------------------------------------------------------------------- */
21000
21007typedef struct {
21008 __I uint8_t PERID;
21009 uint8_t RESERVED_0[3];
21010 __I uint8_t IDCOMP;
21011 uint8_t RESERVED_1[3];
21012 __I uint8_t REV;
21013 uint8_t RESERVED_2[3];
21014 __I uint8_t ADDINFO;
21015 uint8_t RESERVED_3[3];
21016 __IO uint8_t OTGISTAT;
21017 uint8_t RESERVED_4[3];
21018 __IO uint8_t OTGICR;
21019 uint8_t RESERVED_5[3];
21020 __IO uint8_t OTGSTAT;
21021 uint8_t RESERVED_6[3];
21022 __IO uint8_t OTGCTL;
21023 uint8_t RESERVED_7[99];
21024 __IO uint8_t ISTAT;
21025 uint8_t RESERVED_8[3];
21026 __IO uint8_t INTEN;
21027 uint8_t RESERVED_9[3];
21028 __IO uint8_t ERRSTAT;
21029 uint8_t RESERVED_10[3];
21030 __IO uint8_t ERREN;
21031 uint8_t RESERVED_11[3];
21032 __I uint8_t STAT;
21033 uint8_t RESERVED_12[3];
21034 __IO uint8_t CTL;
21035 uint8_t RESERVED_13[3];
21036 __IO uint8_t ADDR;
21037 uint8_t RESERVED_14[3];
21038 __IO uint8_t BDTPAGE1;
21039 uint8_t RESERVED_15[3];
21040 __IO uint8_t FRMNUML;
21041 uint8_t RESERVED_16[3];
21042 __IO uint8_t FRMNUMH;
21043 uint8_t RESERVED_17[3];
21044 __IO uint8_t TOKEN;
21045 uint8_t RESERVED_18[3];
21046 __IO uint8_t SOFTHLD;
21047 uint8_t RESERVED_19[3];
21048 __IO uint8_t BDTPAGE2;
21049 uint8_t RESERVED_20[3];
21050 __IO uint8_t BDTPAGE3;
21051 uint8_t RESERVED_21[11];
21052 struct { /* offset: 0xC0, array step: 0x4 */
21053 __IO uint8_t ENDPT;
21054 uint8_t RESERVED_0[3];
21055 } ENDPOINT[16];
21056 __IO uint8_t USBCTRL;
21057 uint8_t RESERVED_22[3];
21058 __I uint8_t OBSERVE;
21059 uint8_t RESERVED_23[3];
21060 __IO uint8_t CONTROL;
21061 uint8_t RESERVED_24[3];
21062 __IO uint8_t USBTRC0;
21063 uint8_t RESERVED_25[7];
21064 __IO uint8_t USBFRMADJUST;
21065 uint8_t RESERVED_26[43];
21066 __IO uint8_t CLK_RECOVER_CTRL;
21067 uint8_t RESERVED_27[3];
21068 __IO uint8_t CLK_RECOVER_IRC_EN;
21069 uint8_t RESERVED_28[23];
21070 __IO uint8_t CLK_RECOVER_INT_STATUS;
21071} USB_Type;
21072
21073/* ----------------------------------------------------------------------------
21074 -- USB Register Masks
21075 ---------------------------------------------------------------------------- */
21076
21084#define USB_PERID_ID_MASK (0x3FU)
21085#define USB_PERID_ID_SHIFT (0U)
21086#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
21091#define USB_IDCOMP_NID_MASK (0x3FU)
21092#define USB_IDCOMP_NID_SHIFT (0U)
21093#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
21098#define USB_REV_REV_MASK (0xFFU)
21099#define USB_REV_REV_SHIFT (0U)
21100#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
21105#define USB_ADDINFO_IEHOST_MASK (0x1U)
21106#define USB_ADDINFO_IEHOST_SHIFT (0U)
21107#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
21108#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
21109#define USB_ADDINFO_IRQNUM_SHIFT (3U)
21110#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
21115#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
21116#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
21117#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
21118#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
21119#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
21120#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
21121#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
21122#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
21123#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
21124#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
21125#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
21126#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
21127#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
21128#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
21129#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
21130#define USB_OTGISTAT_IDCHG_MASK (0x80U)
21131#define USB_OTGISTAT_IDCHG_SHIFT (7U)
21132#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
21137#define USB_OTGICR_AVBUSEN_MASK (0x1U)
21138#define USB_OTGICR_AVBUSEN_SHIFT (0U)
21143#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
21144#define USB_OTGICR_BSESSEN_MASK (0x4U)
21145#define USB_OTGICR_BSESSEN_SHIFT (2U)
21150#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
21151#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
21152#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
21157#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
21158#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
21159#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
21164#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
21165#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
21166#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
21171#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
21172#define USB_OTGICR_IDEN_MASK (0x80U)
21173#define USB_OTGICR_IDEN_SHIFT (7U)
21178#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
21183#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
21184#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
21189#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
21190#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
21191#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
21196#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
21197#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
21198#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
21203#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
21204#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
21205#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
21210#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
21211#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
21212#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
21213#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
21214#define USB_OTGSTAT_ID_MASK (0x80U)
21215#define USB_OTGSTAT_ID_SHIFT (7U)
21220#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
21225#define USB_OTGCTL_OTGEN_MASK (0x4U)
21226#define USB_OTGCTL_OTGEN_SHIFT (2U)
21231#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
21232#define USB_OTGCTL_DMLOW_MASK (0x10U)
21233#define USB_OTGCTL_DMLOW_SHIFT (4U)
21238#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
21239#define USB_OTGCTL_DPLOW_MASK (0x20U)
21240#define USB_OTGCTL_DPLOW_SHIFT (5U)
21245#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
21246#define USB_OTGCTL_DPHIGH_MASK (0x80U)
21247#define USB_OTGCTL_DPHIGH_SHIFT (7U)
21252#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
21257#define USB_ISTAT_USBRST_MASK (0x1U)
21258#define USB_ISTAT_USBRST_SHIFT (0U)
21259#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
21260#define USB_ISTAT_ERROR_MASK (0x2U)
21261#define USB_ISTAT_ERROR_SHIFT (1U)
21262#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
21263#define USB_ISTAT_SOFTOK_MASK (0x4U)
21264#define USB_ISTAT_SOFTOK_SHIFT (2U)
21265#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
21266#define USB_ISTAT_TOKDNE_MASK (0x8U)
21267#define USB_ISTAT_TOKDNE_SHIFT (3U)
21268#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
21269#define USB_ISTAT_SLEEP_MASK (0x10U)
21270#define USB_ISTAT_SLEEP_SHIFT (4U)
21271#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
21272#define USB_ISTAT_RESUME_MASK (0x20U)
21273#define USB_ISTAT_RESUME_SHIFT (5U)
21274#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
21275#define USB_ISTAT_ATTACH_MASK (0x40U)
21276#define USB_ISTAT_ATTACH_SHIFT (6U)
21277#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
21278#define USB_ISTAT_STALL_MASK (0x80U)
21279#define USB_ISTAT_STALL_SHIFT (7U)
21280#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
21285#define USB_INTEN_USBRSTEN_MASK (0x1U)
21286#define USB_INTEN_USBRSTEN_SHIFT (0U)
21291#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
21292#define USB_INTEN_ERROREN_MASK (0x2U)
21293#define USB_INTEN_ERROREN_SHIFT (1U)
21298#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
21299#define USB_INTEN_SOFTOKEN_MASK (0x4U)
21300#define USB_INTEN_SOFTOKEN_SHIFT (2U)
21305#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
21306#define USB_INTEN_TOKDNEEN_MASK (0x8U)
21307#define USB_INTEN_TOKDNEEN_SHIFT (3U)
21312#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
21313#define USB_INTEN_SLEEPEN_MASK (0x10U)
21314#define USB_INTEN_SLEEPEN_SHIFT (4U)
21319#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
21320#define USB_INTEN_RESUMEEN_MASK (0x20U)
21321#define USB_INTEN_RESUMEEN_SHIFT (5U)
21326#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
21327#define USB_INTEN_ATTACHEN_MASK (0x40U)
21328#define USB_INTEN_ATTACHEN_SHIFT (6U)
21333#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
21334#define USB_INTEN_STALLEN_MASK (0x80U)
21335#define USB_INTEN_STALLEN_SHIFT (7U)
21340#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
21345#define USB_ERRSTAT_PIDERR_MASK (0x1U)
21346#define USB_ERRSTAT_PIDERR_SHIFT (0U)
21347#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
21348#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
21349#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
21350#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
21351#define USB_ERRSTAT_CRC16_MASK (0x4U)
21352#define USB_ERRSTAT_CRC16_SHIFT (2U)
21353#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
21354#define USB_ERRSTAT_DFN8_MASK (0x8U)
21355#define USB_ERRSTAT_DFN8_SHIFT (3U)
21356#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
21357#define USB_ERRSTAT_BTOERR_MASK (0x10U)
21358#define USB_ERRSTAT_BTOERR_SHIFT (4U)
21359#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
21360#define USB_ERRSTAT_DMAERR_MASK (0x20U)
21361#define USB_ERRSTAT_DMAERR_SHIFT (5U)
21362#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
21363#define USB_ERRSTAT_BTSERR_MASK (0x80U)
21364#define USB_ERRSTAT_BTSERR_SHIFT (7U)
21365#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
21370#define USB_ERREN_PIDERREN_MASK (0x1U)
21371#define USB_ERREN_PIDERREN_SHIFT (0U)
21376#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
21377#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
21378#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
21383#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
21384#define USB_ERREN_CRC16EN_MASK (0x4U)
21385#define USB_ERREN_CRC16EN_SHIFT (2U)
21390#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
21391#define USB_ERREN_DFN8EN_MASK (0x8U)
21392#define USB_ERREN_DFN8EN_SHIFT (3U)
21397#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
21398#define USB_ERREN_BTOERREN_MASK (0x10U)
21399#define USB_ERREN_BTOERREN_SHIFT (4U)
21404#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
21405#define USB_ERREN_DMAERREN_MASK (0x20U)
21406#define USB_ERREN_DMAERREN_SHIFT (5U)
21411#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
21412#define USB_ERREN_BTSERREN_MASK (0x80U)
21413#define USB_ERREN_BTSERREN_SHIFT (7U)
21418#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
21423#define USB_STAT_ODD_MASK (0x4U)
21424#define USB_STAT_ODD_SHIFT (2U)
21425#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
21426#define USB_STAT_TX_MASK (0x8U)
21427#define USB_STAT_TX_SHIFT (3U)
21432#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
21433#define USB_STAT_ENDP_MASK (0xF0U)
21434#define USB_STAT_ENDP_SHIFT (4U)
21435#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
21440#define USB_CTL_USBENSOFEN_MASK (0x1U)
21441#define USB_CTL_USBENSOFEN_SHIFT (0U)
21446#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
21447#define USB_CTL_ODDRST_MASK (0x2U)
21448#define USB_CTL_ODDRST_SHIFT (1U)
21449#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
21450#define USB_CTL_RESUME_MASK (0x4U)
21451#define USB_CTL_RESUME_SHIFT (2U)
21452#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
21453#define USB_CTL_HOSTMODEEN_MASK (0x8U)
21454#define USB_CTL_HOSTMODEEN_SHIFT (3U)
21455#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
21456#define USB_CTL_RESET_MASK (0x10U)
21457#define USB_CTL_RESET_SHIFT (4U)
21458#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
21459#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
21460#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
21461#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
21462#define USB_CTL_SE0_MASK (0x40U)
21463#define USB_CTL_SE0_SHIFT (6U)
21464#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
21465#define USB_CTL_JSTATE_MASK (0x80U)
21466#define USB_CTL_JSTATE_SHIFT (7U)
21467#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
21472#define USB_ADDR_ADDR_MASK (0x7FU)
21473#define USB_ADDR_ADDR_SHIFT (0U)
21474#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
21475#define USB_ADDR_LSEN_MASK (0x80U)
21476#define USB_ADDR_LSEN_SHIFT (7U)
21477#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
21482#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
21483#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
21484#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
21489#define USB_FRMNUML_FRM_MASK (0xFFU)
21490#define USB_FRMNUML_FRM_SHIFT (0U)
21491#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
21496#define USB_FRMNUMH_FRM_MASK (0x7U)
21497#define USB_FRMNUMH_FRM_SHIFT (0U)
21498#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
21503#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
21504#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
21505#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
21506#define USB_TOKEN_TOKENPID_MASK (0xF0U)
21507#define USB_TOKEN_TOKENPID_SHIFT (4U)
21513#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
21518#define USB_SOFTHLD_CNT_MASK (0xFFU)
21519#define USB_SOFTHLD_CNT_SHIFT (0U)
21520#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
21525#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
21526#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
21527#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
21532#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
21533#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
21534#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
21539#define USB_ENDPT_EPHSHK_MASK (0x1U)
21540#define USB_ENDPT_EPHSHK_SHIFT (0U)
21541#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
21542#define USB_ENDPT_EPSTALL_MASK (0x2U)
21543#define USB_ENDPT_EPSTALL_SHIFT (1U)
21544#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
21545#define USB_ENDPT_EPTXEN_MASK (0x4U)
21546#define USB_ENDPT_EPTXEN_SHIFT (2U)
21547#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
21548#define USB_ENDPT_EPRXEN_MASK (0x8U)
21549#define USB_ENDPT_EPRXEN_SHIFT (3U)
21550#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
21551#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
21552#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
21553#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
21554#define USB_ENDPT_RETRYDIS_MASK (0x40U)
21555#define USB_ENDPT_RETRYDIS_SHIFT (6U)
21556#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
21557#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
21558#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
21559#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
21562/* The count of USB_ENDPT */
21563#define USB_ENDPT_COUNT (16U)
21564
21567#define USB_USBCTRL_PDE_MASK (0x40U)
21568#define USB_USBCTRL_PDE_SHIFT (6U)
21573#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
21574#define USB_USBCTRL_SUSP_MASK (0x80U)
21575#define USB_USBCTRL_SUSP_SHIFT (7U)
21580#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
21585#define USB_OBSERVE_DMPD_MASK (0x10U)
21586#define USB_OBSERVE_DMPD_SHIFT (4U)
21591#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
21592#define USB_OBSERVE_DPPD_MASK (0x40U)
21593#define USB_OBSERVE_DPPD_SHIFT (6U)
21598#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
21599#define USB_OBSERVE_DPPU_MASK (0x80U)
21600#define USB_OBSERVE_DPPU_SHIFT (7U)
21605#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
21610#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
21611#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
21616#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
21621#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
21622#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
21627#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
21628#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
21629#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
21634#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
21635#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
21636#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
21637#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
21638#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
21639#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
21644#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
21645#define USB_USBTRC0_USBRESET_MASK (0x80U)
21646#define USB_USBTRC0_USBRESET_SHIFT (7U)
21651#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
21656#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
21657#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
21658#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
21663#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
21664#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
21669#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
21670#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
21671#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
21676#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
21677#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
21678#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
21683#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
21688#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
21689#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
21694#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
21695#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
21696#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
21701#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
21706#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
21707#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
21712#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
21718 /* end of group USB_Register_Masks */
21719
21720
21721/* USB - Peripheral instance base addresses */
21723#define USB0_BASE (0x40072000u)
21725#define USB0 ((USB_Type *)USB0_BASE)
21727#define USB_BASE_ADDRS { USB0_BASE }
21729#define USB_BASE_PTRS { USB0 }
21731#define USB_IRQS { USB0_IRQn }
21732
21735 /* end of group USB_Peripheral_Access_Layer */
21736
21737
21738/* ----------------------------------------------------------------------------
21739 -- USBDCD Peripheral Access Layer
21740 ---------------------------------------------------------------------------- */
21741
21748typedef struct {
21749 __IO uint32_t CONTROL;
21750 __IO uint32_t CLOCK;
21751 __I uint32_t STATUS;
21752 uint8_t RESERVED_0[4];
21753 __IO uint32_t TIMER0;
21754 __IO uint32_t TIMER1;
21755 union { /* offset: 0x18 */
21756 __IO uint32_t TIMER2_BC11;
21757 __IO uint32_t TIMER2_BC12;
21758 };
21759} USBDCD_Type;
21760
21761/* ----------------------------------------------------------------------------
21762 -- USBDCD Register Masks
21763 ---------------------------------------------------------------------------- */
21764
21772#define USBDCD_CONTROL_IACK_MASK (0x1U)
21773#define USBDCD_CONTROL_IACK_SHIFT (0U)
21778#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
21779#define USBDCD_CONTROL_IF_MASK (0x100U)
21780#define USBDCD_CONTROL_IF_SHIFT (8U)
21785#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
21786#define USBDCD_CONTROL_IE_MASK (0x10000U)
21787#define USBDCD_CONTROL_IE_SHIFT (16U)
21792#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
21793#define USBDCD_CONTROL_BC12_MASK (0x20000U)
21794#define USBDCD_CONTROL_BC12_SHIFT (17U)
21799#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
21800#define USBDCD_CONTROL_START_MASK (0x1000000U)
21801#define USBDCD_CONTROL_START_SHIFT (24U)
21806#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
21807#define USBDCD_CONTROL_SR_MASK (0x2000000U)
21808#define USBDCD_CONTROL_SR_SHIFT (25U)
21813#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
21818#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
21819#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
21824#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
21825#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
21826#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
21827#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
21832#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
21833#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
21840#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
21841#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
21842#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
21849#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
21850#define USBDCD_STATUS_ERR_MASK (0x100000U)
21851#define USBDCD_STATUS_ERR_SHIFT (20U)
21856#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
21857#define USBDCD_STATUS_TO_MASK (0x200000U)
21858#define USBDCD_STATUS_TO_SHIFT (21U)
21863#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
21864#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
21865#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
21870#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
21875#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
21876#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
21877#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
21878#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
21879#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
21880#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
21885#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
21886#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
21887#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
21888#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
21889#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
21890#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
21895#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
21896#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
21897#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
21898#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
21899#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
21900#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
21905#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
21906#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
21907#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
21908#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
21909#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
21910#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
21916 /* end of group USBDCD_Register_Masks */
21917
21918
21919/* USBDCD - Peripheral instance base addresses */
21921#define USBDCD_BASE (0x40035000u)
21923#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
21925#define USBDCD_BASE_ADDRS { USBDCD_BASE }
21927#define USBDCD_BASE_PTRS { USBDCD }
21929#define USBDCD_IRQS { USBDCD_IRQn }
21930
21933 /* end of group USBDCD_Peripheral_Access_Layer */
21934
21935
21936/* ----------------------------------------------------------------------------
21937 -- VREF Peripheral Access Layer
21938 ---------------------------------------------------------------------------- */
21939
21946typedef struct {
21947 __IO uint8_t TRM;
21948 __IO uint8_t SC;
21949} VREF_Type;
21950
21951/* ----------------------------------------------------------------------------
21952 -- VREF Register Masks
21953 ---------------------------------------------------------------------------- */
21954
21962#define VREF_TRM_TRIM_MASK (0x3FU)
21963#define VREF_TRM_TRIM_SHIFT (0U)
21968#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
21969#define VREF_TRM_CHOPEN_MASK (0x40U)
21970#define VREF_TRM_CHOPEN_SHIFT (6U)
21975#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
21980#define VREF_SC_MODE_LV_MASK (0x3U)
21981#define VREF_SC_MODE_LV_SHIFT (0U)
21988#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
21989#define VREF_SC_VREFST_MASK (0x4U)
21990#define VREF_SC_VREFST_SHIFT (2U)
21995#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
21996#define VREF_SC_ICOMPEN_MASK (0x20U)
21997#define VREF_SC_ICOMPEN_SHIFT (5U)
22002#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
22003#define VREF_SC_REGEN_MASK (0x40U)
22004#define VREF_SC_REGEN_SHIFT (6U)
22009#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
22010#define VREF_SC_VREFEN_MASK (0x80U)
22011#define VREF_SC_VREFEN_SHIFT (7U)
22016#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
22022 /* end of group VREF_Register_Masks */
22023
22024
22025/* VREF - Peripheral instance base addresses */
22027#define VREF_BASE (0x40074000u)
22029#define VREF ((VREF_Type *)VREF_BASE)
22031#define VREF_BASE_ADDRS { VREF_BASE }
22033#define VREF_BASE_PTRS { VREF }
22034
22037 /* end of group VREF_Peripheral_Access_Layer */
22038
22039
22040/* ----------------------------------------------------------------------------
22041 -- WDOG Peripheral Access Layer
22042 ---------------------------------------------------------------------------- */
22043
22050typedef struct {
22051 __IO uint16_t STCTRLH;
22052 __IO uint16_t STCTRLL;
22053 __IO uint16_t TOVALH;
22054 __IO uint16_t TOVALL;
22055 __IO uint16_t WINH;
22056 __IO uint16_t WINL;
22057 __IO uint16_t REFRESH;
22058 __IO uint16_t UNLOCK;
22059 __IO uint16_t TMROUTH;
22060 __IO uint16_t TMROUTL;
22061 __IO uint16_t RSTCNT;
22062 __IO uint16_t PRESC;
22063} WDOG_Type;
22064
22065/* ----------------------------------------------------------------------------
22066 -- WDOG Register Masks
22067 ---------------------------------------------------------------------------- */
22068
22076#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
22077#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
22082#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
22083#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
22084#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
22089#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
22090#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
22091#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
22096#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
22097#define WDOG_STCTRLH_WINEN_MASK (0x8U)
22098#define WDOG_STCTRLH_WINEN_SHIFT (3U)
22103#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
22104#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
22105#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
22110#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
22111#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
22112#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
22117#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
22118#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
22119#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
22124#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
22125#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
22126#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
22131#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
22132#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
22133#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
22134#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
22135#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
22136#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
22141#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
22142#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
22143#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
22150#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
22151#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
22152#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
22157#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
22162#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
22163#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
22164#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
22169#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
22170#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
22171#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
22176#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
22177#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
22178#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
22183#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
22184#define WDOG_WINH_WINHIGH_SHIFT (0U)
22185#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
22190#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
22191#define WDOG_WINL_WINLOW_SHIFT (0U)
22192#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
22197#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
22198#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
22199#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
22204#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
22205#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
22206#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
22211#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
22212#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
22213#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
22218#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
22219#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
22220#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
22225#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
22226#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
22227#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
22232#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
22233#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
22234#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
22240 /* end of group WDOG_Register_Masks */
22241
22242
22243/* WDOG - Peripheral instance base addresses */
22245#define WDOG_BASE (0x40052000u)
22247#define WDOG ((WDOG_Type *)WDOG_BASE)
22249#define WDOG_BASE_ADDRS { WDOG_BASE }
22251#define WDOG_BASE_PTRS { WDOG }
22253#define WDOG_IRQS { WDOG_EWM_IRQn }
22254
22257 /* end of group WDOG_Peripheral_Access_Layer */
22258
22259
22260/*
22261** End of section using anonymous unions
22262*/
22263
22264#if defined(__ARMCC_VERSION)
22265 #if (__ARMCC_VERSION >= 6010050)
22266 #pragma clang diagnostic pop
22267 #else
22268 #pragma pop
22269 #endif
22270#elif defined(__CWCC__)
22271 #pragma pop
22272#elif defined(__GNUC__)
22273 /* leave anonymous unions enabled */
22274#elif defined(__IAR_SYSTEMS_ICC__)
22275 #pragma language=default
22276#else
22277 #error Not supported compiler type
22278#endif
22279
22282 /* end of group Peripheral_access_layer */
22283
22284
22285/* ----------------------------------------------------------------------------
22286 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
22287 ---------------------------------------------------------------------------- */
22288
22294#if defined(__ARMCC_VERSION)
22295 #if (__ARMCC_VERSION >= 6010050)
22296 #pragma clang system_header
22297 #endif
22298#elif defined(__IAR_SYSTEMS_ICC__)
22299 #pragma system_include
22300#endif
22301
22308#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
22315#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
22316
22319 /* end of group Bit_Field_Generic_Macros */
22320
22321
22322/* ----------------------------------------------------------------------------
22323 -- SDK Compatibility
22324 ---------------------------------------------------------------------------- */
22325
22331#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
22332#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
22333#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
22334#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
22335#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
22336#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
22337#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
22338#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
22339#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
22340#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
22341#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
22342#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
22343#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
22344#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
22345#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
22346#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
22347#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
22348#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
22349#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
22350#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
22351#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
22352#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
22353#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
22354#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
22355#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
22356#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
22357#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
22358#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
22359#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
22360#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
22361#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
22362#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
22363#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
22364#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
22365#define DSPI0 SPI0
22366#define DSPI1 SPI1
22367#define DSPI2 SPI2
22368#define FLEXCAN0 CAN0
22369#define PTA_BASE GPIOA_BASE
22370#define PTA GPIOA
22371#define PTB_BASE GPIOB_BASE
22372#define PTB GPIOB
22373#define PTC_BASE GPIOC_BASE
22374#define PTC GPIOC
22375#define PTD_BASE GPIOD_BASE
22376#define PTD GPIOD
22377#define PTE_BASE GPIOE_BASE
22378#define PTE GPIOE
22379#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
22380#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
22381#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
22382#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
22383#define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
22384#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
22385#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
22386#define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
22387#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
22388#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
22389#define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
22390#define Watchdog_IRQn WDOG_EWM_IRQn
22391#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
22392#define LPTimer_IRQn LPTMR0_IRQn
22393#define LPTimer_IRQHandler LPTMR0_IRQHandler
22394#define LLW_IRQn LLWU_IRQn
22395#define LLW_IRQHandler LLWU_IRQHandler
22396#define DMAMUX0 DMAMUX
22397#define WDOG0 WDOG
22398#define MCM0 MCM
22399#define RTC0 RTC
22400
22403 /* end of group SDK_Compatibility_Symbols */
22404
22405
22406#endif /* _MK64F12_H_ */
22407
__O
#define __O
Definition core_cm3.h:169
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
DMA
#define DMA
Definition MK60N512MD100.h:2945
IRQn
IRQn
Definition MK60D10.h:157
MCM_IRQn
@ MCM_IRQn
Definition MK64F12.h:174
PendSV_IRQn
@ PendSV_IRQn
Definition MK64F12.h:153
DMA7_IRQn
@ DMA7_IRQn
Definition MK64F12.h:164
FTM0_IRQn
@ FTM0_IRQn
Definition MK64F12.h:199
ADC0_IRQn
@ ADC0_IRQn
Definition MK64F12.h:196
WDOG_EWM_IRQn
@ WDOG_EWM_IRQn
Definition MK64F12.h:179
PORTE_IRQn
@ PORTE_IRQn
Definition MK64F12.h:220
I2C2_IRQn
@ I2C2_IRQn
Definition MK64F12.h:231
I2C0_IRQn
@ I2C0_IRQn
Definition MK64F12.h:181
MCG_IRQn
@ MCG_IRQn
Definition MK64F12.h:214
DMA11_IRQn
@ DMA11_IRQn
Definition MK64F12.h:168
NotAvail_IRQn
@ NotAvail_IRQn
Definition MK64F12.h:143
DMA2_IRQn
@ DMA2_IRQn
Definition MK64F12.h:159
RTC_Seconds_IRQn
@ RTC_Seconds_IRQn
Definition MK64F12.h:204
UART4_RX_TX_IRQn
@ UART4_RX_TX_IRQn
Definition MK64F12.h:223
DMA13_IRQn
@ DMA13_IRQn
Definition MK64F12.h:170
PORTD_IRQn
@ PORTD_IRQn
Definition MK64F12.h:219
UART0_LON_IRQn
@ UART0_LON_IRQn
Definition MK64F12.h:187
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition MK64F12.h:148
DMA3_IRQn
@ DMA3_IRQn
Definition MK64F12.h:160
ADC1_IRQn
@ ADC1_IRQn
Definition MK64F12.h:230
CAN0_ORed_Message_buffer_IRQn
@ CAN0_ORed_Message_buffer_IRQn
Definition MK64F12.h:232
DMA12_IRQn
@ DMA12_IRQn
Definition MK64F12.h:169
UART5_ERR_IRQn
@ UART5_ERR_IRQn
Definition MK64F12.h:226
SDHC_IRQn
@ SDHC_IRQn
Definition MK64F12.h:238
FTM1_IRQn
@ FTM1_IRQn
Definition MK64F12.h:200
I2S0_Tx_IRQn
@ I2S0_Tx_IRQn
Definition MK64F12.h:185
CAN0_Wake_Up_IRQn
@ CAN0_Wake_Up_IRQn
Definition MK64F12.h:237
SWI_IRQn
@ SWI_IRQn
Definition MK64F12.h:221
I2S0_Rx_IRQn
@ I2S0_Rx_IRQn
Definition MK64F12.h:186
SVCall_IRQn
@ SVCall_IRQn
Definition MK64F12.h:151
CAN0_Tx_Warning_IRQn
@ CAN0_Tx_Warning_IRQn
Definition MK64F12.h:235
SPI2_IRQn
@ SPI2_IRQn
Definition MK64F12.h:222
DMA_Error_IRQn
@ DMA_Error_IRQn
Definition MK64F12.h:173
DMA0_IRQn
@ DMA0_IRQn
Definition MK64F12.h:157
DMA1_IRQn
@ DMA1_IRQn
Definition MK64F12.h:158
UART0_RX_TX_IRQn
@ UART0_RX_TX_IRQn
Definition MK64F12.h:188
DAC0_IRQn
@ DAC0_IRQn
Definition MK64F12.h:213
FTM2_IRQn
@ FTM2_IRQn
Definition MK64F12.h:201
CMT_IRQn
@ CMT_IRQn
Definition MK64F12.h:202
UsageFault_IRQn
@ UsageFault_IRQn
Definition MK64F12.h:150
UART4_ERR_IRQn
@ UART4_ERR_IRQn
Definition MK64F12.h:224
SysTick_IRQn
@ SysTick_IRQn
Definition MK64F12.h:154
DMA4_IRQn
@ DMA4_IRQn
Definition MK64F12.h:161
CAN0_Error_IRQn
@ CAN0_Error_IRQn
Definition MK64F12.h:234
UART5_RX_TX_IRQn
@ UART5_RX_TX_IRQn
Definition MK64F12.h:225
UART0_ERR_IRQn
@ UART0_ERR_IRQn
Definition MK64F12.h:189
CMP2_IRQn
@ CMP2_IRQn
Definition MK64F12.h:227
DMA5_IRQn
@ DMA5_IRQn
Definition MK64F12.h:162
DMA15_IRQn
@ DMA15_IRQn
Definition MK64F12.h:172
DMA10_IRQn
@ DMA10_IRQn
Definition MK64F12.h:167
BusFault_IRQn
@ BusFault_IRQn
Definition MK64F12.h:149
CMP0_IRQn
@ CMP0_IRQn
Definition MK64F12.h:197
ENET_Receive_IRQn
@ ENET_Receive_IRQn
Definition MK64F12.h:241
PDB0_IRQn
@ PDB0_IRQn
Definition MK64F12.h:209
UART2_RX_TX_IRQn
@ UART2_RX_TX_IRQn
Definition MK64F12.h:192
LLWU_IRQn
@ LLWU_IRQn
Definition MK64F12.h:178
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition MK64F12.h:152
RNG_IRQn
@ RNG_IRQn
Definition MK64F12.h:180
UART1_ERR_IRQn
@ UART1_ERR_IRQn
Definition MK64F12.h:191
USBDCD_IRQn
@ USBDCD_IRQn
Definition MK64F12.h:211
LPTMR0_IRQn
@ LPTMR0_IRQn
Definition MK64F12.h:215
Read_Collision_IRQn
@ Read_Collision_IRQn
Definition MK64F12.h:176
DMA6_IRQn
@ DMA6_IRQn
Definition MK64F12.h:163
LVD_LVW_IRQn
@ LVD_LVW_IRQn
Definition MK64F12.h:177
PIT3_IRQn
@ PIT3_IRQn
Definition MK64F12.h:208
Reserved71_IRQn
@ Reserved71_IRQn
Definition MK64F12.h:212
UART2_ERR_IRQn
@ UART2_ERR_IRQn
Definition MK64F12.h:193
SPI1_IRQn
@ SPI1_IRQn
Definition MK64F12.h:184
HardFault_IRQn
@ HardFault_IRQn
Definition MK64F12.h:147
CAN0_Rx_Warning_IRQn
@ CAN0_Rx_Warning_IRQn
Definition MK64F12.h:236
PIT0_IRQn
@ PIT0_IRQn
Definition MK64F12.h:205
UART3_RX_TX_IRQn
@ UART3_RX_TX_IRQn
Definition MK64F12.h:194
ENET_Error_IRQn
@ ENET_Error_IRQn
Definition MK64F12.h:242
PORTA_IRQn
@ PORTA_IRQn
Definition MK64F12.h:216
FTFE_IRQn
@ FTFE_IRQn
Definition MK64F12.h:175
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition MK64F12.h:239
CMP1_IRQn
@ CMP1_IRQn
Definition MK64F12.h:198
PORTC_IRQn
@ PORTC_IRQn
Definition MK64F12.h:218
ENET_Transmit_IRQn
@ ENET_Transmit_IRQn
Definition MK64F12.h:240
PORTB_IRQn
@ PORTB_IRQn
Definition MK64F12.h:217
UART3_ERR_IRQn
@ UART3_ERR_IRQn
Definition MK64F12.h:195
DMA14_IRQn
@ DMA14_IRQn
Definition MK64F12.h:171
FTM3_IRQn
@ FTM3_IRQn
Definition MK64F12.h:228
UART1_RX_TX_IRQn
@ UART1_RX_TX_IRQn
Definition MK64F12.h:190
USB0_IRQn
@ USB0_IRQn
Definition MK64F12.h:210
CAN0_Bus_Off_IRQn
@ CAN0_Bus_Off_IRQn
Definition MK64F12.h:233
RTC_IRQn
@ RTC_IRQn
Definition MK64F12.h:203
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition MK64F12.h:146
PIT1_IRQn
@ PIT1_IRQn
Definition MK64F12.h:206
DAC1_IRQn
@ DAC1_IRQn
Definition MK64F12.h:229
I2C1_IRQn
@ I2C1_IRQn
Definition MK64F12.h:182
DMA8_IRQn
@ DMA8_IRQn
Definition MK64F12.h:165
SPI0_IRQn
@ SPI0_IRQn
Definition MK64F12.h:183
DMA9_IRQn
@ DMA9_IRQn
Definition MK64F12.h:166
PIT2_IRQn
@ PIT2_IRQn
Definition MK64F12.h:207
ENET_Type::IEEE_T_DEF
__I uint32_t IEEE_T_DEF
Definition MK64F12.h:8337
FTFE_Type::FCCOB3
__IO uint8_t FCCOB3
Definition MK64F12.h:10311
ENET_Type::IEEE_R_CRC
__I uint32_t IEEE_R_CRC
Definition MK64F12.h:8365
FTFE_Type::FCCOB0
__IO uint8_t FCCOB0
Definition MK64F12.h:10314
ENET_Type::RMON_R_JAB
__I uint32_t RMON_R_JAB
Definition MK64F12.h:8353
CRC_Type::DATAH
__IO uint16_t DATAH
Definition MK64F12.h:6031
ENET_Type::RMON_T_P256TO511
__I uint32_t RMON_T_P256TO511
Definition MK64F12.h:8328
PIT_Type::@135::LDVAL
__IO uint32_t LDVAL
Definition MK64F12.h:15293
DAC_Type::@121::DATH
__IO uint8_t DATH
Definition MK64F12.h:6302
FMC_Type::@131::DATA_U
__IO uint32_t DATA_U
Definition MK64F12.h:9918
CAN_Type::@109::WORD0
__IO uint32_t WORD0
Definition MK64F12.h:4195
FTFE_Type::FPROT2
__IO uint8_t FPROT2
Definition MK64F12.h:10324
ENET_Type::RMON_R_P65TO127
__I uint32_t RMON_R_P65TO127
Definition MK64F12.h:8356
ENET_Type::IEEE_R_ALIGN
__I uint32_t IEEE_R_ALIGN
Definition MK64F12.h:8366
ENET_Type::RMON_T_FRAG
__I uint32_t RMON_T_FRAG
Definition MK64F12.h:8322
FTFE_Type::FEPROT
__IO uint8_t FEPROT
Definition MK64F12.h:10328
CRC_Type::DATAL
__IO uint16_t DATAL
Definition MK64F12.h:6030
FTM_Type::@132::CnSC
__IO uint32_t CnSC
Definition MK64F12.h:10672
DMA_Type::@122::SLAST
__IO uint32_t SLAST
Definition MK64F12.h:6555
ENET_Type::RMON_T_JAB
__I uint32_t RMON_T_JAB
Definition MK64F12.h:8323
ENET_Type::IEEE_R_FDXFC
__I uint32_t IEEE_R_FDXFC
Definition MK64F12.h:8368
FTFE_Type::FSTAT
__IO uint8_t FSTAT
Definition MK64F12.h:10307
DMA_Type::@122::CSR
__IO uint16_t CSR
Definition MK64F12.h:6563
ENET_Type::IEEE_T_EXCOL
__I uint32_t IEEE_T_EXCOL
Definition MK64F12.h:8339
CRC_Type::@112::@118::GPOLYL
__IO uint16_t GPOLYL
Definition MK64F12.h:6043
ENET_Type::RMON_T_OVERSIZE
__I uint32_t RMON_T_OVERSIZE
Definition MK64F12.h:8321
AXBS_Type::@108::PRS
__IO uint32_t PRS
Definition MK64F12.h:3873
USB_Type::CLK_RECOVER_INT_STATUS
__IO uint8_t CLK_RECOVER_INT_STATUS
Definition MK64F12.h:21070
FTFE_Type::FCCOB9
__IO uint8_t FCCOB9
Definition MK64F12.h:10321
ENET_Type::RMON_T_P_GTE2048
__I uint32_t RMON_T_P_GTE2048
Definition MK64F12.h:8331
ENET_Type::IEEE_T_FRAME_OK
__I uint32_t IEEE_T_FRAME_OK
Definition MK64F12.h:8334
ENET_Type::RMON_R_P64
__I uint32_t RMON_R_P64
Definition MK64F12.h:8355
ENET_Type::RMON_R_FRAG
__I uint32_t RMON_R_FRAG
Definition MK64F12.h:8352
FTM_Type::@132::CnV
__IO uint32_t CnV
Definition MK64F12.h:10673
ENET_Type::RMON_T_UNDERSIZE
__I uint32_t RMON_T_UNDERSIZE
Definition MK64F12.h:8320
DMA_Type::@122::@123::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition MK64F12.h:6552
CRC_Type::@112::GPOLY
__IO uint32_t GPOLY
Definition MK64F12.h:6046
FMC_Type::@131::DATA_L
__IO uint32_t DATA_L
Definition MK64F12.h:9919
DMA_Type::HRS
__I uint32_t HRS
Definition MK64F12.h:6527
CAN_Type::@109::ID
__IO uint32_t ID
Definition MK64F12.h:4194
ENET_Type::ATSTMP
__I uint32_t ATSTMP
Definition MK64F12.h:8377
PDB_Type::@133::S
__IO uint32_t S
Definition MK64F12.h:14999
ENET_Type::RMON_T_BC_PKT
__I uint32_t RMON_T_BC_PKT
Definition MK64F12.h:8317
DMA_Type::@122::DOFF
__IO uint16_t DOFF
Definition MK64F12.h:6557
SPI_Type::@138::PUSHR_SLAVE
__IO uint32_t PUSHR_SLAVE
Definition MK64F12.h:19142
ENET_Type::RMON_T_P128TO255
__I uint32_t RMON_T_P128TO255
Definition MK64F12.h:8327
ENET_Type::RMON_R_CRC_ALIGN
__I uint32_t RMON_R_CRC_ALIGN
Definition MK64F12.h:8349
CRC_Type::@114::@120::CTRLHU
__IO uint8_t CTRLHU
Definition MK64F12.h:6058
SYSMPU_Type::@140::EDR
__I uint32_t EDR
Definition MK64F12.h:19703
DMA_Type::@122::@127::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition MK64F12.h:6566
ENET_Type::RMON_T_P65TO127
__I uint32_t RMON_T_P65TO127
Definition MK64F12.h:8326
DMA_Type::@122::SADDR
__IO uint32_t SADDR
Definition MK64F12.h:6547
ENET_Type::IEEE_T_CSERR
__I uint32_t IEEE_T_CSERR
Definition MK64F12.h:8341
DAC_Type::@121::DATL
__IO uint8_t DATL
Definition MK64F12.h:6301
SYSMPU_Type::@140::EAR
__I uint32_t EAR
Definition MK64F12.h:19702
ENET_Type::IEEE_R_DROP
__I uint32_t IEEE_R_DROP
Definition MK64F12.h:8363
FB_Type::@130::CSCR
__IO uint32_t CSCR
Definition MK64F12.h:9682
PDB_Type::@134::INT
__IO uint32_t INT
Definition MK64F12.h:15006
USB_Type::CLK_RECOVER_IRC_EN
__IO uint8_t CLK_RECOVER_IRC_EN
Definition MK64F12.h:21068
DMA_Type::@122::@123::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition MK64F12.h:6551
FTFE_Type::FCNFG
__IO uint8_t FCNFG
Definition MK64F12.h:10308
ENET_Type::@129::TCSR
__IO uint32_t TCSR
Definition MK64F12.h:8381
FTFE_Type::FPROT3
__IO uint8_t FPROT3
Definition MK64F12.h:10323
FTFE_Type::FSEC
__I uint8_t FSEC
Definition MK64F12.h:10309
PIT_Type::@135::TFLG
__IO uint32_t TFLG
Definition MK64F12.h:15296
ENET_Type::@129::TCCR
__IO uint32_t TCCR
Definition MK64F12.h:8382
ENET_Type::RMON_R_P_GTE2048
__I uint32_t RMON_R_P_GTE2048
Definition MK64F12.h:8361
ENET_Type::IEEE_T_FDXFC
__I uint32_t IEEE_T_FDXFC
Definition MK64F12.h:8343
ENET_Type::RMON_T_COL
__I uint32_t RMON_T_COL
Definition MK64F12.h:8324
FTFE_Type::FCCOB4
__IO uint8_t FCCOB4
Definition MK64F12.h:10318
ENET_Type::RMON_R_OVERSIZE
__I uint32_t RMON_R_OVERSIZE
Definition MK64F12.h:8351
ENET_Type::RMON_T_P1024TO2047
__I uint32_t RMON_T_P1024TO2047
Definition MK64F12.h:8330
FTFE_Type::FCCOB8
__IO uint8_t FCCOB8
Definition MK64F12.h:10322
PIT_Type::@135::CVAL
__I uint32_t CVAL
Definition MK64F12.h:15294
CRC_Type::@112::@119::GPOLYHL
__IO uint8_t GPOLYHL
Definition MK64F12.h:6050
FTFE_Type::FCCOB7
__IO uint8_t FCCOB7
Definition MK64F12.h:10315
ENET_Type::IEEE_T_MACERR
__I uint32_t IEEE_T_MACERR
Definition MK64F12.h:8340
CRC_Type::DATA
__IO uint32_t DATA
Definition MK64F12.h:6033
CRC_Type::@114::CTRL
__IO uint32_t CTRL
Definition MK64F12.h:6055
AIPS_Type::PACRU
__IO uint32_t PACRU
Definition MK64F12.h:896
CRC_Type::DATAHL
__IO uint8_t DATAHL
Definition MK64F12.h:6037
PIT_Type::@135::TCTRL
__IO uint32_t TCTRL
Definition MK64F12.h:15295
FTFE_Type::FCCOB6
__IO uint8_t FCCOB6
Definition MK64F12.h:10316
USB_Type::@143::ENDPT
__IO uint8_t ENDPT
Definition MK64F12.h:21053
ENET_Type::IEEE_T_1COL
__I uint32_t IEEE_T_1COL
Definition MK64F12.h:8335
DMA_Type::@122::@127::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition MK64F12.h:6565
DMA_Type::@122::@123::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition MK64F12.h:6553
ENET_Type::RMON_R_BC_PKT
__I uint32_t RMON_R_BC_PKT
Definition MK64F12.h:8347
ENET_Type::RMON_T_MC_PKT
__I uint32_t RMON_T_MC_PKT
Definition MK64F12.h:8318
ENET_Type::RMON_R_P512TO1023
__I uint32_t RMON_R_P512TO1023
Definition MK64F12.h:8359
ENET_Type::RMON_R_P128TO255
__I uint32_t RMON_R_P128TO255
Definition MK64F12.h:8357
CRC_Type::@112::@119::GPOLYLU
__IO uint8_t GPOLYLU
Definition MK64F12.h:6049
CAN_Type::@109::WORD1
__IO uint32_t WORD1
Definition MK64F12.h:4196
FB_Type::@130::CSMR
__IO uint32_t CSMR
Definition MK64F12.h:9681
UART_Type::@141::WP7816T0
__IO uint8_t WP7816T0
Definition MK64F12.h:20102
FTFE_Type::FCCOB5
__IO uint8_t FCCOB5
Definition MK64F12.h:10317
ENET_Type::IEEE_R_MACERR
__I uint32_t IEEE_R_MACERR
Definition MK64F12.h:8367
DMA_Type::@122::@125::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition MK64F12.h:6559
CAN_Type::@109::CS
__IO uint32_t CS
Definition MK64F12.h:4193
CRC_Type::DATALL
__IO uint8_t DATALL
Definition MK64F12.h:6035
CRC_Type::DATALU
__IO uint8_t DATALU
Definition MK64F12.h:6036
FTFE_Type::FDPROT
__IO uint8_t FDPROT
Definition MK64F12.h:10329
ENET_Type::RMON_R_MC_PKT
__I uint32_t RMON_R_MC_PKT
Definition MK64F12.h:8348
FTFE_Type::FOPT
__I uint8_t FOPT
Definition MK64F12.h:10310
DMA_Type::@122::DLAST_SGA
__IO uint32_t DLAST_SGA
Definition MK64F12.h:6562
CRC_Type::DATAHU
__IO uint8_t DATAHU
Definition MK64F12.h:6038
ENET_Type::RMON_T_CRC_ALIGN
__I uint32_t RMON_T_CRC_ALIGN
Definition MK64F12.h:8319
AXBS_Type::@108::CRS
__IO uint32_t CRS
Definition MK64F12.h:3875
ENET_Type::IEEE_R_FRAME_OK
__I uint32_t IEEE_R_FRAME_OK
Definition MK64F12.h:8364
FTFE_Type::FCCOBA
__IO uint8_t FCCOBA
Definition MK64F12.h:10320
FTFE_Type::FPROT0
__IO uint8_t FPROT0
Definition MK64F12.h:10326
PDB_Type::@134::INTC
__IO uint32_t INTC
Definition MK64F12.h:15005
USBDCD_Type::TIMER2_BC11
__IO uint32_t TIMER2_BC11
Definition MK64F12.h:21756
MCM_Type::ISCR
__IO uint32_t ISCR
Definition MK64F12.h:14424
ENET_Type::IEEE_T_MCOL
__I uint32_t IEEE_T_MCOL
Definition MK64F12.h:8336
DMA_Type::@122::SOFF
__IO uint16_t SOFF
Definition MK64F12.h:6548
ENET_Type::RMON_T_P64
__I uint32_t RMON_T_P64
Definition MK64F12.h:8325
ENET_Type::RMON_R_UNDERSIZE
__I uint32_t RMON_R_UNDERSIZE
Definition MK64F12.h:8350
DMA_Type::@122::DADDR
__IO uint32_t DADDR
Definition MK64F12.h:6556
UART_Type::@141::WP7816T1
__IO uint8_t WP7816T1
Definition MK64F12.h:20103
USBDCD_Type::TIMER2_BC12
__IO uint32_t TIMER2_BC12
Definition MK64F12.h:21757
DMA_Type::@122::ATTR
__IO uint16_t ATTR
Definition MK64F12.h:6549
SPI_Type::@138::PUSHR
__IO uint32_t PUSHR
Definition MK64F12.h:19141
CRC_Type::@112::@119::GPOLYLL
__IO uint8_t GPOLYLL
Definition MK64F12.h:6048
ENET_Type::RMON_R_PACKETS
__I uint32_t RMON_R_PACKETS
Definition MK64F12.h:8346
ENET_Type::IEEE_T_LCOL
__I uint32_t IEEE_T_LCOL
Definition MK64F12.h:8338
PDB_Type::@133::C1
__IO uint32_t C1
Definition MK64F12.h:14998
ENET_Type::RMON_R_P1024TO2047
__I uint32_t RMON_R_P1024TO2047
Definition MK64F12.h:8360
ENET_Type::RMON_T_P512TO1023
__I uint32_t RMON_T_P512TO1023
Definition MK64F12.h:8329
ENET_Type::RMON_T_PACKETS
__I uint32_t RMON_T_PACKETS
Definition MK64F12.h:8316
CRC_Type::@112::@119::GPOLYHU
__IO uint8_t GPOLYHU
Definition MK64F12.h:6051
USB_Type::CLK_RECOVER_CTRL
__IO uint8_t CLK_RECOVER_CTRL
Definition MK64F12.h:21066
FTFE_Type::FCCOB2
__IO uint8_t FCCOB2
Definition MK64F12.h:10312
ENET_Type::RMON_R_P256TO511
__I uint32_t RMON_R_P256TO511
Definition MK64F12.h:8358
FTFE_Type::FCCOB1
__IO uint8_t FCCOB1
Definition MK64F12.h:10313
FTFE_Type::FCCOBB
__IO uint8_t FCCOBB
Definition MK64F12.h:10319
DMA_Type::@122::@125::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition MK64F12.h:6560
FB_Type::@130::CSAR
__IO uint32_t CSAR
Definition MK64F12.h:9680
FTFE_Type::FPROT1
__IO uint8_t FPROT1
Definition MK64F12.h:10325
CRC_Type::@112::@118::GPOLYH
__IO uint16_t GPOLYH
Definition MK64F12.h:6044
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition MK60D10.h:336
kDmaRequestMux0FTM1Channel0
@ kDmaRequestMux0FTM1Channel0
Definition MK64F12.h:333
kDmaRequestMux0DAC0
@ kDmaRequestMux0DAC0
Definition MK64F12.h:350
kDmaRequestMux0FTM0Channel7
@ kDmaRequestMux0FTM0Channel7
Definition MK64F12.h:332
kDmaRequestMux0UART2Tx
@ kDmaRequestMux0UART2Tx
Definition MK64F12.h:310
kDmaRequestMux0I2C0
@ kDmaRequestMux0I2C0
Definition MK64F12.h:321
kDmaRequestMux0CMP0
@ kDmaRequestMux0CMP0
Definition MK64F12.h:347
kDmaRequestMux0DAC1
@ kDmaRequestMux0DAC1
Definition MK64F12.h:351
kDmaRequestMux0UART3Tx
@ kDmaRequestMux0UART3Tx
Definition MK64F12.h:312
kDmaRequestMux0FTM3Channel1
@ kDmaRequestMux0FTM3Channel1
Definition MK64F12.h:338
kDmaRequestMux0SPI2
@ kDmaRequestMux0SPI2
Definition MK64F12.h:320
kDmaRequestMux0CMP1
@ kDmaRequestMux0CMP1
Definition MK64F12.h:348
kDmaRequestMux0FTM3Channel7
@ kDmaRequestMux0FTM3Channel7
Definition MK64F12.h:344
kDmaRequestMux0IEEE1588Timer1
@ kDmaRequestMux0IEEE1588Timer1
Definition MK64F12.h:360
kDmaRequestMux0FTM2Channel1
@ kDmaRequestMux0FTM2Channel1
Definition MK64F12.h:336
kDmaRequestMux0I2S0Tx
@ kDmaRequestMux0I2S0Tx
Definition MK64F12.h:316
kDmaRequestMux0PortE
@ kDmaRequestMux0PortE
Definition MK64F12.h:358
kDmaRequestMux0AlwaysOn63
@ kDmaRequestMux0AlwaysOn63
Definition MK64F12.h:368
kDmaRequestMux0IEEE1588Timer3
@ kDmaRequestMux0IEEE1588Timer3
Definition MK64F12.h:362
kDmaRequestMux0SPI0Tx
@ kDmaRequestMux0SPI0Tx
Definition MK64F12.h:318
kDmaRequestMux0FTM0Channel1
@ kDmaRequestMux0FTM0Channel1
Definition MK64F12.h:326
kDmaRequestMux0FTM0Channel5
@ kDmaRequestMux0FTM0Channel5
Definition MK64F12.h:330
kDmaRequestMux0FTM2Channel0
@ kDmaRequestMux0FTM2Channel0
Definition MK64F12.h:335
kDmaRequestMux0I2C2
@ kDmaRequestMux0I2C2
Definition MK64F12.h:324
kDmaRequestMux0AlwaysOn61
@ kDmaRequestMux0AlwaysOn61
Definition MK64F12.h:366
kDmaRequestMux0UART1Tx
@ kDmaRequestMux0UART1Tx
Definition MK64F12.h:308
kDmaRequestMux0UART5
@ kDmaRequestMux0UART5
Definition MK64F12.h:314
kDmaRequestMux0SPI1
@ kDmaRequestMux0SPI1
Definition MK64F12.h:319
kDmaRequestMux0UART4
@ kDmaRequestMux0UART4
Definition MK64F12.h:313
kDmaRequestMux0FTM0Channel6
@ kDmaRequestMux0FTM0Channel6
Definition MK64F12.h:331
kDmaRequestMux0UART3Rx
@ kDmaRequestMux0UART3Rx
Definition MK64F12.h:311
kDmaRequestMux0UART1Rx
@ kDmaRequestMux0UART1Rx
Definition MK64F12.h:307
kDmaRequestMux0PortB
@ kDmaRequestMux0PortB
Definition MK64F12.h:355
kDmaRequestMux0ADC1
@ kDmaRequestMux0ADC1
Definition MK64F12.h:346
kDmaRequestMux0PortC
@ kDmaRequestMux0PortC
Definition MK64F12.h:356
kDmaRequestMux0FTM3Channel0
@ kDmaRequestMux0FTM3Channel0
Definition MK64F12.h:337
kDmaRequestMux0FTM1Channel1
@ kDmaRequestMux0FTM1Channel1
Definition MK64F12.h:334
kDmaRequestMux0CMP2
@ kDmaRequestMux0CMP2
Definition MK64F12.h:349
kDmaRequestMux0Reserved1
@ kDmaRequestMux0Reserved1
Definition MK64F12.h:304
kDmaRequestMux0FTM0Channel4
@ kDmaRequestMux0FTM0Channel4
Definition MK64F12.h:329
kDmaRequestMux0CMT
@ kDmaRequestMux0CMT
Definition MK64F12.h:352
kDmaRequestMux0I2S0Rx
@ kDmaRequestMux0I2S0Rx
Definition MK64F12.h:315
kDmaRequestMux0AlwaysOn60
@ kDmaRequestMux0AlwaysOn60
Definition MK64F12.h:365
kDmaRequestMux0FTM3Channel2
@ kDmaRequestMux0FTM3Channel2
Definition MK64F12.h:339
kDmaRequestMux0AlwaysOn58
@ kDmaRequestMux0AlwaysOn58
Definition MK64F12.h:363
kDmaRequestMux0IEEE1588Timer0
@ kDmaRequestMux0IEEE1588Timer0
Definition MK64F12.h:359
kDmaRequestMux0I2C1I2C2
@ kDmaRequestMux0I2C1I2C2
Definition MK64F12.h:322
kDmaRequestMux0FTM3Channel4
@ kDmaRequestMux0FTM3Channel4
Definition MK64F12.h:341
kDmaRequestMux0FTM3Channel5
@ kDmaRequestMux0FTM3Channel5
Definition MK64F12.h:342
kDmaRequestMux0Disable
@ kDmaRequestMux0Disable
Definition MK64F12.h:303
kDmaRequestMux0PortA
@ kDmaRequestMux0PortA
Definition MK64F12.h:354
kDmaRequestMux0PortD
@ kDmaRequestMux0PortD
Definition MK64F12.h:357
kDmaRequestMux0UART2Rx
@ kDmaRequestMux0UART2Rx
Definition MK64F12.h:309
kDmaRequestMux0ADC0
@ kDmaRequestMux0ADC0
Definition MK64F12.h:345
kDmaRequestMux0FTM3Channel3
@ kDmaRequestMux0FTM3Channel3
Definition MK64F12.h:340
kDmaRequestMux0FTM0Channel3
@ kDmaRequestMux0FTM0Channel3
Definition MK64F12.h:328
kDmaRequestMux0IEEE1588Timer2
@ kDmaRequestMux0IEEE1588Timer2
Definition MK64F12.h:361
kDmaRequestMux0UART0Rx
@ kDmaRequestMux0UART0Rx
Definition MK64F12.h:305
kDmaRequestMux0AlwaysOn59
@ kDmaRequestMux0AlwaysOn59
Definition MK64F12.h:364
kDmaRequestMux0FTM0Channel0
@ kDmaRequestMux0FTM0Channel0
Definition MK64F12.h:325
kDmaRequestMux0FTM3Channel6
@ kDmaRequestMux0FTM3Channel6
Definition MK64F12.h:343
kDmaRequestMux0AlwaysOn62
@ kDmaRequestMux0AlwaysOn62
Definition MK64F12.h:367
kDmaRequestMux0FTM0Channel2
@ kDmaRequestMux0FTM0Channel2
Definition MK64F12.h:327
kDmaRequestMux0UART0Tx
@ kDmaRequestMux0UART0Tx
Definition MK64F12.h:306
kDmaRequestMux0SPI0Rx
@ kDmaRequestMux0SPI0Rx
Definition MK64F12.h:317
kDmaRequestMux0I2C1
@ kDmaRequestMux0I2C1
Definition MK64F12.h:323
kDmaRequestMux0PDB
@ kDmaRequestMux0PDB
Definition MK64F12.h:353
ADC_Type
Definition MK60D10.h:449
AIPS_Type
Definition MK60D10.h:726
AXBS_Type
Definition MK60D10.h:2032
CAN_Type
Definition MK60D10.h:2166
CAU_Type
Definition MK60D10.h:2591
CMP_Type
Definition MK60D10.h:3104
CMT_Type
Definition MK60D10.h:3241
CRC_Type
Definition MK60D10.h:3382
DAC_Type
Definition MK60D10.h:3574
DMAMUX_Type
Definition MK60D10.h:4580
DMA_Type
Definition MK60D10.h:3706
ENET_Type
Definition MK60D10.h:4638
EWM_Type
Definition MK60D10.h:5537
FB_Type
Definition MK60D10.h:5622
FMC_Type
Definition MK60D10.h:5755
FTFE_Type
Definition MK64F12.h:10306
FTM_Type
Definition MK60D10.h:6173
GPIO_Type
Definition MK60D10.h:6852
I2C_Type
Definition MK60D10.h:6947
I2S_Type
Definition MK60D10.h:7149
LLWU_Type
Definition MK60D10.h:7536
LPTMR_Type
Definition MK60D10.h:7782
MCG_Type
Definition MK60D10.h:7875
MCM_Type
Definition MK60D10.h:8113
NV_Type
Definition MK60D10.h:8235
OSC_Type
Definition MK60D10.h:8389
PDB_Type
Definition MK60D10.h:8453
PIT_Type
Definition MK60D10.h:8640
PMC_Type
Definition MK60D10.h:8739
PORT_Type
Definition MK60D10.h:8832
RCM_Type
Definition MK60D10.h:8973
RFSYS_Type
Definition MK60D10.h:9084
RFVBAT_Type
Definition MK60D10.h:9145
RNG_Type
Definition MK60D10.h:9206
RTC_Type
Definition MK60D10.h:9305
SDHC_Type
Definition MK60D10.h:9520
SIM_Type
Definition MK60D10.h:10117
SMC_Type
Definition MK60D10.h:10560
SPI_Type
Definition MK60D10.h:10645
SYSMPU_Type
Definition MK60D10.h:10978
UART_Type
Definition MK60D10.h:11447
USBDCD_Type
Definition MK60D10.h:12538
USB_Type
Definition MK60D10.h:12089
VREF_Type
Definition MK60D10.h:12656
WDOG_Type
Definition MK60D10.h:12726