mikroSDK Reference Manual
MKV58F24.h
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1/*
2** ###################################################################
3** Processors: MKV58F1M0VLL24
4** MKV58F1M0VLQ24
5** MKV58F1M0VMD24
6** MKV58F512VLL24
7** MKV58F512VLQ24
8** MKV58F512VMD24
9**
10** Compilers: Keil ARM C/C++ Compiler
11** Freescale C/C++ for Embedded ARM
12** GNU C Compiler
13** IAR ANSI C/C++ Compiler for ARM
14** MCUXpresso Compiler
15**
16** Reference manual: KV5XP144M240RM Rev. 3, 02/2016
17** Version: rev. 0.3, 2016-02-29
18** Build: b180801
19**
20** Abstract:
21** CMSIS Peripheral Access Layer for MKV58F24
22**
23** Copyright 1997-2016 Freescale Semiconductor, Inc.
24** Copyright 2016-2018 NXP
25**
26** SPDX-License-Identifier: BSD-3-Clause
27**
28** http: www.nxp.com
29** mail: support@nxp.com
30**
31** Revisions:
32** - rev. 0.1 (2015-02-24)
33** Initial version.
34** - rev. 0.2 (2015-10-21)
35** UART0 - removed LON functionality.
36** FMC - corrected base address.
37** - rev. 0.3 (2016-02-29)
38** PORT - removed registers GICLR, GICHR.
39**
40** ###################################################################
41*/
42
52#ifndef _MKV58F24_H_
53#define _MKV58F24_H_
57#define MCU_MEM_MAP_VERSION 0x0000U
59#define MCU_MEM_MAP_VERSION_MINOR 0x0003U
60
69#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
78#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
79#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
88#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
97#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
98
99/* ----------------------------------------------------------------------------
100 -- Interrupt vector numbers
101 ---------------------------------------------------------------------------- */
102
109#define NUMBER_OF_INT_VECTORS 137
111typedef enum IRQn {
112 /* Auxiliary constants */
113 NotAvail_IRQn = -128,
115 /* Core interrupts */
116 NonMaskableInt_IRQn = -14,
117 HardFault_IRQn = -13,
118 MemoryManagement_IRQn = -12,
119 BusFault_IRQn = -11,
120 UsageFault_IRQn = -10,
121 SVCall_IRQn = -5,
122 DebugMonitor_IRQn = -4,
123 PendSV_IRQn = -2,
124 SysTick_IRQn = -1,
126 /* Device specific interrupts */
127 DMA0_DMA16_IRQn = 0,
128 DMA1_DMA17_IRQn = 1,
129 DMA2_DMA18_IRQn = 2,
130 DMA3_DMA19_IRQn = 3,
131 DMA4_DMA20_IRQn = 4,
132 DMA5_DMA21_IRQn = 5,
133 DMA6_DMA22_IRQn = 6,
134 DMA7_DMA23_IRQn = 7,
135 DMA8_DMA24_IRQn = 8,
136 DMA9_DMA25_IRQn = 9,
137 DMA10_DMA26_IRQn = 10,
138 DMA11_DMA27_IRQn = 11,
139 DMA12_DMA28_IRQn = 12,
140 DMA13_DMA29_IRQn = 13,
141 DMA14_DMA30_IRQn = 14,
142 DMA15_DMA31_IRQn = 15,
143 DMA_Error_IRQn = 16,
144 MCM_IRQn = 17,
145 FTFE_IRQn = 18,
146 Read_Collision_IRQn = 19,
147 PMC_IRQn = 20,
148 LLWU_IRQn = 21,
149 WDOG_EWM_IRQn = 22,
150 TRNG0_IRQn = 23,
151 I2C0_IRQn = 24,
152 I2C1_IRQn = 25,
153 SPI0_IRQn = 26,
154 SPI1_IRQn = 27,
155 UART5_RX_TX_IRQn = 28,
156 UART5_ERR_IRQn = 29,
157 Reserved46_IRQn = 30,
158 UART0_RX_TX_IRQn = 31,
159 UART0_ERR_IRQn = 32,
160 UART1_RX_TX_IRQn = 33,
161 UART1_ERR_IRQn = 34,
162 UART2_RX_TX_IRQn = 35,
163 UART2_ERR_IRQn = 36,
164 ADC0_IRQn = 37,
165 HSADC_ERR_IRQn = 38,
166 HSADC0_CCA_IRQn = 39,
167 CMP0_IRQn = 40,
168 CMP1_IRQn = 41,
169 FTM0_IRQn = 42,
170 FTM1_IRQn = 43,
171 UART3_RX_TX_IRQn = 44,
172 UART3_ERR_IRQn = 45,
173 UART4_RX_TX_IRQn = 46,
174 UART4_ERR_IRQn = 47,
175 PIT0_IRQn = 48,
176 PIT1_IRQn = 49,
177 PIT2_IRQn = 50,
178 PIT3_IRQn = 51,
179 PDB0_IRQn = 52,
180 FTM2_IRQn = 53,
181 XBARA_IRQn = 54,
182 PDB1_IRQn = 55,
183 DAC0_IRQn = 56,
184 MCG_IRQn = 57,
185 LPTMR0_IRQn = 58,
186 PORTA_IRQn = 59,
187 PORTB_IRQn = 60,
188 PORTC_IRQn = 61,
189 PORTD_IRQn = 62,
190 PORTE_IRQn = 63,
191 SWI_IRQn = 64,
192 SPI2_IRQn = 65,
193 ENC_COMPARE_IRQn = 66,
194 ENC_HOME_IRQn = 67,
195 ENC_WDOG_SAB_IRQn = 68,
196 ENC_INDEX_IRQn = 69,
197 CMP2_IRQn = 70,
198 FTM3_IRQn = 71,
199 Reserved88_IRQn = 72,
200 HSADC0_CCB_IRQn = 73,
201 HSADC1_CCA_IRQn = 74,
202 CAN0_ORed_Message_buffer_IRQn = 75,
203 CAN0_Bus_Off_IRQn = 76,
204 CAN0_Error_IRQn = 77,
205 CAN0_Tx_Warning_IRQn = 78,
206 CAN0_Rx_Warning_IRQn = 79,
207 CAN0_Wake_Up_IRQn = 80,
208 PWM0_CMP0_IRQn = 81,
209 PWM0_RELOAD0_IRQn = 82,
210 PWM0_CMP1_IRQn = 83,
211 PWM0_RELOAD1_IRQn = 84,
212 PWM0_CMP2_IRQn = 85,
213 PWM0_RELOAD2_IRQn = 86,
214 PWM0_CMP3_IRQn = 87,
215 PWM0_RELOAD3_IRQn = 88,
216 PWM0_CAP_IRQn = 89,
217 PWM0_RERR_IRQn = 90,
218 PWM0_FAULT_IRQn = 91,
219 CMP3_IRQn = 92,
220 HSADC1_CCB_IRQn = 93,
221 CAN1_ORed_Message_buffer_IRQn = 94,
222 CAN1_Bus_Off_IRQn = 95,
223 CAN1_Error_IRQn = 96,
224 CAN1_Tx_Warning_IRQn = 97,
225 CAN1_Rx_Warning_IRQn = 98,
226 CAN1_Wake_Up_IRQn = 99,
227 ENET_1588_Timer_IRQn = 100,
228 ENET_Transmit_IRQn = 101,
229 ENET_Receive_IRQn = 102,
230 ENET_Error_IRQn = 103,
231 PWM1_CMP0_IRQn = 104,
232 PWM1_RELOAD0_IRQn = 105,
233 PWM1_CMP1_IRQn = 106,
234 PWM1_RELOAD1_IRQn = 107,
235 PWM1_CMP2_IRQn = 108,
236 PWM1_RELOAD2_IRQn = 109,
237 PWM1_CMP3_IRQn = 110,
238 PWM1_RELOAD3_IRQn = 111,
239 PWM1_CAP_IRQn = 112,
240 PWM1_RERR_IRQn = 113,
241 PWM1_FAULT_IRQn = 114,
242 CAN2_ORed_Message_buffer_IRQn = 115,
243 CAN2_Bus_Off_IRQn = 116,
244 CAN2_Error_IRQn = 117,
245 CAN2_Tx_Warning_IRQn = 118,
246 CAN2_Rx_Warning_IRQn = 119,
247 CAN2_Wake_Up_IRQn = 120
248} IRQn_Type;
249
252 /* end of group Interrupt_vector_numbers */
253
254
255/* ----------------------------------------------------------------------------
256 -- Cortex M7 Core Configuration
257 ---------------------------------------------------------------------------- */
258
264#define __MPU_PRESENT 1
265#define __ICACHE_PRESENT 1
266#define __DCACHE_PRESENT 1
267#define __DTCM_PRESENT 1
268#define __NVIC_PRIO_BITS 4
269#define __Vendor_SysTickConfig 0
270#define __FPU_PRESENT 1
272#include "core_cm7.h" /* Core Peripheral Access Layer */
273#ifndef __PROJECT_MIKROSDK_MIKROE__
274// Note: Added for MikroE implementation.
275#include "system_MKV58F24.h" /* Device specific configuration file */
276#endif
277
278
281 /* end of group Cortex_Core_Configuration */
282
283
284/* ----------------------------------------------------------------------------
285 -- Mapping Information
286 ---------------------------------------------------------------------------- */
287
299/*******************************************************************************
300 * Definitions
301 ******************************************************************************/
302
310typedef enum _dma_request_source
311{
312 kDmaRequestMux0Disable = 0|0x100U,
313 kDmaRequestMux0Reserved1 = 1|0x100U,
314 kDmaRequestMux0UART0Rx = 2|0x100U,
315 kDmaRequestMux0UART0Tx = 3|0x100U,
316 kDmaRequestMux0UART1Rx = 4|0x100U,
317 kDmaRequestMux0UART1Tx = 5|0x100U,
318 kDmaRequestMux0PWM0WR0 = 6|0x100U,
319 kDmaRequestMux0PWM0WR1 = 7|0x100U,
320 kDmaRequestMux0PWM0WR2 = 8|0x100U,
321 kDmaRequestMux0PWM0WR3 = 9|0x100U,
322 kDmaRequestMux0PWM0CP0 = 10|0x100U,
323 kDmaRequestMux0PWM0CP1 = 11|0x100U,
324 kDmaRequestMux0PWM0CP2 = 12|0x100U,
325 kDmaRequestMux0PWM0CP3 = 13|0x100U,
326 kDmaRequestMux0CAN0 = 14|0x100U,
327 kDmaRequestMux0CAN1 = 15|0x100U,
328 kDmaRequestMux0SPI0Rx = 16|0x100U,
329 kDmaRequestMux0SPI0Tx = 17|0x100U,
330 kDmaRequestMux0XBARAOUT0 = 18|0x100U,
331 kDmaRequestMux0XBARAOUT1 = 19|0x100U,
332 kDmaRequestMux0XBARAOUT2 = 20|0x100U,
333 kDmaRequestMux0XBARAOUT3 = 21|0x100U,
334 kDmaRequestMux0I2C0 = 22|0x100U,
335 kDmaRequestMux0Reserved23 = 23|0x100U,
336 kDmaRequestMux0FTM0Channel0 = 24|0x100U,
337 kDmaRequestMux0FTM0Channel1 = 25|0x100U,
338 kDmaRequestMux0FTM0Channel2 = 26|0x100U,
339 kDmaRequestMux0FTM0Channel3 = 27|0x100U,
340 kDmaRequestMux0FTM0Channel4 = 28|0x100U,
341 kDmaRequestMux0FTM0Channel5 = 29|0x100U,
342 kDmaRequestMux0FTM0Channel6 = 30|0x100U,
343 kDmaRequestMux0FTM0Channel7 = 31|0x100U,
344 kDmaRequestMux0FTM1Channel0 = 32|0x100U,
345 kDmaRequestMux0FTM1Channel1 = 33|0x100U,
346 kDmaRequestMux0CMP3 = 34|0x100U,
347 kDmaRequestMux0Reserved35 = 35|0x100U,
348 kDmaRequestMux0FTM3Channel0 = 36|0x100U,
349 kDmaRequestMux0FTM3Channel1 = 37|0x100U,
350 kDmaRequestMux0FTM3Channel2 = 38|0x100U,
351 kDmaRequestMux0FTM3Channel3 = 39|0x100U,
352 kDmaRequestMux0HSADC0A = 40|0x100U,
353 kDmaRequestMux0HSADC0B = 41|0x100U,
354 kDmaRequestMux0CMP0 = 42|0x100U,
355 kDmaRequestMux0CMP1 = 43|0x100U,
356 kDmaRequestMux0CMP2 = 44|0x100U,
357 kDmaRequestMux0DAC0 = 45|0x100U,
358 kDmaRequestMux0Reserved46 = 46|0x100U,
359 kDmaRequestMux0PDB1 = 47|0x100U,
360 kDmaRequestMux0PDB0 = 48|0x100U,
361 kDmaRequestMux0PortA = 49|0x100U,
362 kDmaRequestMux0PortB = 50|0x100U,
363 kDmaRequestMux0PortC = 51|0x100U,
364 kDmaRequestMux0PortD = 52|0x100U,
365 kDmaRequestMux0PortE = 53|0x100U,
366 kDmaRequestMux0FTM3Channel4 = 54|0x100U,
367 kDmaRequestMux0FTM3Channel5 = 55|0x100U,
368 kDmaRequestMux0FTM3Channel6 = 56|0x100U,
369 kDmaRequestMux0FTM3Channel7 = 57|0x100U,
370 kDmaRequestMux0Reserved58 = 58|0x100U,
371 kDmaRequestMux0Reserved59 = 59|0x100U,
372 kDmaRequestMux0AlwaysOn60 = 60|0x100U,
373 kDmaRequestMux0AlwaysOn61 = 61|0x100U,
374 kDmaRequestMux0AlwaysOn62 = 62|0x100U,
375 kDmaRequestMux0AlwaysOn63 = 63|0x100U,
376 kDmaRequestMux0Group1Disable = 0|0x200U,
377 kDmaRequestMux0Group1Reserved1 = 1|0x200U,
378 kDmaRequestMux0Group1UART2Rx = 2|0x200U,
379 kDmaRequestMux0Group1UART2Tx = 3|0x200U,
380 kDmaRequestMux0Group1UART3Rx = 4|0x200U,
381 kDmaRequestMux0Group1UART3Tx = 5|0x200U,
382 kDmaRequestMux0Group1PWM1WR0 = 6|0x200U,
383 kDmaRequestMux0Group1PWM1WR1 = 7|0x200U,
384 kDmaRequestMux0Group1PWM1WR2 = 8|0x200U,
385 kDmaRequestMux0Group1PWM1WR3 = 9|0x200U,
386 kDmaRequestMux0Group1PWM1CP0 = 10|0x200U,
387 kDmaRequestMux0Group1PWM1CP1 = 11|0x200U,
388 kDmaRequestMux0Group1PWM1CP2 = 12|0x200U,
389 kDmaRequestMux0Group1PWM1CP3 = 13|0x200U,
390 kDmaRequestMux0Group1CAN2 = 14|0x200U,
391 kDmaRequestMux0Group1Reserved15 = 15|0x200U,
392 kDmaRequestMux0Group1SPI1Rx = 16|0x200U,
393 kDmaRequestMux0Group1SPI1Tx = 17|0x200U,
394 kDmaRequestMux0Group1Reserved18 = 18|0x200U,
395 kDmaRequestMux0Group1Reserved19 = 19|0x200U,
396 kDmaRequestMux0Group1Reserved20 = 20|0x200U,
397 kDmaRequestMux0Group1Reserved21 = 21|0x200U,
398 kDmaRequestMux0Group1I2C1 = 22|0x200U,
399 kDmaRequestMux0Group1Reserved23 = 23|0x200U,
400 kDmaRequestMux0Group1Reserved24 = 24|0x200U,
401 kDmaRequestMux0Group1Reserved25 = 25|0x200U,
402 kDmaRequestMux0Group1Reserved26 = 26|0x200U,
403 kDmaRequestMux0Group1Reserved27 = 27|0x200U,
404 kDmaRequestMux0Group1Reserved28 = 28|0x200U,
405 kDmaRequestMux0Group1Reserved29 = 29|0x200U,
406 kDmaRequestMux0Group1Reserved30 = 30|0x200U,
407 kDmaRequestMux0Group1Reserved31 = 31|0x200U,
408 kDmaRequestMux0Group1FTM2Channel0 = 32|0x200U,
409 kDmaRequestMux0Group1FTM2Channel1 = 33|0x200U,
410 kDmaRequestMux0Group1SPI2Rx = 34|0x200U,
411 kDmaRequestMux0Group1SPI2Tx = 35|0x200U,
412 kDmaRequestMux0Group1IEEE1588Timer0 = 36|0x200U,
413 kDmaRequestMux0Group1IEEE1588Timer1 = 37|0x200U,
414 kDmaRequestMux0Group1IEEE1588Timer2 = 38|0x200U,
415 kDmaRequestMux0Group1IEEE1588Timer3 = 39|0x200U,
416 kDmaRequestMux0Group1HSADC1A = 40|0x200U,
417 kDmaRequestMux0Group1HSADC1B = 41|0x200U,
418 kDmaRequestMux0Group1Reserved42 = 42|0x200U,
419 kDmaRequestMux0Group1Reserved43 = 43|0x200U,
420 kDmaRequestMux0Group1Reserved44 = 44|0x200U,
421 kDmaRequestMux0Group1ADC0 = 45|0x200U,
422 kDmaRequestMux0Group1Reserved46 = 46|0x200U,
423 kDmaRequestMux0Group1Reserved47 = 47|0x200U,
424 kDmaRequestMux0Group1Reserved48 = 48|0x200U,
425 kDmaRequestMux0Group1Reserved49 = 49|0x200U,
426 kDmaRequestMux0Group1Reserved50 = 50|0x200U,
427 kDmaRequestMux0Group1Reserved51 = 51|0x200U,
428 kDmaRequestMux0Group1Reserved52 = 52|0x200U,
429 kDmaRequestMux0Group1Reserved53 = 53|0x200U,
430 kDmaRequestMux0Group1UART4Rx = 54|0x200U,
431 kDmaRequestMux0Group1UART4Tx = 55|0x200U,
432 kDmaRequestMux0Group1UART5Rx = 56|0x200U,
433 kDmaRequestMux0Group1UART5Tx = 57|0x200U,
434 kDmaRequestMux0Group1Reserved58 = 58|0x200U,
435 kDmaRequestMux0Group1Reserved59 = 59|0x200U,
436 kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U,
437 kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U,
438 kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U,
439 kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U,
440} dma_request_source_t;
441
442/* @} */
443
444typedef enum _xbar_input_signal
445{
446 kXBARA_InputVss = 0|0x100U,
447 kXBARA_InputVdd = 1|0x100U,
448 kXBARA_InputXbarIn2 = 2|0x100U,
449 kXBARA_InputXbarIn3 = 3|0x100U,
450 kXBARA_InputXbarIn4 = 4|0x100U,
451 kXBARA_InputXbarIn5 = 5|0x100U,
452 kXBARA_InputXbarIn6 = 6|0x100U,
453 kXBARA_InputXbarIn7 = 7|0x100U,
454 kXBARA_InputXbarIn8 = 8|0x100U,
455 kXBARA_InputXbarIn9 = 9|0x100U,
456 kXBARA_InputXbarIn10 = 10|0x100U,
457 kXBARA_InputXbarIn11 = 11|0x100U,
458 kXBARA_InputCmp0Output = 12|0x100U,
459 kXBARA_InputCmp1Output = 13|0x100U,
460 kXBARA_InputCmp2Output = 14|0x100U,
461 kXBARA_InputCmp3Output = 15|0x100U,
462 kXBARA_InputFtm0Match = 16|0x100U,
463 kXBARA_InputFtm0Extrig = 17|0x100U,
464 kXBARA_InputFtm3Match = 18|0x100U,
465 kXBARA_InputFtm3Extrig = 19|0x100U,
466 kXBARA_InputPwm0Ch0Trg0 = 20|0x100U,
467 kXBARA_InputPwm0Ch0Trg1 = 21|0x100U,
468 kXBARA_InputPwm0Ch1Trg0 = 22|0x100U,
469 kXBARA_InputPwm0Ch1Trg1 = 23|0x100U,
470 kXBARA_InputPwm0Ch2Trg0 = 24|0x100U,
471 kXBARA_InputPwm0Ch2Trg1 = 25|0x100U,
472 kXBARA_InputPwm0Ch3Trg0 = 26|0x100U,
473 kXBARA_InputPwm0Ch3Trg1 = 27|0x100U,
474 kXBARA_InputPdb0Ch1Output = 28|0x100U,
475 kXBARA_InputPdb0Ch0Output = 29|0x100U,
476 kXBARA_InputPdb1Ch1Output = 30|0x100U,
477 kXBARA_InputPdb1Ch0Output = 31|0x100U,
478 kXBARA_InputHsadc1Cca = 32|0x100U,
479 kXBARA_InputHsadc0Cca = 33|0x100U,
480 kXBARA_InputHsadc1Ccb = 34|0x100U,
481 kXBARA_InputHsadc0Ccb = 35|0x100U,
482 kXBARA_InputFtm1Match = 36|0x100U,
483 kXBARA_InputFtm1Extrig = 37|0x100U,
484 kXBARA_InputDmaCh0Done = 38|0x100U,
485 kXBARA_InputDmaCh1Done = 39|0x100U,
486 kXBARA_InputDmaCh6Done = 40|0x100U,
487 kXBARA_InputDmaCh7Done = 41|0x100U,
488 kXBARA_InputPitTrigger0 = 42|0x100U,
489 kXBARA_InputPitTrigger1 = 43|0x100U,
490 kXBARA_InputAdc0Coco = 44|0x100U,
491 kXBARA_InputEnc0CmpPosMatch = 45|0x100U,
492 kXBARA_InputAndOrInvert0 = 46|0x100U,
493 kXBARA_InputAndOrInvert1 = 47|0x100U,
494 kXBARA_InputAndOrInvert2 = 48|0x100U,
495 kXBARA_InputAndOrInvert3 = 49|0x100U,
496 kXBARA_InputPitTrigger2 = 50|0x100U,
497 kXBARA_InputPitTrigger3 = 51|0x100U,
498 kXBARA_InputPwm1Ch0Trg0OrTrg1 = 52|0x100U,
499 kXBARA_InputPwm1Ch1Trg0OrTrg1 = 53|0x100U,
500 kXBARA_InputPwm1Ch2Trg0OrTrg1 = 54|0x100U,
501 kXBARA_InputPwm1Ch3Trg0OrTrg1 = 55|0x100U,
502 kXBARA_InputFtm2Match = 56|0x100U,
503 kXBARA_InputFtm2Extrig = 57|0x100U,
504 kXBARB_InputCmp0Output = 0|0x200U,
505 kXBARB_InputCmp1Output = 1|0x200U,
506 kXBARB_InputCmp2Output = 2|0x200U,
507 kXBARB_InputCmp3Output = 3|0x200U,
508 kXBARB_InputFtm0Match = 4|0x200U,
509 kXBARB_InputFtm0Extrig = 5|0x200U,
510 kXBARB_InputFtm3Match = 6|0x200U,
511 kXBARB_InputFtm3Extrig = 7|0x200U,
512 kXBARB_InputPwm0Ch0Trg0 = 8|0x200U,
513 kXBARB_InputPwm0Ch1Trg0 = 9|0x200U,
514 kXBARB_InputPwm0Ch2Trg0 = 10|0x200U,
515 kXBARB_InputPwm0Ch3Trg0 = 11|0x200U,
516 kXBARB_InputPdb0Ch0Output = 12|0x200U,
517 kXBARB_InputHsadc0Cca = 13|0x200U,
518 kXBARB_InputXbarIn2 = 14|0x200U,
519 kXBARB_InputXbarIn3 = 15|0x200U,
520 kXBARB_InputFtm1Match = 16|0x200U,
521 kXBARB_InputFtm1Extrig = 17|0x200U,
522 kXBARB_InputDmaCh0Done = 18|0x200U,
523 kXBARB_InputDmaCh1Done = 19|0x200U,
524 kXBARB_InputXbarIn10 = 20|0x200U,
525 kXBARB_InputXbarIn11 = 21|0x200U,
526 kXBARB_InputDmaCh6Done = 22|0x200U,
527 kXBARB_InputDmaCh7Done = 23|0x200U,
528 kXBARB_InputPitTrigger0 = 24|0x200U,
529 kXBARB_InputPitTrigger1 = 25|0x200U,
530 kXBARB_InputPdb1Ch0Output = 26|0x200U,
531 kXBARB_InputHsadc0Ccb = 27|0x200U,
532 kXBARB_InputPwm1Ch0Trg0OrTrg1 = 28|0x200U,
533 kXBARB_InputPwm1Ch1Trg0OrTrg1 = 29|0x200U,
534 kXBARB_InputPwm1Ch2Trg0OrTrg1 = 30|0x200U,
535 kXBARB_InputPwm1Ch3Trg0OrTrg1 = 31|0x200U,
536 kXBARB_InputFtm2Match = 32|0x200U,
537 kXBARB_InputFtm2Extrig = 33|0x200U,
538 kXBARB_InputPdb0Ch1Output = 34|0x200U,
539 kXBARB_InputPdb1Ch1Output = 35|0x200U,
540 kXBARB_InputHsadc1Cca = 36|0x200U,
541 kXBARB_InputHsadc1Ccb = 37|0x200U,
542 kXBARB_InputAdc0Coco = 38|0x200U,
543} xbar_input_signal_t;
544
545typedef enum _xbar_output_signal
546{
547 kXBARA_OutputDmamux18 = 0|0x100U,
548 kXBARA_OutputDmamux19 = 1|0x100U,
549 kXBARA_OutputDmamux20 = 2|0x100U,
550 kXBARA_OutputDmamux21 = 3|0x100U,
551 kXBARA_OutputXbOut4 = 4|0x100U,
552 kXBARA_OutputXbOut5 = 5|0x100U,
553 kXBARA_OutputXbOut6 = 6|0x100U,
554 kXBARA_OutputXbOut7 = 7|0x100U,
555 kXBARA_OutputXbOut8 = 8|0x100U,
556 kXBARA_OutputXbOut9 = 9|0x100U,
557 kXBARA_OutputXbOut10 = 10|0x100U,
558 kXBARA_OutputXbOut11 = 11|0x100U,
559 kXBARA_OutputHsadc0ATrig = 12|0x100U,
560 kXBARA_OutputHsadc0BTrig = 13|0x100U,
561 kXBARA_OutputRESERVED14 = 14|0x100U,
562 kXBARA_OutputDac12bSync = 15|0x100U,
563 kXBARA_OutputCmp0 = 16|0x100U,
564 kXBARA_OutputCmp1 = 17|0x100U,
565 kXBARA_OutputCmp2 = 18|0x100U,
566 kXBARA_OutputCmp3 = 19|0x100U,
567 kXBARA_OutputPwmCh0ExtA = 20|0x100U,
568 kXBARA_OutputPwmCh1ExtA = 21|0x100U,
569 kXBARA_OutputPwmCh2ExtA = 22|0x100U,
570 kXBARA_OutputPwmCh3ExtA = 23|0x100U,
571 kXBARA_OutputPwm0Ch0ExtSync = 24|0x100U,
572 kXBARA_OutputPwm0Ch1ExtSync = 25|0x100U,
573 kXBARA_OutputPwm0Ch2ExtSync = 26|0x100U,
574 kXBARA_OutputPwm0Ch3ExtSync = 27|0x100U,
575 kXBARA_OutputPwmExtClk = 28|0x100U,
576 kXBARA_OutputPwm0Fault0 = 29|0x100U,
577 kXBARA_OutputPwm0Fault1 = 30|0x100U,
578 kXBARA_OutputPwm0Fault2 = 31|0x100U,
579 kXBARA_OutputPwm0Fault3 = 32|0x100U,
580 kXBARA_OutputPwm0Force = 33|0x100U,
581 kXBARA_OutputFtm0Trig2 = 34|0x100U,
582 kXBARA_OutputFtm1Trig2 = 35|0x100U,
583 kXBARA_OutputFtm2Trig2 = 36|0x100U,
584 kXBARA_OutputFtm3Trig2 = 37|0x100U,
585 kXBARA_OutputPdb0InCh12 = 38|0x100U,
586 kXBARA_OutputAdc0Hdwt = 39|0x100U,
587 kXBARA_OutputRESERVED40 = 40|0x100U,
588 kXBARA_OutputPdb1InCh12 = 41|0x100U,
589 kXBARA_OutputHsadc1ATrig = 42|0x100U,
590 kXBARA_OutputHsadc1BTrig = 43|0x100U,
591 kXBARA_OutputEncPhA = 44|0x100U,
592 kXBARA_OutputEncPhB = 45|0x100U,
593 kXBARA_OutputEncIndex = 46|0x100U,
594 kXBARA_OutputEncHome = 47|0x100U,
595 kXBARA_OutputEncCapTrigger = 48|0x100U,
596 kXBARA_OutputFtm0Fault3 = 49|0x100U,
597 kXBARA_OutputFtm1Fault1 = 50|0x100U,
598 kXBARA_OutputFtm2Fault1 = 51|0x100U,
599 kXBARA_OutputFtm3Fault3 = 52|0x100U,
600 kXBARA_OutputPwm1Ch0ExtSync = 53|0x100U,
601 kXBARA_OutputPwm1Ch1ExtSync = 54|0x100U,
602 kXBARA_OutputPwm1Ch2ExtSync = 55|0x100U,
603 kXBARA_OutputPwm1Ch3ExtSync = 56|0x100U,
604 kXBARA_OutputPwm1Force = 57|0x100U,
605 kXBARA_OutputEwmIn = 58|0x100U,
606 kXBARB_OutputAoiIn0 = 0|0x200U,
607 kXBARB_OutputAoiIn1 = 1|0x200U,
608 kXBARB_OutputAoiIn2 = 2|0x200U,
609 kXBARB_OutputAoiIn3 = 3|0x200U,
610 kXBARB_OutputAoiIn4 = 4|0x200U,
611 kXBARB_OutputAoiIn5 = 5|0x200U,
612 kXBARB_OutputAoiIn6 = 6|0x200U,
613 kXBARB_OutputAoiIn7 = 7|0x200U,
614 kXBARB_OutputAoiIn8 = 8|0x200U,
615 kXBARB_OutputAoiIn9 = 9|0x200U,
616 kXBARB_OutputAoiIn10 = 10|0x200U,
617 kXBARB_OutputAoiIn11 = 11|0x200U,
618 kXBARB_OutputAoiIn12 = 12|0x200U,
619 kXBARB_OutputAoiIn13 = 13|0x200U,
620 kXBARB_OutputAoiIn14 = 14|0x200U,
621 kXBARB_OutputAoiIn15 = 15|0x200U,
622} xbar_output_signal_t;
623
624
627 /* end of group Mapping_Information */
628
629
630/* ----------------------------------------------------------------------------
631 -- Device Peripheral Access Layer
632 ---------------------------------------------------------------------------- */
633
640/*
641** Start of section using anonymous unions
642*/
643
644#if defined(__ARMCC_VERSION)
645 #if (__ARMCC_VERSION >= 6010050)
646 #pragma clang diagnostic push
647 #else
648 #pragma push
649 #pragma anon_unions
650 #endif
651#elif defined(__CWCC__)
652 #pragma push
653 #pragma cpp_extensions on
654#elif defined(__GNUC__)
655 /* anonymous unions are enabled by default */
656#elif defined(__IAR_SYSTEMS_ICC__)
657 #pragma language=extended
658#else
659 #error Not supported compiler type
660#endif
661
662/* ----------------------------------------------------------------------------
663 -- ADC Peripheral Access Layer
664 ---------------------------------------------------------------------------- */
665
672typedef struct {
673 __IO uint32_t SC1[2];
674 __IO uint32_t CFG1;
675 __IO uint32_t CFG2;
676 __I uint32_t R[2];
677 __IO uint32_t CV1;
678 __IO uint32_t CV2;
679 __IO uint32_t SC2;
680 __IO uint32_t SC3;
681 __IO uint32_t OFS;
682 __IO uint32_t PG;
683 __IO uint32_t MG;
684 __IO uint32_t CLPD;
685 __IO uint32_t CLPS;
686 __IO uint32_t CLP4;
687 __IO uint32_t CLP3;
688 __IO uint32_t CLP2;
689 __IO uint32_t CLP1;
690 __IO uint32_t CLP0;
691 uint8_t RESERVED_0[4];
692 __IO uint32_t CLMD;
693 __IO uint32_t CLMS;
694 __IO uint32_t CLM4;
695 __IO uint32_t CLM3;
696 __IO uint32_t CLM2;
697 __IO uint32_t CLM1;
698 __IO uint32_t CLM0;
699} ADC_Type;
700
701/* ----------------------------------------------------------------------------
702 -- ADC Register Masks
703 ---------------------------------------------------------------------------- */
704
712#define ADC_SC1_ADCH_MASK (0x1FU)
713#define ADC_SC1_ADCH_SHIFT (0U)
748#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
749#define ADC_SC1_DIFF_MASK (0x20U)
750#define ADC_SC1_DIFF_SHIFT (5U)
755#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
756#define ADC_SC1_AIEN_MASK (0x40U)
757#define ADC_SC1_AIEN_SHIFT (6U)
762#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
763#define ADC_SC1_COCO_MASK (0x80U)
764#define ADC_SC1_COCO_SHIFT (7U)
769#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
772/* The count of ADC_SC1 */
773#define ADC_SC1_COUNT (2U)
774
777#define ADC_CFG1_ADICLK_MASK (0x3U)
778#define ADC_CFG1_ADICLK_SHIFT (0U)
785#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
786#define ADC_CFG1_MODE_MASK (0xCU)
787#define ADC_CFG1_MODE_SHIFT (2U)
794#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
795#define ADC_CFG1_ADLSMP_MASK (0x10U)
796#define ADC_CFG1_ADLSMP_SHIFT (4U)
801#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
802#define ADC_CFG1_ADIV_MASK (0x60U)
803#define ADC_CFG1_ADIV_SHIFT (5U)
810#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
811#define ADC_CFG1_ADLPC_MASK (0x80U)
812#define ADC_CFG1_ADLPC_SHIFT (7U)
817#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
822#define ADC_CFG2_ADLSTS_MASK (0x3U)
823#define ADC_CFG2_ADLSTS_SHIFT (0U)
830#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
831#define ADC_CFG2_ADHSC_MASK (0x4U)
832#define ADC_CFG2_ADHSC_SHIFT (2U)
837#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
838#define ADC_CFG2_ADACKEN_MASK (0x8U)
839#define ADC_CFG2_ADACKEN_SHIFT (3U)
844#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
845#define ADC_CFG2_MUXSEL_MASK (0x10U)
846#define ADC_CFG2_MUXSEL_SHIFT (4U)
851#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
856#define ADC_R_D_MASK (0xFFFFU)
857#define ADC_R_D_SHIFT (0U)
858#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
861/* The count of ADC_R */
862#define ADC_R_COUNT (2U)
863
866#define ADC_CV1_CV_MASK (0xFFFFU)
867#define ADC_CV1_CV_SHIFT (0U)
868#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
873#define ADC_CV2_CV_MASK (0xFFFFU)
874#define ADC_CV2_CV_SHIFT (0U)
875#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
880#define ADC_SC2_REFSEL_MASK (0x3U)
881#define ADC_SC2_REFSEL_SHIFT (0U)
888#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
889#define ADC_SC2_DMAEN_MASK (0x4U)
890#define ADC_SC2_DMAEN_SHIFT (2U)
895#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
896#define ADC_SC2_ACREN_MASK (0x8U)
897#define ADC_SC2_ACREN_SHIFT (3U)
902#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
903#define ADC_SC2_ACFGT_MASK (0x10U)
904#define ADC_SC2_ACFGT_SHIFT (4U)
909#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
910#define ADC_SC2_ACFE_MASK (0x20U)
911#define ADC_SC2_ACFE_SHIFT (5U)
916#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
917#define ADC_SC2_ADTRG_MASK (0x40U)
918#define ADC_SC2_ADTRG_SHIFT (6U)
923#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
924#define ADC_SC2_ADACT_MASK (0x80U)
925#define ADC_SC2_ADACT_SHIFT (7U)
930#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
935#define ADC_SC3_AVGS_MASK (0x3U)
936#define ADC_SC3_AVGS_SHIFT (0U)
943#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
944#define ADC_SC3_AVGE_MASK (0x4U)
945#define ADC_SC3_AVGE_SHIFT (2U)
950#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
951#define ADC_SC3_ADCO_MASK (0x8U)
952#define ADC_SC3_ADCO_SHIFT (3U)
957#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
958#define ADC_SC3_CALF_MASK (0x40U)
959#define ADC_SC3_CALF_SHIFT (6U)
964#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
965#define ADC_SC3_CAL_MASK (0x80U)
966#define ADC_SC3_CAL_SHIFT (7U)
967#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
972#define ADC_OFS_OFS_MASK (0xFFFFU)
973#define ADC_OFS_OFS_SHIFT (0U)
974#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
979#define ADC_PG_PG_MASK (0xFFFFU)
980#define ADC_PG_PG_SHIFT (0U)
981#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
986#define ADC_MG_MG_MASK (0xFFFFU)
987#define ADC_MG_MG_SHIFT (0U)
988#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
993#define ADC_CLPD_CLPD_MASK (0x3FU)
994#define ADC_CLPD_CLPD_SHIFT (0U)
995#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
1000#define ADC_CLPS_CLPS_MASK (0x3FU)
1001#define ADC_CLPS_CLPS_SHIFT (0U)
1002#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
1007#define ADC_CLP4_CLP4_MASK (0x3FFU)
1008#define ADC_CLP4_CLP4_SHIFT (0U)
1009#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
1014#define ADC_CLP3_CLP3_MASK (0x1FFU)
1015#define ADC_CLP3_CLP3_SHIFT (0U)
1016#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
1021#define ADC_CLP2_CLP2_MASK (0xFFU)
1022#define ADC_CLP2_CLP2_SHIFT (0U)
1023#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
1028#define ADC_CLP1_CLP1_MASK (0x7FU)
1029#define ADC_CLP1_CLP1_SHIFT (0U)
1030#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
1035#define ADC_CLP0_CLP0_MASK (0x3FU)
1036#define ADC_CLP0_CLP0_SHIFT (0U)
1037#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
1042#define ADC_CLMD_CLMD_MASK (0x3FU)
1043#define ADC_CLMD_CLMD_SHIFT (0U)
1044#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
1049#define ADC_CLMS_CLMS_MASK (0x3FU)
1050#define ADC_CLMS_CLMS_SHIFT (0U)
1051#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
1056#define ADC_CLM4_CLM4_MASK (0x3FFU)
1057#define ADC_CLM4_CLM4_SHIFT (0U)
1058#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
1063#define ADC_CLM3_CLM3_MASK (0x1FFU)
1064#define ADC_CLM3_CLM3_SHIFT (0U)
1065#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
1070#define ADC_CLM2_CLM2_MASK (0xFFU)
1071#define ADC_CLM2_CLM2_SHIFT (0U)
1072#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
1077#define ADC_CLM1_CLM1_MASK (0x7FU)
1078#define ADC_CLM1_CLM1_SHIFT (0U)
1079#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
1084#define ADC_CLM0_CLM0_MASK (0x3FU)
1085#define ADC_CLM0_CLM0_SHIFT (0U)
1086#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
1092 /* end of group ADC_Register_Masks */
1093
1094
1095/* ADC - Peripheral instance base addresses */
1097#define ADC0_BASE (0x4003B000u)
1099#define ADC0 ((ADC_Type *)ADC0_BASE)
1101#define ADC_BASE_ADDRS { ADC0_BASE }
1103#define ADC_BASE_PTRS { ADC0 }
1105#define ADC_IRQS { ADC0_IRQn }
1106
1109 /* end of group ADC_Peripheral_Access_Layer */
1110
1111
1112/* ----------------------------------------------------------------------------
1113 -- AIPS Peripheral Access Layer
1114 ---------------------------------------------------------------------------- */
1115
1122typedef struct {
1123 __IO uint32_t MPRA;
1124 uint8_t RESERVED_0[28];
1125 __IO uint32_t PACRA;
1126 __IO uint32_t PACRB;
1127 __IO uint32_t PACRC;
1128 __IO uint32_t PACRD;
1129 uint8_t RESERVED_1[16];
1130 __IO uint32_t PACRE;
1131 __IO uint32_t PACRF;
1132 __IO uint32_t PACRG;
1133 __IO uint32_t PACRH;
1134 __IO uint32_t PACRI;
1135 __IO uint32_t PACRJ;
1136 __IO uint32_t PACRK;
1137 __IO uint32_t PACRL;
1138 __IO uint32_t PACRM;
1139 __IO uint32_t PACRN;
1140 __IO uint32_t PACRO;
1141 __IO uint32_t PACRP;
1142} AIPS_Type;
1143
1144/* ----------------------------------------------------------------------------
1145 -- AIPS Register Masks
1146 ---------------------------------------------------------------------------- */
1147
1155#define AIPS_MPRA_MPL3_MASK (0x10000U)
1156#define AIPS_MPRA_MPL3_SHIFT (16U)
1161#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
1162#define AIPS_MPRA_MTW3_MASK (0x20000U)
1163#define AIPS_MPRA_MTW3_SHIFT (17U)
1168#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
1169#define AIPS_MPRA_MTR3_MASK (0x40000U)
1170#define AIPS_MPRA_MTR3_SHIFT (18U)
1175#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
1176#define AIPS_MPRA_MPL2_MASK (0x100000U)
1177#define AIPS_MPRA_MPL2_SHIFT (20U)
1182#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
1183#define AIPS_MPRA_MTW2_MASK (0x200000U)
1184#define AIPS_MPRA_MTW2_SHIFT (21U)
1189#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
1190#define AIPS_MPRA_MTR2_MASK (0x400000U)
1191#define AIPS_MPRA_MTR2_SHIFT (22U)
1196#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
1197#define AIPS_MPRA_MPL1_MASK (0x1000000U)
1198#define AIPS_MPRA_MPL1_SHIFT (24U)
1203#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1204#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1205#define AIPS_MPRA_MTW1_SHIFT (25U)
1210#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1211#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1212#define AIPS_MPRA_MTR1_SHIFT (26U)
1217#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1218#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1219#define AIPS_MPRA_MPL0_SHIFT (28U)
1224#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1225#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1226#define AIPS_MPRA_MTW0_SHIFT (29U)
1231#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1232#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1233#define AIPS_MPRA_MTR0_SHIFT (30U)
1238#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1243#define AIPS_PACRA_TP7_MASK (0x1U)
1244#define AIPS_PACRA_TP7_SHIFT (0U)
1249#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1250#define AIPS_PACRA_WP7_MASK (0x2U)
1251#define AIPS_PACRA_WP7_SHIFT (1U)
1256#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1257#define AIPS_PACRA_SP7_MASK (0x4U)
1258#define AIPS_PACRA_SP7_SHIFT (2U)
1263#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1264#define AIPS_PACRA_TP6_MASK (0x10U)
1265#define AIPS_PACRA_TP6_SHIFT (4U)
1270#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1271#define AIPS_PACRA_WP6_MASK (0x20U)
1272#define AIPS_PACRA_WP6_SHIFT (5U)
1277#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1278#define AIPS_PACRA_SP6_MASK (0x40U)
1279#define AIPS_PACRA_SP6_SHIFT (6U)
1284#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1285#define AIPS_PACRA_TP5_MASK (0x100U)
1286#define AIPS_PACRA_TP5_SHIFT (8U)
1291#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1292#define AIPS_PACRA_WP5_MASK (0x200U)
1293#define AIPS_PACRA_WP5_SHIFT (9U)
1298#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1299#define AIPS_PACRA_SP5_MASK (0x400U)
1300#define AIPS_PACRA_SP5_SHIFT (10U)
1305#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1306#define AIPS_PACRA_TP4_MASK (0x1000U)
1307#define AIPS_PACRA_TP4_SHIFT (12U)
1312#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1313#define AIPS_PACRA_WP4_MASK (0x2000U)
1314#define AIPS_PACRA_WP4_SHIFT (13U)
1319#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1320#define AIPS_PACRA_SP4_MASK (0x4000U)
1321#define AIPS_PACRA_SP4_SHIFT (14U)
1326#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1327#define AIPS_PACRA_TP3_MASK (0x10000U)
1328#define AIPS_PACRA_TP3_SHIFT (16U)
1333#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1334#define AIPS_PACRA_WP3_MASK (0x20000U)
1335#define AIPS_PACRA_WP3_SHIFT (17U)
1340#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1341#define AIPS_PACRA_SP3_MASK (0x40000U)
1342#define AIPS_PACRA_SP3_SHIFT (18U)
1347#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1348#define AIPS_PACRA_TP2_MASK (0x100000U)
1349#define AIPS_PACRA_TP2_SHIFT (20U)
1354#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1355#define AIPS_PACRA_WP2_MASK (0x200000U)
1356#define AIPS_PACRA_WP2_SHIFT (21U)
1361#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1362#define AIPS_PACRA_SP2_MASK (0x400000U)
1363#define AIPS_PACRA_SP2_SHIFT (22U)
1368#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1369#define AIPS_PACRA_TP1_MASK (0x1000000U)
1370#define AIPS_PACRA_TP1_SHIFT (24U)
1375#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1376#define AIPS_PACRA_WP1_MASK (0x2000000U)
1377#define AIPS_PACRA_WP1_SHIFT (25U)
1382#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1383#define AIPS_PACRA_SP1_MASK (0x4000000U)
1384#define AIPS_PACRA_SP1_SHIFT (26U)
1389#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1390#define AIPS_PACRA_TP0_MASK (0x10000000U)
1391#define AIPS_PACRA_TP0_SHIFT (28U)
1396#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1397#define AIPS_PACRA_WP0_MASK (0x20000000U)
1398#define AIPS_PACRA_WP0_SHIFT (29U)
1403#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1404#define AIPS_PACRA_SP0_MASK (0x40000000U)
1405#define AIPS_PACRA_SP0_SHIFT (30U)
1410#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1415#define AIPS_PACRB_TP7_MASK (0x1U)
1416#define AIPS_PACRB_TP7_SHIFT (0U)
1421#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1422#define AIPS_PACRB_WP7_MASK (0x2U)
1423#define AIPS_PACRB_WP7_SHIFT (1U)
1428#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1429#define AIPS_PACRB_SP7_MASK (0x4U)
1430#define AIPS_PACRB_SP7_SHIFT (2U)
1435#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1436#define AIPS_PACRB_TP6_MASK (0x10U)
1437#define AIPS_PACRB_TP6_SHIFT (4U)
1442#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1443#define AIPS_PACRB_WP6_MASK (0x20U)
1444#define AIPS_PACRB_WP6_SHIFT (5U)
1449#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1450#define AIPS_PACRB_SP6_MASK (0x40U)
1451#define AIPS_PACRB_SP6_SHIFT (6U)
1456#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1457#define AIPS_PACRB_TP5_MASK (0x100U)
1458#define AIPS_PACRB_TP5_SHIFT (8U)
1463#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1464#define AIPS_PACRB_WP5_MASK (0x200U)
1465#define AIPS_PACRB_WP5_SHIFT (9U)
1470#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1471#define AIPS_PACRB_SP5_MASK (0x400U)
1472#define AIPS_PACRB_SP5_SHIFT (10U)
1477#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1478#define AIPS_PACRB_TP4_MASK (0x1000U)
1479#define AIPS_PACRB_TP4_SHIFT (12U)
1484#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1485#define AIPS_PACRB_WP4_MASK (0x2000U)
1486#define AIPS_PACRB_WP4_SHIFT (13U)
1491#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1492#define AIPS_PACRB_SP4_MASK (0x4000U)
1493#define AIPS_PACRB_SP4_SHIFT (14U)
1498#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1499#define AIPS_PACRB_TP3_MASK (0x10000U)
1500#define AIPS_PACRB_TP3_SHIFT (16U)
1505#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1506#define AIPS_PACRB_WP3_MASK (0x20000U)
1507#define AIPS_PACRB_WP3_SHIFT (17U)
1512#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1513#define AIPS_PACRB_SP3_MASK (0x40000U)
1514#define AIPS_PACRB_SP3_SHIFT (18U)
1519#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1520#define AIPS_PACRB_TP2_MASK (0x100000U)
1521#define AIPS_PACRB_TP2_SHIFT (20U)
1526#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1527#define AIPS_PACRB_WP2_MASK (0x200000U)
1528#define AIPS_PACRB_WP2_SHIFT (21U)
1533#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1534#define AIPS_PACRB_SP2_MASK (0x400000U)
1535#define AIPS_PACRB_SP2_SHIFT (22U)
1540#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1541#define AIPS_PACRB_TP1_MASK (0x1000000U)
1542#define AIPS_PACRB_TP1_SHIFT (24U)
1547#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1548#define AIPS_PACRB_WP1_MASK (0x2000000U)
1549#define AIPS_PACRB_WP1_SHIFT (25U)
1554#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1555#define AIPS_PACRB_SP1_MASK (0x4000000U)
1556#define AIPS_PACRB_SP1_SHIFT (26U)
1561#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1562#define AIPS_PACRB_TP0_MASK (0x10000000U)
1563#define AIPS_PACRB_TP0_SHIFT (28U)
1568#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1569#define AIPS_PACRB_WP0_MASK (0x20000000U)
1570#define AIPS_PACRB_WP0_SHIFT (29U)
1575#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1576#define AIPS_PACRB_SP0_MASK (0x40000000U)
1577#define AIPS_PACRB_SP0_SHIFT (30U)
1582#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1587#define AIPS_PACRC_TP7_MASK (0x1U)
1588#define AIPS_PACRC_TP7_SHIFT (0U)
1593#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1594#define AIPS_PACRC_WP7_MASK (0x2U)
1595#define AIPS_PACRC_WP7_SHIFT (1U)
1600#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1601#define AIPS_PACRC_SP7_MASK (0x4U)
1602#define AIPS_PACRC_SP7_SHIFT (2U)
1607#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1608#define AIPS_PACRC_TP6_MASK (0x10U)
1609#define AIPS_PACRC_TP6_SHIFT (4U)
1614#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1615#define AIPS_PACRC_WP6_MASK (0x20U)
1616#define AIPS_PACRC_WP6_SHIFT (5U)
1621#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1622#define AIPS_PACRC_SP6_MASK (0x40U)
1623#define AIPS_PACRC_SP6_SHIFT (6U)
1628#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1629#define AIPS_PACRC_TP5_MASK (0x100U)
1630#define AIPS_PACRC_TP5_SHIFT (8U)
1635#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1636#define AIPS_PACRC_WP5_MASK (0x200U)
1637#define AIPS_PACRC_WP5_SHIFT (9U)
1642#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1643#define AIPS_PACRC_SP5_MASK (0x400U)
1644#define AIPS_PACRC_SP5_SHIFT (10U)
1649#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1650#define AIPS_PACRC_TP4_MASK (0x1000U)
1651#define AIPS_PACRC_TP4_SHIFT (12U)
1656#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1657#define AIPS_PACRC_WP4_MASK (0x2000U)
1658#define AIPS_PACRC_WP4_SHIFT (13U)
1663#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1664#define AIPS_PACRC_SP4_MASK (0x4000U)
1665#define AIPS_PACRC_SP4_SHIFT (14U)
1670#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1671#define AIPS_PACRC_TP3_MASK (0x10000U)
1672#define AIPS_PACRC_TP3_SHIFT (16U)
1677#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1678#define AIPS_PACRC_WP3_MASK (0x20000U)
1679#define AIPS_PACRC_WP3_SHIFT (17U)
1684#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1685#define AIPS_PACRC_SP3_MASK (0x40000U)
1686#define AIPS_PACRC_SP3_SHIFT (18U)
1691#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1692#define AIPS_PACRC_TP2_MASK (0x100000U)
1693#define AIPS_PACRC_TP2_SHIFT (20U)
1698#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1699#define AIPS_PACRC_WP2_MASK (0x200000U)
1700#define AIPS_PACRC_WP2_SHIFT (21U)
1705#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1706#define AIPS_PACRC_SP2_MASK (0x400000U)
1707#define AIPS_PACRC_SP2_SHIFT (22U)
1712#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1713#define AIPS_PACRC_TP1_MASK (0x1000000U)
1714#define AIPS_PACRC_TP1_SHIFT (24U)
1719#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1720#define AIPS_PACRC_WP1_MASK (0x2000000U)
1721#define AIPS_PACRC_WP1_SHIFT (25U)
1726#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1727#define AIPS_PACRC_SP1_MASK (0x4000000U)
1728#define AIPS_PACRC_SP1_SHIFT (26U)
1733#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1734#define AIPS_PACRC_TP0_MASK (0x10000000U)
1735#define AIPS_PACRC_TP0_SHIFT (28U)
1740#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1741#define AIPS_PACRC_WP0_MASK (0x20000000U)
1742#define AIPS_PACRC_WP0_SHIFT (29U)
1747#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1748#define AIPS_PACRC_SP0_MASK (0x40000000U)
1749#define AIPS_PACRC_SP0_SHIFT (30U)
1754#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1759#define AIPS_PACRD_TP7_MASK (0x1U)
1760#define AIPS_PACRD_TP7_SHIFT (0U)
1765#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1766#define AIPS_PACRD_WP7_MASK (0x2U)
1767#define AIPS_PACRD_WP7_SHIFT (1U)
1772#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1773#define AIPS_PACRD_SP7_MASK (0x4U)
1774#define AIPS_PACRD_SP7_SHIFT (2U)
1779#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1780#define AIPS_PACRD_TP6_MASK (0x10U)
1781#define AIPS_PACRD_TP6_SHIFT (4U)
1786#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1787#define AIPS_PACRD_WP6_MASK (0x20U)
1788#define AIPS_PACRD_WP6_SHIFT (5U)
1793#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1794#define AIPS_PACRD_SP6_MASK (0x40U)
1795#define AIPS_PACRD_SP6_SHIFT (6U)
1800#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1801#define AIPS_PACRD_TP5_MASK (0x100U)
1802#define AIPS_PACRD_TP5_SHIFT (8U)
1807#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1808#define AIPS_PACRD_WP5_MASK (0x200U)
1809#define AIPS_PACRD_WP5_SHIFT (9U)
1814#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1815#define AIPS_PACRD_SP5_MASK (0x400U)
1816#define AIPS_PACRD_SP5_SHIFT (10U)
1821#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1822#define AIPS_PACRD_TP4_MASK (0x1000U)
1823#define AIPS_PACRD_TP4_SHIFT (12U)
1828#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1829#define AIPS_PACRD_WP4_MASK (0x2000U)
1830#define AIPS_PACRD_WP4_SHIFT (13U)
1835#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1836#define AIPS_PACRD_SP4_MASK (0x4000U)
1837#define AIPS_PACRD_SP4_SHIFT (14U)
1842#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1843#define AIPS_PACRD_TP3_MASK (0x10000U)
1844#define AIPS_PACRD_TP3_SHIFT (16U)
1849#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1850#define AIPS_PACRD_WP3_MASK (0x20000U)
1851#define AIPS_PACRD_WP3_SHIFT (17U)
1856#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1857#define AIPS_PACRD_SP3_MASK (0x40000U)
1858#define AIPS_PACRD_SP3_SHIFT (18U)
1863#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1864#define AIPS_PACRD_TP2_MASK (0x100000U)
1865#define AIPS_PACRD_TP2_SHIFT (20U)
1870#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1871#define AIPS_PACRD_WP2_MASK (0x200000U)
1872#define AIPS_PACRD_WP2_SHIFT (21U)
1877#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1878#define AIPS_PACRD_SP2_MASK (0x400000U)
1879#define AIPS_PACRD_SP2_SHIFT (22U)
1884#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1885#define AIPS_PACRD_TP1_MASK (0x1000000U)
1886#define AIPS_PACRD_TP1_SHIFT (24U)
1891#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1892#define AIPS_PACRD_WP1_MASK (0x2000000U)
1893#define AIPS_PACRD_WP1_SHIFT (25U)
1898#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1899#define AIPS_PACRD_SP1_MASK (0x4000000U)
1900#define AIPS_PACRD_SP1_SHIFT (26U)
1905#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1906#define AIPS_PACRD_TP0_MASK (0x10000000U)
1907#define AIPS_PACRD_TP0_SHIFT (28U)
1912#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1913#define AIPS_PACRD_WP0_MASK (0x20000000U)
1914#define AIPS_PACRD_WP0_SHIFT (29U)
1919#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1920#define AIPS_PACRD_SP0_MASK (0x40000000U)
1921#define AIPS_PACRD_SP0_SHIFT (30U)
1926#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1931#define AIPS_PACRE_TP7_MASK (0x1U)
1932#define AIPS_PACRE_TP7_SHIFT (0U)
1937#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1938#define AIPS_PACRE_WP7_MASK (0x2U)
1939#define AIPS_PACRE_WP7_SHIFT (1U)
1944#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1945#define AIPS_PACRE_SP7_MASK (0x4U)
1946#define AIPS_PACRE_SP7_SHIFT (2U)
1951#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1952#define AIPS_PACRE_TP6_MASK (0x10U)
1953#define AIPS_PACRE_TP6_SHIFT (4U)
1958#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1959#define AIPS_PACRE_WP6_MASK (0x20U)
1960#define AIPS_PACRE_WP6_SHIFT (5U)
1965#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1966#define AIPS_PACRE_SP6_MASK (0x40U)
1967#define AIPS_PACRE_SP6_SHIFT (6U)
1972#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1973#define AIPS_PACRE_TP5_MASK (0x100U)
1974#define AIPS_PACRE_TP5_SHIFT (8U)
1979#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1980#define AIPS_PACRE_WP5_MASK (0x200U)
1981#define AIPS_PACRE_WP5_SHIFT (9U)
1986#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1987#define AIPS_PACRE_SP5_MASK (0x400U)
1988#define AIPS_PACRE_SP5_SHIFT (10U)
1993#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1994#define AIPS_PACRE_TP4_MASK (0x1000U)
1995#define AIPS_PACRE_TP4_SHIFT (12U)
2000#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
2001#define AIPS_PACRE_WP4_MASK (0x2000U)
2002#define AIPS_PACRE_WP4_SHIFT (13U)
2007#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
2008#define AIPS_PACRE_SP4_MASK (0x4000U)
2009#define AIPS_PACRE_SP4_SHIFT (14U)
2014#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
2015#define AIPS_PACRE_TP3_MASK (0x10000U)
2016#define AIPS_PACRE_TP3_SHIFT (16U)
2021#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
2022#define AIPS_PACRE_WP3_MASK (0x20000U)
2023#define AIPS_PACRE_WP3_SHIFT (17U)
2028#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
2029#define AIPS_PACRE_SP3_MASK (0x40000U)
2030#define AIPS_PACRE_SP3_SHIFT (18U)
2035#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
2036#define AIPS_PACRE_TP2_MASK (0x100000U)
2037#define AIPS_PACRE_TP2_SHIFT (20U)
2042#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
2043#define AIPS_PACRE_WP2_MASK (0x200000U)
2044#define AIPS_PACRE_WP2_SHIFT (21U)
2049#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
2050#define AIPS_PACRE_SP2_MASK (0x400000U)
2051#define AIPS_PACRE_SP2_SHIFT (22U)
2056#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
2057#define AIPS_PACRE_TP1_MASK (0x1000000U)
2058#define AIPS_PACRE_TP1_SHIFT (24U)
2063#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
2064#define AIPS_PACRE_WP1_MASK (0x2000000U)
2065#define AIPS_PACRE_WP1_SHIFT (25U)
2070#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
2071#define AIPS_PACRE_SP1_MASK (0x4000000U)
2072#define AIPS_PACRE_SP1_SHIFT (26U)
2077#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
2078#define AIPS_PACRE_TP0_MASK (0x10000000U)
2079#define AIPS_PACRE_TP0_SHIFT (28U)
2084#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
2085#define AIPS_PACRE_WP0_MASK (0x20000000U)
2086#define AIPS_PACRE_WP0_SHIFT (29U)
2091#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
2092#define AIPS_PACRE_SP0_MASK (0x40000000U)
2093#define AIPS_PACRE_SP0_SHIFT (30U)
2098#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
2103#define AIPS_PACRF_TP7_MASK (0x1U)
2104#define AIPS_PACRF_TP7_SHIFT (0U)
2109#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
2110#define AIPS_PACRF_WP7_MASK (0x2U)
2111#define AIPS_PACRF_WP7_SHIFT (1U)
2116#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
2117#define AIPS_PACRF_SP7_MASK (0x4U)
2118#define AIPS_PACRF_SP7_SHIFT (2U)
2123#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
2124#define AIPS_PACRF_TP6_MASK (0x10U)
2125#define AIPS_PACRF_TP6_SHIFT (4U)
2130#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
2131#define AIPS_PACRF_WP6_MASK (0x20U)
2132#define AIPS_PACRF_WP6_SHIFT (5U)
2137#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
2138#define AIPS_PACRF_SP6_MASK (0x40U)
2139#define AIPS_PACRF_SP6_SHIFT (6U)
2144#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
2145#define AIPS_PACRF_TP5_MASK (0x100U)
2146#define AIPS_PACRF_TP5_SHIFT (8U)
2151#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
2152#define AIPS_PACRF_WP5_MASK (0x200U)
2153#define AIPS_PACRF_WP5_SHIFT (9U)
2158#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
2159#define AIPS_PACRF_SP5_MASK (0x400U)
2160#define AIPS_PACRF_SP5_SHIFT (10U)
2165#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
2166#define AIPS_PACRF_TP4_MASK (0x1000U)
2167#define AIPS_PACRF_TP4_SHIFT (12U)
2172#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
2173#define AIPS_PACRF_WP4_MASK (0x2000U)
2174#define AIPS_PACRF_WP4_SHIFT (13U)
2179#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
2180#define AIPS_PACRF_SP4_MASK (0x4000U)
2181#define AIPS_PACRF_SP4_SHIFT (14U)
2186#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
2187#define AIPS_PACRF_TP3_MASK (0x10000U)
2188#define AIPS_PACRF_TP3_SHIFT (16U)
2193#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
2194#define AIPS_PACRF_WP3_MASK (0x20000U)
2195#define AIPS_PACRF_WP3_SHIFT (17U)
2200#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
2201#define AIPS_PACRF_SP3_MASK (0x40000U)
2202#define AIPS_PACRF_SP3_SHIFT (18U)
2207#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2208#define AIPS_PACRF_TP2_MASK (0x100000U)
2209#define AIPS_PACRF_TP2_SHIFT (20U)
2214#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2215#define AIPS_PACRF_WP2_MASK (0x200000U)
2216#define AIPS_PACRF_WP2_SHIFT (21U)
2221#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2222#define AIPS_PACRF_SP2_MASK (0x400000U)
2223#define AIPS_PACRF_SP2_SHIFT (22U)
2228#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2229#define AIPS_PACRF_TP1_MASK (0x1000000U)
2230#define AIPS_PACRF_TP1_SHIFT (24U)
2235#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2236#define AIPS_PACRF_WP1_MASK (0x2000000U)
2237#define AIPS_PACRF_WP1_SHIFT (25U)
2242#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2243#define AIPS_PACRF_SP1_MASK (0x4000000U)
2244#define AIPS_PACRF_SP1_SHIFT (26U)
2249#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2250#define AIPS_PACRF_TP0_MASK (0x10000000U)
2251#define AIPS_PACRF_TP0_SHIFT (28U)
2256#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2257#define AIPS_PACRF_WP0_MASK (0x20000000U)
2258#define AIPS_PACRF_WP0_SHIFT (29U)
2263#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2264#define AIPS_PACRF_SP0_MASK (0x40000000U)
2265#define AIPS_PACRF_SP0_SHIFT (30U)
2270#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2275#define AIPS_PACRG_TP7_MASK (0x1U)
2276#define AIPS_PACRG_TP7_SHIFT (0U)
2281#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2282#define AIPS_PACRG_WP7_MASK (0x2U)
2283#define AIPS_PACRG_WP7_SHIFT (1U)
2288#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2289#define AIPS_PACRG_SP7_MASK (0x4U)
2290#define AIPS_PACRG_SP7_SHIFT (2U)
2295#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2296#define AIPS_PACRG_TP6_MASK (0x10U)
2297#define AIPS_PACRG_TP6_SHIFT (4U)
2302#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2303#define AIPS_PACRG_WP6_MASK (0x20U)
2304#define AIPS_PACRG_WP6_SHIFT (5U)
2309#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2310#define AIPS_PACRG_SP6_MASK (0x40U)
2311#define AIPS_PACRG_SP6_SHIFT (6U)
2316#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2317#define AIPS_PACRG_TP5_MASK (0x100U)
2318#define AIPS_PACRG_TP5_SHIFT (8U)
2323#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2324#define AIPS_PACRG_WP5_MASK (0x200U)
2325#define AIPS_PACRG_WP5_SHIFT (9U)
2330#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2331#define AIPS_PACRG_SP5_MASK (0x400U)
2332#define AIPS_PACRG_SP5_SHIFT (10U)
2337#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2338#define AIPS_PACRG_TP4_MASK (0x1000U)
2339#define AIPS_PACRG_TP4_SHIFT (12U)
2344#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2345#define AIPS_PACRG_WP4_MASK (0x2000U)
2346#define AIPS_PACRG_WP4_SHIFT (13U)
2351#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2352#define AIPS_PACRG_SP4_MASK (0x4000U)
2353#define AIPS_PACRG_SP4_SHIFT (14U)
2358#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2359#define AIPS_PACRG_TP3_MASK (0x10000U)
2360#define AIPS_PACRG_TP3_SHIFT (16U)
2365#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2366#define AIPS_PACRG_WP3_MASK (0x20000U)
2367#define AIPS_PACRG_WP3_SHIFT (17U)
2372#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2373#define AIPS_PACRG_SP3_MASK (0x40000U)
2374#define AIPS_PACRG_SP3_SHIFT (18U)
2379#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2380#define AIPS_PACRG_TP2_MASK (0x100000U)
2381#define AIPS_PACRG_TP2_SHIFT (20U)
2386#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2387#define AIPS_PACRG_WP2_MASK (0x200000U)
2388#define AIPS_PACRG_WP2_SHIFT (21U)
2393#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2394#define AIPS_PACRG_SP2_MASK (0x400000U)
2395#define AIPS_PACRG_SP2_SHIFT (22U)
2400#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2401#define AIPS_PACRG_TP1_MASK (0x1000000U)
2402#define AIPS_PACRG_TP1_SHIFT (24U)
2407#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2408#define AIPS_PACRG_WP1_MASK (0x2000000U)
2409#define AIPS_PACRG_WP1_SHIFT (25U)
2414#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2415#define AIPS_PACRG_SP1_MASK (0x4000000U)
2416#define AIPS_PACRG_SP1_SHIFT (26U)
2421#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2422#define AIPS_PACRG_TP0_MASK (0x10000000U)
2423#define AIPS_PACRG_TP0_SHIFT (28U)
2428#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2429#define AIPS_PACRG_WP0_MASK (0x20000000U)
2430#define AIPS_PACRG_WP0_SHIFT (29U)
2435#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2436#define AIPS_PACRG_SP0_MASK (0x40000000U)
2437#define AIPS_PACRG_SP0_SHIFT (30U)
2442#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2447#define AIPS_PACRH_TP7_MASK (0x1U)
2448#define AIPS_PACRH_TP7_SHIFT (0U)
2453#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2454#define AIPS_PACRH_WP7_MASK (0x2U)
2455#define AIPS_PACRH_WP7_SHIFT (1U)
2460#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2461#define AIPS_PACRH_SP7_MASK (0x4U)
2462#define AIPS_PACRH_SP7_SHIFT (2U)
2467#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2468#define AIPS_PACRH_TP6_MASK (0x10U)
2469#define AIPS_PACRH_TP6_SHIFT (4U)
2474#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2475#define AIPS_PACRH_WP6_MASK (0x20U)
2476#define AIPS_PACRH_WP6_SHIFT (5U)
2481#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2482#define AIPS_PACRH_SP6_MASK (0x40U)
2483#define AIPS_PACRH_SP6_SHIFT (6U)
2488#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2489#define AIPS_PACRH_TP5_MASK (0x100U)
2490#define AIPS_PACRH_TP5_SHIFT (8U)
2495#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2496#define AIPS_PACRH_WP5_MASK (0x200U)
2497#define AIPS_PACRH_WP5_SHIFT (9U)
2502#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2503#define AIPS_PACRH_SP5_MASK (0x400U)
2504#define AIPS_PACRH_SP5_SHIFT (10U)
2509#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2510#define AIPS_PACRH_TP4_MASK (0x1000U)
2511#define AIPS_PACRH_TP4_SHIFT (12U)
2516#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2517#define AIPS_PACRH_WP4_MASK (0x2000U)
2518#define AIPS_PACRH_WP4_SHIFT (13U)
2523#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2524#define AIPS_PACRH_SP4_MASK (0x4000U)
2525#define AIPS_PACRH_SP4_SHIFT (14U)
2530#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2531#define AIPS_PACRH_TP3_MASK (0x10000U)
2532#define AIPS_PACRH_TP3_SHIFT (16U)
2537#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2538#define AIPS_PACRH_WP3_MASK (0x20000U)
2539#define AIPS_PACRH_WP3_SHIFT (17U)
2544#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2545#define AIPS_PACRH_SP3_MASK (0x40000U)
2546#define AIPS_PACRH_SP3_SHIFT (18U)
2551#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2552#define AIPS_PACRH_TP2_MASK (0x100000U)
2553#define AIPS_PACRH_TP2_SHIFT (20U)
2558#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2559#define AIPS_PACRH_WP2_MASK (0x200000U)
2560#define AIPS_PACRH_WP2_SHIFT (21U)
2565#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2566#define AIPS_PACRH_SP2_MASK (0x400000U)
2567#define AIPS_PACRH_SP2_SHIFT (22U)
2572#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2573#define AIPS_PACRH_TP1_MASK (0x1000000U)
2574#define AIPS_PACRH_TP1_SHIFT (24U)
2579#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2580#define AIPS_PACRH_WP1_MASK (0x2000000U)
2581#define AIPS_PACRH_WP1_SHIFT (25U)
2586#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2587#define AIPS_PACRH_SP1_MASK (0x4000000U)
2588#define AIPS_PACRH_SP1_SHIFT (26U)
2593#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2594#define AIPS_PACRH_TP0_MASK (0x10000000U)
2595#define AIPS_PACRH_TP0_SHIFT (28U)
2600#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2601#define AIPS_PACRH_WP0_MASK (0x20000000U)
2602#define AIPS_PACRH_WP0_SHIFT (29U)
2607#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2608#define AIPS_PACRH_SP0_MASK (0x40000000U)
2609#define AIPS_PACRH_SP0_SHIFT (30U)
2614#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2619#define AIPS_PACRI_TP7_MASK (0x1U)
2620#define AIPS_PACRI_TP7_SHIFT (0U)
2625#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2626#define AIPS_PACRI_WP7_MASK (0x2U)
2627#define AIPS_PACRI_WP7_SHIFT (1U)
2632#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2633#define AIPS_PACRI_SP7_MASK (0x4U)
2634#define AIPS_PACRI_SP7_SHIFT (2U)
2639#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2640#define AIPS_PACRI_TP6_MASK (0x10U)
2641#define AIPS_PACRI_TP6_SHIFT (4U)
2646#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2647#define AIPS_PACRI_WP6_MASK (0x20U)
2648#define AIPS_PACRI_WP6_SHIFT (5U)
2653#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2654#define AIPS_PACRI_SP6_MASK (0x40U)
2655#define AIPS_PACRI_SP6_SHIFT (6U)
2660#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2661#define AIPS_PACRI_TP5_MASK (0x100U)
2662#define AIPS_PACRI_TP5_SHIFT (8U)
2667#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2668#define AIPS_PACRI_WP5_MASK (0x200U)
2669#define AIPS_PACRI_WP5_SHIFT (9U)
2674#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2675#define AIPS_PACRI_SP5_MASK (0x400U)
2676#define AIPS_PACRI_SP5_SHIFT (10U)
2681#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2682#define AIPS_PACRI_TP4_MASK (0x1000U)
2683#define AIPS_PACRI_TP4_SHIFT (12U)
2688#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2689#define AIPS_PACRI_WP4_MASK (0x2000U)
2690#define AIPS_PACRI_WP4_SHIFT (13U)
2695#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2696#define AIPS_PACRI_SP4_MASK (0x4000U)
2697#define AIPS_PACRI_SP4_SHIFT (14U)
2702#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2703#define AIPS_PACRI_TP3_MASK (0x10000U)
2704#define AIPS_PACRI_TP3_SHIFT (16U)
2709#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2710#define AIPS_PACRI_WP3_MASK (0x20000U)
2711#define AIPS_PACRI_WP3_SHIFT (17U)
2716#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2717#define AIPS_PACRI_SP3_MASK (0x40000U)
2718#define AIPS_PACRI_SP3_SHIFT (18U)
2723#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2724#define AIPS_PACRI_TP2_MASK (0x100000U)
2725#define AIPS_PACRI_TP2_SHIFT (20U)
2730#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2731#define AIPS_PACRI_WP2_MASK (0x200000U)
2732#define AIPS_PACRI_WP2_SHIFT (21U)
2737#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2738#define AIPS_PACRI_SP2_MASK (0x400000U)
2739#define AIPS_PACRI_SP2_SHIFT (22U)
2744#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2745#define AIPS_PACRI_TP1_MASK (0x1000000U)
2746#define AIPS_PACRI_TP1_SHIFT (24U)
2751#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2752#define AIPS_PACRI_WP1_MASK (0x2000000U)
2753#define AIPS_PACRI_WP1_SHIFT (25U)
2758#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2759#define AIPS_PACRI_SP1_MASK (0x4000000U)
2760#define AIPS_PACRI_SP1_SHIFT (26U)
2765#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2766#define AIPS_PACRI_TP0_MASK (0x10000000U)
2767#define AIPS_PACRI_TP0_SHIFT (28U)
2772#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2773#define AIPS_PACRI_WP0_MASK (0x20000000U)
2774#define AIPS_PACRI_WP0_SHIFT (29U)
2779#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2780#define AIPS_PACRI_SP0_MASK (0x40000000U)
2781#define AIPS_PACRI_SP0_SHIFT (30U)
2786#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2791#define AIPS_PACRJ_TP7_MASK (0x1U)
2792#define AIPS_PACRJ_TP7_SHIFT (0U)
2797#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2798#define AIPS_PACRJ_WP7_MASK (0x2U)
2799#define AIPS_PACRJ_WP7_SHIFT (1U)
2804#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2805#define AIPS_PACRJ_SP7_MASK (0x4U)
2806#define AIPS_PACRJ_SP7_SHIFT (2U)
2811#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2812#define AIPS_PACRJ_TP6_MASK (0x10U)
2813#define AIPS_PACRJ_TP6_SHIFT (4U)
2818#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2819#define AIPS_PACRJ_WP6_MASK (0x20U)
2820#define AIPS_PACRJ_WP6_SHIFT (5U)
2825#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2826#define AIPS_PACRJ_SP6_MASK (0x40U)
2827#define AIPS_PACRJ_SP6_SHIFT (6U)
2832#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2833#define AIPS_PACRJ_TP5_MASK (0x100U)
2834#define AIPS_PACRJ_TP5_SHIFT (8U)
2839#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2840#define AIPS_PACRJ_WP5_MASK (0x200U)
2841#define AIPS_PACRJ_WP5_SHIFT (9U)
2846#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2847#define AIPS_PACRJ_SP5_MASK (0x400U)
2848#define AIPS_PACRJ_SP5_SHIFT (10U)
2853#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2854#define AIPS_PACRJ_TP4_MASK (0x1000U)
2855#define AIPS_PACRJ_TP4_SHIFT (12U)
2860#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2861#define AIPS_PACRJ_WP4_MASK (0x2000U)
2862#define AIPS_PACRJ_WP4_SHIFT (13U)
2867#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2868#define AIPS_PACRJ_SP4_MASK (0x4000U)
2869#define AIPS_PACRJ_SP4_SHIFT (14U)
2874#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2875#define AIPS_PACRJ_TP3_MASK (0x10000U)
2876#define AIPS_PACRJ_TP3_SHIFT (16U)
2881#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2882#define AIPS_PACRJ_WP3_MASK (0x20000U)
2883#define AIPS_PACRJ_WP3_SHIFT (17U)
2888#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2889#define AIPS_PACRJ_SP3_MASK (0x40000U)
2890#define AIPS_PACRJ_SP3_SHIFT (18U)
2895#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2896#define AIPS_PACRJ_TP2_MASK (0x100000U)
2897#define AIPS_PACRJ_TP2_SHIFT (20U)
2902#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2903#define AIPS_PACRJ_WP2_MASK (0x200000U)
2904#define AIPS_PACRJ_WP2_SHIFT (21U)
2909#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2910#define AIPS_PACRJ_SP2_MASK (0x400000U)
2911#define AIPS_PACRJ_SP2_SHIFT (22U)
2916#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2917#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2918#define AIPS_PACRJ_TP1_SHIFT (24U)
2923#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2924#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2925#define AIPS_PACRJ_WP1_SHIFT (25U)
2930#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2931#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2932#define AIPS_PACRJ_SP1_SHIFT (26U)
2937#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2938#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2939#define AIPS_PACRJ_TP0_SHIFT (28U)
2944#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2945#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2946#define AIPS_PACRJ_WP0_SHIFT (29U)
2951#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2952#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2953#define AIPS_PACRJ_SP0_SHIFT (30U)
2958#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2963#define AIPS_PACRK_TP7_MASK (0x1U)
2964#define AIPS_PACRK_TP7_SHIFT (0U)
2969#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2970#define AIPS_PACRK_WP7_MASK (0x2U)
2971#define AIPS_PACRK_WP7_SHIFT (1U)
2976#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2977#define AIPS_PACRK_SP7_MASK (0x4U)
2978#define AIPS_PACRK_SP7_SHIFT (2U)
2983#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2984#define AIPS_PACRK_TP6_MASK (0x10U)
2985#define AIPS_PACRK_TP6_SHIFT (4U)
2990#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2991#define AIPS_PACRK_WP6_MASK (0x20U)
2992#define AIPS_PACRK_WP6_SHIFT (5U)
2997#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2998#define AIPS_PACRK_SP6_MASK (0x40U)
2999#define AIPS_PACRK_SP6_SHIFT (6U)
3004#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
3005#define AIPS_PACRK_TP5_MASK (0x100U)
3006#define AIPS_PACRK_TP5_SHIFT (8U)
3011#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
3012#define AIPS_PACRK_WP5_MASK (0x200U)
3013#define AIPS_PACRK_WP5_SHIFT (9U)
3018#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
3019#define AIPS_PACRK_SP5_MASK (0x400U)
3020#define AIPS_PACRK_SP5_SHIFT (10U)
3025#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
3026#define AIPS_PACRK_TP4_MASK (0x1000U)
3027#define AIPS_PACRK_TP4_SHIFT (12U)
3032#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
3033#define AIPS_PACRK_WP4_MASK (0x2000U)
3034#define AIPS_PACRK_WP4_SHIFT (13U)
3039#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
3040#define AIPS_PACRK_SP4_MASK (0x4000U)
3041#define AIPS_PACRK_SP4_SHIFT (14U)
3046#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
3047#define AIPS_PACRK_TP3_MASK (0x10000U)
3048#define AIPS_PACRK_TP3_SHIFT (16U)
3053#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
3054#define AIPS_PACRK_WP3_MASK (0x20000U)
3055#define AIPS_PACRK_WP3_SHIFT (17U)
3060#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
3061#define AIPS_PACRK_SP3_MASK (0x40000U)
3062#define AIPS_PACRK_SP3_SHIFT (18U)
3067#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
3068#define AIPS_PACRK_TP2_MASK (0x100000U)
3069#define AIPS_PACRK_TP2_SHIFT (20U)
3074#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
3075#define AIPS_PACRK_WP2_MASK (0x200000U)
3076#define AIPS_PACRK_WP2_SHIFT (21U)
3081#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
3082#define AIPS_PACRK_SP2_MASK (0x400000U)
3083#define AIPS_PACRK_SP2_SHIFT (22U)
3088#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
3089#define AIPS_PACRK_TP1_MASK (0x1000000U)
3090#define AIPS_PACRK_TP1_SHIFT (24U)
3095#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
3096#define AIPS_PACRK_WP1_MASK (0x2000000U)
3097#define AIPS_PACRK_WP1_SHIFT (25U)
3102#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
3103#define AIPS_PACRK_SP1_MASK (0x4000000U)
3104#define AIPS_PACRK_SP1_SHIFT (26U)
3109#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
3110#define AIPS_PACRK_TP0_MASK (0x10000000U)
3111#define AIPS_PACRK_TP0_SHIFT (28U)
3116#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
3117#define AIPS_PACRK_WP0_MASK (0x20000000U)
3118#define AIPS_PACRK_WP0_SHIFT (29U)
3123#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
3124#define AIPS_PACRK_SP0_MASK (0x40000000U)
3125#define AIPS_PACRK_SP0_SHIFT (30U)
3130#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
3135#define AIPS_PACRL_TP7_MASK (0x1U)
3136#define AIPS_PACRL_TP7_SHIFT (0U)
3141#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
3142#define AIPS_PACRL_WP7_MASK (0x2U)
3143#define AIPS_PACRL_WP7_SHIFT (1U)
3148#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
3149#define AIPS_PACRL_SP7_MASK (0x4U)
3150#define AIPS_PACRL_SP7_SHIFT (2U)
3155#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
3156#define AIPS_PACRL_TP6_MASK (0x10U)
3157#define AIPS_PACRL_TP6_SHIFT (4U)
3162#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
3163#define AIPS_PACRL_WP6_MASK (0x20U)
3164#define AIPS_PACRL_WP6_SHIFT (5U)
3169#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
3170#define AIPS_PACRL_SP6_MASK (0x40U)
3171#define AIPS_PACRL_SP6_SHIFT (6U)
3176#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
3177#define AIPS_PACRL_TP5_MASK (0x100U)
3178#define AIPS_PACRL_TP5_SHIFT (8U)
3183#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
3184#define AIPS_PACRL_WP5_MASK (0x200U)
3185#define AIPS_PACRL_WP5_SHIFT (9U)
3190#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
3191#define AIPS_PACRL_SP5_MASK (0x400U)
3192#define AIPS_PACRL_SP5_SHIFT (10U)
3197#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
3198#define AIPS_PACRL_TP4_MASK (0x1000U)
3199#define AIPS_PACRL_TP4_SHIFT (12U)
3204#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3205#define AIPS_PACRL_WP4_MASK (0x2000U)
3206#define AIPS_PACRL_WP4_SHIFT (13U)
3211#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3212#define AIPS_PACRL_SP4_MASK (0x4000U)
3213#define AIPS_PACRL_SP4_SHIFT (14U)
3218#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3219#define AIPS_PACRL_TP3_MASK (0x10000U)
3220#define AIPS_PACRL_TP3_SHIFT (16U)
3225#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3226#define AIPS_PACRL_WP3_MASK (0x20000U)
3227#define AIPS_PACRL_WP3_SHIFT (17U)
3232#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3233#define AIPS_PACRL_SP3_MASK (0x40000U)
3234#define AIPS_PACRL_SP3_SHIFT (18U)
3239#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3240#define AIPS_PACRL_TP2_MASK (0x100000U)
3241#define AIPS_PACRL_TP2_SHIFT (20U)
3246#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3247#define AIPS_PACRL_WP2_MASK (0x200000U)
3248#define AIPS_PACRL_WP2_SHIFT (21U)
3253#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3254#define AIPS_PACRL_SP2_MASK (0x400000U)
3255#define AIPS_PACRL_SP2_SHIFT (22U)
3260#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3261#define AIPS_PACRL_TP1_MASK (0x1000000U)
3262#define AIPS_PACRL_TP1_SHIFT (24U)
3267#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3268#define AIPS_PACRL_WP1_MASK (0x2000000U)
3269#define AIPS_PACRL_WP1_SHIFT (25U)
3274#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3275#define AIPS_PACRL_SP1_MASK (0x4000000U)
3276#define AIPS_PACRL_SP1_SHIFT (26U)
3281#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3282#define AIPS_PACRL_TP0_MASK (0x10000000U)
3283#define AIPS_PACRL_TP0_SHIFT (28U)
3288#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3289#define AIPS_PACRL_WP0_MASK (0x20000000U)
3290#define AIPS_PACRL_WP0_SHIFT (29U)
3295#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3296#define AIPS_PACRL_SP0_MASK (0x40000000U)
3297#define AIPS_PACRL_SP0_SHIFT (30U)
3302#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3307#define AIPS_PACRM_TP7_MASK (0x1U)
3308#define AIPS_PACRM_TP7_SHIFT (0U)
3313#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3314#define AIPS_PACRM_WP7_MASK (0x2U)
3315#define AIPS_PACRM_WP7_SHIFT (1U)
3320#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3321#define AIPS_PACRM_SP7_MASK (0x4U)
3322#define AIPS_PACRM_SP7_SHIFT (2U)
3327#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3328#define AIPS_PACRM_TP6_MASK (0x10U)
3329#define AIPS_PACRM_TP6_SHIFT (4U)
3334#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3335#define AIPS_PACRM_WP6_MASK (0x20U)
3336#define AIPS_PACRM_WP6_SHIFT (5U)
3341#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3342#define AIPS_PACRM_SP6_MASK (0x40U)
3343#define AIPS_PACRM_SP6_SHIFT (6U)
3348#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3349#define AIPS_PACRM_TP5_MASK (0x100U)
3350#define AIPS_PACRM_TP5_SHIFT (8U)
3355#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3356#define AIPS_PACRM_WP5_MASK (0x200U)
3357#define AIPS_PACRM_WP5_SHIFT (9U)
3362#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3363#define AIPS_PACRM_SP5_MASK (0x400U)
3364#define AIPS_PACRM_SP5_SHIFT (10U)
3369#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3370#define AIPS_PACRM_TP4_MASK (0x1000U)
3371#define AIPS_PACRM_TP4_SHIFT (12U)
3376#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3377#define AIPS_PACRM_WP4_MASK (0x2000U)
3378#define AIPS_PACRM_WP4_SHIFT (13U)
3383#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3384#define AIPS_PACRM_SP4_MASK (0x4000U)
3385#define AIPS_PACRM_SP4_SHIFT (14U)
3390#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3391#define AIPS_PACRM_TP3_MASK (0x10000U)
3392#define AIPS_PACRM_TP3_SHIFT (16U)
3397#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3398#define AIPS_PACRM_WP3_MASK (0x20000U)
3399#define AIPS_PACRM_WP3_SHIFT (17U)
3404#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3405#define AIPS_PACRM_SP3_MASK (0x40000U)
3406#define AIPS_PACRM_SP3_SHIFT (18U)
3411#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3412#define AIPS_PACRM_TP2_MASK (0x100000U)
3413#define AIPS_PACRM_TP2_SHIFT (20U)
3418#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3419#define AIPS_PACRM_WP2_MASK (0x200000U)
3420#define AIPS_PACRM_WP2_SHIFT (21U)
3425#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3426#define AIPS_PACRM_SP2_MASK (0x400000U)
3427#define AIPS_PACRM_SP2_SHIFT (22U)
3432#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3433#define AIPS_PACRM_TP1_MASK (0x1000000U)
3434#define AIPS_PACRM_TP1_SHIFT (24U)
3439#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3440#define AIPS_PACRM_WP1_MASK (0x2000000U)
3441#define AIPS_PACRM_WP1_SHIFT (25U)
3446#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3447#define AIPS_PACRM_SP1_MASK (0x4000000U)
3448#define AIPS_PACRM_SP1_SHIFT (26U)
3453#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3454#define AIPS_PACRM_TP0_MASK (0x10000000U)
3455#define AIPS_PACRM_TP0_SHIFT (28U)
3460#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3461#define AIPS_PACRM_WP0_MASK (0x20000000U)
3462#define AIPS_PACRM_WP0_SHIFT (29U)
3467#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3468#define AIPS_PACRM_SP0_MASK (0x40000000U)
3469#define AIPS_PACRM_SP0_SHIFT (30U)
3474#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3479#define AIPS_PACRN_TP7_MASK (0x1U)
3480#define AIPS_PACRN_TP7_SHIFT (0U)
3485#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3486#define AIPS_PACRN_WP7_MASK (0x2U)
3487#define AIPS_PACRN_WP7_SHIFT (1U)
3492#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3493#define AIPS_PACRN_SP7_MASK (0x4U)
3494#define AIPS_PACRN_SP7_SHIFT (2U)
3499#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3500#define AIPS_PACRN_TP6_MASK (0x10U)
3501#define AIPS_PACRN_TP6_SHIFT (4U)
3506#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3507#define AIPS_PACRN_WP6_MASK (0x20U)
3508#define AIPS_PACRN_WP6_SHIFT (5U)
3513#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3514#define AIPS_PACRN_SP6_MASK (0x40U)
3515#define AIPS_PACRN_SP6_SHIFT (6U)
3520#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3521#define AIPS_PACRN_TP5_MASK (0x100U)
3522#define AIPS_PACRN_TP5_SHIFT (8U)
3527#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3528#define AIPS_PACRN_WP5_MASK (0x200U)
3529#define AIPS_PACRN_WP5_SHIFT (9U)
3534#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3535#define AIPS_PACRN_SP5_MASK (0x400U)
3536#define AIPS_PACRN_SP5_SHIFT (10U)
3541#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3542#define AIPS_PACRN_TP4_MASK (0x1000U)
3543#define AIPS_PACRN_TP4_SHIFT (12U)
3548#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3549#define AIPS_PACRN_WP4_MASK (0x2000U)
3550#define AIPS_PACRN_WP4_SHIFT (13U)
3555#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3556#define AIPS_PACRN_SP4_MASK (0x4000U)
3557#define AIPS_PACRN_SP4_SHIFT (14U)
3562#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3563#define AIPS_PACRN_TP3_MASK (0x10000U)
3564#define AIPS_PACRN_TP3_SHIFT (16U)
3569#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3570#define AIPS_PACRN_WP3_MASK (0x20000U)
3571#define AIPS_PACRN_WP3_SHIFT (17U)
3576#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3577#define AIPS_PACRN_SP3_MASK (0x40000U)
3578#define AIPS_PACRN_SP3_SHIFT (18U)
3583#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3584#define AIPS_PACRN_TP2_MASK (0x100000U)
3585#define AIPS_PACRN_TP2_SHIFT (20U)
3590#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3591#define AIPS_PACRN_WP2_MASK (0x200000U)
3592#define AIPS_PACRN_WP2_SHIFT (21U)
3597#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3598#define AIPS_PACRN_SP2_MASK (0x400000U)
3599#define AIPS_PACRN_SP2_SHIFT (22U)
3604#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3605#define AIPS_PACRN_TP1_MASK (0x1000000U)
3606#define AIPS_PACRN_TP1_SHIFT (24U)
3611#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3612#define AIPS_PACRN_WP1_MASK (0x2000000U)
3613#define AIPS_PACRN_WP1_SHIFT (25U)
3618#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3619#define AIPS_PACRN_SP1_MASK (0x4000000U)
3620#define AIPS_PACRN_SP1_SHIFT (26U)
3625#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3626#define AIPS_PACRN_TP0_MASK (0x10000000U)
3627#define AIPS_PACRN_TP0_SHIFT (28U)
3632#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3633#define AIPS_PACRN_WP0_MASK (0x20000000U)
3634#define AIPS_PACRN_WP0_SHIFT (29U)
3639#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3640#define AIPS_PACRN_SP0_MASK (0x40000000U)
3641#define AIPS_PACRN_SP0_SHIFT (30U)
3646#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3651#define AIPS_PACRO_TP7_MASK (0x1U)
3652#define AIPS_PACRO_TP7_SHIFT (0U)
3657#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3658#define AIPS_PACRO_WP7_MASK (0x2U)
3659#define AIPS_PACRO_WP7_SHIFT (1U)
3664#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3665#define AIPS_PACRO_SP7_MASK (0x4U)
3666#define AIPS_PACRO_SP7_SHIFT (2U)
3671#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3672#define AIPS_PACRO_TP6_MASK (0x10U)
3673#define AIPS_PACRO_TP6_SHIFT (4U)
3678#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3679#define AIPS_PACRO_WP6_MASK (0x20U)
3680#define AIPS_PACRO_WP6_SHIFT (5U)
3685#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3686#define AIPS_PACRO_SP6_MASK (0x40U)
3687#define AIPS_PACRO_SP6_SHIFT (6U)
3692#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3693#define AIPS_PACRO_TP5_MASK (0x100U)
3694#define AIPS_PACRO_TP5_SHIFT (8U)
3699#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3700#define AIPS_PACRO_WP5_MASK (0x200U)
3701#define AIPS_PACRO_WP5_SHIFT (9U)
3706#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3707#define AIPS_PACRO_SP5_MASK (0x400U)
3708#define AIPS_PACRO_SP5_SHIFT (10U)
3713#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3714#define AIPS_PACRO_TP4_MASK (0x1000U)
3715#define AIPS_PACRO_TP4_SHIFT (12U)
3720#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3721#define AIPS_PACRO_WP4_MASK (0x2000U)
3722#define AIPS_PACRO_WP4_SHIFT (13U)
3727#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3728#define AIPS_PACRO_SP4_MASK (0x4000U)
3729#define AIPS_PACRO_SP4_SHIFT (14U)
3734#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3735#define AIPS_PACRO_TP3_MASK (0x10000U)
3736#define AIPS_PACRO_TP3_SHIFT (16U)
3741#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3742#define AIPS_PACRO_WP3_MASK (0x20000U)
3743#define AIPS_PACRO_WP3_SHIFT (17U)
3748#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3749#define AIPS_PACRO_SP3_MASK (0x40000U)
3750#define AIPS_PACRO_SP3_SHIFT (18U)
3755#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3756#define AIPS_PACRO_TP2_MASK (0x100000U)
3757#define AIPS_PACRO_TP2_SHIFT (20U)
3762#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3763#define AIPS_PACRO_WP2_MASK (0x200000U)
3764#define AIPS_PACRO_WP2_SHIFT (21U)
3769#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3770#define AIPS_PACRO_SP2_MASK (0x400000U)
3771#define AIPS_PACRO_SP2_SHIFT (22U)
3776#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3777#define AIPS_PACRO_TP1_MASK (0x1000000U)
3778#define AIPS_PACRO_TP1_SHIFT (24U)
3783#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3784#define AIPS_PACRO_WP1_MASK (0x2000000U)
3785#define AIPS_PACRO_WP1_SHIFT (25U)
3790#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3791#define AIPS_PACRO_SP1_MASK (0x4000000U)
3792#define AIPS_PACRO_SP1_SHIFT (26U)
3797#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3798#define AIPS_PACRO_TP0_MASK (0x10000000U)
3799#define AIPS_PACRO_TP0_SHIFT (28U)
3804#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3805#define AIPS_PACRO_WP0_MASK (0x20000000U)
3806#define AIPS_PACRO_WP0_SHIFT (29U)
3811#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3812#define AIPS_PACRO_SP0_MASK (0x40000000U)
3813#define AIPS_PACRO_SP0_SHIFT (30U)
3818#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3823#define AIPS_PACRP_TP7_MASK (0x1U)
3824#define AIPS_PACRP_TP7_SHIFT (0U)
3829#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3830#define AIPS_PACRP_WP7_MASK (0x2U)
3831#define AIPS_PACRP_WP7_SHIFT (1U)
3836#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3837#define AIPS_PACRP_SP7_MASK (0x4U)
3838#define AIPS_PACRP_SP7_SHIFT (2U)
3843#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3844#define AIPS_PACRP_TP6_MASK (0x10U)
3845#define AIPS_PACRP_TP6_SHIFT (4U)
3850#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3851#define AIPS_PACRP_WP6_MASK (0x20U)
3852#define AIPS_PACRP_WP6_SHIFT (5U)
3857#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3858#define AIPS_PACRP_SP6_MASK (0x40U)
3859#define AIPS_PACRP_SP6_SHIFT (6U)
3864#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3865#define AIPS_PACRP_TP5_MASK (0x100U)
3866#define AIPS_PACRP_TP5_SHIFT (8U)
3871#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3872#define AIPS_PACRP_WP5_MASK (0x200U)
3873#define AIPS_PACRP_WP5_SHIFT (9U)
3878#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3879#define AIPS_PACRP_SP5_MASK (0x400U)
3880#define AIPS_PACRP_SP5_SHIFT (10U)
3885#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3886#define AIPS_PACRP_TP4_MASK (0x1000U)
3887#define AIPS_PACRP_TP4_SHIFT (12U)
3892#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3893#define AIPS_PACRP_WP4_MASK (0x2000U)
3894#define AIPS_PACRP_WP4_SHIFT (13U)
3899#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3900#define AIPS_PACRP_SP4_MASK (0x4000U)
3901#define AIPS_PACRP_SP4_SHIFT (14U)
3906#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3907#define AIPS_PACRP_TP3_MASK (0x10000U)
3908#define AIPS_PACRP_TP3_SHIFT (16U)
3913#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3914#define AIPS_PACRP_WP3_MASK (0x20000U)
3915#define AIPS_PACRP_WP3_SHIFT (17U)
3920#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3921#define AIPS_PACRP_SP3_MASK (0x40000U)
3922#define AIPS_PACRP_SP3_SHIFT (18U)
3927#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3928#define AIPS_PACRP_TP2_MASK (0x100000U)
3929#define AIPS_PACRP_TP2_SHIFT (20U)
3934#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3935#define AIPS_PACRP_WP2_MASK (0x200000U)
3936#define AIPS_PACRP_WP2_SHIFT (21U)
3941#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3942#define AIPS_PACRP_SP2_MASK (0x400000U)
3943#define AIPS_PACRP_SP2_SHIFT (22U)
3948#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3949#define AIPS_PACRP_TP1_MASK (0x1000000U)
3950#define AIPS_PACRP_TP1_SHIFT (24U)
3955#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3956#define AIPS_PACRP_WP1_MASK (0x2000000U)
3957#define AIPS_PACRP_WP1_SHIFT (25U)
3962#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3963#define AIPS_PACRP_SP1_MASK (0x4000000U)
3964#define AIPS_PACRP_SP1_SHIFT (26U)
3969#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3970#define AIPS_PACRP_TP0_MASK (0x10000000U)
3971#define AIPS_PACRP_TP0_SHIFT (28U)
3976#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3977#define AIPS_PACRP_WP0_MASK (0x20000000U)
3978#define AIPS_PACRP_WP0_SHIFT (29U)
3983#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3984#define AIPS_PACRP_SP0_MASK (0x40000000U)
3985#define AIPS_PACRP_SP0_SHIFT (30U)
3990#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3996 /* end of group AIPS_Register_Masks */
3997
3998
3999/* AIPS - Peripheral instance base addresses */
4001#define AIPS0_BASE (0x40000000u)
4003#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
4005#define AIPS1_BASE (0x40080000u)
4007#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
4009#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
4011#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
4012
4015 /* end of group AIPS_Peripheral_Access_Layer */
4016
4017
4018/* ----------------------------------------------------------------------------
4019 -- AOI Peripheral Access Layer
4020 ---------------------------------------------------------------------------- */
4021
4028typedef struct {
4029 struct { /* offset: 0x0, array step: 0x4 */
4030 __IO uint16_t BFCRT01;
4031 __IO uint16_t BFCRT23;
4032 } BFCRT[4];
4033} AOI_Type;
4034
4035/* ----------------------------------------------------------------------------
4036 -- AOI Register Masks
4037 ---------------------------------------------------------------------------- */
4038
4046#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
4047#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
4054#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
4055#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
4056#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
4063#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
4064#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
4065#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
4072#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
4073#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
4074#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
4081#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
4082#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
4083#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
4090#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
4091#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
4092#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
4099#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
4100#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
4101#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
4108#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
4109#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
4110#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
4117#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
4120/* The count of AOI_BFCRT01 */
4121#define AOI_BFCRT01_COUNT (4U)
4122
4125#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
4126#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
4133#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
4134#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
4135#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
4142#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
4143#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
4144#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
4151#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
4152#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
4153#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
4160#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
4161#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
4162#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
4169#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
4170#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
4171#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
4178#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
4179#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
4180#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
4187#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
4188#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
4189#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
4196#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
4199/* The count of AOI_BFCRT23 */
4200#define AOI_BFCRT23_COUNT (4U)
4201
4202
4205 /* end of group AOI_Register_Masks */
4206
4207
4208/* AOI - Peripheral instance base addresses */
4210#define AOI0_BASE (0x4005B000u)
4212#define AOI0 ((AOI_Type *)AOI0_BASE)
4214#define AOI_BASE_ADDRS { AOI0_BASE }
4216#define AOI_BASE_PTRS { AOI0 }
4217
4220 /* end of group AOI_Peripheral_Access_Layer */
4221
4222
4223/* ----------------------------------------------------------------------------
4224 -- AXBS Peripheral Access Layer
4225 ---------------------------------------------------------------------------- */
4226
4233typedef struct {
4234 struct { /* offset: 0x0, array step: 0x100 */
4235 __IO uint32_t PRS;
4236 uint8_t RESERVED_0[12];
4237 __IO uint32_t CRS;
4238 uint8_t RESERVED_1[236];
4239 } SLAVE[7];
4240 uint8_t RESERVED_0[256];
4241 __IO uint32_t MGPCR0;
4242 uint8_t RESERVED_1[252];
4243 __IO uint32_t MGPCR1;
4244 uint8_t RESERVED_2[252];
4245 __IO uint32_t MGPCR2;
4246 uint8_t RESERVED_3[252];
4247 __IO uint32_t MGPCR3;
4248} AXBS_Type;
4249
4250/* ----------------------------------------------------------------------------
4251 -- AXBS Register Masks
4252 ---------------------------------------------------------------------------- */
4253
4261#define AXBS_PRS_M0_MASK (0x7U)
4262#define AXBS_PRS_M0_SHIFT (0U)
4273#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
4274#define AXBS_PRS_M1_MASK (0x70U)
4275#define AXBS_PRS_M1_SHIFT (4U)
4286#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
4287#define AXBS_PRS_M2_MASK (0x700U)
4288#define AXBS_PRS_M2_SHIFT (8U)
4299#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
4300#define AXBS_PRS_M3_MASK (0x7000U)
4301#define AXBS_PRS_M3_SHIFT (12U)
4312#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
4315/* The count of AXBS_PRS */
4316#define AXBS_PRS_COUNT (7U)
4317
4320#define AXBS_CRS_PARK_MASK (0x7U)
4321#define AXBS_CRS_PARK_SHIFT (0U)
4332#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
4333#define AXBS_CRS_PCTL_MASK (0x30U)
4334#define AXBS_CRS_PCTL_SHIFT (4U)
4341#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
4342#define AXBS_CRS_ARB_MASK (0x300U)
4343#define AXBS_CRS_ARB_SHIFT (8U)
4350#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
4351#define AXBS_CRS_HLP_MASK (0x40000000U)
4352#define AXBS_CRS_HLP_SHIFT (30U)
4357#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
4358#define AXBS_CRS_RO_MASK (0x80000000U)
4359#define AXBS_CRS_RO_SHIFT (31U)
4364#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4367/* The count of AXBS_CRS */
4368#define AXBS_CRS_COUNT (7U)
4369
4372#define AXBS_MGPCR0_AULB_MASK (0x7U)
4373#define AXBS_MGPCR0_AULB_SHIFT (0U)
4384#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4389#define AXBS_MGPCR1_AULB_MASK (0x7U)
4390#define AXBS_MGPCR1_AULB_SHIFT (0U)
4401#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4406#define AXBS_MGPCR2_AULB_MASK (0x7U)
4407#define AXBS_MGPCR2_AULB_SHIFT (0U)
4418#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4423#define AXBS_MGPCR3_AULB_MASK (0x7U)
4424#define AXBS_MGPCR3_AULB_SHIFT (0U)
4435#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
4441 /* end of group AXBS_Register_Masks */
4442
4443
4444/* AXBS - Peripheral instance base addresses */
4446#define AXBS_BASE (0x40004000u)
4448#define AXBS ((AXBS_Type *)AXBS_BASE)
4450#define AXBS_BASE_ADDRS { AXBS_BASE }
4452#define AXBS_BASE_PTRS { AXBS }
4453
4456 /* end of group AXBS_Peripheral_Access_Layer */
4457
4458
4459/* ----------------------------------------------------------------------------
4460 -- CAN Peripheral Access Layer
4461 ---------------------------------------------------------------------------- */
4462
4469typedef struct {
4470 __IO uint32_t MCR;
4471 __IO uint32_t CTRL1;
4472 __IO uint32_t TIMER;
4473 uint8_t RESERVED_0[4];
4474 __IO uint32_t RXMGMASK;
4475 __IO uint32_t RX14MASK;
4476 __IO uint32_t RX15MASK;
4477 __IO uint32_t ECR;
4478 __IO uint32_t ESR1;
4479 uint8_t RESERVED_1[4];
4480 __IO uint32_t IMASK1;
4481 uint8_t RESERVED_2[4];
4482 __IO uint32_t IFLAG1;
4483 __IO uint32_t CTRL2;
4484 __I uint32_t ESR2;
4485 uint8_t RESERVED_3[8];
4486 __I uint32_t CRCR;
4487 __IO uint32_t RXFGMASK;
4488 __I uint32_t RXFIR;
4489 __IO uint32_t CBT;
4490 uint8_t RESERVED_4[44];
4491 struct { /* offset: 0x80, array step: 0x10 */
4492 __IO uint32_t CS;
4493 __IO uint32_t ID;
4494 __IO uint32_t WORD0;
4495 __IO uint32_t WORD1;
4496 } MB[16];
4497 uint8_t RESERVED_5[1792];
4498 __IO uint32_t RXIMR[16];
4499} CAN_Type;
4500
4501/* ----------------------------------------------------------------------------
4502 -- CAN Register Masks
4503 ---------------------------------------------------------------------------- */
4504
4512#define CAN_MCR_MAXMB_MASK (0x7FU)
4513#define CAN_MCR_MAXMB_SHIFT (0U)
4514#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4515#define CAN_MCR_IDAM_MASK (0x300U)
4516#define CAN_MCR_IDAM_SHIFT (8U)
4523#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4524#define CAN_MCR_AEN_MASK (0x1000U)
4525#define CAN_MCR_AEN_SHIFT (12U)
4530#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4531#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4532#define CAN_MCR_LPRIOEN_SHIFT (13U)
4537#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4538#define CAN_MCR_DMA_MASK (0x8000U)
4539#define CAN_MCR_DMA_SHIFT (15U)
4544#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
4545#define CAN_MCR_IRMQ_MASK (0x10000U)
4546#define CAN_MCR_IRMQ_SHIFT (16U)
4551#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4552#define CAN_MCR_SRXDIS_MASK (0x20000U)
4553#define CAN_MCR_SRXDIS_SHIFT (17U)
4558#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4559#define CAN_MCR_DOZE_MASK (0x40000U)
4560#define CAN_MCR_DOZE_SHIFT (18U)
4565#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
4566#define CAN_MCR_WAKSRC_MASK (0x80000U)
4567#define CAN_MCR_WAKSRC_SHIFT (19U)
4572#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4573#define CAN_MCR_LPMACK_MASK (0x100000U)
4574#define CAN_MCR_LPMACK_SHIFT (20U)
4579#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4580#define CAN_MCR_WRNEN_MASK (0x200000U)
4581#define CAN_MCR_WRNEN_SHIFT (21U)
4586#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4587#define CAN_MCR_SLFWAK_MASK (0x400000U)
4588#define CAN_MCR_SLFWAK_SHIFT (22U)
4593#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4594#define CAN_MCR_SUPV_MASK (0x800000U)
4595#define CAN_MCR_SUPV_SHIFT (23U)
4600#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4601#define CAN_MCR_FRZACK_MASK (0x1000000U)
4602#define CAN_MCR_FRZACK_SHIFT (24U)
4607#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4608#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4609#define CAN_MCR_SOFTRST_SHIFT (25U)
4614#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4615#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4616#define CAN_MCR_WAKMSK_SHIFT (26U)
4621#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4622#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4623#define CAN_MCR_NOTRDY_SHIFT (27U)
4628#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4629#define CAN_MCR_HALT_MASK (0x10000000U)
4630#define CAN_MCR_HALT_SHIFT (28U)
4635#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4636#define CAN_MCR_RFEN_MASK (0x20000000U)
4637#define CAN_MCR_RFEN_SHIFT (29U)
4642#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4643#define CAN_MCR_FRZ_MASK (0x40000000U)
4644#define CAN_MCR_FRZ_SHIFT (30U)
4649#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4650#define CAN_MCR_MDIS_MASK (0x80000000U)
4651#define CAN_MCR_MDIS_SHIFT (31U)
4656#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4661#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4662#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4663#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4664#define CAN_CTRL1_LOM_MASK (0x8U)
4665#define CAN_CTRL1_LOM_SHIFT (3U)
4670#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4671#define CAN_CTRL1_LBUF_MASK (0x10U)
4672#define CAN_CTRL1_LBUF_SHIFT (4U)
4677#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4678#define CAN_CTRL1_TSYN_MASK (0x20U)
4679#define CAN_CTRL1_TSYN_SHIFT (5U)
4684#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4685#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4686#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4691#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4692#define CAN_CTRL1_SMP_MASK (0x80U)
4693#define CAN_CTRL1_SMP_SHIFT (7U)
4698#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4699#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4700#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4705#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4706#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4707#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4712#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4713#define CAN_CTRL1_LPB_MASK (0x1000U)
4714#define CAN_CTRL1_LPB_SHIFT (12U)
4719#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4720#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4721#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4726#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4727#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4728#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4733#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4734#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4735#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4740#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4741#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4742#define CAN_CTRL1_PSEG2_SHIFT (16U)
4743#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4744#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4745#define CAN_CTRL1_PSEG1_SHIFT (19U)
4746#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4747#define CAN_CTRL1_RJW_MASK (0xC00000U)
4748#define CAN_CTRL1_RJW_SHIFT (22U)
4749#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4750#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4751#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4752#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4757#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4758#define CAN_TIMER_TIMER_SHIFT (0U)
4759#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4764#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4765#define CAN_RXMGMASK_MG_SHIFT (0U)
4770#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4775#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4776#define CAN_RX14MASK_RX14M_SHIFT (0U)
4781#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4786#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4787#define CAN_RX15MASK_RX15M_SHIFT (0U)
4792#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4797#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4798#define CAN_ECR_TXERRCNT_SHIFT (0U)
4799#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4800#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4801#define CAN_ECR_RXERRCNT_SHIFT (8U)
4802#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4807#define CAN_ESR1_WAKINT_MASK (0x1U)
4808#define CAN_ESR1_WAKINT_SHIFT (0U)
4813#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4814#define CAN_ESR1_ERRINT_MASK (0x2U)
4815#define CAN_ESR1_ERRINT_SHIFT (1U)
4820#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4821#define CAN_ESR1_BOFFINT_MASK (0x4U)
4822#define CAN_ESR1_BOFFINT_SHIFT (2U)
4827#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4828#define CAN_ESR1_RX_MASK (0x8U)
4829#define CAN_ESR1_RX_SHIFT (3U)
4834#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4835#define CAN_ESR1_FLTCONF_MASK (0x30U)
4836#define CAN_ESR1_FLTCONF_SHIFT (4U)
4842#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4843#define CAN_ESR1_TX_MASK (0x40U)
4844#define CAN_ESR1_TX_SHIFT (6U)
4849#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4850#define CAN_ESR1_IDLE_MASK (0x80U)
4851#define CAN_ESR1_IDLE_SHIFT (7U)
4856#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4857#define CAN_ESR1_RXWRN_MASK (0x100U)
4858#define CAN_ESR1_RXWRN_SHIFT (8U)
4863#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4864#define CAN_ESR1_TXWRN_MASK (0x200U)
4865#define CAN_ESR1_TXWRN_SHIFT (9U)
4870#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4871#define CAN_ESR1_STFERR_MASK (0x400U)
4872#define CAN_ESR1_STFERR_SHIFT (10U)
4877#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4878#define CAN_ESR1_FRMERR_MASK (0x800U)
4879#define CAN_ESR1_FRMERR_SHIFT (11U)
4884#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4885#define CAN_ESR1_CRCERR_MASK (0x1000U)
4886#define CAN_ESR1_CRCERR_SHIFT (12U)
4891#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4892#define CAN_ESR1_ACKERR_MASK (0x2000U)
4893#define CAN_ESR1_ACKERR_SHIFT (13U)
4898#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4899#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4900#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4905#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4906#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4907#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4912#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4913#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4914#define CAN_ESR1_RWRNINT_SHIFT (16U)
4919#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4920#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4921#define CAN_ESR1_TWRNINT_SHIFT (17U)
4926#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4927#define CAN_ESR1_SYNCH_MASK (0x40000U)
4928#define CAN_ESR1_SYNCH_SHIFT (18U)
4933#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4934#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
4935#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
4940#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4941#define CAN_ESR1_ERROVR_MASK (0x200000U)
4942#define CAN_ESR1_ERROVR_SHIFT (21U)
4947#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4952#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4953#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4958#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4963#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4964#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4969#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4970#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4971#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4976#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4977#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4978#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4983#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4984#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4985#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4990#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4991#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4992#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4997#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4998#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4999#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
5004#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
5009#define CAN_CTRL2_EACEN_MASK (0x10000U)
5010#define CAN_CTRL2_EACEN_SHIFT (16U)
5015#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
5016#define CAN_CTRL2_RRS_MASK (0x20000U)
5017#define CAN_CTRL2_RRS_SHIFT (17U)
5022#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
5023#define CAN_CTRL2_MRP_MASK (0x40000U)
5024#define CAN_CTRL2_MRP_SHIFT (18U)
5029#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
5030#define CAN_CTRL2_TASD_MASK (0xF80000U)
5031#define CAN_CTRL2_TASD_SHIFT (19U)
5032#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
5033#define CAN_CTRL2_RFFN_MASK (0xF000000U)
5034#define CAN_CTRL2_RFFN_SHIFT (24U)
5035#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
5036#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
5037#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
5042#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
5047#define CAN_ESR2_IMB_MASK (0x2000U)
5048#define CAN_ESR2_IMB_SHIFT (13U)
5053#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
5054#define CAN_ESR2_VPS_MASK (0x4000U)
5055#define CAN_ESR2_VPS_SHIFT (14U)
5060#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
5061#define CAN_ESR2_LPTM_MASK (0x7F0000U)
5062#define CAN_ESR2_LPTM_SHIFT (16U)
5063#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
5068#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
5069#define CAN_CRCR_TXCRC_SHIFT (0U)
5070#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
5071#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
5072#define CAN_CRCR_MBCRC_SHIFT (16U)
5073#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
5078#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
5079#define CAN_RXFGMASK_FGM_SHIFT (0U)
5084#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
5089#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
5090#define CAN_RXFIR_IDHIT_SHIFT (0U)
5091#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
5096#define CAN_CBT_EPSEG2_MASK (0x1FU)
5097#define CAN_CBT_EPSEG2_SHIFT (0U)
5098#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
5099#define CAN_CBT_EPSEG1_MASK (0x3E0U)
5100#define CAN_CBT_EPSEG1_SHIFT (5U)
5101#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
5102#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
5103#define CAN_CBT_EPROPSEG_SHIFT (10U)
5104#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
5105#define CAN_CBT_ERJW_MASK (0xF0000U)
5106#define CAN_CBT_ERJW_SHIFT (16U)
5107#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
5108#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
5109#define CAN_CBT_EPRESDIV_SHIFT (21U)
5110#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
5111#define CAN_CBT_BTF_MASK (0x80000000U)
5112#define CAN_CBT_BTF_SHIFT (31U)
5117#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
5122#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
5123#define CAN_CS_TIME_STAMP_SHIFT (0U)
5124#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
5125#define CAN_CS_DLC_MASK (0xF0000U)
5126#define CAN_CS_DLC_SHIFT (16U)
5127#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
5128#define CAN_CS_RTR_MASK (0x100000U)
5129#define CAN_CS_RTR_SHIFT (20U)
5130#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
5131#define CAN_CS_IDE_MASK (0x200000U)
5132#define CAN_CS_IDE_SHIFT (21U)
5133#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
5134#define CAN_CS_SRR_MASK (0x400000U)
5135#define CAN_CS_SRR_SHIFT (22U)
5136#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
5137#define CAN_CS_CODE_MASK (0xF000000U)
5138#define CAN_CS_CODE_SHIFT (24U)
5139#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
5140#define CAN_CS_ESI_MASK (0x20000000U)
5141#define CAN_CS_ESI_SHIFT (29U)
5142#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
5143#define CAN_CS_BRS_MASK (0x40000000U)
5144#define CAN_CS_BRS_SHIFT (30U)
5145#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
5146#define CAN_CS_EDL_MASK (0x80000000U)
5147#define CAN_CS_EDL_SHIFT (31U)
5148#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
5151/* The count of CAN_CS */
5152#define CAN_CS_COUNT (16U)
5153
5156#define CAN_ID_EXT_MASK (0x3FFFFU)
5157#define CAN_ID_EXT_SHIFT (0U)
5158#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
5159#define CAN_ID_STD_MASK (0x1FFC0000U)
5160#define CAN_ID_STD_SHIFT (18U)
5161#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
5162#define CAN_ID_PRIO_MASK (0xE0000000U)
5163#define CAN_ID_PRIO_SHIFT (29U)
5164#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
5167/* The count of CAN_ID */
5168#define CAN_ID_COUNT (16U)
5169
5172#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
5173#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
5174#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
5175#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
5176#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
5177#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
5178#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
5179#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
5180#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
5181#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
5182#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
5183#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
5186/* The count of CAN_WORD0 */
5187#define CAN_WORD0_COUNT (16U)
5188
5191#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
5192#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
5193#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
5194#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
5195#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
5196#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
5197#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
5198#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
5199#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
5200#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
5201#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
5202#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
5205/* The count of CAN_WORD1 */
5206#define CAN_WORD1_COUNT (16U)
5207
5210#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
5211#define CAN_RXIMR_MI_SHIFT (0U)
5216#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5219/* The count of CAN_RXIMR */
5220#define CAN_RXIMR_COUNT (16U)
5221
5222
5225 /* end of group CAN_Register_Masks */
5226
5227
5228/* CAN - Peripheral instance base addresses */
5230#define CAN0_BASE (0x40024000u)
5232#define CAN0 ((CAN_Type *)CAN0_BASE)
5234#define CAN1_BASE (0x40025000u)
5236#define CAN1 ((CAN_Type *)CAN1_BASE)
5238#define CAN2_BASE (0x400A4000u)
5240#define CAN2 ((CAN_Type *)CAN2_BASE)
5242#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE }
5244#define CAN_BASE_PTRS { CAN0, CAN1, CAN2 }
5246#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn, CAN2_Rx_Warning_IRQn }
5247#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn, CAN2_Tx_Warning_IRQn }
5248#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn, CAN2_Wake_Up_IRQn }
5249#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn, CAN2_Error_IRQn }
5250#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn, CAN2_Bus_Off_IRQn }
5251#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn, CAN2_ORed_Message_buffer_IRQn }
5252#define CAN_IMASK1_BUFLM_MASK CAN_IMASK1_BUF31TO0M_MASK
5253#define CAN_IMASK1_BUFLM_SHIFT CAN_IMASK1_BUF31TO0M_SHIFT
5254#define CAN_IMASK1_BUFLM_WIDTH CAN_IMASK1_BUF31TO0M_WIDTH
5255#define CAN_IMASK1_BUFLM(x) CAN_IMASK1_BUF31TO0M(x)
5256
5257
5260 /* end of group CAN_Peripheral_Access_Layer */
5261
5262
5263/* ----------------------------------------------------------------------------
5264 -- CAU Peripheral Access Layer
5265 ---------------------------------------------------------------------------- */
5266
5273typedef struct {
5274 __O uint32_t DIRECT[16];
5275 uint8_t RESERVED_0[2048];
5276 __O uint32_t LDR_CASR;
5277 __O uint32_t LDR_CAA;
5278 __O uint32_t LDR_CA[9];
5279 uint8_t RESERVED_1[20];
5280 __I uint32_t STR_CASR;
5281 __I uint32_t STR_CAA;
5282 __I uint32_t STR_CA[9];
5283 uint8_t RESERVED_2[20];
5284 __O uint32_t ADR_CASR;
5285 __O uint32_t ADR_CAA;
5286 __O uint32_t ADR_CA[9];
5287 uint8_t RESERVED_3[20];
5288 __O uint32_t RADR_CASR;
5289 __O uint32_t RADR_CAA;
5290 __O uint32_t RADR_CA[9];
5291 uint8_t RESERVED_4[84];
5292 __O uint32_t XOR_CASR;
5293 __O uint32_t XOR_CAA;
5294 __O uint32_t XOR_CA[9];
5295 uint8_t RESERVED_5[20];
5296 __O uint32_t ROTL_CASR;
5297 __O uint32_t ROTL_CAA;
5298 __O uint32_t ROTL_CA[9];
5299 uint8_t RESERVED_6[276];
5300 __O uint32_t AESC_CASR;
5301 __O uint32_t AESC_CAA;
5302 __O uint32_t AESC_CA[9];
5303 uint8_t RESERVED_7[20];
5304 __O uint32_t AESIC_CASR;
5305 __O uint32_t AESIC_CAA;
5306 __O uint32_t AESIC_CA[9];
5307} CAU_Type;
5308
5309/* ----------------------------------------------------------------------------
5310 -- CAU Register Masks
5311 ---------------------------------------------------------------------------- */
5312
5320#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
5321#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
5322#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
5323#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
5324#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
5325#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
5326#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
5327#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
5328#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
5329#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
5330#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
5331#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
5332#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
5333#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
5334#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
5335#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
5336#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
5337#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
5338#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
5339#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
5340#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
5341#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
5342#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
5343#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
5344#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
5345#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
5346#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
5347#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
5348#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
5349#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
5350#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
5351#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
5352#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
5353#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
5354#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
5355#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
5356#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
5357#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
5358#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
5359#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
5360#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
5361#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
5362#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
5363#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
5364#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
5365#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
5366#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
5367#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
5370/* The count of CAU_DIRECT */
5371#define CAU_DIRECT_COUNT (16U)
5372
5375#define CAU_LDR_CASR_IC_MASK (0x1U)
5376#define CAU_LDR_CASR_IC_SHIFT (0U)
5381#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
5382#define CAU_LDR_CASR_DPE_MASK (0x2U)
5383#define CAU_LDR_CASR_DPE_SHIFT (1U)
5388#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
5389#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
5390#define CAU_LDR_CASR_VER_SHIFT (28U)
5395#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
5400#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
5401#define CAU_LDR_CAA_ACC_SHIFT (0U)
5402#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
5407#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
5408#define CAU_LDR_CA_CA0_SHIFT (0U)
5409#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
5410#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
5411#define CAU_LDR_CA_CA1_SHIFT (0U)
5412#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
5413#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
5414#define CAU_LDR_CA_CA2_SHIFT (0U)
5415#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
5416#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
5417#define CAU_LDR_CA_CA3_SHIFT (0U)
5418#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
5419#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
5420#define CAU_LDR_CA_CA4_SHIFT (0U)
5421#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
5422#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
5423#define CAU_LDR_CA_CA5_SHIFT (0U)
5424#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
5425#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
5426#define CAU_LDR_CA_CA6_SHIFT (0U)
5427#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
5428#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
5429#define CAU_LDR_CA_CA7_SHIFT (0U)
5430#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
5431#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
5432#define CAU_LDR_CA_CA8_SHIFT (0U)
5433#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
5436/* The count of CAU_LDR_CA */
5437#define CAU_LDR_CA_COUNT (9U)
5438
5441#define CAU_STR_CASR_IC_MASK (0x1U)
5442#define CAU_STR_CASR_IC_SHIFT (0U)
5447#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
5448#define CAU_STR_CASR_DPE_MASK (0x2U)
5449#define CAU_STR_CASR_DPE_SHIFT (1U)
5454#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
5455#define CAU_STR_CASR_VER_MASK (0xF0000000U)
5456#define CAU_STR_CASR_VER_SHIFT (28U)
5461#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
5466#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
5467#define CAU_STR_CAA_ACC_SHIFT (0U)
5468#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
5473#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
5474#define CAU_STR_CA_CA0_SHIFT (0U)
5475#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
5476#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
5477#define CAU_STR_CA_CA1_SHIFT (0U)
5478#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
5479#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
5480#define CAU_STR_CA_CA2_SHIFT (0U)
5481#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
5482#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
5483#define CAU_STR_CA_CA3_SHIFT (0U)
5484#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
5485#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
5486#define CAU_STR_CA_CA4_SHIFT (0U)
5487#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
5488#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
5489#define CAU_STR_CA_CA5_SHIFT (0U)
5490#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
5491#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
5492#define CAU_STR_CA_CA6_SHIFT (0U)
5493#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
5494#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
5495#define CAU_STR_CA_CA7_SHIFT (0U)
5496#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
5497#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
5498#define CAU_STR_CA_CA8_SHIFT (0U)
5499#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
5502/* The count of CAU_STR_CA */
5503#define CAU_STR_CA_COUNT (9U)
5504
5507#define CAU_ADR_CASR_IC_MASK (0x1U)
5508#define CAU_ADR_CASR_IC_SHIFT (0U)
5513#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
5514#define CAU_ADR_CASR_DPE_MASK (0x2U)
5515#define CAU_ADR_CASR_DPE_SHIFT (1U)
5520#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
5521#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
5522#define CAU_ADR_CASR_VER_SHIFT (28U)
5527#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
5532#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
5533#define CAU_ADR_CAA_ACC_SHIFT (0U)
5534#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
5539#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
5540#define CAU_ADR_CA_CA0_SHIFT (0U)
5541#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
5542#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
5543#define CAU_ADR_CA_CA1_SHIFT (0U)
5544#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
5545#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
5546#define CAU_ADR_CA_CA2_SHIFT (0U)
5547#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
5548#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
5549#define CAU_ADR_CA_CA3_SHIFT (0U)
5550#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
5551#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
5552#define CAU_ADR_CA_CA4_SHIFT (0U)
5553#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
5554#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
5555#define CAU_ADR_CA_CA5_SHIFT (0U)
5556#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
5557#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
5558#define CAU_ADR_CA_CA6_SHIFT (0U)
5559#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
5560#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
5561#define CAU_ADR_CA_CA7_SHIFT (0U)
5562#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
5563#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
5564#define CAU_ADR_CA_CA8_SHIFT (0U)
5565#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
5568/* The count of CAU_ADR_CA */
5569#define CAU_ADR_CA_COUNT (9U)
5570
5573#define CAU_RADR_CASR_IC_MASK (0x1U)
5574#define CAU_RADR_CASR_IC_SHIFT (0U)
5579#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
5580#define CAU_RADR_CASR_DPE_MASK (0x2U)
5581#define CAU_RADR_CASR_DPE_SHIFT (1U)
5586#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
5587#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
5588#define CAU_RADR_CASR_VER_SHIFT (28U)
5593#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
5598#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
5599#define CAU_RADR_CAA_ACC_SHIFT (0U)
5600#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
5605#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
5606#define CAU_RADR_CA_CA0_SHIFT (0U)
5607#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
5608#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
5609#define CAU_RADR_CA_CA1_SHIFT (0U)
5610#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
5611#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
5612#define CAU_RADR_CA_CA2_SHIFT (0U)
5613#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
5614#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
5615#define CAU_RADR_CA_CA3_SHIFT (0U)
5616#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
5617#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
5618#define CAU_RADR_CA_CA4_SHIFT (0U)
5619#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
5620#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
5621#define CAU_RADR_CA_CA5_SHIFT (0U)
5622#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
5623#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
5624#define CAU_RADR_CA_CA6_SHIFT (0U)
5625#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
5626#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
5627#define CAU_RADR_CA_CA7_SHIFT (0U)
5628#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
5629#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
5630#define CAU_RADR_CA_CA8_SHIFT (0U)
5631#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
5634/* The count of CAU_RADR_CA */
5635#define CAU_RADR_CA_COUNT (9U)
5636
5639#define CAU_XOR_CASR_IC_MASK (0x1U)
5640#define CAU_XOR_CASR_IC_SHIFT (0U)
5645#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
5646#define CAU_XOR_CASR_DPE_MASK (0x2U)
5647#define CAU_XOR_CASR_DPE_SHIFT (1U)
5652#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
5653#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
5654#define CAU_XOR_CASR_VER_SHIFT (28U)
5659#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
5664#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
5665#define CAU_XOR_CAA_ACC_SHIFT (0U)
5666#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
5671#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
5672#define CAU_XOR_CA_CA0_SHIFT (0U)
5673#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
5674#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
5675#define CAU_XOR_CA_CA1_SHIFT (0U)
5676#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
5677#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
5678#define CAU_XOR_CA_CA2_SHIFT (0U)
5679#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
5680#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
5681#define CAU_XOR_CA_CA3_SHIFT (0U)
5682#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
5683#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
5684#define CAU_XOR_CA_CA4_SHIFT (0U)
5685#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
5686#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
5687#define CAU_XOR_CA_CA5_SHIFT (0U)
5688#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
5689#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
5690#define CAU_XOR_CA_CA6_SHIFT (0U)
5691#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
5692#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
5693#define CAU_XOR_CA_CA7_SHIFT (0U)
5694#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
5695#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
5696#define CAU_XOR_CA_CA8_SHIFT (0U)
5697#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
5700/* The count of CAU_XOR_CA */
5701#define CAU_XOR_CA_COUNT (9U)
5702
5705#define CAU_ROTL_CASR_IC_MASK (0x1U)
5706#define CAU_ROTL_CASR_IC_SHIFT (0U)
5711#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
5712#define CAU_ROTL_CASR_DPE_MASK (0x2U)
5713#define CAU_ROTL_CASR_DPE_SHIFT (1U)
5718#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
5719#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
5720#define CAU_ROTL_CASR_VER_SHIFT (28U)
5725#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
5730#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
5731#define CAU_ROTL_CAA_ACC_SHIFT (0U)
5732#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
5737#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
5738#define CAU_ROTL_CA_CA0_SHIFT (0U)
5739#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
5740#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
5741#define CAU_ROTL_CA_CA1_SHIFT (0U)
5742#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
5743#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
5744#define CAU_ROTL_CA_CA2_SHIFT (0U)
5745#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
5746#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
5747#define CAU_ROTL_CA_CA3_SHIFT (0U)
5748#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
5749#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
5750#define CAU_ROTL_CA_CA4_SHIFT (0U)
5751#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
5752#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
5753#define CAU_ROTL_CA_CA5_SHIFT (0U)
5754#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
5755#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
5756#define CAU_ROTL_CA_CA6_SHIFT (0U)
5757#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
5758#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
5759#define CAU_ROTL_CA_CA7_SHIFT (0U)
5760#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
5761#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
5762#define CAU_ROTL_CA_CA8_SHIFT (0U)
5763#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
5766/* The count of CAU_ROTL_CA */
5767#define CAU_ROTL_CA_COUNT (9U)
5768
5771#define CAU_AESC_CASR_IC_MASK (0x1U)
5772#define CAU_AESC_CASR_IC_SHIFT (0U)
5777#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
5778#define CAU_AESC_CASR_DPE_MASK (0x2U)
5779#define CAU_AESC_CASR_DPE_SHIFT (1U)
5784#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
5785#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
5786#define CAU_AESC_CASR_VER_SHIFT (28U)
5791#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
5796#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
5797#define CAU_AESC_CAA_ACC_SHIFT (0U)
5798#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
5803#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
5804#define CAU_AESC_CA_CA0_SHIFT (0U)
5805#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
5806#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
5807#define CAU_AESC_CA_CA1_SHIFT (0U)
5808#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
5809#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
5810#define CAU_AESC_CA_CA2_SHIFT (0U)
5811#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
5812#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
5813#define CAU_AESC_CA_CA3_SHIFT (0U)
5814#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
5815#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
5816#define CAU_AESC_CA_CA4_SHIFT (0U)
5817#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
5818#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
5819#define CAU_AESC_CA_CA5_SHIFT (0U)
5820#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
5821#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
5822#define CAU_AESC_CA_CA6_SHIFT (0U)
5823#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
5824#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
5825#define CAU_AESC_CA_CA7_SHIFT (0U)
5826#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
5827#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
5828#define CAU_AESC_CA_CA8_SHIFT (0U)
5829#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
5832/* The count of CAU_AESC_CA */
5833#define CAU_AESC_CA_COUNT (9U)
5834
5837#define CAU_AESIC_CASR_IC_MASK (0x1U)
5838#define CAU_AESIC_CASR_IC_SHIFT (0U)
5843#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
5844#define CAU_AESIC_CASR_DPE_MASK (0x2U)
5845#define CAU_AESIC_CASR_DPE_SHIFT (1U)
5850#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
5851#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
5852#define CAU_AESIC_CASR_VER_SHIFT (28U)
5857#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
5862#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
5863#define CAU_AESIC_CAA_ACC_SHIFT (0U)
5864#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
5869#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
5870#define CAU_AESIC_CA_CA0_SHIFT (0U)
5871#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
5872#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
5873#define CAU_AESIC_CA_CA1_SHIFT (0U)
5874#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
5875#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
5876#define CAU_AESIC_CA_CA2_SHIFT (0U)
5877#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
5878#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
5879#define CAU_AESIC_CA_CA3_SHIFT (0U)
5880#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
5881#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
5882#define CAU_AESIC_CA_CA4_SHIFT (0U)
5883#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
5884#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
5885#define CAU_AESIC_CA_CA5_SHIFT (0U)
5886#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
5887#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
5888#define CAU_AESIC_CA_CA6_SHIFT (0U)
5889#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
5890#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
5891#define CAU_AESIC_CA_CA7_SHIFT (0U)
5892#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
5893#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
5894#define CAU_AESIC_CA_CA8_SHIFT (0U)
5895#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
5898/* The count of CAU_AESIC_CA */
5899#define CAU_AESIC_CA_COUNT (9U)
5900
5901
5904 /* end of group CAU_Register_Masks */
5905
5906
5907/* CAU - Peripheral instance base addresses */
5909#define CAU_BASE (0xE0081000u)
5911#define CAU ((CAU_Type *)CAU_BASE)
5913#define CAU_BASE_ADDRS { CAU_BASE }
5915#define CAU_BASE_PTRS { CAU }
5916
5919 /* end of group CAU_Peripheral_Access_Layer */
5920
5921
5922/* ----------------------------------------------------------------------------
5923 -- CMP Peripheral Access Layer
5924 ---------------------------------------------------------------------------- */
5925
5932typedef struct {
5933 __IO uint8_t CR0;
5934 __IO uint8_t CR1;
5935 __IO uint8_t FPR;
5936 __IO uint8_t SCR;
5937 __IO uint8_t DACCR;
5938 __IO uint8_t MUXCR;
5939} CMP_Type;
5940
5941/* ----------------------------------------------------------------------------
5942 -- CMP Register Masks
5943 ---------------------------------------------------------------------------- */
5944
5952#define CMP_CR0_HYSTCTR_MASK (0x3U)
5953#define CMP_CR0_HYSTCTR_SHIFT (0U)
5960#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
5961#define CMP_CR0_FILTER_CNT_MASK (0x70U)
5962#define CMP_CR0_FILTER_CNT_SHIFT (4U)
5973#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
5978#define CMP_CR1_EN_MASK (0x1U)
5979#define CMP_CR1_EN_SHIFT (0U)
5984#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
5985#define CMP_CR1_OPE_MASK (0x2U)
5986#define CMP_CR1_OPE_SHIFT (1U)
5991#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
5992#define CMP_CR1_COS_MASK (0x4U)
5993#define CMP_CR1_COS_SHIFT (2U)
5998#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
5999#define CMP_CR1_INV_MASK (0x8U)
6000#define CMP_CR1_INV_SHIFT (3U)
6005#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
6006#define CMP_CR1_PMODE_MASK (0x10U)
6007#define CMP_CR1_PMODE_SHIFT (4U)
6012#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
6013#define CMP_CR1_TRIGM_MASK (0x20U)
6014#define CMP_CR1_TRIGM_SHIFT (5U)
6019#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
6020#define CMP_CR1_WE_MASK (0x40U)
6021#define CMP_CR1_WE_SHIFT (6U)
6026#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
6027#define CMP_CR1_SE_MASK (0x80U)
6028#define CMP_CR1_SE_SHIFT (7U)
6033#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
6038#define CMP_FPR_FILT_PER_MASK (0xFFU)
6039#define CMP_FPR_FILT_PER_SHIFT (0U)
6040#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
6045#define CMP_SCR_COUT_MASK (0x1U)
6046#define CMP_SCR_COUT_SHIFT (0U)
6047#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
6048#define CMP_SCR_CFF_MASK (0x2U)
6049#define CMP_SCR_CFF_SHIFT (1U)
6054#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
6055#define CMP_SCR_CFR_MASK (0x4U)
6056#define CMP_SCR_CFR_SHIFT (2U)
6061#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
6062#define CMP_SCR_IEF_MASK (0x8U)
6063#define CMP_SCR_IEF_SHIFT (3U)
6068#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
6069#define CMP_SCR_IER_MASK (0x10U)
6070#define CMP_SCR_IER_SHIFT (4U)
6075#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
6076#define CMP_SCR_DMAEN_MASK (0x40U)
6077#define CMP_SCR_DMAEN_SHIFT (6U)
6082#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
6087#define CMP_DACCR_VOSEL_MASK (0x3FU)
6088#define CMP_DACCR_VOSEL_SHIFT (0U)
6089#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
6090#define CMP_DACCR_VRSEL_MASK (0x40U)
6091#define CMP_DACCR_VRSEL_SHIFT (6U)
6096#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
6097#define CMP_DACCR_DACEN_MASK (0x80U)
6098#define CMP_DACCR_DACEN_SHIFT (7U)
6103#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
6108#define CMP_MUXCR_MSEL_MASK (0x7U)
6109#define CMP_MUXCR_MSEL_SHIFT (0U)
6120#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
6121#define CMP_MUXCR_PSEL_MASK (0x38U)
6122#define CMP_MUXCR_PSEL_SHIFT (3U)
6133#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
6139 /* end of group CMP_Register_Masks */
6140
6141
6142/* CMP - Peripheral instance base addresses */
6144#define CMP0_BASE (0x40073000u)
6146#define CMP0 ((CMP_Type *)CMP0_BASE)
6148#define CMP1_BASE (0x40073008u)
6150#define CMP1 ((CMP_Type *)CMP1_BASE)
6152#define CMP2_BASE (0x40073010u)
6154#define CMP2 ((CMP_Type *)CMP2_BASE)
6156#define CMP3_BASE (0x40073018u)
6158#define CMP3 ((CMP_Type *)CMP3_BASE)
6160#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
6162#define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
6164#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
6165
6168 /* end of group CMP_Peripheral_Access_Layer */
6169
6170
6171/* ----------------------------------------------------------------------------
6172 -- CRC Peripheral Access Layer
6173 ---------------------------------------------------------------------------- */
6174
6181typedef struct {
6182 union { /* offset: 0x0 */
6183 struct { /* offset: 0x0 */
6184 __IO uint16_t DATAL;
6185 __IO uint16_t DATAH;
6186 } ACCESS16BIT;
6187 __IO uint32_t DATA;
6188 struct { /* offset: 0x0 */
6189 __IO uint8_t DATALL;
6190 __IO uint8_t DATALU;
6191 __IO uint8_t DATAHL;
6192 __IO uint8_t DATAHU;
6193 } ACCESS8BIT;
6194 };
6195 union { /* offset: 0x4 */
6196 struct { /* offset: 0x4 */
6197 __IO uint16_t GPOLYL;
6198 __IO uint16_t GPOLYH;
6199 } GPOLY_ACCESS16BIT;
6200 __IO uint32_t GPOLY;
6201 struct { /* offset: 0x4 */
6202 __IO uint8_t GPOLYLL;
6203 __IO uint8_t GPOLYLU;
6204 __IO uint8_t GPOLYHL;
6205 __IO uint8_t GPOLYHU;
6206 } GPOLY_ACCESS8BIT;
6207 };
6208 union { /* offset: 0x8 */
6209 __IO uint32_t CTRL;
6210 struct { /* offset: 0x8 */
6211 uint8_t RESERVED_0[3];
6212 __IO uint8_t CTRLHU;
6213 } CTRL_ACCESS8BIT;
6214 };
6215} CRC_Type;
6216
6217/* ----------------------------------------------------------------------------
6218 -- CRC Register Masks
6219 ---------------------------------------------------------------------------- */
6220
6228#define CRC_DATAL_DATAL_MASK (0xFFFFU)
6229#define CRC_DATAL_DATAL_SHIFT (0U)
6230#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
6235#define CRC_DATAH_DATAH_MASK (0xFFFFU)
6236#define CRC_DATAH_DATAH_SHIFT (0U)
6237#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
6242#define CRC_DATA_LL_MASK (0xFFU)
6243#define CRC_DATA_LL_SHIFT (0U)
6244#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
6245#define CRC_DATA_LU_MASK (0xFF00U)
6246#define CRC_DATA_LU_SHIFT (8U)
6247#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
6248#define CRC_DATA_HL_MASK (0xFF0000U)
6249#define CRC_DATA_HL_SHIFT (16U)
6250#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
6251#define CRC_DATA_HU_MASK (0xFF000000U)
6252#define CRC_DATA_HU_SHIFT (24U)
6253#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
6258#define CRC_DATALL_DATALL_MASK (0xFFU)
6259#define CRC_DATALL_DATALL_SHIFT (0U)
6260#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
6265#define CRC_DATALU_DATALU_MASK (0xFFU)
6266#define CRC_DATALU_DATALU_SHIFT (0U)
6267#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
6272#define CRC_DATAHL_DATAHL_MASK (0xFFU)
6273#define CRC_DATAHL_DATAHL_SHIFT (0U)
6274#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
6279#define CRC_DATAHU_DATAHU_MASK (0xFFU)
6280#define CRC_DATAHU_DATAHU_SHIFT (0U)
6281#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
6286#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
6287#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
6288#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
6293#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
6294#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
6295#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
6300#define CRC_GPOLY_LOW_MASK (0xFFFFU)
6301#define CRC_GPOLY_LOW_SHIFT (0U)
6302#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
6303#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
6304#define CRC_GPOLY_HIGH_SHIFT (16U)
6305#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
6310#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
6311#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
6312#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
6317#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
6318#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
6319#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
6324#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
6325#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
6326#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
6331#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
6332#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
6333#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
6338#define CRC_CTRL_TCRC_MASK (0x1000000U)
6339#define CRC_CTRL_TCRC_SHIFT (24U)
6344#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
6345#define CRC_CTRL_WAS_MASK (0x2000000U)
6346#define CRC_CTRL_WAS_SHIFT (25U)
6351#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
6352#define CRC_CTRL_FXOR_MASK (0x4000000U)
6353#define CRC_CTRL_FXOR_SHIFT (26U)
6358#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
6359#define CRC_CTRL_TOTR_MASK (0x30000000U)
6360#define CRC_CTRL_TOTR_SHIFT (28U)
6367#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
6368#define CRC_CTRL_TOT_MASK (0xC0000000U)
6369#define CRC_CTRL_TOT_SHIFT (30U)
6376#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
6381#define CRC_CTRLHU_TCRC_MASK (0x1U)
6382#define CRC_CTRLHU_TCRC_SHIFT (0U)
6387#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
6388#define CRC_CTRLHU_WAS_MASK (0x2U)
6389#define CRC_CTRLHU_WAS_SHIFT (1U)
6394#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
6395#define CRC_CTRLHU_FXOR_MASK (0x4U)
6396#define CRC_CTRLHU_FXOR_SHIFT (2U)
6401#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
6402#define CRC_CTRLHU_TOTR_MASK (0x30U)
6403#define CRC_CTRLHU_TOTR_SHIFT (4U)
6410#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
6411#define CRC_CTRLHU_TOT_MASK (0xC0U)
6412#define CRC_CTRLHU_TOT_SHIFT (6U)
6419#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
6425 /* end of group CRC_Register_Masks */
6426
6427
6428/* CRC - Peripheral instance base addresses */
6430#define CRC_BASE (0x40032000u)
6432#define CRC0 ((CRC_Type *)CRC_BASE)
6434#define CRC_BASE_ADDRS { CRC_BASE }
6436#define CRC_BASE_PTRS { CRC0 }
6437
6440 /* end of group CRC_Peripheral_Access_Layer */
6441
6442
6443/* ----------------------------------------------------------------------------
6444 -- DAC Peripheral Access Layer
6445 ---------------------------------------------------------------------------- */
6446
6453typedef struct {
6454 struct { /* offset: 0x0, array step: 0x2 */
6455 __IO uint8_t DATL;
6456 __IO uint8_t DATH;
6457 } DAT[16];
6458 __IO uint8_t SR;
6459 __IO uint8_t C0;
6460 __IO uint8_t C1;
6461 __IO uint8_t C2;
6462} DAC_Type;
6463
6464/* ----------------------------------------------------------------------------
6465 -- DAC Register Masks
6466 ---------------------------------------------------------------------------- */
6467
6475#define DAC_DATL_DATA0_MASK (0xFFU)
6476#define DAC_DATL_DATA0_SHIFT (0U)
6477#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
6480/* The count of DAC_DATL */
6481#define DAC_DATL_COUNT (16U)
6482
6485#define DAC_DATH_DATA1_MASK (0xFU)
6486#define DAC_DATH_DATA1_SHIFT (0U)
6487#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
6490/* The count of DAC_DATH */
6491#define DAC_DATH_COUNT (16U)
6492
6495#define DAC_SR_DACBFRPBF_MASK (0x1U)
6496#define DAC_SR_DACBFRPBF_SHIFT (0U)
6501#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
6502#define DAC_SR_DACBFRPTF_MASK (0x2U)
6503#define DAC_SR_DACBFRPTF_SHIFT (1U)
6508#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
6509#define DAC_SR_DACBFWMF_MASK (0x4U)
6510#define DAC_SR_DACBFWMF_SHIFT (2U)
6515#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
6520#define DAC_C0_DACBBIEN_MASK (0x1U)
6521#define DAC_C0_DACBBIEN_SHIFT (0U)
6526#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
6527#define DAC_C0_DACBTIEN_MASK (0x2U)
6528#define DAC_C0_DACBTIEN_SHIFT (1U)
6533#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
6534#define DAC_C0_DACBWIEN_MASK (0x4U)
6535#define DAC_C0_DACBWIEN_SHIFT (2U)
6540#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
6541#define DAC_C0_LPEN_MASK (0x8U)
6542#define DAC_C0_LPEN_SHIFT (3U)
6547#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
6548#define DAC_C0_DACSWTRG_MASK (0x10U)
6549#define DAC_C0_DACSWTRG_SHIFT (4U)
6554#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
6555#define DAC_C0_DACTRGSEL_MASK (0x20U)
6556#define DAC_C0_DACTRGSEL_SHIFT (5U)
6561#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
6562#define DAC_C0_DACRFS_MASK (0x40U)
6563#define DAC_C0_DACRFS_SHIFT (6U)
6568#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
6569#define DAC_C0_DACEN_MASK (0x80U)
6570#define DAC_C0_DACEN_SHIFT (7U)
6575#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
6580#define DAC_C1_DACBFEN_MASK (0x1U)
6581#define DAC_C1_DACBFEN_SHIFT (0U)
6586#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
6587#define DAC_C1_DACBFMD_MASK (0x6U)
6588#define DAC_C1_DACBFMD_SHIFT (1U)
6595#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
6596#define DAC_C1_DACBFWM_MASK (0x18U)
6597#define DAC_C1_DACBFWM_SHIFT (3U)
6604#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
6605#define DAC_C1_DMAEN_MASK (0x80U)
6606#define DAC_C1_DMAEN_SHIFT (7U)
6611#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
6616#define DAC_C2_DACBFUP_MASK (0xFU)
6617#define DAC_C2_DACBFUP_SHIFT (0U)
6618#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
6619#define DAC_C2_DACBFRP_MASK (0xF0U)
6620#define DAC_C2_DACBFRP_SHIFT (4U)
6621#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
6627 /* end of group DAC_Register_Masks */
6628
6629
6630/* DAC - Peripheral instance base addresses */
6632#define DAC0_BASE (0x4003F000u)
6634#define DAC0 ((DAC_Type *)DAC0_BASE)
6636#define DAC_BASE_ADDRS { DAC0_BASE }
6638#define DAC_BASE_PTRS { DAC0 }
6640#define DAC_IRQS { DAC0_IRQn }
6641
6644 /* end of group DAC_Peripheral_Access_Layer */
6645
6646
6647/* ----------------------------------------------------------------------------
6648 -- DMA Peripheral Access Layer
6649 ---------------------------------------------------------------------------- */
6650
6657typedef struct {
6658 __IO uint32_t CR;
6659 __I uint32_t ES;
6660 uint8_t RESERVED_0[4];
6661 __IO uint32_t ERQ;
6662 uint8_t RESERVED_1[4];
6663 __IO uint32_t EEI;
6664 __O uint8_t CEEI;
6665 __O uint8_t SEEI;
6666 __O uint8_t CERQ;
6667 __O uint8_t SERQ;
6668 __O uint8_t CDNE;
6669 __O uint8_t SSRT;
6670 __O uint8_t CERR;
6671 __O uint8_t CINT;
6672 uint8_t RESERVED_2[4];
6673 __IO uint32_t INT;
6674 uint8_t RESERVED_3[4];
6675 __IO uint32_t ERR;
6676 uint8_t RESERVED_4[4];
6677 __I uint32_t HRS;
6678 uint8_t RESERVED_5[12];
6679 __IO uint32_t EARS;
6680 uint8_t RESERVED_6[184];
6681 __IO uint8_t DCHPRI3;
6682 __IO uint8_t DCHPRI2;
6683 __IO uint8_t DCHPRI1;
6684 __IO uint8_t DCHPRI0;
6685 __IO uint8_t DCHPRI7;
6686 __IO uint8_t DCHPRI6;
6687 __IO uint8_t DCHPRI5;
6688 __IO uint8_t DCHPRI4;
6689 __IO uint8_t DCHPRI11;
6690 __IO uint8_t DCHPRI10;
6691 __IO uint8_t DCHPRI9;
6692 __IO uint8_t DCHPRI8;
6693 __IO uint8_t DCHPRI15;
6694 __IO uint8_t DCHPRI14;
6695 __IO uint8_t DCHPRI13;
6696 __IO uint8_t DCHPRI12;
6697 __IO uint8_t DCHPRI19;
6698 __IO uint8_t DCHPRI18;
6699 __IO uint8_t DCHPRI17;
6700 __IO uint8_t DCHPRI16;
6701 __IO uint8_t DCHPRI23;
6702 __IO uint8_t DCHPRI22;
6703 __IO uint8_t DCHPRI21;
6704 __IO uint8_t DCHPRI20;
6705 __IO uint8_t DCHPRI27;
6706 __IO uint8_t DCHPRI26;
6707 __IO uint8_t DCHPRI25;
6708 __IO uint8_t DCHPRI24;
6709 __IO uint8_t DCHPRI31;
6710 __IO uint8_t DCHPRI30;
6711 __IO uint8_t DCHPRI29;
6712 __IO uint8_t DCHPRI28;
6713 uint8_t RESERVED_7[3808];
6714 struct { /* offset: 0x1000, array step: 0x20 */
6715 __IO uint32_t SADDR;
6716 __IO uint16_t SOFF;
6717 __IO uint16_t ATTR;
6718 union { /* offset: 0x1008, array step: 0x20 */
6719 __IO uint32_t NBYTES_MLNO;
6720 __IO uint32_t NBYTES_MLOFFNO;
6721 __IO uint32_t NBYTES_MLOFFYES;
6722 };
6723 __IO uint32_t SLAST;
6724 __IO uint32_t DADDR;
6725 __IO uint16_t DOFF;
6726 union { /* offset: 0x1016, array step: 0x20 */
6727 __IO uint16_t CITER_ELINKNO;
6728 __IO uint16_t CITER_ELINKYES;
6729 };
6730 __IO uint32_t DLAST_SGA;
6731 __IO uint16_t CSR;
6732 union { /* offset: 0x101E, array step: 0x20 */
6733 __IO uint16_t BITER_ELINKNO;
6734 __IO uint16_t BITER_ELINKYES;
6735 };
6736 } TCD[32];
6737} DMA_Type;
6738
6739/* ----------------------------------------------------------------------------
6740 -- DMA Register Masks
6741 ---------------------------------------------------------------------------- */
6742
6750#define DMA_CR_EDBG_MASK (0x2U)
6751#define DMA_CR_EDBG_SHIFT (1U)
6756#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
6757#define DMA_CR_ERCA_MASK (0x4U)
6758#define DMA_CR_ERCA_SHIFT (2U)
6763#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
6764#define DMA_CR_ERGA_MASK (0x8U)
6765#define DMA_CR_ERGA_SHIFT (3U)
6770#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
6771#define DMA_CR_HOE_MASK (0x10U)
6772#define DMA_CR_HOE_SHIFT (4U)
6777#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
6778#define DMA_CR_HALT_MASK (0x20U)
6779#define DMA_CR_HALT_SHIFT (5U)
6784#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
6785#define DMA_CR_CLM_MASK (0x40U)
6786#define DMA_CR_CLM_SHIFT (6U)
6791#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
6792#define DMA_CR_EMLM_MASK (0x80U)
6793#define DMA_CR_EMLM_SHIFT (7U)
6798#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
6799#define DMA_CR_GRP0PRI_MASK (0x100U)
6800#define DMA_CR_GRP0PRI_SHIFT (8U)
6801#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
6802#define DMA_CR_GRP1PRI_MASK (0x400U)
6803#define DMA_CR_GRP1PRI_SHIFT (10U)
6804#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
6805#define DMA_CR_ECX_MASK (0x10000U)
6806#define DMA_CR_ECX_SHIFT (16U)
6811#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
6812#define DMA_CR_CX_MASK (0x20000U)
6813#define DMA_CR_CX_SHIFT (17U)
6818#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
6823#define DMA_ES_DBE_MASK (0x1U)
6824#define DMA_ES_DBE_SHIFT (0U)
6829#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
6830#define DMA_ES_SBE_MASK (0x2U)
6831#define DMA_ES_SBE_SHIFT (1U)
6836#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
6837#define DMA_ES_SGE_MASK (0x4U)
6838#define DMA_ES_SGE_SHIFT (2U)
6843#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
6844#define DMA_ES_NCE_MASK (0x8U)
6845#define DMA_ES_NCE_SHIFT (3U)
6850#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
6851#define DMA_ES_DOE_MASK (0x10U)
6852#define DMA_ES_DOE_SHIFT (4U)
6857#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
6858#define DMA_ES_DAE_MASK (0x20U)
6859#define DMA_ES_DAE_SHIFT (5U)
6864#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
6865#define DMA_ES_SOE_MASK (0x40U)
6866#define DMA_ES_SOE_SHIFT (6U)
6871#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
6872#define DMA_ES_SAE_MASK (0x80U)
6873#define DMA_ES_SAE_SHIFT (7U)
6878#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
6879#define DMA_ES_ERRCHN_MASK (0x1F00U)
6880#define DMA_ES_ERRCHN_SHIFT (8U)
6881#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
6882#define DMA_ES_CPE_MASK (0x4000U)
6883#define DMA_ES_CPE_SHIFT (14U)
6888#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
6889#define DMA_ES_GPE_MASK (0x8000U)
6890#define DMA_ES_GPE_SHIFT (15U)
6895#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
6896#define DMA_ES_ECX_MASK (0x10000U)
6897#define DMA_ES_ECX_SHIFT (16U)
6902#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
6903#define DMA_ES_VLD_MASK (0x80000000U)
6904#define DMA_ES_VLD_SHIFT (31U)
6909#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
6914#define DMA_ERQ_ERQ0_MASK (0x1U)
6915#define DMA_ERQ_ERQ0_SHIFT (0U)
6920#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
6921#define DMA_ERQ_ERQ1_MASK (0x2U)
6922#define DMA_ERQ_ERQ1_SHIFT (1U)
6927#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
6928#define DMA_ERQ_ERQ2_MASK (0x4U)
6929#define DMA_ERQ_ERQ2_SHIFT (2U)
6934#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
6935#define DMA_ERQ_ERQ3_MASK (0x8U)
6936#define DMA_ERQ_ERQ3_SHIFT (3U)
6941#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
6942#define DMA_ERQ_ERQ4_MASK (0x10U)
6943#define DMA_ERQ_ERQ4_SHIFT (4U)
6948#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
6949#define DMA_ERQ_ERQ5_MASK (0x20U)
6950#define DMA_ERQ_ERQ5_SHIFT (5U)
6955#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
6956#define DMA_ERQ_ERQ6_MASK (0x40U)
6957#define DMA_ERQ_ERQ6_SHIFT (6U)
6962#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
6963#define DMA_ERQ_ERQ7_MASK (0x80U)
6964#define DMA_ERQ_ERQ7_SHIFT (7U)
6969#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
6970#define DMA_ERQ_ERQ8_MASK (0x100U)
6971#define DMA_ERQ_ERQ8_SHIFT (8U)
6976#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
6977#define DMA_ERQ_ERQ9_MASK (0x200U)
6978#define DMA_ERQ_ERQ9_SHIFT (9U)
6983#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
6984#define DMA_ERQ_ERQ10_MASK (0x400U)
6985#define DMA_ERQ_ERQ10_SHIFT (10U)
6990#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
6991#define DMA_ERQ_ERQ11_MASK (0x800U)
6992#define DMA_ERQ_ERQ11_SHIFT (11U)
6997#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
6998#define DMA_ERQ_ERQ12_MASK (0x1000U)
6999#define DMA_ERQ_ERQ12_SHIFT (12U)
7004#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
7005#define DMA_ERQ_ERQ13_MASK (0x2000U)
7006#define DMA_ERQ_ERQ13_SHIFT (13U)
7011#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
7012#define DMA_ERQ_ERQ14_MASK (0x4000U)
7013#define DMA_ERQ_ERQ14_SHIFT (14U)
7018#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
7019#define DMA_ERQ_ERQ15_MASK (0x8000U)
7020#define DMA_ERQ_ERQ15_SHIFT (15U)
7025#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
7026#define DMA_ERQ_ERQ16_MASK (0x10000U)
7027#define DMA_ERQ_ERQ16_SHIFT (16U)
7032#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
7033#define DMA_ERQ_ERQ17_MASK (0x20000U)
7034#define DMA_ERQ_ERQ17_SHIFT (17U)
7039#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
7040#define DMA_ERQ_ERQ18_MASK (0x40000U)
7041#define DMA_ERQ_ERQ18_SHIFT (18U)
7046#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
7047#define DMA_ERQ_ERQ19_MASK (0x80000U)
7048#define DMA_ERQ_ERQ19_SHIFT (19U)
7053#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
7054#define DMA_ERQ_ERQ20_MASK (0x100000U)
7055#define DMA_ERQ_ERQ20_SHIFT (20U)
7060#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
7061#define DMA_ERQ_ERQ21_MASK (0x200000U)
7062#define DMA_ERQ_ERQ21_SHIFT (21U)
7067#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
7068#define DMA_ERQ_ERQ22_MASK (0x400000U)
7069#define DMA_ERQ_ERQ22_SHIFT (22U)
7074#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
7075#define DMA_ERQ_ERQ23_MASK (0x800000U)
7076#define DMA_ERQ_ERQ23_SHIFT (23U)
7081#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
7082#define DMA_ERQ_ERQ24_MASK (0x1000000U)
7083#define DMA_ERQ_ERQ24_SHIFT (24U)
7088#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
7089#define DMA_ERQ_ERQ25_MASK (0x2000000U)
7090#define DMA_ERQ_ERQ25_SHIFT (25U)
7095#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
7096#define DMA_ERQ_ERQ26_MASK (0x4000000U)
7097#define DMA_ERQ_ERQ26_SHIFT (26U)
7102#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
7103#define DMA_ERQ_ERQ27_MASK (0x8000000U)
7104#define DMA_ERQ_ERQ27_SHIFT (27U)
7109#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
7110#define DMA_ERQ_ERQ28_MASK (0x10000000U)
7111#define DMA_ERQ_ERQ28_SHIFT (28U)
7116#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
7117#define DMA_ERQ_ERQ29_MASK (0x20000000U)
7118#define DMA_ERQ_ERQ29_SHIFT (29U)
7123#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
7124#define DMA_ERQ_ERQ30_MASK (0x40000000U)
7125#define DMA_ERQ_ERQ30_SHIFT (30U)
7130#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
7131#define DMA_ERQ_ERQ31_MASK (0x80000000U)
7132#define DMA_ERQ_ERQ31_SHIFT (31U)
7137#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
7142#define DMA_EEI_EEI0_MASK (0x1U)
7143#define DMA_EEI_EEI0_SHIFT (0U)
7148#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
7149#define DMA_EEI_EEI1_MASK (0x2U)
7150#define DMA_EEI_EEI1_SHIFT (1U)
7155#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
7156#define DMA_EEI_EEI2_MASK (0x4U)
7157#define DMA_EEI_EEI2_SHIFT (2U)
7162#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
7163#define DMA_EEI_EEI3_MASK (0x8U)
7164#define DMA_EEI_EEI3_SHIFT (3U)
7169#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
7170#define DMA_EEI_EEI4_MASK (0x10U)
7171#define DMA_EEI_EEI4_SHIFT (4U)
7176#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
7177#define DMA_EEI_EEI5_MASK (0x20U)
7178#define DMA_EEI_EEI5_SHIFT (5U)
7183#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
7184#define DMA_EEI_EEI6_MASK (0x40U)
7185#define DMA_EEI_EEI6_SHIFT (6U)
7190#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
7191#define DMA_EEI_EEI7_MASK (0x80U)
7192#define DMA_EEI_EEI7_SHIFT (7U)
7197#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
7198#define DMA_EEI_EEI8_MASK (0x100U)
7199#define DMA_EEI_EEI8_SHIFT (8U)
7204#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
7205#define DMA_EEI_EEI9_MASK (0x200U)
7206#define DMA_EEI_EEI9_SHIFT (9U)
7211#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
7212#define DMA_EEI_EEI10_MASK (0x400U)
7213#define DMA_EEI_EEI10_SHIFT (10U)
7218#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
7219#define DMA_EEI_EEI11_MASK (0x800U)
7220#define DMA_EEI_EEI11_SHIFT (11U)
7225#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
7226#define DMA_EEI_EEI12_MASK (0x1000U)
7227#define DMA_EEI_EEI12_SHIFT (12U)
7232#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
7233#define DMA_EEI_EEI13_MASK (0x2000U)
7234#define DMA_EEI_EEI13_SHIFT (13U)
7239#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
7240#define DMA_EEI_EEI14_MASK (0x4000U)
7241#define DMA_EEI_EEI14_SHIFT (14U)
7246#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
7247#define DMA_EEI_EEI15_MASK (0x8000U)
7248#define DMA_EEI_EEI15_SHIFT (15U)
7253#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
7254#define DMA_EEI_EEI16_MASK (0x10000U)
7255#define DMA_EEI_EEI16_SHIFT (16U)
7260#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
7261#define DMA_EEI_EEI17_MASK (0x20000U)
7262#define DMA_EEI_EEI17_SHIFT (17U)
7267#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
7268#define DMA_EEI_EEI18_MASK (0x40000U)
7269#define DMA_EEI_EEI18_SHIFT (18U)
7274#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
7275#define DMA_EEI_EEI19_MASK (0x80000U)
7276#define DMA_EEI_EEI19_SHIFT (19U)
7281#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
7282#define DMA_EEI_EEI20_MASK (0x100000U)
7283#define DMA_EEI_EEI20_SHIFT (20U)
7288#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
7289#define DMA_EEI_EEI21_MASK (0x200000U)
7290#define DMA_EEI_EEI21_SHIFT (21U)
7295#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
7296#define DMA_EEI_EEI22_MASK (0x400000U)
7297#define DMA_EEI_EEI22_SHIFT (22U)
7302#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
7303#define DMA_EEI_EEI23_MASK (0x800000U)
7304#define DMA_EEI_EEI23_SHIFT (23U)
7309#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
7310#define DMA_EEI_EEI24_MASK (0x1000000U)
7311#define DMA_EEI_EEI24_SHIFT (24U)
7316#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
7317#define DMA_EEI_EEI25_MASK (0x2000000U)
7318#define DMA_EEI_EEI25_SHIFT (25U)
7323#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
7324#define DMA_EEI_EEI26_MASK (0x4000000U)
7325#define DMA_EEI_EEI26_SHIFT (26U)
7330#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
7331#define DMA_EEI_EEI27_MASK (0x8000000U)
7332#define DMA_EEI_EEI27_SHIFT (27U)
7337#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
7338#define DMA_EEI_EEI28_MASK (0x10000000U)
7339#define DMA_EEI_EEI28_SHIFT (28U)
7344#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
7345#define DMA_EEI_EEI29_MASK (0x20000000U)
7346#define DMA_EEI_EEI29_SHIFT (29U)
7351#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
7352#define DMA_EEI_EEI30_MASK (0x40000000U)
7353#define DMA_EEI_EEI30_SHIFT (30U)
7358#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
7359#define DMA_EEI_EEI31_MASK (0x80000000U)
7360#define DMA_EEI_EEI31_SHIFT (31U)
7365#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
7370#define DMA_CEEI_CEEI_MASK (0x1FU)
7371#define DMA_CEEI_CEEI_SHIFT (0U)
7372#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
7373#define DMA_CEEI_CAEE_MASK (0x40U)
7374#define DMA_CEEI_CAEE_SHIFT (6U)
7379#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
7380#define DMA_CEEI_NOP_MASK (0x80U)
7381#define DMA_CEEI_NOP_SHIFT (7U)
7386#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
7391#define DMA_SEEI_SEEI_MASK (0x1FU)
7392#define DMA_SEEI_SEEI_SHIFT (0U)
7393#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
7394#define DMA_SEEI_SAEE_MASK (0x40U)
7395#define DMA_SEEI_SAEE_SHIFT (6U)
7400#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
7401#define DMA_SEEI_NOP_MASK (0x80U)
7402#define DMA_SEEI_NOP_SHIFT (7U)
7407#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
7412#define DMA_CERQ_CERQ_MASK (0x1FU)
7413#define DMA_CERQ_CERQ_SHIFT (0U)
7414#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
7415#define DMA_CERQ_CAER_MASK (0x40U)
7416#define DMA_CERQ_CAER_SHIFT (6U)
7421#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
7422#define DMA_CERQ_NOP_MASK (0x80U)
7423#define DMA_CERQ_NOP_SHIFT (7U)
7428#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
7433#define DMA_SERQ_SERQ_MASK (0x1FU)
7434#define DMA_SERQ_SERQ_SHIFT (0U)
7435#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
7436#define DMA_SERQ_SAER_MASK (0x40U)
7437#define DMA_SERQ_SAER_SHIFT (6U)
7442#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
7443#define DMA_SERQ_NOP_MASK (0x80U)
7444#define DMA_SERQ_NOP_SHIFT (7U)
7449#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
7454#define DMA_CDNE_CDNE_MASK (0x1FU)
7455#define DMA_CDNE_CDNE_SHIFT (0U)
7456#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
7457#define DMA_CDNE_CADN_MASK (0x40U)
7458#define DMA_CDNE_CADN_SHIFT (6U)
7463#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
7464#define DMA_CDNE_NOP_MASK (0x80U)
7465#define DMA_CDNE_NOP_SHIFT (7U)
7470#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
7475#define DMA_SSRT_SSRT_MASK (0x1FU)
7476#define DMA_SSRT_SSRT_SHIFT (0U)
7477#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
7478#define DMA_SSRT_SAST_MASK (0x40U)
7479#define DMA_SSRT_SAST_SHIFT (6U)
7484#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
7485#define DMA_SSRT_NOP_MASK (0x80U)
7486#define DMA_SSRT_NOP_SHIFT (7U)
7491#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
7496#define DMA_CERR_CERR_MASK (0x1FU)
7497#define DMA_CERR_CERR_SHIFT (0U)
7498#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
7499#define DMA_CERR_CAEI_MASK (0x40U)
7500#define DMA_CERR_CAEI_SHIFT (6U)
7505#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
7506#define DMA_CERR_NOP_MASK (0x80U)
7507#define DMA_CERR_NOP_SHIFT (7U)
7512#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
7517#define DMA_CINT_CINT_MASK (0x1FU)
7518#define DMA_CINT_CINT_SHIFT (0U)
7519#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
7520#define DMA_CINT_CAIR_MASK (0x40U)
7521#define DMA_CINT_CAIR_SHIFT (6U)
7526#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
7527#define DMA_CINT_NOP_MASK (0x80U)
7528#define DMA_CINT_NOP_SHIFT (7U)
7533#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
7538#define DMA_INT_INT0_MASK (0x1U)
7539#define DMA_INT_INT0_SHIFT (0U)
7544#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
7545#define DMA_INT_INT1_MASK (0x2U)
7546#define DMA_INT_INT1_SHIFT (1U)
7551#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
7552#define DMA_INT_INT2_MASK (0x4U)
7553#define DMA_INT_INT2_SHIFT (2U)
7558#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
7559#define DMA_INT_INT3_MASK (0x8U)
7560#define DMA_INT_INT3_SHIFT (3U)
7565#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
7566#define DMA_INT_INT4_MASK (0x10U)
7567#define DMA_INT_INT4_SHIFT (4U)
7572#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
7573#define DMA_INT_INT5_MASK (0x20U)
7574#define DMA_INT_INT5_SHIFT (5U)
7579#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
7580#define DMA_INT_INT6_MASK (0x40U)
7581#define DMA_INT_INT6_SHIFT (6U)
7586#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
7587#define DMA_INT_INT7_MASK (0x80U)
7588#define DMA_INT_INT7_SHIFT (7U)
7593#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
7594#define DMA_INT_INT8_MASK (0x100U)
7595#define DMA_INT_INT8_SHIFT (8U)
7600#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
7601#define DMA_INT_INT9_MASK (0x200U)
7602#define DMA_INT_INT9_SHIFT (9U)
7607#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
7608#define DMA_INT_INT10_MASK (0x400U)
7609#define DMA_INT_INT10_SHIFT (10U)
7614#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
7615#define DMA_INT_INT11_MASK (0x800U)
7616#define DMA_INT_INT11_SHIFT (11U)
7621#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
7622#define DMA_INT_INT12_MASK (0x1000U)
7623#define DMA_INT_INT12_SHIFT (12U)
7628#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
7629#define DMA_INT_INT13_MASK (0x2000U)
7630#define DMA_INT_INT13_SHIFT (13U)
7635#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
7636#define DMA_INT_INT14_MASK (0x4000U)
7637#define DMA_INT_INT14_SHIFT (14U)
7642#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
7643#define DMA_INT_INT15_MASK (0x8000U)
7644#define DMA_INT_INT15_SHIFT (15U)
7649#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
7650#define DMA_INT_INT16_MASK (0x10000U)
7651#define DMA_INT_INT16_SHIFT (16U)
7656#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
7657#define DMA_INT_INT17_MASK (0x20000U)
7658#define DMA_INT_INT17_SHIFT (17U)
7663#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
7664#define DMA_INT_INT18_MASK (0x40000U)
7665#define DMA_INT_INT18_SHIFT (18U)
7670#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
7671#define DMA_INT_INT19_MASK (0x80000U)
7672#define DMA_INT_INT19_SHIFT (19U)
7677#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
7678#define DMA_INT_INT20_MASK (0x100000U)
7679#define DMA_INT_INT20_SHIFT (20U)
7684#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
7685#define DMA_INT_INT21_MASK (0x200000U)
7686#define DMA_INT_INT21_SHIFT (21U)
7691#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
7692#define DMA_INT_INT22_MASK (0x400000U)
7693#define DMA_INT_INT22_SHIFT (22U)
7698#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
7699#define DMA_INT_INT23_MASK (0x800000U)
7700#define DMA_INT_INT23_SHIFT (23U)
7705#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
7706#define DMA_INT_INT24_MASK (0x1000000U)
7707#define DMA_INT_INT24_SHIFT (24U)
7712#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
7713#define DMA_INT_INT25_MASK (0x2000000U)
7714#define DMA_INT_INT25_SHIFT (25U)
7719#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
7720#define DMA_INT_INT26_MASK (0x4000000U)
7721#define DMA_INT_INT26_SHIFT (26U)
7726#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
7727#define DMA_INT_INT27_MASK (0x8000000U)
7728#define DMA_INT_INT27_SHIFT (27U)
7733#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
7734#define DMA_INT_INT28_MASK (0x10000000U)
7735#define DMA_INT_INT28_SHIFT (28U)
7740#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
7741#define DMA_INT_INT29_MASK (0x20000000U)
7742#define DMA_INT_INT29_SHIFT (29U)
7747#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
7748#define DMA_INT_INT30_MASK (0x40000000U)
7749#define DMA_INT_INT30_SHIFT (30U)
7754#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
7755#define DMA_INT_INT31_MASK (0x80000000U)
7756#define DMA_INT_INT31_SHIFT (31U)
7761#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
7766#define DMA_ERR_ERR0_MASK (0x1U)
7767#define DMA_ERR_ERR0_SHIFT (0U)
7772#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
7773#define DMA_ERR_ERR1_MASK (0x2U)
7774#define DMA_ERR_ERR1_SHIFT (1U)
7779#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
7780#define DMA_ERR_ERR2_MASK (0x4U)
7781#define DMA_ERR_ERR2_SHIFT (2U)
7786#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
7787#define DMA_ERR_ERR3_MASK (0x8U)
7788#define DMA_ERR_ERR3_SHIFT (3U)
7793#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
7794#define DMA_ERR_ERR4_MASK (0x10U)
7795#define DMA_ERR_ERR4_SHIFT (4U)
7800#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
7801#define DMA_ERR_ERR5_MASK (0x20U)
7802#define DMA_ERR_ERR5_SHIFT (5U)
7807#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
7808#define DMA_ERR_ERR6_MASK (0x40U)
7809#define DMA_ERR_ERR6_SHIFT (6U)
7814#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
7815#define DMA_ERR_ERR7_MASK (0x80U)
7816#define DMA_ERR_ERR7_SHIFT (7U)
7821#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
7822#define DMA_ERR_ERR8_MASK (0x100U)
7823#define DMA_ERR_ERR8_SHIFT (8U)
7828#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
7829#define DMA_ERR_ERR9_MASK (0x200U)
7830#define DMA_ERR_ERR9_SHIFT (9U)
7835#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
7836#define DMA_ERR_ERR10_MASK (0x400U)
7837#define DMA_ERR_ERR10_SHIFT (10U)
7842#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
7843#define DMA_ERR_ERR11_MASK (0x800U)
7844#define DMA_ERR_ERR11_SHIFT (11U)
7849#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
7850#define DMA_ERR_ERR12_MASK (0x1000U)
7851#define DMA_ERR_ERR12_SHIFT (12U)
7856#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
7857#define DMA_ERR_ERR13_MASK (0x2000U)
7858#define DMA_ERR_ERR13_SHIFT (13U)
7863#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
7864#define DMA_ERR_ERR14_MASK (0x4000U)
7865#define DMA_ERR_ERR14_SHIFT (14U)
7870#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
7871#define DMA_ERR_ERR15_MASK (0x8000U)
7872#define DMA_ERR_ERR15_SHIFT (15U)
7877#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
7878#define DMA_ERR_ERR16_MASK (0x10000U)
7879#define DMA_ERR_ERR16_SHIFT (16U)
7884#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
7885#define DMA_ERR_ERR17_MASK (0x20000U)
7886#define DMA_ERR_ERR17_SHIFT (17U)
7891#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
7892#define DMA_ERR_ERR18_MASK (0x40000U)
7893#define DMA_ERR_ERR18_SHIFT (18U)
7898#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
7899#define DMA_ERR_ERR19_MASK (0x80000U)
7900#define DMA_ERR_ERR19_SHIFT (19U)
7905#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
7906#define DMA_ERR_ERR20_MASK (0x100000U)
7907#define DMA_ERR_ERR20_SHIFT (20U)
7912#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
7913#define DMA_ERR_ERR21_MASK (0x200000U)
7914#define DMA_ERR_ERR21_SHIFT (21U)
7919#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
7920#define DMA_ERR_ERR22_MASK (0x400000U)
7921#define DMA_ERR_ERR22_SHIFT (22U)
7926#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
7927#define DMA_ERR_ERR23_MASK (0x800000U)
7928#define DMA_ERR_ERR23_SHIFT (23U)
7933#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
7934#define DMA_ERR_ERR24_MASK (0x1000000U)
7935#define DMA_ERR_ERR24_SHIFT (24U)
7940#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
7941#define DMA_ERR_ERR25_MASK (0x2000000U)
7942#define DMA_ERR_ERR25_SHIFT (25U)
7947#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
7948#define DMA_ERR_ERR26_MASK (0x4000000U)
7949#define DMA_ERR_ERR26_SHIFT (26U)
7954#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
7955#define DMA_ERR_ERR27_MASK (0x8000000U)
7956#define DMA_ERR_ERR27_SHIFT (27U)
7961#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
7962#define DMA_ERR_ERR28_MASK (0x10000000U)
7963#define DMA_ERR_ERR28_SHIFT (28U)
7968#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
7969#define DMA_ERR_ERR29_MASK (0x20000000U)
7970#define DMA_ERR_ERR29_SHIFT (29U)
7975#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
7976#define DMA_ERR_ERR30_MASK (0x40000000U)
7977#define DMA_ERR_ERR30_SHIFT (30U)
7982#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
7983#define DMA_ERR_ERR31_MASK (0x80000000U)
7984#define DMA_ERR_ERR31_SHIFT (31U)
7989#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
7994#define DMA_HRS_HRS0_MASK (0x1U)
7995#define DMA_HRS_HRS0_SHIFT (0U)
8000#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
8001#define DMA_HRS_HRS1_MASK (0x2U)
8002#define DMA_HRS_HRS1_SHIFT (1U)
8007#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
8008#define DMA_HRS_HRS2_MASK (0x4U)
8009#define DMA_HRS_HRS2_SHIFT (2U)
8014#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
8015#define DMA_HRS_HRS3_MASK (0x8U)
8016#define DMA_HRS_HRS3_SHIFT (3U)
8021#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
8022#define DMA_HRS_HRS4_MASK (0x10U)
8023#define DMA_HRS_HRS4_SHIFT (4U)
8028#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
8029#define DMA_HRS_HRS5_MASK (0x20U)
8030#define DMA_HRS_HRS5_SHIFT (5U)
8035#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
8036#define DMA_HRS_HRS6_MASK (0x40U)
8037#define DMA_HRS_HRS6_SHIFT (6U)
8042#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
8043#define DMA_HRS_HRS7_MASK (0x80U)
8044#define DMA_HRS_HRS7_SHIFT (7U)
8049#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
8050#define DMA_HRS_HRS8_MASK (0x100U)
8051#define DMA_HRS_HRS8_SHIFT (8U)
8056#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
8057#define DMA_HRS_HRS9_MASK (0x200U)
8058#define DMA_HRS_HRS9_SHIFT (9U)
8063#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
8064#define DMA_HRS_HRS10_MASK (0x400U)
8065#define DMA_HRS_HRS10_SHIFT (10U)
8070#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
8071#define DMA_HRS_HRS11_MASK (0x800U)
8072#define DMA_HRS_HRS11_SHIFT (11U)
8077#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
8078#define DMA_HRS_HRS12_MASK (0x1000U)
8079#define DMA_HRS_HRS12_SHIFT (12U)
8084#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
8085#define DMA_HRS_HRS13_MASK (0x2000U)
8086#define DMA_HRS_HRS13_SHIFT (13U)
8091#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
8092#define DMA_HRS_HRS14_MASK (0x4000U)
8093#define DMA_HRS_HRS14_SHIFT (14U)
8098#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
8099#define DMA_HRS_HRS15_MASK (0x8000U)
8100#define DMA_HRS_HRS15_SHIFT (15U)
8105#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
8106#define DMA_HRS_HRS16_MASK (0x10000U)
8107#define DMA_HRS_HRS16_SHIFT (16U)
8112#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
8113#define DMA_HRS_HRS17_MASK (0x20000U)
8114#define DMA_HRS_HRS17_SHIFT (17U)
8119#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
8120#define DMA_HRS_HRS18_MASK (0x40000U)
8121#define DMA_HRS_HRS18_SHIFT (18U)
8126#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
8127#define DMA_HRS_HRS19_MASK (0x80000U)
8128#define DMA_HRS_HRS19_SHIFT (19U)
8133#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
8134#define DMA_HRS_HRS20_MASK (0x100000U)
8135#define DMA_HRS_HRS20_SHIFT (20U)
8140#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
8141#define DMA_HRS_HRS21_MASK (0x200000U)
8142#define DMA_HRS_HRS21_SHIFT (21U)
8147#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
8148#define DMA_HRS_HRS22_MASK (0x400000U)
8149#define DMA_HRS_HRS22_SHIFT (22U)
8154#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
8155#define DMA_HRS_HRS23_MASK (0x800000U)
8156#define DMA_HRS_HRS23_SHIFT (23U)
8161#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
8162#define DMA_HRS_HRS24_MASK (0x1000000U)
8163#define DMA_HRS_HRS24_SHIFT (24U)
8168#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
8169#define DMA_HRS_HRS25_MASK (0x2000000U)
8170#define DMA_HRS_HRS25_SHIFT (25U)
8175#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
8176#define DMA_HRS_HRS26_MASK (0x4000000U)
8177#define DMA_HRS_HRS26_SHIFT (26U)
8182#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
8183#define DMA_HRS_HRS27_MASK (0x8000000U)
8184#define DMA_HRS_HRS27_SHIFT (27U)
8189#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
8190#define DMA_HRS_HRS28_MASK (0x10000000U)
8191#define DMA_HRS_HRS28_SHIFT (28U)
8196#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
8197#define DMA_HRS_HRS29_MASK (0x20000000U)
8198#define DMA_HRS_HRS29_SHIFT (29U)
8203#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
8204#define DMA_HRS_HRS30_MASK (0x40000000U)
8205#define DMA_HRS_HRS30_SHIFT (30U)
8210#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
8211#define DMA_HRS_HRS31_MASK (0x80000000U)
8212#define DMA_HRS_HRS31_SHIFT (31U)
8217#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
8222#define DMA_EARS_EDREQ_0_MASK (0x1U)
8223#define DMA_EARS_EDREQ_0_SHIFT (0U)
8228#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
8229#define DMA_EARS_EDREQ_1_MASK (0x2U)
8230#define DMA_EARS_EDREQ_1_SHIFT (1U)
8235#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
8236#define DMA_EARS_EDREQ_2_MASK (0x4U)
8237#define DMA_EARS_EDREQ_2_SHIFT (2U)
8242#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
8243#define DMA_EARS_EDREQ_3_MASK (0x8U)
8244#define DMA_EARS_EDREQ_3_SHIFT (3U)
8249#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
8250#define DMA_EARS_EDREQ_4_MASK (0x10U)
8251#define DMA_EARS_EDREQ_4_SHIFT (4U)
8256#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
8257#define DMA_EARS_EDREQ_5_MASK (0x20U)
8258#define DMA_EARS_EDREQ_5_SHIFT (5U)
8263#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
8264#define DMA_EARS_EDREQ_6_MASK (0x40U)
8265#define DMA_EARS_EDREQ_6_SHIFT (6U)
8270#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
8271#define DMA_EARS_EDREQ_7_MASK (0x80U)
8272#define DMA_EARS_EDREQ_7_SHIFT (7U)
8277#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
8278#define DMA_EARS_EDREQ_8_MASK (0x100U)
8279#define DMA_EARS_EDREQ_8_SHIFT (8U)
8284#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
8285#define DMA_EARS_EDREQ_9_MASK (0x200U)
8286#define DMA_EARS_EDREQ_9_SHIFT (9U)
8291#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
8292#define DMA_EARS_EDREQ_10_MASK (0x400U)
8293#define DMA_EARS_EDREQ_10_SHIFT (10U)
8298#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
8299#define DMA_EARS_EDREQ_11_MASK (0x800U)
8300#define DMA_EARS_EDREQ_11_SHIFT (11U)
8305#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
8306#define DMA_EARS_EDREQ_12_MASK (0x1000U)
8307#define DMA_EARS_EDREQ_12_SHIFT (12U)
8312#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
8313#define DMA_EARS_EDREQ_13_MASK (0x2000U)
8314#define DMA_EARS_EDREQ_13_SHIFT (13U)
8319#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
8320#define DMA_EARS_EDREQ_14_MASK (0x4000U)
8321#define DMA_EARS_EDREQ_14_SHIFT (14U)
8326#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
8327#define DMA_EARS_EDREQ_15_MASK (0x8000U)
8328#define DMA_EARS_EDREQ_15_SHIFT (15U)
8333#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
8334#define DMA_EARS_EDREQ_16_MASK (0x10000U)
8335#define DMA_EARS_EDREQ_16_SHIFT (16U)
8340#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
8341#define DMA_EARS_EDREQ_17_MASK (0x20000U)
8342#define DMA_EARS_EDREQ_17_SHIFT (17U)
8347#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
8348#define DMA_EARS_EDREQ_18_MASK (0x40000U)
8349#define DMA_EARS_EDREQ_18_SHIFT (18U)
8354#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
8355#define DMA_EARS_EDREQ_19_MASK (0x80000U)
8356#define DMA_EARS_EDREQ_19_SHIFT (19U)
8361#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
8362#define DMA_EARS_EDREQ_20_MASK (0x100000U)
8363#define DMA_EARS_EDREQ_20_SHIFT (20U)
8368#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
8369#define DMA_EARS_EDREQ_21_MASK (0x200000U)
8370#define DMA_EARS_EDREQ_21_SHIFT (21U)
8375#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
8376#define DMA_EARS_EDREQ_22_MASK (0x400000U)
8377#define DMA_EARS_EDREQ_22_SHIFT (22U)
8382#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
8383#define DMA_EARS_EDREQ_23_MASK (0x800000U)
8384#define DMA_EARS_EDREQ_23_SHIFT (23U)
8389#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
8390#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
8391#define DMA_EARS_EDREQ_24_SHIFT (24U)
8396#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
8397#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
8398#define DMA_EARS_EDREQ_25_SHIFT (25U)
8403#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
8404#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
8405#define DMA_EARS_EDREQ_26_SHIFT (26U)
8410#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
8411#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
8412#define DMA_EARS_EDREQ_27_SHIFT (27U)
8417#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
8418#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
8419#define DMA_EARS_EDREQ_28_SHIFT (28U)
8424#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
8425#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
8426#define DMA_EARS_EDREQ_29_SHIFT (29U)
8431#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
8432#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
8433#define DMA_EARS_EDREQ_30_SHIFT (30U)
8438#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
8439#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
8440#define DMA_EARS_EDREQ_31_SHIFT (31U)
8445#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
8450#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
8451#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
8452#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
8453#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
8454#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
8455#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
8456#define DMA_DCHPRI3_DPA_MASK (0x40U)
8457#define DMA_DCHPRI3_DPA_SHIFT (6U)
8462#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
8463#define DMA_DCHPRI3_ECP_MASK (0x80U)
8464#define DMA_DCHPRI3_ECP_SHIFT (7U)
8469#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
8474#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
8475#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
8476#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
8477#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
8478#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
8479#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
8480#define DMA_DCHPRI2_DPA_MASK (0x40U)
8481#define DMA_DCHPRI2_DPA_SHIFT (6U)
8486#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
8487#define DMA_DCHPRI2_ECP_MASK (0x80U)
8488#define DMA_DCHPRI2_ECP_SHIFT (7U)
8493#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
8498#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
8499#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
8500#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
8501#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
8502#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
8503#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
8504#define DMA_DCHPRI1_DPA_MASK (0x40U)
8505#define DMA_DCHPRI1_DPA_SHIFT (6U)
8510#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
8511#define DMA_DCHPRI1_ECP_MASK (0x80U)
8512#define DMA_DCHPRI1_ECP_SHIFT (7U)
8517#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
8522#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
8523#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
8524#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
8525#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
8526#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
8527#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
8528#define DMA_DCHPRI0_DPA_MASK (0x40U)
8529#define DMA_DCHPRI0_DPA_SHIFT (6U)
8534#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
8535#define DMA_DCHPRI0_ECP_MASK (0x80U)
8536#define DMA_DCHPRI0_ECP_SHIFT (7U)
8541#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
8546#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
8547#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
8548#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
8549#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
8550#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
8551#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
8552#define DMA_DCHPRI7_DPA_MASK (0x40U)
8553#define DMA_DCHPRI7_DPA_SHIFT (6U)
8558#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
8559#define DMA_DCHPRI7_ECP_MASK (0x80U)
8560#define DMA_DCHPRI7_ECP_SHIFT (7U)
8565#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
8570#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
8571#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
8572#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
8573#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
8574#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
8575#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
8576#define DMA_DCHPRI6_DPA_MASK (0x40U)
8577#define DMA_DCHPRI6_DPA_SHIFT (6U)
8582#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
8583#define DMA_DCHPRI6_ECP_MASK (0x80U)
8584#define DMA_DCHPRI6_ECP_SHIFT (7U)
8589#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
8594#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
8595#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
8596#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
8597#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
8598#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
8599#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
8600#define DMA_DCHPRI5_DPA_MASK (0x40U)
8601#define DMA_DCHPRI5_DPA_SHIFT (6U)
8606#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
8607#define DMA_DCHPRI5_ECP_MASK (0x80U)
8608#define DMA_DCHPRI5_ECP_SHIFT (7U)
8613#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
8618#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
8619#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
8620#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
8621#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
8622#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
8623#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
8624#define DMA_DCHPRI4_DPA_MASK (0x40U)
8625#define DMA_DCHPRI4_DPA_SHIFT (6U)
8630#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
8631#define DMA_DCHPRI4_ECP_MASK (0x80U)
8632#define DMA_DCHPRI4_ECP_SHIFT (7U)
8637#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
8642#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
8643#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
8644#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
8645#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
8646#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
8647#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
8648#define DMA_DCHPRI11_DPA_MASK (0x40U)
8649#define DMA_DCHPRI11_DPA_SHIFT (6U)
8654#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
8655#define DMA_DCHPRI11_ECP_MASK (0x80U)
8656#define DMA_DCHPRI11_ECP_SHIFT (7U)
8661#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
8666#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
8667#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
8668#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
8669#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
8670#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
8671#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
8672#define DMA_DCHPRI10_DPA_MASK (0x40U)
8673#define DMA_DCHPRI10_DPA_SHIFT (6U)
8678#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
8679#define DMA_DCHPRI10_ECP_MASK (0x80U)
8680#define DMA_DCHPRI10_ECP_SHIFT (7U)
8685#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
8690#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
8691#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
8692#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
8693#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
8694#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
8695#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
8696#define DMA_DCHPRI9_DPA_MASK (0x40U)
8697#define DMA_DCHPRI9_DPA_SHIFT (6U)
8702#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
8703#define DMA_DCHPRI9_ECP_MASK (0x80U)
8704#define DMA_DCHPRI9_ECP_SHIFT (7U)
8709#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
8714#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
8715#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
8716#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
8717#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
8718#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
8719#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
8720#define DMA_DCHPRI8_DPA_MASK (0x40U)
8721#define DMA_DCHPRI8_DPA_SHIFT (6U)
8726#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
8727#define DMA_DCHPRI8_ECP_MASK (0x80U)
8728#define DMA_DCHPRI8_ECP_SHIFT (7U)
8733#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
8738#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
8739#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
8740#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
8741#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
8742#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
8743#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
8744#define DMA_DCHPRI15_DPA_MASK (0x40U)
8745#define DMA_DCHPRI15_DPA_SHIFT (6U)
8750#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
8751#define DMA_DCHPRI15_ECP_MASK (0x80U)
8752#define DMA_DCHPRI15_ECP_SHIFT (7U)
8757#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
8762#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
8763#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
8764#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
8765#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
8766#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
8767#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
8768#define DMA_DCHPRI14_DPA_MASK (0x40U)
8769#define DMA_DCHPRI14_DPA_SHIFT (6U)
8774#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
8775#define DMA_DCHPRI14_ECP_MASK (0x80U)
8776#define DMA_DCHPRI14_ECP_SHIFT (7U)
8781#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
8786#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
8787#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
8788#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
8789#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
8790#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
8791#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
8792#define DMA_DCHPRI13_DPA_MASK (0x40U)
8793#define DMA_DCHPRI13_DPA_SHIFT (6U)
8798#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
8799#define DMA_DCHPRI13_ECP_MASK (0x80U)
8800#define DMA_DCHPRI13_ECP_SHIFT (7U)
8805#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
8810#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
8811#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
8812#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
8813#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
8814#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
8815#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
8816#define DMA_DCHPRI12_DPA_MASK (0x40U)
8817#define DMA_DCHPRI12_DPA_SHIFT (6U)
8822#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
8823#define DMA_DCHPRI12_ECP_MASK (0x80U)
8824#define DMA_DCHPRI12_ECP_SHIFT (7U)
8829#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
8834#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
8835#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
8836#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
8837#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
8838#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
8839#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
8840#define DMA_DCHPRI19_DPA_MASK (0x40U)
8841#define DMA_DCHPRI19_DPA_SHIFT (6U)
8846#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
8847#define DMA_DCHPRI19_ECP_MASK (0x80U)
8848#define DMA_DCHPRI19_ECP_SHIFT (7U)
8853#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
8858#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
8859#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
8860#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
8861#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
8862#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
8863#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
8864#define DMA_DCHPRI18_DPA_MASK (0x40U)
8865#define DMA_DCHPRI18_DPA_SHIFT (6U)
8870#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
8871#define DMA_DCHPRI18_ECP_MASK (0x80U)
8872#define DMA_DCHPRI18_ECP_SHIFT (7U)
8877#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
8882#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
8883#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
8884#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
8885#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
8886#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
8887#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
8888#define DMA_DCHPRI17_DPA_MASK (0x40U)
8889#define DMA_DCHPRI17_DPA_SHIFT (6U)
8894#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
8895#define DMA_DCHPRI17_ECP_MASK (0x80U)
8896#define DMA_DCHPRI17_ECP_SHIFT (7U)
8901#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
8906#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
8907#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
8908#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
8909#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
8910#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
8911#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
8912#define DMA_DCHPRI16_DPA_MASK (0x40U)
8913#define DMA_DCHPRI16_DPA_SHIFT (6U)
8918#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
8919#define DMA_DCHPRI16_ECP_MASK (0x80U)
8920#define DMA_DCHPRI16_ECP_SHIFT (7U)
8925#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
8930#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
8931#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
8932#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
8933#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
8934#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
8935#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
8936#define DMA_DCHPRI23_DPA_MASK (0x40U)
8937#define DMA_DCHPRI23_DPA_SHIFT (6U)
8942#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
8943#define DMA_DCHPRI23_ECP_MASK (0x80U)
8944#define DMA_DCHPRI23_ECP_SHIFT (7U)
8949#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
8954#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
8955#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
8956#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
8957#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
8958#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
8959#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
8960#define DMA_DCHPRI22_DPA_MASK (0x40U)
8961#define DMA_DCHPRI22_DPA_SHIFT (6U)
8966#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
8967#define DMA_DCHPRI22_ECP_MASK (0x80U)
8968#define DMA_DCHPRI22_ECP_SHIFT (7U)
8973#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
8978#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
8979#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
8980#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
8981#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
8982#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
8983#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
8984#define DMA_DCHPRI21_DPA_MASK (0x40U)
8985#define DMA_DCHPRI21_DPA_SHIFT (6U)
8990#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
8991#define DMA_DCHPRI21_ECP_MASK (0x80U)
8992#define DMA_DCHPRI21_ECP_SHIFT (7U)
8997#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
9002#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
9003#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
9004#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
9005#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
9006#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
9007#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
9008#define DMA_DCHPRI20_DPA_MASK (0x40U)
9009#define DMA_DCHPRI20_DPA_SHIFT (6U)
9014#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
9015#define DMA_DCHPRI20_ECP_MASK (0x80U)
9016#define DMA_DCHPRI20_ECP_SHIFT (7U)
9021#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
9026#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
9027#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
9028#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
9029#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
9030#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
9031#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
9032#define DMA_DCHPRI27_DPA_MASK (0x40U)
9033#define DMA_DCHPRI27_DPA_SHIFT (6U)
9038#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
9039#define DMA_DCHPRI27_ECP_MASK (0x80U)
9040#define DMA_DCHPRI27_ECP_SHIFT (7U)
9045#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
9050#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
9051#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
9052#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
9053#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
9054#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
9055#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
9056#define DMA_DCHPRI26_DPA_MASK (0x40U)
9057#define DMA_DCHPRI26_DPA_SHIFT (6U)
9062#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
9063#define DMA_DCHPRI26_ECP_MASK (0x80U)
9064#define DMA_DCHPRI26_ECP_SHIFT (7U)
9069#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
9074#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
9075#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
9076#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
9077#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
9078#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
9079#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
9080#define DMA_DCHPRI25_DPA_MASK (0x40U)
9081#define DMA_DCHPRI25_DPA_SHIFT (6U)
9086#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
9087#define DMA_DCHPRI25_ECP_MASK (0x80U)
9088#define DMA_DCHPRI25_ECP_SHIFT (7U)
9093#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
9098#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
9099#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
9100#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
9101#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
9102#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
9103#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
9104#define DMA_DCHPRI24_DPA_MASK (0x40U)
9105#define DMA_DCHPRI24_DPA_SHIFT (6U)
9110#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
9111#define DMA_DCHPRI24_ECP_MASK (0x80U)
9112#define DMA_DCHPRI24_ECP_SHIFT (7U)
9117#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
9122#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
9123#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
9124#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
9125#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
9126#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
9127#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
9128#define DMA_DCHPRI31_DPA_MASK (0x40U)
9129#define DMA_DCHPRI31_DPA_SHIFT (6U)
9134#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
9135#define DMA_DCHPRI31_ECP_MASK (0x80U)
9136#define DMA_DCHPRI31_ECP_SHIFT (7U)
9141#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
9146#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
9147#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
9148#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
9149#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
9150#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
9151#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
9152#define DMA_DCHPRI30_DPA_MASK (0x40U)
9153#define DMA_DCHPRI30_DPA_SHIFT (6U)
9158#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
9159#define DMA_DCHPRI30_ECP_MASK (0x80U)
9160#define DMA_DCHPRI30_ECP_SHIFT (7U)
9165#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
9170#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
9171#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
9172#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
9173#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
9174#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
9175#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
9176#define DMA_DCHPRI29_DPA_MASK (0x40U)
9177#define DMA_DCHPRI29_DPA_SHIFT (6U)
9182#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
9183#define DMA_DCHPRI29_ECP_MASK (0x80U)
9184#define DMA_DCHPRI29_ECP_SHIFT (7U)
9189#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
9194#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
9195#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
9196#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
9197#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
9198#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
9199#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
9200#define DMA_DCHPRI28_DPA_MASK (0x40U)
9201#define DMA_DCHPRI28_DPA_SHIFT (6U)
9206#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
9207#define DMA_DCHPRI28_ECP_MASK (0x80U)
9208#define DMA_DCHPRI28_ECP_SHIFT (7U)
9213#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
9218#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
9219#define DMA_SADDR_SADDR_SHIFT (0U)
9220#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
9223/* The count of DMA_SADDR */
9224#define DMA_SADDR_COUNT (32U)
9225
9228#define DMA_SOFF_SOFF_MASK (0xFFFFU)
9229#define DMA_SOFF_SOFF_SHIFT (0U)
9230#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
9233/* The count of DMA_SOFF */
9234#define DMA_SOFF_COUNT (32U)
9235
9238#define DMA_ATTR_DSIZE_MASK (0x7U)
9239#define DMA_ATTR_DSIZE_SHIFT (0U)
9240#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
9241#define DMA_ATTR_DMOD_MASK (0xF8U)
9242#define DMA_ATTR_DMOD_SHIFT (3U)
9243#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
9244#define DMA_ATTR_SSIZE_MASK (0x700U)
9245#define DMA_ATTR_SSIZE_SHIFT (8U)
9256#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
9257#define DMA_ATTR_SMOD_MASK (0xF800U)
9258#define DMA_ATTR_SMOD_SHIFT (11U)
9262#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
9265/* The count of DMA_ATTR */
9266#define DMA_ATTR_COUNT (32U)
9267
9270#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
9271#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
9272#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
9275/* The count of DMA_NBYTES_MLNO */
9276#define DMA_NBYTES_MLNO_COUNT (32U)
9277
9280#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
9281#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
9282#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
9283#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
9284#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
9289#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
9290#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
9291#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
9296#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
9299/* The count of DMA_NBYTES_MLOFFNO */
9300#define DMA_NBYTES_MLOFFNO_COUNT (32U)
9301
9304#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
9305#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
9306#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
9307#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
9308#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
9309#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
9310#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
9311#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
9316#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
9317#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
9318#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
9323#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
9326/* The count of DMA_NBYTES_MLOFFYES */
9327#define DMA_NBYTES_MLOFFYES_COUNT (32U)
9328
9331#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
9332#define DMA_SLAST_SLAST_SHIFT (0U)
9333#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
9336/* The count of DMA_SLAST */
9337#define DMA_SLAST_COUNT (32U)
9338
9341#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
9342#define DMA_DADDR_DADDR_SHIFT (0U)
9343#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
9346/* The count of DMA_DADDR */
9347#define DMA_DADDR_COUNT (32U)
9348
9351#define DMA_DOFF_DOFF_MASK (0xFFFFU)
9352#define DMA_DOFF_DOFF_SHIFT (0U)
9353#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
9356/* The count of DMA_DOFF */
9357#define DMA_DOFF_COUNT (32U)
9358
9361#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
9362#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
9363#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
9364#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
9365#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
9370#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
9373/* The count of DMA_CITER_ELINKNO */
9374#define DMA_CITER_ELINKNO_COUNT (32U)
9375
9378#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
9379#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
9380#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
9381#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
9382#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
9383#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
9384#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
9385#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
9390#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
9393/* The count of DMA_CITER_ELINKYES */
9394#define DMA_CITER_ELINKYES_COUNT (32U)
9395
9398#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
9399#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
9400#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
9403/* The count of DMA_DLAST_SGA */
9404#define DMA_DLAST_SGA_COUNT (32U)
9405
9408#define DMA_CSR_START_MASK (0x1U)
9409#define DMA_CSR_START_SHIFT (0U)
9414#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
9415#define DMA_CSR_INTMAJOR_MASK (0x2U)
9416#define DMA_CSR_INTMAJOR_SHIFT (1U)
9421#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
9422#define DMA_CSR_INTHALF_MASK (0x4U)
9423#define DMA_CSR_INTHALF_SHIFT (2U)
9428#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
9429#define DMA_CSR_DREQ_MASK (0x8U)
9430#define DMA_CSR_DREQ_SHIFT (3U)
9435#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
9436#define DMA_CSR_ESG_MASK (0x10U)
9437#define DMA_CSR_ESG_SHIFT (4U)
9442#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
9443#define DMA_CSR_MAJORELINK_MASK (0x20U)
9444#define DMA_CSR_MAJORELINK_SHIFT (5U)
9449#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
9450#define DMA_CSR_ACTIVE_MASK (0x40U)
9451#define DMA_CSR_ACTIVE_SHIFT (6U)
9452#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
9453#define DMA_CSR_DONE_MASK (0x80U)
9454#define DMA_CSR_DONE_SHIFT (7U)
9455#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
9456#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
9457#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
9458#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
9459#define DMA_CSR_BWC_MASK (0xC000U)
9460#define DMA_CSR_BWC_SHIFT (14U)
9467#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
9470/* The count of DMA_CSR */
9471#define DMA_CSR_COUNT (32U)
9472
9475#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
9476#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
9477#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
9478#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
9479#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
9484#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
9487/* The count of DMA_BITER_ELINKNO */
9488#define DMA_BITER_ELINKNO_COUNT (32U)
9489
9492#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
9493#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
9494#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
9495#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
9496#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
9497#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
9498#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
9499#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
9504#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
9507/* The count of DMA_BITER_ELINKYES */
9508#define DMA_BITER_ELINKYES_COUNT (32U)
9509
9510
9513 /* end of group DMA_Register_Masks */
9514
9515
9516/* DMA - Peripheral instance base addresses */
9518#define DMA_BASE (0x40008000u)
9520#define DMA0 ((DMA_Type *)DMA_BASE)
9522#define DMA_BASE_ADDRS { DMA_BASE }
9524#define DMA_BASE_PTRS { DMA0 }
9526#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
9527#define DMA_ERROR_IRQS { DMA_Error_IRQn }
9528
9531 /* end of group DMA_Peripheral_Access_Layer */
9532
9533
9534/* ----------------------------------------------------------------------------
9535 -- DMAMUX Peripheral Access Layer
9536 ---------------------------------------------------------------------------- */
9537
9544typedef struct {
9545 __IO uint8_t CHCFG[32];
9546} DMAMUX_Type;
9547
9548/* ----------------------------------------------------------------------------
9549 -- DMAMUX Register Masks
9550 ---------------------------------------------------------------------------- */
9551
9559#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
9560#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
9621#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
9622#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
9623#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
9628#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
9629#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
9630#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
9635#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
9638/* The count of DMAMUX_CHCFG */
9639#define DMAMUX_CHCFG_COUNT (32U)
9640
9641
9644 /* end of group DMAMUX_Register_Masks */
9645
9646
9647/* DMAMUX - Peripheral instance base addresses */
9649#define DMAMUX_BASE (0x40021000u)
9651#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
9653#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
9655#define DMAMUX_BASE_PTRS { DMAMUX }
9656
9659 /* end of group DMAMUX_Peripheral_Access_Layer */
9660
9661
9662/* ----------------------------------------------------------------------------
9663 -- ENC Peripheral Access Layer
9664 ---------------------------------------------------------------------------- */
9665
9672typedef struct {
9673 __IO uint16_t CTRL;
9674 __IO uint16_t FILT;
9675 __IO uint16_t WTR;
9676 __IO uint16_t POSD;
9677 __I uint16_t POSDH;
9678 __IO uint16_t REV;
9679 __I uint16_t REVH;
9680 __IO uint16_t UPOS;
9681 __IO uint16_t LPOS;
9682 __I uint16_t UPOSH;
9683 __I uint16_t LPOSH;
9684 __IO uint16_t UINIT;
9685 __IO uint16_t LINIT;
9686 __I uint16_t IMR;
9687 __IO uint16_t TST;
9688 __IO uint16_t CTRL2;
9689 __IO uint16_t UMOD;
9690 __IO uint16_t LMOD;
9691 __IO uint16_t UCOMP;
9692 __IO uint16_t LCOMP;
9693} ENC_Type;
9694
9695/* ----------------------------------------------------------------------------
9696 -- ENC Register Masks
9697 ---------------------------------------------------------------------------- */
9698
9706#define ENC_CTRL_CMPIE_MASK (0x1U)
9707#define ENC_CTRL_CMPIE_SHIFT (0U)
9712#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
9713#define ENC_CTRL_CMPIRQ_MASK (0x2U)
9714#define ENC_CTRL_CMPIRQ_SHIFT (1U)
9719#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
9720#define ENC_CTRL_WDE_MASK (0x4U)
9721#define ENC_CTRL_WDE_SHIFT (2U)
9726#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
9727#define ENC_CTRL_DIE_MASK (0x8U)
9728#define ENC_CTRL_DIE_SHIFT (3U)
9733#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
9734#define ENC_CTRL_DIRQ_MASK (0x10U)
9735#define ENC_CTRL_DIRQ_SHIFT (4U)
9740#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
9741#define ENC_CTRL_XNE_MASK (0x20U)
9742#define ENC_CTRL_XNE_SHIFT (5U)
9747#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
9748#define ENC_CTRL_XIP_MASK (0x40U)
9749#define ENC_CTRL_XIP_SHIFT (6U)
9754#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
9755#define ENC_CTRL_XIE_MASK (0x80U)
9756#define ENC_CTRL_XIE_SHIFT (7U)
9761#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
9762#define ENC_CTRL_XIRQ_MASK (0x100U)
9763#define ENC_CTRL_XIRQ_SHIFT (8U)
9768#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
9769#define ENC_CTRL_PH1_MASK (0x200U)
9770#define ENC_CTRL_PH1_SHIFT (9U)
9775#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
9776#define ENC_CTRL_REV_MASK (0x400U)
9777#define ENC_CTRL_REV_SHIFT (10U)
9782#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
9783#define ENC_CTRL_SWIP_MASK (0x800U)
9784#define ENC_CTRL_SWIP_SHIFT (11U)
9789#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
9790#define ENC_CTRL_HNE_MASK (0x1000U)
9791#define ENC_CTRL_HNE_SHIFT (12U)
9796#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
9797#define ENC_CTRL_HIP_MASK (0x2000U)
9798#define ENC_CTRL_HIP_SHIFT (13U)
9803#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
9804#define ENC_CTRL_HIE_MASK (0x4000U)
9805#define ENC_CTRL_HIE_SHIFT (14U)
9810#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
9811#define ENC_CTRL_HIRQ_MASK (0x8000U)
9812#define ENC_CTRL_HIRQ_SHIFT (15U)
9817#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
9822#define ENC_FILT_FILT_PER_MASK (0xFFU)
9823#define ENC_FILT_FILT_PER_SHIFT (0U)
9824#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
9825#define ENC_FILT_FILT_CNT_MASK (0x700U)
9826#define ENC_FILT_FILT_CNT_SHIFT (8U)
9827#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
9832#define ENC_WTR_WDOG_MASK (0xFFFFU)
9833#define ENC_WTR_WDOG_SHIFT (0U)
9834#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
9839#define ENC_POSD_POSD_MASK (0xFFFFU)
9840#define ENC_POSD_POSD_SHIFT (0U)
9841#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
9846#define ENC_POSDH_POSDH_MASK (0xFFFFU)
9847#define ENC_POSDH_POSDH_SHIFT (0U)
9848#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
9853#define ENC_REV_REV_MASK (0xFFFFU)
9854#define ENC_REV_REV_SHIFT (0U)
9855#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
9860#define ENC_REVH_REVH_MASK (0xFFFFU)
9861#define ENC_REVH_REVH_SHIFT (0U)
9862#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
9867#define ENC_UPOS_POS_MASK (0xFFFFU)
9868#define ENC_UPOS_POS_SHIFT (0U)
9869#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
9874#define ENC_LPOS_POS_MASK (0xFFFFU)
9875#define ENC_LPOS_POS_SHIFT (0U)
9876#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
9881#define ENC_UPOSH_POSH_MASK (0xFFFFU)
9882#define ENC_UPOSH_POSH_SHIFT (0U)
9883#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
9888#define ENC_LPOSH_POSH_MASK (0xFFFFU)
9889#define ENC_LPOSH_POSH_SHIFT (0U)
9890#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
9895#define ENC_UINIT_INIT_MASK (0xFFFFU)
9896#define ENC_UINIT_INIT_SHIFT (0U)
9897#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
9902#define ENC_LINIT_INIT_MASK (0xFFFFU)
9903#define ENC_LINIT_INIT_SHIFT (0U)
9904#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
9909#define ENC_IMR_HOME_MASK (0x1U)
9910#define ENC_IMR_HOME_SHIFT (0U)
9911#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
9912#define ENC_IMR_INDEX_MASK (0x2U)
9913#define ENC_IMR_INDEX_SHIFT (1U)
9914#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
9915#define ENC_IMR_PHB_MASK (0x4U)
9916#define ENC_IMR_PHB_SHIFT (2U)
9917#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
9918#define ENC_IMR_PHA_MASK (0x8U)
9919#define ENC_IMR_PHA_SHIFT (3U)
9920#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
9921#define ENC_IMR_FHOM_MASK (0x10U)
9922#define ENC_IMR_FHOM_SHIFT (4U)
9923#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
9924#define ENC_IMR_FIND_MASK (0x20U)
9925#define ENC_IMR_FIND_SHIFT (5U)
9926#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
9927#define ENC_IMR_FPHB_MASK (0x40U)
9928#define ENC_IMR_FPHB_SHIFT (6U)
9929#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
9930#define ENC_IMR_FPHA_MASK (0x80U)
9931#define ENC_IMR_FPHA_SHIFT (7U)
9932#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
9937#define ENC_TST_TEST_COUNT_MASK (0xFFU)
9938#define ENC_TST_TEST_COUNT_SHIFT (0U)
9939#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
9940#define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
9941#define ENC_TST_TEST_PERIOD_SHIFT (8U)
9942#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
9943#define ENC_TST_QDN_MASK (0x2000U)
9944#define ENC_TST_QDN_SHIFT (13U)
9949#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
9950#define ENC_TST_TCE_MASK (0x4000U)
9951#define ENC_TST_TCE_SHIFT (14U)
9956#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
9957#define ENC_TST_TEN_MASK (0x8000U)
9958#define ENC_TST_TEN_SHIFT (15U)
9963#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
9968#define ENC_CTRL2_UPDHLD_MASK (0x1U)
9969#define ENC_CTRL2_UPDHLD_SHIFT (0U)
9974#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
9975#define ENC_CTRL2_UPDPOS_MASK (0x2U)
9976#define ENC_CTRL2_UPDPOS_SHIFT (1U)
9981#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
9982#define ENC_CTRL2_MOD_MASK (0x4U)
9983#define ENC_CTRL2_MOD_SHIFT (2U)
9988#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
9989#define ENC_CTRL2_DIR_MASK (0x8U)
9990#define ENC_CTRL2_DIR_SHIFT (3U)
9995#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
9996#define ENC_CTRL2_RUIE_MASK (0x10U)
9997#define ENC_CTRL2_RUIE_SHIFT (4U)
10002#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
10003#define ENC_CTRL2_RUIRQ_MASK (0x20U)
10004#define ENC_CTRL2_RUIRQ_SHIFT (5U)
10009#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
10010#define ENC_CTRL2_ROIE_MASK (0x40U)
10011#define ENC_CTRL2_ROIE_SHIFT (6U)
10016#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
10017#define ENC_CTRL2_ROIRQ_MASK (0x80U)
10018#define ENC_CTRL2_ROIRQ_SHIFT (7U)
10023#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
10024#define ENC_CTRL2_REVMOD_MASK (0x100U)
10025#define ENC_CTRL2_REVMOD_SHIFT (8U)
10030#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
10031#define ENC_CTRL2_OUTCTL_MASK (0x200U)
10032#define ENC_CTRL2_OUTCTL_SHIFT (9U)
10037#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
10038#define ENC_CTRL2_SABIE_MASK (0x400U)
10039#define ENC_CTRL2_SABIE_SHIFT (10U)
10044#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
10045#define ENC_CTRL2_SABIRQ_MASK (0x800U)
10046#define ENC_CTRL2_SABIRQ_SHIFT (11U)
10051#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
10056#define ENC_UMOD_MOD_MASK (0xFFFFU)
10057#define ENC_UMOD_MOD_SHIFT (0U)
10058#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
10063#define ENC_LMOD_MOD_MASK (0xFFFFU)
10064#define ENC_LMOD_MOD_SHIFT (0U)
10065#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
10070#define ENC_UCOMP_COMP_MASK (0xFFFFU)
10071#define ENC_UCOMP_COMP_SHIFT (0U)
10072#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
10077#define ENC_LCOMP_COMP_MASK (0xFFFFU)
10078#define ENC_LCOMP_COMP_SHIFT (0U)
10079#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
10085 /* end of group ENC_Register_Masks */
10086
10087
10088/* ENC - Peripheral instance base addresses */
10090#define ENC_BASE (0x40055000u)
10092#define ENC ((ENC_Type *)ENC_BASE)
10094#define ENC_BASE_ADDRS { ENC_BASE }
10096#define ENC_BASE_PTRS { ENC }
10098#define ENC_COMPARE_IRQS { ENC_COMPARE_IRQn }
10099#define ENC_HOME_IRQS { ENC_HOME_IRQn }
10100#define ENC_WDOG_IRQS { ENC_WDOG_SAB_IRQn }
10101#define ENC_INDEX_IRQS { ENC_INDEX_IRQn }
10102
10105 /* end of group ENC_Peripheral_Access_Layer */
10106
10107
10108/* ----------------------------------------------------------------------------
10109 -- ENET Peripheral Access Layer
10110 ---------------------------------------------------------------------------- */
10111
10118typedef struct {
10119 uint8_t RESERVED_0[4];
10120 __IO uint32_t EIR;
10121 __IO uint32_t EIMR;
10122 uint8_t RESERVED_1[4];
10123 __IO uint32_t RDAR;
10124 __IO uint32_t TDAR;
10125 uint8_t RESERVED_2[12];
10126 __IO uint32_t ECR;
10127 uint8_t RESERVED_3[24];
10128 __IO uint32_t MMFR;
10129 __IO uint32_t MSCR;
10130 uint8_t RESERVED_4[28];
10131 __IO uint32_t MIBC;
10132 uint8_t RESERVED_5[28];
10133 __IO uint32_t RCR;
10134 uint8_t RESERVED_6[60];
10135 __IO uint32_t TCR;
10136 uint8_t RESERVED_7[28];
10137 __IO uint32_t PALR;
10138 __IO uint32_t PAUR;
10139 __IO uint32_t OPD;
10140 uint8_t RESERVED_8[40];
10141 __IO uint32_t IAUR;
10142 __IO uint32_t IALR;
10143 __IO uint32_t GAUR;
10144 __IO uint32_t GALR;
10145 uint8_t RESERVED_9[28];
10146 __IO uint32_t TFWR;
10147 uint8_t RESERVED_10[56];
10148 __IO uint32_t RDSR;
10149 __IO uint32_t TDSR;
10150 __IO uint32_t MRBR;
10151 uint8_t RESERVED_11[4];
10152 __IO uint32_t RSFL;
10153 __IO uint32_t RSEM;
10154 __IO uint32_t RAEM;
10155 __IO uint32_t RAFL;
10156 __IO uint32_t TSEM;
10157 __IO uint32_t TAEM;
10158 __IO uint32_t TAFL;
10159 __IO uint32_t TIPG;
10160 __IO uint32_t FTRL;
10161 uint8_t RESERVED_12[12];
10162 __IO uint32_t TACC;
10163 __IO uint32_t RACC;
10164 uint8_t RESERVED_13[56];
10165 uint32_t RMON_T_DROP;
10166 __I uint32_t RMON_T_PACKETS;
10167 __I uint32_t RMON_T_BC_PKT;
10168 __I uint32_t RMON_T_MC_PKT;
10169 __I uint32_t RMON_T_CRC_ALIGN;
10170 __I uint32_t RMON_T_UNDERSIZE;
10171 __I uint32_t RMON_T_OVERSIZE;
10172 __I uint32_t RMON_T_FRAG;
10173 __I uint32_t RMON_T_JAB;
10174 __I uint32_t RMON_T_COL;
10175 __I uint32_t RMON_T_P64;
10176 __I uint32_t RMON_T_P65TO127;
10177 __I uint32_t RMON_T_P128TO255;
10178 __I uint32_t RMON_T_P256TO511;
10179 __I uint32_t RMON_T_P512TO1023;
10180 __I uint32_t RMON_T_P1024TO2047;
10181 __I uint32_t RMON_T_P_GTE2048;
10182 __I uint32_t RMON_T_OCTETS;
10183 uint32_t IEEE_T_DROP;
10184 __I uint32_t IEEE_T_FRAME_OK;
10185 __I uint32_t IEEE_T_1COL;
10186 __I uint32_t IEEE_T_MCOL;
10187 __I uint32_t IEEE_T_DEF;
10188 __I uint32_t IEEE_T_LCOL;
10189 __I uint32_t IEEE_T_EXCOL;
10190 __I uint32_t IEEE_T_MACERR;
10191 __I uint32_t IEEE_T_CSERR;
10192 __I uint32_t IEEE_T_SQE;
10193 __I uint32_t IEEE_T_FDXFC;
10194 __I uint32_t IEEE_T_OCTETS_OK;
10195 uint8_t RESERVED_14[12];
10196 __I uint32_t RMON_R_PACKETS;
10197 __I uint32_t RMON_R_BC_PKT;
10198 __I uint32_t RMON_R_MC_PKT;
10199 __I uint32_t RMON_R_CRC_ALIGN;
10200 __I uint32_t RMON_R_UNDERSIZE;
10201 __I uint32_t RMON_R_OVERSIZE;
10202 __I uint32_t RMON_R_FRAG;
10203 __I uint32_t RMON_R_JAB;
10204 uint32_t RMON_R_RESVD_0;
10205 __I uint32_t RMON_R_P64;
10206 __I uint32_t RMON_R_P65TO127;
10207 __I uint32_t RMON_R_P128TO255;
10208 __I uint32_t RMON_R_P256TO511;
10209 __I uint32_t RMON_R_P512TO1023;
10210 __I uint32_t RMON_R_P1024TO2047;
10211 __I uint32_t RMON_R_P_GTE2048;
10212 __I uint32_t RMON_R_OCTETS;
10213 __I uint32_t IEEE_R_DROP;
10214 __I uint32_t IEEE_R_FRAME_OK;
10215 __I uint32_t IEEE_R_CRC;
10216 __I uint32_t IEEE_R_ALIGN;
10217 __I uint32_t IEEE_R_MACERR;
10218 __I uint32_t IEEE_R_FDXFC;
10219 __I uint32_t IEEE_R_OCTETS_OK;
10220 uint8_t RESERVED_15[284];
10221 __IO uint32_t ATCR;
10222 __IO uint32_t ATVR;
10223 __IO uint32_t ATOFF;
10224 __IO uint32_t ATPER;
10225 __IO uint32_t ATCOR;
10226 __IO uint32_t ATINC;
10227 __I uint32_t ATSTMP;
10228 uint8_t RESERVED_16[488];
10229 __IO uint32_t TGSR;
10230 struct { /* offset: 0x608, array step: 0x8 */
10231 __IO uint32_t TCSR;
10232 __IO uint32_t TCCR;
10233 } CHANNEL[4];
10234} ENET_Type;
10235
10236/* ----------------------------------------------------------------------------
10237 -- ENET Register Masks
10238 ---------------------------------------------------------------------------- */
10239
10247#define ENET_EIR_TS_TIMER_MASK (0x8000U)
10248#define ENET_EIR_TS_TIMER_SHIFT (15U)
10249#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
10250#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
10251#define ENET_EIR_TS_AVAIL_SHIFT (16U)
10252#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
10253#define ENET_EIR_WAKEUP_MASK (0x20000U)
10254#define ENET_EIR_WAKEUP_SHIFT (17U)
10255#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
10256#define ENET_EIR_PLR_MASK (0x40000U)
10257#define ENET_EIR_PLR_SHIFT (18U)
10258#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
10259#define ENET_EIR_UN_MASK (0x80000U)
10260#define ENET_EIR_UN_SHIFT (19U)
10261#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
10262#define ENET_EIR_RL_MASK (0x100000U)
10263#define ENET_EIR_RL_SHIFT (20U)
10264#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
10265#define ENET_EIR_LC_MASK (0x200000U)
10266#define ENET_EIR_LC_SHIFT (21U)
10267#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
10268#define ENET_EIR_EBERR_MASK (0x400000U)
10269#define ENET_EIR_EBERR_SHIFT (22U)
10270#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
10271#define ENET_EIR_MII_MASK (0x800000U)
10272#define ENET_EIR_MII_SHIFT (23U)
10273#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
10274#define ENET_EIR_RXB_MASK (0x1000000U)
10275#define ENET_EIR_RXB_SHIFT (24U)
10276#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
10277#define ENET_EIR_RXF_MASK (0x2000000U)
10278#define ENET_EIR_RXF_SHIFT (25U)
10279#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
10280#define ENET_EIR_TXB_MASK (0x4000000U)
10281#define ENET_EIR_TXB_SHIFT (26U)
10282#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
10283#define ENET_EIR_TXF_MASK (0x8000000U)
10284#define ENET_EIR_TXF_SHIFT (27U)
10285#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
10286#define ENET_EIR_GRA_MASK (0x10000000U)
10287#define ENET_EIR_GRA_SHIFT (28U)
10288#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
10289#define ENET_EIR_BABT_MASK (0x20000000U)
10290#define ENET_EIR_BABT_SHIFT (29U)
10291#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
10292#define ENET_EIR_BABR_MASK (0x40000000U)
10293#define ENET_EIR_BABR_SHIFT (30U)
10294#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
10299#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
10300#define ENET_EIMR_TS_TIMER_SHIFT (15U)
10301#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
10302#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
10303#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
10304#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
10305#define ENET_EIMR_WAKEUP_MASK (0x20000U)
10306#define ENET_EIMR_WAKEUP_SHIFT (17U)
10307#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
10308#define ENET_EIMR_PLR_MASK (0x40000U)
10309#define ENET_EIMR_PLR_SHIFT (18U)
10310#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
10311#define ENET_EIMR_UN_MASK (0x80000U)
10312#define ENET_EIMR_UN_SHIFT (19U)
10313#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
10314#define ENET_EIMR_RL_MASK (0x100000U)
10315#define ENET_EIMR_RL_SHIFT (20U)
10316#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
10317#define ENET_EIMR_LC_MASK (0x200000U)
10318#define ENET_EIMR_LC_SHIFT (21U)
10319#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
10320#define ENET_EIMR_EBERR_MASK (0x400000U)
10321#define ENET_EIMR_EBERR_SHIFT (22U)
10322#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
10323#define ENET_EIMR_MII_MASK (0x800000U)
10324#define ENET_EIMR_MII_SHIFT (23U)
10325#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
10326#define ENET_EIMR_RXB_MASK (0x1000000U)
10327#define ENET_EIMR_RXB_SHIFT (24U)
10328#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
10329#define ENET_EIMR_RXF_MASK (0x2000000U)
10330#define ENET_EIMR_RXF_SHIFT (25U)
10331#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
10332#define ENET_EIMR_TXB_MASK (0x4000000U)
10333#define ENET_EIMR_TXB_SHIFT (26U)
10338#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
10339#define ENET_EIMR_TXF_MASK (0x8000000U)
10340#define ENET_EIMR_TXF_SHIFT (27U)
10345#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
10346#define ENET_EIMR_GRA_MASK (0x10000000U)
10347#define ENET_EIMR_GRA_SHIFT (28U)
10352#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
10353#define ENET_EIMR_BABT_MASK (0x20000000U)
10354#define ENET_EIMR_BABT_SHIFT (29U)
10359#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
10360#define ENET_EIMR_BABR_MASK (0x40000000U)
10361#define ENET_EIMR_BABR_SHIFT (30U)
10366#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
10371#define ENET_RDAR_RDAR_MASK (0x1000000U)
10372#define ENET_RDAR_RDAR_SHIFT (24U)
10373#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
10378#define ENET_TDAR_TDAR_MASK (0x1000000U)
10379#define ENET_TDAR_TDAR_SHIFT (24U)
10380#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
10385#define ENET_ECR_RESET_MASK (0x1U)
10386#define ENET_ECR_RESET_SHIFT (0U)
10387#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
10388#define ENET_ECR_ETHEREN_MASK (0x2U)
10389#define ENET_ECR_ETHEREN_SHIFT (1U)
10394#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
10395#define ENET_ECR_MAGICEN_MASK (0x4U)
10396#define ENET_ECR_MAGICEN_SHIFT (2U)
10401#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
10402#define ENET_ECR_SLEEP_MASK (0x8U)
10403#define ENET_ECR_SLEEP_SHIFT (3U)
10408#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
10409#define ENET_ECR_EN1588_MASK (0x10U)
10410#define ENET_ECR_EN1588_SHIFT (4U)
10415#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
10416#define ENET_ECR_DBGEN_MASK (0x40U)
10417#define ENET_ECR_DBGEN_SHIFT (6U)
10422#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
10423#define ENET_ECR_STOPEN_MASK (0x80U)
10424#define ENET_ECR_STOPEN_SHIFT (7U)
10425#define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
10426#define ENET_ECR_DBSWP_MASK (0x100U)
10427#define ENET_ECR_DBSWP_SHIFT (8U)
10432#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
10437#define ENET_MMFR_DATA_MASK (0xFFFFU)
10438#define ENET_MMFR_DATA_SHIFT (0U)
10439#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
10440#define ENET_MMFR_TA_MASK (0x30000U)
10441#define ENET_MMFR_TA_SHIFT (16U)
10442#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
10443#define ENET_MMFR_RA_MASK (0x7C0000U)
10444#define ENET_MMFR_RA_SHIFT (18U)
10445#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
10446#define ENET_MMFR_PA_MASK (0xF800000U)
10447#define ENET_MMFR_PA_SHIFT (23U)
10448#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
10449#define ENET_MMFR_OP_MASK (0x30000000U)
10450#define ENET_MMFR_OP_SHIFT (28U)
10451#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
10452#define ENET_MMFR_ST_MASK (0xC0000000U)
10453#define ENET_MMFR_ST_SHIFT (30U)
10454#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
10459#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
10460#define ENET_MSCR_MII_SPEED_SHIFT (1U)
10461#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
10462#define ENET_MSCR_DIS_PRE_MASK (0x80U)
10463#define ENET_MSCR_DIS_PRE_SHIFT (7U)
10468#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
10469#define ENET_MSCR_HOLDTIME_MASK (0x700U)
10470#define ENET_MSCR_HOLDTIME_SHIFT (8U)
10477#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
10482#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
10483#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
10488#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
10489#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
10490#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
10495#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
10496#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
10497#define ENET_MIBC_MIB_DIS_SHIFT (31U)
10502#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
10507#define ENET_RCR_LOOP_MASK (0x1U)
10508#define ENET_RCR_LOOP_SHIFT (0U)
10513#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
10514#define ENET_RCR_DRT_MASK (0x2U)
10515#define ENET_RCR_DRT_SHIFT (1U)
10520#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
10521#define ENET_RCR_MII_MODE_MASK (0x4U)
10522#define ENET_RCR_MII_MODE_SHIFT (2U)
10527#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
10528#define ENET_RCR_PROM_MASK (0x8U)
10529#define ENET_RCR_PROM_SHIFT (3U)
10534#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
10535#define ENET_RCR_BC_REJ_MASK (0x10U)
10536#define ENET_RCR_BC_REJ_SHIFT (4U)
10537#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
10538#define ENET_RCR_FCE_MASK (0x20U)
10539#define ENET_RCR_FCE_SHIFT (5U)
10540#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
10541#define ENET_RCR_RMII_MODE_MASK (0x100U)
10542#define ENET_RCR_RMII_MODE_SHIFT (8U)
10547#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
10548#define ENET_RCR_RMII_10T_MASK (0x200U)
10549#define ENET_RCR_RMII_10T_SHIFT (9U)
10554#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
10555#define ENET_RCR_PADEN_MASK (0x1000U)
10556#define ENET_RCR_PADEN_SHIFT (12U)
10561#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
10562#define ENET_RCR_PAUFWD_MASK (0x2000U)
10563#define ENET_RCR_PAUFWD_SHIFT (13U)
10568#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
10569#define ENET_RCR_CRCFWD_MASK (0x4000U)
10570#define ENET_RCR_CRCFWD_SHIFT (14U)
10575#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
10576#define ENET_RCR_CFEN_MASK (0x8000U)
10577#define ENET_RCR_CFEN_SHIFT (15U)
10582#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
10583#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
10584#define ENET_RCR_MAX_FL_SHIFT (16U)
10585#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
10586#define ENET_RCR_NLC_MASK (0x40000000U)
10587#define ENET_RCR_NLC_SHIFT (30U)
10592#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
10593#define ENET_RCR_GRS_MASK (0x80000000U)
10594#define ENET_RCR_GRS_SHIFT (31U)
10595#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
10600#define ENET_TCR_GTS_MASK (0x1U)
10601#define ENET_TCR_GTS_SHIFT (0U)
10602#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
10603#define ENET_TCR_FDEN_MASK (0x4U)
10604#define ENET_TCR_FDEN_SHIFT (2U)
10605#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
10606#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
10607#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
10612#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
10613#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
10614#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
10615#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
10616#define ENET_TCR_ADDSEL_MASK (0xE0U)
10617#define ENET_TCR_ADDSEL_SHIFT (5U)
10624#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
10625#define ENET_TCR_ADDINS_MASK (0x100U)
10626#define ENET_TCR_ADDINS_SHIFT (8U)
10631#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
10632#define ENET_TCR_CRCFWD_MASK (0x200U)
10633#define ENET_TCR_CRCFWD_SHIFT (9U)
10638#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
10643#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
10644#define ENET_PALR_PADDR1_SHIFT (0U)
10645#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
10650#define ENET_PAUR_TYPE_MASK (0xFFFFU)
10651#define ENET_PAUR_TYPE_SHIFT (0U)
10652#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
10653#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
10654#define ENET_PAUR_PADDR2_SHIFT (16U)
10655#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
10660#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
10661#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
10662#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
10663#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
10664#define ENET_OPD_OPCODE_SHIFT (16U)
10665#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
10670#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
10671#define ENET_IAUR_IADDR1_SHIFT (0U)
10672#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
10677#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
10678#define ENET_IALR_IADDR2_SHIFT (0U)
10679#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
10684#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
10685#define ENET_GAUR_GADDR1_SHIFT (0U)
10686#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
10691#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
10692#define ENET_GALR_GADDR2_SHIFT (0U)
10693#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
10698#define ENET_TFWR_TFWR_MASK (0x3FU)
10699#define ENET_TFWR_TFWR_SHIFT (0U)
10707#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
10708#define ENET_TFWR_STRFWD_MASK (0x100U)
10709#define ENET_TFWR_STRFWD_SHIFT (8U)
10714#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
10719#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
10720#define ENET_RDSR_R_DES_START_SHIFT (3U)
10721#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
10726#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
10727#define ENET_TDSR_X_DES_START_SHIFT (3U)
10728#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
10733#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
10734#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
10735#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
10740#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
10741#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
10742#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
10747#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
10748#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
10749#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
10750#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
10751#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
10752#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
10757#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
10758#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
10759#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
10764#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
10765#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
10766#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
10771#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
10772#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
10773#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
10778#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
10779#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
10780#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
10785#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
10786#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
10787#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
10792#define ENET_TIPG_IPG_MASK (0x1FU)
10793#define ENET_TIPG_IPG_SHIFT (0U)
10794#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
10799#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
10800#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
10801#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
10806#define ENET_TACC_SHIFT16_MASK (0x1U)
10807#define ENET_TACC_SHIFT16_SHIFT (0U)
10812#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
10813#define ENET_TACC_IPCHK_MASK (0x8U)
10814#define ENET_TACC_IPCHK_SHIFT (3U)
10819#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
10820#define ENET_TACC_PROCHK_MASK (0x10U)
10821#define ENET_TACC_PROCHK_SHIFT (4U)
10826#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
10831#define ENET_RACC_PADREM_MASK (0x1U)
10832#define ENET_RACC_PADREM_SHIFT (0U)
10837#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
10838#define ENET_RACC_IPDIS_MASK (0x2U)
10839#define ENET_RACC_IPDIS_SHIFT (1U)
10844#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
10845#define ENET_RACC_PRODIS_MASK (0x4U)
10846#define ENET_RACC_PRODIS_SHIFT (2U)
10851#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
10852#define ENET_RACC_LINEDIS_MASK (0x40U)
10853#define ENET_RACC_LINEDIS_SHIFT (6U)
10858#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
10859#define ENET_RACC_SHIFT16_MASK (0x80U)
10860#define ENET_RACC_SHIFT16_SHIFT (7U)
10865#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
10870#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
10871#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
10872#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
10877#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
10878#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
10879#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
10884#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
10885#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
10886#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
10891#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
10892#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
10893#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
10898#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
10899#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
10900#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
10905#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
10906#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
10907#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
10912#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
10913#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
10914#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
10919#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
10920#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
10921#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
10926#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
10927#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
10928#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
10933#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
10934#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
10935#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
10940#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
10941#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
10942#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
10947#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
10948#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
10949#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
10954#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
10955#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
10956#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
10961#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
10962#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
10963#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
10968#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
10969#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
10970#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
10975#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
10976#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
10977#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
10982#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
10983#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
10984#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
10989#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
10990#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
10991#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
10996#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
10997#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
10998#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
11003#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
11004#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
11005#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
11010#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
11011#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
11012#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
11017#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
11018#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
11019#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
11024#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
11025#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
11026#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
11031#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
11032#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
11033#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
11038#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
11039#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
11040#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
11045#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
11046#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
11047#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
11052#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
11053#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
11054#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
11059#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
11060#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
11061#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
11066#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
11067#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
11068#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
11073#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
11074#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
11075#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
11080#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
11081#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
11082#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
11087#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
11088#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
11089#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
11094#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
11095#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
11096#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
11101#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
11102#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
11103#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
11108#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
11109#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
11110#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
11115#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
11116#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
11117#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
11122#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
11123#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
11124#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
11129#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
11130#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
11131#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
11136#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
11137#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
11138#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
11143#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
11144#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
11145#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
11150#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
11151#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
11152#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
11157#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
11158#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
11159#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
11164#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
11165#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
11166#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
11171#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
11172#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
11173#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
11178#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
11179#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
11180#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
11185#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
11186#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
11187#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
11192#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
11193#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
11194#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
11199#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
11200#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
11201#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
11206#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
11207#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
11208#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
11213#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
11214#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
11215#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
11220#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
11221#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
11222#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
11227#define ENET_ATCR_EN_MASK (0x1U)
11228#define ENET_ATCR_EN_SHIFT (0U)
11233#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
11234#define ENET_ATCR_OFFEN_MASK (0x4U)
11235#define ENET_ATCR_OFFEN_SHIFT (2U)
11240#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
11241#define ENET_ATCR_OFFRST_MASK (0x8U)
11242#define ENET_ATCR_OFFRST_SHIFT (3U)
11247#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
11248#define ENET_ATCR_PEREN_MASK (0x10U)
11249#define ENET_ATCR_PEREN_SHIFT (4U)
11254#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
11255#define ENET_ATCR_PINPER_MASK (0x80U)
11256#define ENET_ATCR_PINPER_SHIFT (7U)
11261#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
11262#define ENET_ATCR_RESTART_MASK (0x200U)
11263#define ENET_ATCR_RESTART_SHIFT (9U)
11264#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
11265#define ENET_ATCR_CAPTURE_MASK (0x800U)
11266#define ENET_ATCR_CAPTURE_SHIFT (11U)
11271#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
11272#define ENET_ATCR_SLAVE_MASK (0x2000U)
11273#define ENET_ATCR_SLAVE_SHIFT (13U)
11278#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
11283#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
11284#define ENET_ATVR_ATIME_SHIFT (0U)
11285#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
11290#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
11291#define ENET_ATOFF_OFFSET_SHIFT (0U)
11292#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
11297#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
11298#define ENET_ATPER_PERIOD_SHIFT (0U)
11299#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
11304#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
11305#define ENET_ATCOR_COR_SHIFT (0U)
11306#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
11311#define ENET_ATINC_INC_MASK (0x7FU)
11312#define ENET_ATINC_INC_SHIFT (0U)
11313#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
11314#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
11315#define ENET_ATINC_INC_CORR_SHIFT (8U)
11316#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
11321#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
11322#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
11323#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
11328#define ENET_TGSR_TF0_MASK (0x1U)
11329#define ENET_TGSR_TF0_SHIFT (0U)
11334#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
11335#define ENET_TGSR_TF1_MASK (0x2U)
11336#define ENET_TGSR_TF1_SHIFT (1U)
11341#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
11342#define ENET_TGSR_TF2_MASK (0x4U)
11343#define ENET_TGSR_TF2_SHIFT (2U)
11348#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
11349#define ENET_TGSR_TF3_MASK (0x8U)
11350#define ENET_TGSR_TF3_SHIFT (3U)
11355#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
11360#define ENET_TCSR_TDRE_MASK (0x1U)
11361#define ENET_TCSR_TDRE_SHIFT (0U)
11366#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
11367#define ENET_TCSR_TMODE_MASK (0x3CU)
11368#define ENET_TCSR_TMODE_SHIFT (2U)
11385#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
11386#define ENET_TCSR_TIE_MASK (0x40U)
11387#define ENET_TCSR_TIE_SHIFT (6U)
11392#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
11393#define ENET_TCSR_TF_MASK (0x80U)
11394#define ENET_TCSR_TF_SHIFT (7U)
11399#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
11402/* The count of ENET_TCSR */
11403#define ENET_TCSR_COUNT (4U)
11404
11407#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
11408#define ENET_TCCR_TCC_SHIFT (0U)
11409#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
11412/* The count of ENET_TCCR */
11413#define ENET_TCCR_COUNT (4U)
11414
11415
11418 /* end of group ENET_Register_Masks */
11419
11420
11421/* ENET - Peripheral instance base addresses */
11423#define ENET_BASE (0x400C0000u)
11425#define ENET ((ENET_Type *)ENET_BASE)
11427#define ENET_BASE_ADDRS { ENET_BASE }
11429#define ENET_BASE_PTRS { ENET }
11431#define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
11432#define ENET_Receive_IRQS { ENET_Receive_IRQn }
11433#define ENET_Error_IRQS { ENET_Error_IRQn }
11434#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
11435/* ENET Buffer Descriptor and Buffer Address Alignment. */
11436#define ENET_BUFF_ALIGNMENT (64U)
11437
11438
11441 /* end of group ENET_Peripheral_Access_Layer */
11442
11443
11444/* ----------------------------------------------------------------------------
11445 -- EWM Peripheral Access Layer
11446 ---------------------------------------------------------------------------- */
11447
11454typedef struct {
11455 __IO uint8_t CTRL;
11456 __O uint8_t SERV;
11457 __IO uint8_t CMPL;
11458 __IO uint8_t CMPH;
11459 __IO uint8_t CLKCTRL;
11460 __IO uint8_t CLKPRESCALER;
11461} EWM_Type;
11462
11463/* ----------------------------------------------------------------------------
11464 -- EWM Register Masks
11465 ---------------------------------------------------------------------------- */
11466
11474#define EWM_CTRL_EWMEN_MASK (0x1U)
11475#define EWM_CTRL_EWMEN_SHIFT (0U)
11476#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
11477#define EWM_CTRL_ASSIN_MASK (0x2U)
11478#define EWM_CTRL_ASSIN_SHIFT (1U)
11479#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
11480#define EWM_CTRL_INEN_MASK (0x4U)
11481#define EWM_CTRL_INEN_SHIFT (2U)
11482#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
11483#define EWM_CTRL_INTEN_MASK (0x8U)
11484#define EWM_CTRL_INTEN_SHIFT (3U)
11485#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
11490#define EWM_SERV_SERVICE_MASK (0xFFU)
11491#define EWM_SERV_SERVICE_SHIFT (0U)
11492#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
11497#define EWM_CMPL_COMPAREL_MASK (0xFFU)
11498#define EWM_CMPL_COMPAREL_SHIFT (0U)
11499#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
11504#define EWM_CMPH_COMPAREH_MASK (0xFFU)
11505#define EWM_CMPH_COMPAREH_SHIFT (0U)
11506#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
11511#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
11512#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
11513#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
11518#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
11519#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
11520#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
11526 /* end of group EWM_Register_Masks */
11527
11528
11529/* EWM - Peripheral instance base addresses */
11531#define EWM_BASE (0x40061000u)
11533#define EWM ((EWM_Type *)EWM_BASE)
11535#define EWM_BASE_ADDRS { EWM_BASE }
11537#define EWM_BASE_PTRS { EWM }
11539#define EWM_IRQS { WDOG_EWM_IRQn }
11540
11543 /* end of group EWM_Peripheral_Access_Layer */
11544
11545
11546/* ----------------------------------------------------------------------------
11547 -- FB Peripheral Access Layer
11548 ---------------------------------------------------------------------------- */
11549
11556typedef struct {
11557 struct { /* offset: 0x0, array step: 0xC */
11558 __IO uint32_t CSAR;
11559 __IO uint32_t CSMR;
11560 __IO uint32_t CSCR;
11561 } CS[6];
11562 uint8_t RESERVED_0[24];
11563 __IO uint32_t CSPMCR;
11564} FB_Type;
11565
11566/* ----------------------------------------------------------------------------
11567 -- FB Register Masks
11568 ---------------------------------------------------------------------------- */
11569
11577#define FB_CSAR_BA_MASK (0xFFFF0000U)
11578#define FB_CSAR_BA_SHIFT (16U)
11579#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
11582/* The count of FB_CSAR */
11583#define FB_CSAR_COUNT (6U)
11584
11587#define FB_CSMR_V_MASK (0x1U)
11588#define FB_CSMR_V_SHIFT (0U)
11593#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
11594#define FB_CSMR_WP_MASK (0x100U)
11595#define FB_CSMR_WP_SHIFT (8U)
11600#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
11601#define FB_CSMR_BAM_MASK (0xFFFF0000U)
11602#define FB_CSMR_BAM_SHIFT (16U)
11607#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
11610/* The count of FB_CSMR */
11611#define FB_CSMR_COUNT (6U)
11612
11615#define FB_CSCR_BSTW_MASK (0x8U)
11616#define FB_CSCR_BSTW_SHIFT (3U)
11621#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
11622#define FB_CSCR_BSTR_MASK (0x10U)
11623#define FB_CSCR_BSTR_SHIFT (4U)
11628#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
11629#define FB_CSCR_BEM_MASK (0x20U)
11630#define FB_CSCR_BEM_SHIFT (5U)
11635#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
11636#define FB_CSCR_PS_MASK (0xC0U)
11637#define FB_CSCR_PS_SHIFT (6U)
11643#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
11644#define FB_CSCR_AA_MASK (0x100U)
11645#define FB_CSCR_AA_SHIFT (8U)
11650#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
11651#define FB_CSCR_BLS_MASK (0x200U)
11652#define FB_CSCR_BLS_SHIFT (9U)
11657#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
11658#define FB_CSCR_WS_MASK (0xFC00U)
11659#define FB_CSCR_WS_SHIFT (10U)
11660#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
11661#define FB_CSCR_WRAH_MASK (0x30000U)
11662#define FB_CSCR_WRAH_SHIFT (16U)
11669#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
11670#define FB_CSCR_RDAH_MASK (0xC0000U)
11671#define FB_CSCR_RDAH_SHIFT (18U)
11678#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
11679#define FB_CSCR_ASET_MASK (0x300000U)
11680#define FB_CSCR_ASET_SHIFT (20U)
11687#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
11688#define FB_CSCR_EXTS_MASK (0x400000U)
11689#define FB_CSCR_EXTS_SHIFT (22U)
11694#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
11695#define FB_CSCR_SWSEN_MASK (0x800000U)
11696#define FB_CSCR_SWSEN_SHIFT (23U)
11701#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
11702#define FB_CSCR_SWS_MASK (0xFC000000U)
11703#define FB_CSCR_SWS_SHIFT (26U)
11704#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
11707/* The count of FB_CSCR */
11708#define FB_CSCR_COUNT (6U)
11709
11712#define FB_CSPMCR_GROUP5_MASK (0xF000U)
11713#define FB_CSPMCR_GROUP5_SHIFT (12U)
11719#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
11720#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
11721#define FB_CSPMCR_GROUP4_SHIFT (16U)
11727#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
11728#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
11729#define FB_CSPMCR_GROUP3_SHIFT (20U)
11735#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
11736#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
11737#define FB_CSPMCR_GROUP2_SHIFT (24U)
11743#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
11744#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
11745#define FB_CSPMCR_GROUP1_SHIFT (28U)
11751#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
11757 /* end of group FB_Register_Masks */
11758
11759
11760/* FB - Peripheral instance base addresses */
11762#define FB_BASE (0x4000C000u)
11764#define FB ((FB_Type *)FB_BASE)
11766#define FB_BASE_ADDRS { FB_BASE }
11768#define FB_BASE_PTRS { FB }
11769
11772 /* end of group FB_Peripheral_Access_Layer */
11773
11774
11775/* ----------------------------------------------------------------------------
11776 -- FMC Peripheral Access Layer
11777 ---------------------------------------------------------------------------- */
11778
11785typedef struct {
11786 __IO uint32_t PFAPR;
11787 __IO uint32_t PFB0CR;
11788} FMC_Type;
11789
11790/* ----------------------------------------------------------------------------
11791 -- FMC Register Masks
11792 ---------------------------------------------------------------------------- */
11793
11801#define FMC_PFAPR_M0AP_MASK (0x3U)
11802#define FMC_PFAPR_M0AP_SHIFT (0U)
11809#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
11810#define FMC_PFAPR_M1AP_MASK (0xCU)
11811#define FMC_PFAPR_M1AP_SHIFT (2U)
11818#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
11819#define FMC_PFAPR_M2AP_MASK (0x30U)
11820#define FMC_PFAPR_M2AP_SHIFT (4U)
11827#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
11828#define FMC_PFAPR_M3AP_MASK (0xC0U)
11829#define FMC_PFAPR_M3AP_SHIFT (6U)
11836#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
11837#define FMC_PFAPR_M0PFD_MASK (0x10000U)
11838#define FMC_PFAPR_M0PFD_SHIFT (16U)
11843#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
11844#define FMC_PFAPR_M1PFD_MASK (0x20000U)
11845#define FMC_PFAPR_M1PFD_SHIFT (17U)
11850#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
11851#define FMC_PFAPR_M2PFD_MASK (0x40000U)
11852#define FMC_PFAPR_M2PFD_SHIFT (18U)
11857#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
11858#define FMC_PFAPR_M3PFD_MASK (0x80000U)
11859#define FMC_PFAPR_M3PFD_SHIFT (19U)
11864#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
11869#define FMC_PFB0CR_B0IPE_MASK (0x2U)
11870#define FMC_PFB0CR_B0IPE_SHIFT (1U)
11875#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
11876#define FMC_PFB0CR_B0DPE_MASK (0x4U)
11877#define FMC_PFB0CR_B0DPE_SHIFT (2U)
11882#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
11883#define FMC_PFB0CR_B0MW_MASK (0x60000U)
11884#define FMC_PFB0CR_B0MW_SHIFT (17U)
11891#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
11892#define FMC_PFB0CR_S_INV_MASK (0x80000U)
11893#define FMC_PFB0CR_S_INV_SHIFT (19U)
11898#define FMC_PFB0CR_S_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_INV_SHIFT)) & FMC_PFB0CR_S_INV_MASK)
11899#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
11900#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
11901#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
11907 /* end of group FMC_Register_Masks */
11908
11909
11910/* FMC - Peripheral instance base addresses */
11912#define FMC_BASE (0x4001F000u)
11914#define FMC ((FMC_Type *)FMC_BASE)
11916#define FMC_BASE_ADDRS { FMC_BASE }
11918#define FMC_BASE_PTRS { FMC }
11919
11922 /* end of group FMC_Peripheral_Access_Layer */
11923
11924
11925/* ----------------------------------------------------------------------------
11926 -- FTFE Peripheral Access Layer
11927 ---------------------------------------------------------------------------- */
11928
11935typedef struct {
11936 __IO uint8_t FSTAT;
11937 __IO uint8_t FCNFG;
11938 __I uint8_t FSEC;
11939 __I uint8_t FOPT;
11940 __IO uint8_t FCCOB3;
11941 __IO uint8_t FCCOB2;
11942 __IO uint8_t FCCOB1;
11943 __IO uint8_t FCCOB0;
11944 __IO uint8_t FCCOB7;
11945 __IO uint8_t FCCOB6;
11946 __IO uint8_t FCCOB5;
11947 __IO uint8_t FCCOB4;
11948 __IO uint8_t FCCOBB;
11949 __IO uint8_t FCCOBA;
11950 __IO uint8_t FCCOB9;
11951 __IO uint8_t FCCOB8;
11952 __IO uint8_t FPROT3;
11953 __IO uint8_t FPROT2;
11954 __IO uint8_t FPROT1;
11955 __IO uint8_t FPROT0;
11956} FTFE_Type;
11957
11958/* ----------------------------------------------------------------------------
11959 -- FTFE Register Masks
11960 ---------------------------------------------------------------------------- */
11961
11969#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
11970#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
11971#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
11972#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
11973#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
11978#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
11979#define FTFE_FSTAT_ACCERR_MASK (0x20U)
11980#define FTFE_FSTAT_ACCERR_SHIFT (5U)
11985#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
11986#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
11987#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
11992#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
11993#define FTFE_FSTAT_CCIF_MASK (0x80U)
11994#define FTFE_FSTAT_CCIF_SHIFT (7U)
11999#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
12004#define FTFE_FCNFG_EEERDY_MASK (0x1U)
12005#define FTFE_FCNFG_EEERDY_SHIFT (0U)
12010#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
12011#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
12012#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
12017#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
12018#define FTFE_FCNFG_PFLSH_MASK (0x4U)
12019#define FTFE_FCNFG_PFLSH_SHIFT (2U)
12020#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
12021#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
12022#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
12027#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
12028#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
12029#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
12034#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
12035#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
12036#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
12041#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
12042#define FTFE_FCNFG_CCIE_MASK (0x80U)
12043#define FTFE_FCNFG_CCIE_SHIFT (7U)
12048#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
12053#define FTFE_FSEC_SEC_MASK (0x3U)
12054#define FTFE_FSEC_SEC_SHIFT (0U)
12061#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
12062#define FTFE_FSEC_FSLACC_MASK (0xCU)
12063#define FTFE_FSEC_FSLACC_SHIFT (2U)
12070#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
12071#define FTFE_FSEC_MEEN_MASK (0x30U)
12072#define FTFE_FSEC_MEEN_SHIFT (4U)
12079#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
12080#define FTFE_FSEC_KEYEN_MASK (0xC0U)
12081#define FTFE_FSEC_KEYEN_SHIFT (6U)
12088#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
12093#define FTFE_FOPT_OPT_MASK (0xFFU)
12094#define FTFE_FOPT_OPT_SHIFT (0U)
12095#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
12100#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
12101#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
12102#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
12107#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
12108#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
12109#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
12114#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
12115#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
12116#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
12121#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
12122#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
12123#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
12128#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
12129#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
12130#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
12135#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
12136#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
12137#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
12142#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
12143#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
12144#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
12149#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
12150#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
12151#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
12156#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
12157#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
12158#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
12163#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
12164#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
12165#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
12170#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
12171#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
12172#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
12177#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
12178#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
12179#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
12184#define FTFE_FPROT3_PROT_MASK (0xFFU)
12185#define FTFE_FPROT3_PROT_SHIFT (0U)
12190#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
12195#define FTFE_FPROT2_PROT_MASK (0xFFU)
12196#define FTFE_FPROT2_PROT_SHIFT (0U)
12201#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
12206#define FTFE_FPROT1_PROT_MASK (0xFFU)
12207#define FTFE_FPROT1_PROT_SHIFT (0U)
12212#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
12217#define FTFE_FPROT0_PROT_MASK (0xFFU)
12218#define FTFE_FPROT0_PROT_SHIFT (0U)
12223#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
12229 /* end of group FTFE_Register_Masks */
12230
12231
12232/* FTFE - Peripheral instance base addresses */
12234#define FTFE_BASE (0x40020000u)
12236#define FTFE ((FTFE_Type *)FTFE_BASE)
12238#define FTFE_BASE_ADDRS { FTFE_BASE }
12240#define FTFE_BASE_PTRS { FTFE }
12242#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
12243#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
12244
12247 /* end of group FTFE_Peripheral_Access_Layer */
12248
12249
12250/* ----------------------------------------------------------------------------
12251 -- FTM Peripheral Access Layer
12252 ---------------------------------------------------------------------------- */
12253
12260typedef struct {
12261 __IO uint32_t SC;
12262 __IO uint32_t CNT;
12263 __IO uint32_t MOD;
12264 struct { /* offset: 0xC, array step: 0x8 */
12265 __IO uint32_t CnSC;
12266 __IO uint32_t CnV;
12267 } CONTROLS[8];
12268 __IO uint32_t CNTIN;
12269 __IO uint32_t STATUS;
12270 __IO uint32_t MODE;
12271 __IO uint32_t SYNC;
12272 __IO uint32_t OUTINIT;
12273 __IO uint32_t OUTMASK;
12274 __IO uint32_t COMBINE;
12275 __IO uint32_t DEADTIME;
12276 __IO uint32_t EXTTRIG;
12277 __IO uint32_t POL;
12278 __IO uint32_t FMS;
12279 __IO uint32_t FILTER;
12280 __IO uint32_t FLTCTRL;
12281 __IO uint32_t QDCTRL;
12282 __IO uint32_t CONF;
12283 __IO uint32_t FLTPOL;
12284 __IO uint32_t SYNCONF;
12285 __IO uint32_t INVCTRL;
12286 __IO uint32_t SWOCTRL;
12287 __IO uint32_t PWMLOAD;
12288} FTM_Type;
12289
12290/* ----------------------------------------------------------------------------
12291 -- FTM Register Masks
12292 ---------------------------------------------------------------------------- */
12293
12301#define FTM_SC_PS_MASK (0x7U)
12302#define FTM_SC_PS_SHIFT (0U)
12313#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
12314#define FTM_SC_CLKS_MASK (0x18U)
12315#define FTM_SC_CLKS_SHIFT (3U)
12322#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
12323#define FTM_SC_CPWMS_MASK (0x20U)
12324#define FTM_SC_CPWMS_SHIFT (5U)
12329#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
12330#define FTM_SC_TOIE_MASK (0x40U)
12331#define FTM_SC_TOIE_SHIFT (6U)
12336#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
12337#define FTM_SC_TOF_MASK (0x80U)
12338#define FTM_SC_TOF_SHIFT (7U)
12343#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
12348#define FTM_CNT_COUNT_MASK (0xFFFFU)
12349#define FTM_CNT_COUNT_SHIFT (0U)
12350#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
12355#define FTM_MOD_MOD_MASK (0xFFFFU)
12356#define FTM_MOD_MOD_SHIFT (0U)
12357#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
12362#define FTM_CnSC_DMA_MASK (0x1U)
12363#define FTM_CnSC_DMA_SHIFT (0U)
12368#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
12369#define FTM_CnSC_ICRST_MASK (0x2U)
12370#define FTM_CnSC_ICRST_SHIFT (1U)
12375#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
12376#define FTM_CnSC_ELSA_MASK (0x4U)
12377#define FTM_CnSC_ELSA_SHIFT (2U)
12378#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
12379#define FTM_CnSC_ELSB_MASK (0x8U)
12380#define FTM_CnSC_ELSB_SHIFT (3U)
12381#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
12382#define FTM_CnSC_MSA_MASK (0x10U)
12383#define FTM_CnSC_MSA_SHIFT (4U)
12384#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
12385#define FTM_CnSC_MSB_MASK (0x20U)
12386#define FTM_CnSC_MSB_SHIFT (5U)
12387#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
12388#define FTM_CnSC_CHIE_MASK (0x40U)
12389#define FTM_CnSC_CHIE_SHIFT (6U)
12394#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
12395#define FTM_CnSC_CHF_MASK (0x80U)
12396#define FTM_CnSC_CHF_SHIFT (7U)
12401#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
12404/* The count of FTM_CnSC */
12405#define FTM_CnSC_COUNT (8U)
12406
12409#define FTM_CnV_VAL_MASK (0xFFFFU)
12410#define FTM_CnV_VAL_SHIFT (0U)
12411#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
12414/* The count of FTM_CnV */
12415#define FTM_CnV_COUNT (8U)
12416
12419#define FTM_CNTIN_INIT_MASK (0xFFFFU)
12420#define FTM_CNTIN_INIT_SHIFT (0U)
12421#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
12426#define FTM_STATUS_CH0F_MASK (0x1U)
12427#define FTM_STATUS_CH0F_SHIFT (0U)
12432#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
12433#define FTM_STATUS_CH1F_MASK (0x2U)
12434#define FTM_STATUS_CH1F_SHIFT (1U)
12439#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
12440#define FTM_STATUS_CH2F_MASK (0x4U)
12441#define FTM_STATUS_CH2F_SHIFT (2U)
12446#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
12447#define FTM_STATUS_CH3F_MASK (0x8U)
12448#define FTM_STATUS_CH3F_SHIFT (3U)
12453#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
12454#define FTM_STATUS_CH4F_MASK (0x10U)
12455#define FTM_STATUS_CH4F_SHIFT (4U)
12460#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
12461#define FTM_STATUS_CH5F_MASK (0x20U)
12462#define FTM_STATUS_CH5F_SHIFT (5U)
12467#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
12468#define FTM_STATUS_CH6F_MASK (0x40U)
12469#define FTM_STATUS_CH6F_SHIFT (6U)
12474#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
12475#define FTM_STATUS_CH7F_MASK (0x80U)
12476#define FTM_STATUS_CH7F_SHIFT (7U)
12481#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
12486#define FTM_MODE_FTMEN_MASK (0x1U)
12487#define FTM_MODE_FTMEN_SHIFT (0U)
12492#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
12493#define FTM_MODE_INIT_MASK (0x2U)
12494#define FTM_MODE_INIT_SHIFT (1U)
12495#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
12496#define FTM_MODE_WPDIS_MASK (0x4U)
12497#define FTM_MODE_WPDIS_SHIFT (2U)
12502#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
12503#define FTM_MODE_PWMSYNC_MASK (0x8U)
12504#define FTM_MODE_PWMSYNC_SHIFT (3U)
12509#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
12510#define FTM_MODE_CAPTEST_MASK (0x10U)
12511#define FTM_MODE_CAPTEST_SHIFT (4U)
12516#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
12517#define FTM_MODE_FAULTM_MASK (0x60U)
12518#define FTM_MODE_FAULTM_SHIFT (5U)
12525#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
12526#define FTM_MODE_FAULTIE_MASK (0x80U)
12527#define FTM_MODE_FAULTIE_SHIFT (7U)
12532#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
12537#define FTM_SYNC_CNTMIN_MASK (0x1U)
12538#define FTM_SYNC_CNTMIN_SHIFT (0U)
12543#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
12544#define FTM_SYNC_CNTMAX_MASK (0x2U)
12545#define FTM_SYNC_CNTMAX_SHIFT (1U)
12550#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
12551#define FTM_SYNC_REINIT_MASK (0x4U)
12552#define FTM_SYNC_REINIT_SHIFT (2U)
12557#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
12558#define FTM_SYNC_SYNCHOM_MASK (0x8U)
12559#define FTM_SYNC_SYNCHOM_SHIFT (3U)
12564#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
12565#define FTM_SYNC_TRIG0_MASK (0x10U)
12566#define FTM_SYNC_TRIG0_SHIFT (4U)
12571#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
12572#define FTM_SYNC_TRIG1_MASK (0x20U)
12573#define FTM_SYNC_TRIG1_SHIFT (5U)
12578#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
12579#define FTM_SYNC_TRIG2_MASK (0x40U)
12580#define FTM_SYNC_TRIG2_SHIFT (6U)
12585#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
12586#define FTM_SYNC_SWSYNC_MASK (0x80U)
12587#define FTM_SYNC_SWSYNC_SHIFT (7U)
12592#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
12597#define FTM_OUTINIT_CH0OI_MASK (0x1U)
12598#define FTM_OUTINIT_CH0OI_SHIFT (0U)
12603#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
12604#define FTM_OUTINIT_CH1OI_MASK (0x2U)
12605#define FTM_OUTINIT_CH1OI_SHIFT (1U)
12610#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
12611#define FTM_OUTINIT_CH2OI_MASK (0x4U)
12612#define FTM_OUTINIT_CH2OI_SHIFT (2U)
12617#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
12618#define FTM_OUTINIT_CH3OI_MASK (0x8U)
12619#define FTM_OUTINIT_CH3OI_SHIFT (3U)
12624#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
12625#define FTM_OUTINIT_CH4OI_MASK (0x10U)
12626#define FTM_OUTINIT_CH4OI_SHIFT (4U)
12631#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
12632#define FTM_OUTINIT_CH5OI_MASK (0x20U)
12633#define FTM_OUTINIT_CH5OI_SHIFT (5U)
12638#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
12639#define FTM_OUTINIT_CH6OI_MASK (0x40U)
12640#define FTM_OUTINIT_CH6OI_SHIFT (6U)
12645#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
12646#define FTM_OUTINIT_CH7OI_MASK (0x80U)
12647#define FTM_OUTINIT_CH7OI_SHIFT (7U)
12652#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
12657#define FTM_OUTMASK_CH0OM_MASK (0x1U)
12658#define FTM_OUTMASK_CH0OM_SHIFT (0U)
12663#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
12664#define FTM_OUTMASK_CH1OM_MASK (0x2U)
12665#define FTM_OUTMASK_CH1OM_SHIFT (1U)
12670#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
12671#define FTM_OUTMASK_CH2OM_MASK (0x4U)
12672#define FTM_OUTMASK_CH2OM_SHIFT (2U)
12677#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
12678#define FTM_OUTMASK_CH3OM_MASK (0x8U)
12679#define FTM_OUTMASK_CH3OM_SHIFT (3U)
12684#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
12685#define FTM_OUTMASK_CH4OM_MASK (0x10U)
12686#define FTM_OUTMASK_CH4OM_SHIFT (4U)
12691#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
12692#define FTM_OUTMASK_CH5OM_MASK (0x20U)
12693#define FTM_OUTMASK_CH5OM_SHIFT (5U)
12698#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
12699#define FTM_OUTMASK_CH6OM_MASK (0x40U)
12700#define FTM_OUTMASK_CH6OM_SHIFT (6U)
12705#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
12706#define FTM_OUTMASK_CH7OM_MASK (0x80U)
12707#define FTM_OUTMASK_CH7OM_SHIFT (7U)
12712#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
12717#define FTM_COMBINE_COMBINE0_MASK (0x1U)
12718#define FTM_COMBINE_COMBINE0_SHIFT (0U)
12723#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
12724#define FTM_COMBINE_COMP0_MASK (0x2U)
12725#define FTM_COMBINE_COMP0_SHIFT (1U)
12730#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
12731#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
12732#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
12737#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
12738#define FTM_COMBINE_DECAP0_MASK (0x8U)
12739#define FTM_COMBINE_DECAP0_SHIFT (3U)
12744#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
12745#define FTM_COMBINE_DTEN0_MASK (0x10U)
12746#define FTM_COMBINE_DTEN0_SHIFT (4U)
12751#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
12752#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
12753#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
12758#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
12759#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
12760#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
12765#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
12766#define FTM_COMBINE_COMBINE1_MASK (0x100U)
12767#define FTM_COMBINE_COMBINE1_SHIFT (8U)
12772#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
12773#define FTM_COMBINE_COMP1_MASK (0x200U)
12774#define FTM_COMBINE_COMP1_SHIFT (9U)
12779#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
12780#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
12781#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
12786#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
12787#define FTM_COMBINE_DECAP1_MASK (0x800U)
12788#define FTM_COMBINE_DECAP1_SHIFT (11U)
12793#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
12794#define FTM_COMBINE_DTEN1_MASK (0x1000U)
12795#define FTM_COMBINE_DTEN1_SHIFT (12U)
12800#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
12801#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
12802#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
12807#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
12808#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
12809#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
12814#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
12815#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
12816#define FTM_COMBINE_COMBINE2_SHIFT (16U)
12821#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
12822#define FTM_COMBINE_COMP2_MASK (0x20000U)
12823#define FTM_COMBINE_COMP2_SHIFT (17U)
12828#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
12829#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
12830#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
12835#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
12836#define FTM_COMBINE_DECAP2_MASK (0x80000U)
12837#define FTM_COMBINE_DECAP2_SHIFT (19U)
12842#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
12843#define FTM_COMBINE_DTEN2_MASK (0x100000U)
12844#define FTM_COMBINE_DTEN2_SHIFT (20U)
12849#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
12850#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
12851#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
12856#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
12857#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
12858#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
12863#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
12864#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
12865#define FTM_COMBINE_COMBINE3_SHIFT (24U)
12870#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
12871#define FTM_COMBINE_COMP3_MASK (0x2000000U)
12872#define FTM_COMBINE_COMP3_SHIFT (25U)
12877#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
12878#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
12879#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
12884#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
12885#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
12886#define FTM_COMBINE_DECAP3_SHIFT (27U)
12891#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
12892#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
12893#define FTM_COMBINE_DTEN3_SHIFT (28U)
12898#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
12899#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
12900#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
12905#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
12906#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
12907#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
12912#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
12917#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
12918#define FTM_DEADTIME_DTVAL_SHIFT (0U)
12919#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
12920#define FTM_DEADTIME_DTPS_MASK (0xC0U)
12921#define FTM_DEADTIME_DTPS_SHIFT (6U)
12927#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
12932#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
12933#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
12938#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
12939#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
12940#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
12945#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
12946#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
12947#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
12952#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
12953#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
12954#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
12959#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
12960#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
12961#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
12966#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
12967#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
12968#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
12973#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
12974#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
12975#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
12980#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
12981#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
12982#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
12987#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
12992#define FTM_POL_POL0_MASK (0x1U)
12993#define FTM_POL_POL0_SHIFT (0U)
12998#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
12999#define FTM_POL_POL1_MASK (0x2U)
13000#define FTM_POL_POL1_SHIFT (1U)
13005#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
13006#define FTM_POL_POL2_MASK (0x4U)
13007#define FTM_POL_POL2_SHIFT (2U)
13012#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
13013#define FTM_POL_POL3_MASK (0x8U)
13014#define FTM_POL_POL3_SHIFT (3U)
13019#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
13020#define FTM_POL_POL4_MASK (0x10U)
13021#define FTM_POL_POL4_SHIFT (4U)
13026#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
13027#define FTM_POL_POL5_MASK (0x20U)
13028#define FTM_POL_POL5_SHIFT (5U)
13033#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
13034#define FTM_POL_POL6_MASK (0x40U)
13035#define FTM_POL_POL6_SHIFT (6U)
13040#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
13041#define FTM_POL_POL7_MASK (0x80U)
13042#define FTM_POL_POL7_SHIFT (7U)
13047#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
13052#define FTM_FMS_FAULTF0_MASK (0x1U)
13053#define FTM_FMS_FAULTF0_SHIFT (0U)
13058#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
13059#define FTM_FMS_FAULTF1_MASK (0x2U)
13060#define FTM_FMS_FAULTF1_SHIFT (1U)
13065#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
13066#define FTM_FMS_FAULTF2_MASK (0x4U)
13067#define FTM_FMS_FAULTF2_SHIFT (2U)
13072#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
13073#define FTM_FMS_FAULTF3_MASK (0x8U)
13074#define FTM_FMS_FAULTF3_SHIFT (3U)
13079#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
13080#define FTM_FMS_FAULTIN_MASK (0x20U)
13081#define FTM_FMS_FAULTIN_SHIFT (5U)
13086#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
13087#define FTM_FMS_WPEN_MASK (0x40U)
13088#define FTM_FMS_WPEN_SHIFT (6U)
13093#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
13094#define FTM_FMS_FAULTF_MASK (0x80U)
13095#define FTM_FMS_FAULTF_SHIFT (7U)
13100#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
13105#define FTM_FILTER_CH0FVAL_MASK (0xFU)
13106#define FTM_FILTER_CH0FVAL_SHIFT (0U)
13107#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
13108#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
13109#define FTM_FILTER_CH1FVAL_SHIFT (4U)
13110#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
13111#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
13112#define FTM_FILTER_CH2FVAL_SHIFT (8U)
13113#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
13114#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
13115#define FTM_FILTER_CH3FVAL_SHIFT (12U)
13116#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
13121#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
13122#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
13127#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
13128#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
13129#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
13134#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
13135#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
13136#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
13141#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
13142#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
13143#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
13148#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
13149#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
13150#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
13155#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
13156#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
13157#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
13162#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
13163#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
13164#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
13169#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
13170#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
13171#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
13176#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
13177#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
13178#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
13179#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
13184#define FTM_QDCTRL_QUADEN_MASK (0x1U)
13185#define FTM_QDCTRL_QUADEN_SHIFT (0U)
13190#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
13191#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
13192#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
13197#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
13198#define FTM_QDCTRL_QUADIR_MASK (0x4U)
13199#define FTM_QDCTRL_QUADIR_SHIFT (2U)
13204#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
13205#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
13206#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
13211#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
13212#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
13213#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
13218#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
13219#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
13220#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
13225#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
13226#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
13227#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
13232#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
13233#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
13234#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
13239#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
13244#define FTM_CONF_NUMTOF_MASK (0x1FU)
13245#define FTM_CONF_NUMTOF_SHIFT (0U)
13246#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
13247#define FTM_CONF_BDMMODE_MASK (0xC0U)
13248#define FTM_CONF_BDMMODE_SHIFT (6U)
13249#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
13250#define FTM_CONF_GTBEEN_MASK (0x200U)
13251#define FTM_CONF_GTBEEN_SHIFT (9U)
13256#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
13257#define FTM_CONF_GTBEOUT_MASK (0x400U)
13258#define FTM_CONF_GTBEOUT_SHIFT (10U)
13263#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
13268#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
13269#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
13274#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
13275#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
13276#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
13281#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
13282#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
13283#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
13288#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
13289#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
13290#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
13295#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
13300#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
13301#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
13306#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
13307#define FTM_SYNCONF_CNTINC_MASK (0x4U)
13308#define FTM_SYNCONF_CNTINC_SHIFT (2U)
13313#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
13314#define FTM_SYNCONF_INVC_MASK (0x10U)
13315#define FTM_SYNCONF_INVC_SHIFT (4U)
13320#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
13321#define FTM_SYNCONF_SWOC_MASK (0x20U)
13322#define FTM_SYNCONF_SWOC_SHIFT (5U)
13327#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
13328#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
13329#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
13334#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
13335#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
13336#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
13341#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
13342#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
13343#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
13348#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
13349#define FTM_SYNCONF_SWOM_MASK (0x400U)
13350#define FTM_SYNCONF_SWOM_SHIFT (10U)
13355#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
13356#define FTM_SYNCONF_SWINVC_MASK (0x800U)
13357#define FTM_SYNCONF_SWINVC_SHIFT (11U)
13362#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
13363#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
13364#define FTM_SYNCONF_SWSOC_SHIFT (12U)
13369#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
13370#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
13371#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
13376#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
13377#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
13378#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
13383#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
13384#define FTM_SYNCONF_HWOM_MASK (0x40000U)
13385#define FTM_SYNCONF_HWOM_SHIFT (18U)
13390#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
13391#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
13392#define FTM_SYNCONF_HWINVC_SHIFT (19U)
13397#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
13398#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
13399#define FTM_SYNCONF_HWSOC_SHIFT (20U)
13404#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
13409#define FTM_INVCTRL_INV0EN_MASK (0x1U)
13410#define FTM_INVCTRL_INV0EN_SHIFT (0U)
13415#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
13416#define FTM_INVCTRL_INV1EN_MASK (0x2U)
13417#define FTM_INVCTRL_INV1EN_SHIFT (1U)
13422#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
13423#define FTM_INVCTRL_INV2EN_MASK (0x4U)
13424#define FTM_INVCTRL_INV2EN_SHIFT (2U)
13429#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
13430#define FTM_INVCTRL_INV3EN_MASK (0x8U)
13431#define FTM_INVCTRL_INV3EN_SHIFT (3U)
13436#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
13441#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
13442#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
13447#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
13448#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
13449#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
13454#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
13455#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
13456#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
13461#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
13462#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
13463#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
13468#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
13469#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
13470#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
13475#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
13476#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
13477#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
13482#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
13483#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
13484#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
13489#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
13490#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
13491#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
13496#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
13497#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
13498#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
13503#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
13504#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
13505#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
13510#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
13511#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
13512#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
13517#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
13518#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
13519#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
13524#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
13525#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
13526#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
13531#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
13532#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
13533#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
13538#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
13539#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
13540#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
13545#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
13546#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
13547#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
13552#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
13557#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
13558#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
13563#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
13564#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
13565#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
13570#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
13571#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
13572#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
13577#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
13578#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
13579#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
13584#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
13585#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
13586#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
13591#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
13592#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
13593#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
13598#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
13599#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
13600#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
13605#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
13606#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
13607#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
13612#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
13613#define FTM_PWMLOAD_LDOK_MASK (0x200U)
13614#define FTM_PWMLOAD_LDOK_SHIFT (9U)
13619#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
13625 /* end of group FTM_Register_Masks */
13626
13627
13628/* FTM - Peripheral instance base addresses */
13630#define FTM0_BASE (0x40038000u)
13632#define FTM0 ((FTM_Type *)FTM0_BASE)
13634#define FTM1_BASE (0x40039000u)
13636#define FTM1 ((FTM_Type *)FTM1_BASE)
13638#define FTM2_BASE (0x4003A000u)
13640#define FTM2 ((FTM_Type *)FTM2_BASE)
13642#define FTM3_BASE (0x40026000u)
13644#define FTM3 ((FTM_Type *)FTM3_BASE)
13646#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
13648#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
13650#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
13651
13654 /* end of group FTM_Peripheral_Access_Layer */
13655
13656
13657/* ----------------------------------------------------------------------------
13658 -- GPIO Peripheral Access Layer
13659 ---------------------------------------------------------------------------- */
13660
13667typedef struct {
13668 __IO uint32_t PDOR;
13669 __O uint32_t PSOR;
13670 __O uint32_t PCOR;
13671 __O uint32_t PTOR;
13672 __I uint32_t PDIR;
13673 __IO uint32_t PDDR;
13674} GPIO_Type;
13675
13676/* ----------------------------------------------------------------------------
13677 -- GPIO Register Masks
13678 ---------------------------------------------------------------------------- */
13679
13687#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
13688#define GPIO_PDOR_PDO_SHIFT (0U)
13693#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
13698#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
13699#define GPIO_PSOR_PTSO_SHIFT (0U)
13704#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
13709#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
13710#define GPIO_PCOR_PTCO_SHIFT (0U)
13715#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
13720#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
13721#define GPIO_PTOR_PTTO_SHIFT (0U)
13726#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
13731#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
13732#define GPIO_PDIR_PDI_SHIFT (0U)
13737#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
13742#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
13743#define GPIO_PDDR_PDD_SHIFT (0U)
13748#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
13754 /* end of group GPIO_Register_Masks */
13755
13756
13757/* GPIO - Peripheral instance base addresses */
13759#define GPIOA_BASE (0x400FF000u)
13761#define GPIOA ((GPIO_Type *)GPIOA_BASE)
13763#define GPIOB_BASE (0x400FF040u)
13765#define GPIOB ((GPIO_Type *)GPIOB_BASE)
13767#define GPIOC_BASE (0x400FF080u)
13769#define GPIOC ((GPIO_Type *)GPIOC_BASE)
13771#define GPIOD_BASE (0x400FF0C0u)
13773#define GPIOD ((GPIO_Type *)GPIOD_BASE)
13775#define GPIOE_BASE (0x400FF100u)
13777#define GPIOE ((GPIO_Type *)GPIOE_BASE)
13779#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
13781#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
13782
13785 /* end of group GPIO_Peripheral_Access_Layer */
13786
13787
13788/* ----------------------------------------------------------------------------
13789 -- HSADC Peripheral Access Layer
13790 ---------------------------------------------------------------------------- */
13791
13798typedef struct {
13799 __IO uint16_t CTRL1;
13800 __IO uint16_t CTRL2;
13801 __IO uint16_t ZXCTRL1;
13802 __IO uint16_t ZXCTRL2;
13803 __IO uint16_t CLIST1;
13804 __IO uint16_t CLIST2;
13805 __IO uint16_t CLIST3;
13806 __IO uint16_t CLIST4;
13807 __IO uint16_t SDIS;
13808 __IO uint16_t STAT;
13809 __I uint16_t RDY;
13810 __IO uint16_t LOLIMSTAT;
13811 __IO uint16_t HILIMSTAT;
13812 __IO uint16_t ZXSTAT;
13813 __IO uint16_t RSLT[16];
13814 __IO uint16_t LOLIM[16];
13815 __IO uint16_t HILIM[16];
13816 __IO uint16_t OFFST[16];
13817 __IO uint16_t PWR;
13818 uint8_t RESERVED_0[6];
13819 __IO uint16_t SCTRL;
13820 __IO uint16_t PWR2;
13821 __IO uint16_t CTRL3;
13822 __IO uint16_t SCINTEN;
13823 __IO uint16_t SAMPTIM;
13824 __IO uint16_t CALIB;
13825 __IO uint16_t CALVAL_A;
13826 __IO uint16_t CALVAL_B;
13827 uint8_t RESERVED_1[6];
13828 __IO uint16_t MUX67_SEL;
13829} HSADC_Type;
13830
13831/* ----------------------------------------------------------------------------
13832 -- HSADC Register Masks
13833 ---------------------------------------------------------------------------- */
13834
13842#define HSADC_CTRL1_SMODE_MASK (0x7U)
13843#define HSADC_CTRL1_SMODE_SHIFT (0U)
13853#define HSADC_CTRL1_SMODE(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_SMODE_SHIFT)) & HSADC_CTRL1_SMODE_MASK)
13854#define HSADC_CTRL1_CHNCFG_L_MASK (0xF0U)
13855#define HSADC_CTRL1_CHNCFG_L_SHIFT (4U)
13865#define HSADC_CTRL1_CHNCFG_L(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_CHNCFG_L_SHIFT)) & HSADC_CTRL1_CHNCFG_L_MASK)
13866#define HSADC_CTRL1_HLMTIE_MASK (0x100U)
13867#define HSADC_CTRL1_HLMTIE_SHIFT (8U)
13872#define HSADC_CTRL1_HLMTIE(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_HLMTIE_SHIFT)) & HSADC_CTRL1_HLMTIE_MASK)
13873#define HSADC_CTRL1_LLMTIE_MASK (0x200U)
13874#define HSADC_CTRL1_LLMTIE_SHIFT (9U)
13879#define HSADC_CTRL1_LLMTIE(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_LLMTIE_SHIFT)) & HSADC_CTRL1_LLMTIE_MASK)
13880#define HSADC_CTRL1_ZCIE_MASK (0x400U)
13881#define HSADC_CTRL1_ZCIE_SHIFT (10U)
13886#define HSADC_CTRL1_ZCIE(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_ZCIE_SHIFT)) & HSADC_CTRL1_ZCIE_MASK)
13887#define HSADC_CTRL1_EOSIEA_MASK (0x800U)
13888#define HSADC_CTRL1_EOSIEA_SHIFT (11U)
13893#define HSADC_CTRL1_EOSIEA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_EOSIEA_SHIFT)) & HSADC_CTRL1_EOSIEA_MASK)
13894#define HSADC_CTRL1_SYNCA_MASK (0x1000U)
13895#define HSADC_CTRL1_SYNCA_SHIFT (12U)
13900#define HSADC_CTRL1_SYNCA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_SYNCA_SHIFT)) & HSADC_CTRL1_SYNCA_MASK)
13901#define HSADC_CTRL1_STARTA_MASK (0x2000U)
13902#define HSADC_CTRL1_STARTA_SHIFT (13U)
13907#define HSADC_CTRL1_STARTA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_STARTA_SHIFT)) & HSADC_CTRL1_STARTA_MASK)
13908#define HSADC_CTRL1_STOPA_MASK (0x4000U)
13909#define HSADC_CTRL1_STOPA_SHIFT (14U)
13914#define HSADC_CTRL1_STOPA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_STOPA_SHIFT)) & HSADC_CTRL1_STOPA_MASK)
13915#define HSADC_CTRL1_DMAENA_MASK (0x8000U)
13916#define HSADC_CTRL1_DMAENA_SHIFT (15U)
13921#define HSADC_CTRL1_DMAENA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_DMAENA_SHIFT)) & HSADC_CTRL1_DMAENA_MASK)
13926#define HSADC_CTRL2_DIVA_MASK (0x3FU)
13927#define HSADC_CTRL2_DIVA_SHIFT (0U)
13928#define HSADC_CTRL2_DIVA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_DIVA_SHIFT)) & HSADC_CTRL2_DIVA_MASK)
13929#define HSADC_CTRL2_SIMULT_MASK (0x40U)
13930#define HSADC_CTRL2_SIMULT_SHIFT (6U)
13935#define HSADC_CTRL2_SIMULT(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_SIMULT_SHIFT)) & HSADC_CTRL2_SIMULT_MASK)
13936#define HSADC_CTRL2_CHNCFG_H_MASK (0x780U)
13937#define HSADC_CTRL2_CHNCFG_H_SHIFT (7U)
13947#define HSADC_CTRL2_CHNCFG_H(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_CHNCFG_H_SHIFT)) & HSADC_CTRL2_CHNCFG_H_MASK)
13948#define HSADC_CTRL2_EOSIEB_MASK (0x800U)
13949#define HSADC_CTRL2_EOSIEB_SHIFT (11U)
13954#define HSADC_CTRL2_EOSIEB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_EOSIEB_SHIFT)) & HSADC_CTRL2_EOSIEB_MASK)
13955#define HSADC_CTRL2_SYNCB_MASK (0x1000U)
13956#define HSADC_CTRL2_SYNCB_SHIFT (12U)
13961#define HSADC_CTRL2_SYNCB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_SYNCB_SHIFT)) & HSADC_CTRL2_SYNCB_MASK)
13962#define HSADC_CTRL2_STARTB_MASK (0x2000U)
13963#define HSADC_CTRL2_STARTB_SHIFT (13U)
13968#define HSADC_CTRL2_STARTB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_STARTB_SHIFT)) & HSADC_CTRL2_STARTB_MASK)
13969#define HSADC_CTRL2_STOPB_MASK (0x4000U)
13970#define HSADC_CTRL2_STOPB_SHIFT (14U)
13975#define HSADC_CTRL2_STOPB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_STOPB_SHIFT)) & HSADC_CTRL2_STOPB_MASK)
13976#define HSADC_CTRL2_DMAENB_MASK (0x8000U)
13977#define HSADC_CTRL2_DMAENB_SHIFT (15U)
13982#define HSADC_CTRL2_DMAENB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_DMAENB_SHIFT)) & HSADC_CTRL2_DMAENB_MASK)
13987#define HSADC_ZXCTRL1_ZCE0_MASK (0x3U)
13988#define HSADC_ZXCTRL1_ZCE0_SHIFT (0U)
13995#define HSADC_ZXCTRL1_ZCE0(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE0_SHIFT)) & HSADC_ZXCTRL1_ZCE0_MASK)
13996#define HSADC_ZXCTRL1_ZCE1_MASK (0xCU)
13997#define HSADC_ZXCTRL1_ZCE1_SHIFT (2U)
14004#define HSADC_ZXCTRL1_ZCE1(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE1_SHIFT)) & HSADC_ZXCTRL1_ZCE1_MASK)
14005#define HSADC_ZXCTRL1_ZCE2_MASK (0x30U)
14006#define HSADC_ZXCTRL1_ZCE2_SHIFT (4U)
14013#define HSADC_ZXCTRL1_ZCE2(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE2_SHIFT)) & HSADC_ZXCTRL1_ZCE2_MASK)
14014#define HSADC_ZXCTRL1_ZCE3_MASK (0xC0U)
14015#define HSADC_ZXCTRL1_ZCE3_SHIFT (6U)
14022#define HSADC_ZXCTRL1_ZCE3(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE3_SHIFT)) & HSADC_ZXCTRL1_ZCE3_MASK)
14023#define HSADC_ZXCTRL1_ZCE4_MASK (0x300U)
14024#define HSADC_ZXCTRL1_ZCE4_SHIFT (8U)
14031#define HSADC_ZXCTRL1_ZCE4(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE4_SHIFT)) & HSADC_ZXCTRL1_ZCE4_MASK)
14032#define HSADC_ZXCTRL1_ZCE5_MASK (0xC00U)
14033#define HSADC_ZXCTRL1_ZCE5_SHIFT (10U)
14040#define HSADC_ZXCTRL1_ZCE5(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE5_SHIFT)) & HSADC_ZXCTRL1_ZCE5_MASK)
14041#define HSADC_ZXCTRL1_ZCE6_MASK (0x3000U)
14042#define HSADC_ZXCTRL1_ZCE6_SHIFT (12U)
14049#define HSADC_ZXCTRL1_ZCE6(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE6_SHIFT)) & HSADC_ZXCTRL1_ZCE6_MASK)
14050#define HSADC_ZXCTRL1_ZCE7_MASK (0xC000U)
14051#define HSADC_ZXCTRL1_ZCE7_SHIFT (14U)
14058#define HSADC_ZXCTRL1_ZCE7(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE7_SHIFT)) & HSADC_ZXCTRL1_ZCE7_MASK)
14063#define HSADC_ZXCTRL2_ZCE8_MASK (0x3U)
14064#define HSADC_ZXCTRL2_ZCE8_SHIFT (0U)
14071#define HSADC_ZXCTRL2_ZCE8(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE8_SHIFT)) & HSADC_ZXCTRL2_ZCE8_MASK)
14072#define HSADC_ZXCTRL2_ZCE9_MASK (0xCU)
14073#define HSADC_ZXCTRL2_ZCE9_SHIFT (2U)
14080#define HSADC_ZXCTRL2_ZCE9(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE9_SHIFT)) & HSADC_ZXCTRL2_ZCE9_MASK)
14081#define HSADC_ZXCTRL2_ZCE10_MASK (0x30U)
14082#define HSADC_ZXCTRL2_ZCE10_SHIFT (4U)
14089#define HSADC_ZXCTRL2_ZCE10(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE10_SHIFT)) & HSADC_ZXCTRL2_ZCE10_MASK)
14090#define HSADC_ZXCTRL2_ZCE11_MASK (0xC0U)
14091#define HSADC_ZXCTRL2_ZCE11_SHIFT (6U)
14098#define HSADC_ZXCTRL2_ZCE11(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE11_SHIFT)) & HSADC_ZXCTRL2_ZCE11_MASK)
14099#define HSADC_ZXCTRL2_ZCE12_MASK (0x300U)
14100#define HSADC_ZXCTRL2_ZCE12_SHIFT (8U)
14107#define HSADC_ZXCTRL2_ZCE12(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE12_SHIFT)) & HSADC_ZXCTRL2_ZCE12_MASK)
14108#define HSADC_ZXCTRL2_ZCE13_MASK (0xC00U)
14109#define HSADC_ZXCTRL2_ZCE13_SHIFT (10U)
14116#define HSADC_ZXCTRL2_ZCE13(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE13_SHIFT)) & HSADC_ZXCTRL2_ZCE13_MASK)
14117#define HSADC_ZXCTRL2_ZCE14_MASK (0x3000U)
14118#define HSADC_ZXCTRL2_ZCE14_SHIFT (12U)
14125#define HSADC_ZXCTRL2_ZCE14(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE14_SHIFT)) & HSADC_ZXCTRL2_ZCE14_MASK)
14126#define HSADC_ZXCTRL2_ZCE15_MASK (0xC000U)
14127#define HSADC_ZXCTRL2_ZCE15_SHIFT (14U)
14134#define HSADC_ZXCTRL2_ZCE15(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE15_SHIFT)) & HSADC_ZXCTRL2_ZCE15_MASK)
14139#define HSADC_CLIST1_SAMPLE0_MASK (0xFU)
14140#define HSADC_CLIST1_SAMPLE0_SHIFT (0U)
14159#define HSADC_CLIST1_SAMPLE0(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE0_SHIFT)) & HSADC_CLIST1_SAMPLE0_MASK)
14160#define HSADC_CLIST1_SAMPLE1_MASK (0xF0U)
14161#define HSADC_CLIST1_SAMPLE1_SHIFT (4U)
14180#define HSADC_CLIST1_SAMPLE1(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE1_SHIFT)) & HSADC_CLIST1_SAMPLE1_MASK)
14181#define HSADC_CLIST1_SAMPLE2_MASK (0xF00U)
14182#define HSADC_CLIST1_SAMPLE2_SHIFT (8U)
14201#define HSADC_CLIST1_SAMPLE2(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE2_SHIFT)) & HSADC_CLIST1_SAMPLE2_MASK)
14202#define HSADC_CLIST1_SAMPLE3_MASK (0xF000U)
14203#define HSADC_CLIST1_SAMPLE3_SHIFT (12U)
14222#define HSADC_CLIST1_SAMPLE3(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE3_SHIFT)) & HSADC_CLIST1_SAMPLE3_MASK)
14227#define HSADC_CLIST2_SAMPLE4_MASK (0xFU)
14228#define HSADC_CLIST2_SAMPLE4_SHIFT (0U)
14247#define HSADC_CLIST2_SAMPLE4(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE4_SHIFT)) & HSADC_CLIST2_SAMPLE4_MASK)
14248#define HSADC_CLIST2_SAMPLE5_MASK (0xF0U)
14249#define HSADC_CLIST2_SAMPLE5_SHIFT (4U)
14268#define HSADC_CLIST2_SAMPLE5(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE5_SHIFT)) & HSADC_CLIST2_SAMPLE5_MASK)
14269#define HSADC_CLIST2_SAMPLE6_MASK (0xF00U)
14270#define HSADC_CLIST2_SAMPLE6_SHIFT (8U)
14289#define HSADC_CLIST2_SAMPLE6(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE6_SHIFT)) & HSADC_CLIST2_SAMPLE6_MASK)
14290#define HSADC_CLIST2_SAMPLE7_MASK (0xF000U)
14291#define HSADC_CLIST2_SAMPLE7_SHIFT (12U)
14310#define HSADC_CLIST2_SAMPLE7(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE7_SHIFT)) & HSADC_CLIST2_SAMPLE7_MASK)
14315#define HSADC_CLIST3_SAMPLE8_MASK (0xFU)
14316#define HSADC_CLIST3_SAMPLE8_SHIFT (0U)
14335#define HSADC_CLIST3_SAMPLE8(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE8_SHIFT)) & HSADC_CLIST3_SAMPLE8_MASK)
14336#define HSADC_CLIST3_SAMPLE9_MASK (0xF0U)
14337#define HSADC_CLIST3_SAMPLE9_SHIFT (4U)
14356#define HSADC_CLIST3_SAMPLE9(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE9_SHIFT)) & HSADC_CLIST3_SAMPLE9_MASK)
14357#define HSADC_CLIST3_SAMPLE10_MASK (0xF00U)
14358#define HSADC_CLIST3_SAMPLE10_SHIFT (8U)
14377#define HSADC_CLIST3_SAMPLE10(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE10_SHIFT)) & HSADC_CLIST3_SAMPLE10_MASK)
14378#define HSADC_CLIST3_SAMPLE11_MASK (0xF000U)
14379#define HSADC_CLIST3_SAMPLE11_SHIFT (12U)
14398#define HSADC_CLIST3_SAMPLE11(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE11_SHIFT)) & HSADC_CLIST3_SAMPLE11_MASK)
14403#define HSADC_CLIST4_SAMPLE12_MASK (0xFU)
14404#define HSADC_CLIST4_SAMPLE12_SHIFT (0U)
14423#define HSADC_CLIST4_SAMPLE12(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE12_SHIFT)) & HSADC_CLIST4_SAMPLE12_MASK)
14424#define HSADC_CLIST4_SAMPLE13_MASK (0xF0U)
14425#define HSADC_CLIST4_SAMPLE13_SHIFT (4U)
14444#define HSADC_CLIST4_SAMPLE13(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE13_SHIFT)) & HSADC_CLIST4_SAMPLE13_MASK)
14445#define HSADC_CLIST4_SAMPLE14_MASK (0xF00U)
14446#define HSADC_CLIST4_SAMPLE14_SHIFT (8U)
14465#define HSADC_CLIST4_SAMPLE14(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE14_SHIFT)) & HSADC_CLIST4_SAMPLE14_MASK)
14466#define HSADC_CLIST4_SAMPLE15_MASK (0xF000U)
14467#define HSADC_CLIST4_SAMPLE15_SHIFT (12U)
14486#define HSADC_CLIST4_SAMPLE15(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE15_SHIFT)) & HSADC_CLIST4_SAMPLE15_MASK)
14491#define HSADC_SDIS_DS_MASK (0xFFFFU)
14492#define HSADC_SDIS_DS_SHIFT (0U)
14497#define HSADC_SDIS_DS(x) (((uint16_t)(((uint16_t)(x)) << HSADC_SDIS_DS_SHIFT)) & HSADC_SDIS_DS_MASK)
14502#define HSADC_STAT_CALONA_MASK (0x1U)
14503#define HSADC_STAT_CALONA_SHIFT (0U)
14508#define HSADC_STAT_CALONA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CALONA_SHIFT)) & HSADC_STAT_CALONA_MASK)
14509#define HSADC_STAT_CALONB_MASK (0x2U)
14510#define HSADC_STAT_CALONB_SHIFT (1U)
14515#define HSADC_STAT_CALONB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CALONB_SHIFT)) & HSADC_STAT_CALONB_MASK)
14516#define HSADC_STAT_DUMMYA_MASK (0x4U)
14517#define HSADC_STAT_DUMMYA_SHIFT (2U)
14522#define HSADC_STAT_DUMMYA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_DUMMYA_SHIFT)) & HSADC_STAT_DUMMYA_MASK)
14523#define HSADC_STAT_DUMMYB_MASK (0x8U)
14524#define HSADC_STAT_DUMMYB_SHIFT (3U)
14529#define HSADC_STAT_DUMMYB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_DUMMYB_SHIFT)) & HSADC_STAT_DUMMYB_MASK)
14530#define HSADC_STAT_EOCALIA_MASK (0x10U)
14531#define HSADC_STAT_EOCALIA_SHIFT (4U)
14536#define HSADC_STAT_EOCALIA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOCALIA_SHIFT)) & HSADC_STAT_EOCALIA_MASK)
14537#define HSADC_STAT_EOCALIB_MASK (0x20U)
14538#define HSADC_STAT_EOCALIB_SHIFT (5U)
14543#define HSADC_STAT_EOCALIB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOCALIB_SHIFT)) & HSADC_STAT_EOCALIB_MASK)
14544#define HSADC_STAT_HLMTI_MASK (0x100U)
14545#define HSADC_STAT_HLMTI_SHIFT (8U)
14550#define HSADC_STAT_HLMTI(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_HLMTI_SHIFT)) & HSADC_STAT_HLMTI_MASK)
14551#define HSADC_STAT_LLMTI_MASK (0x200U)
14552#define HSADC_STAT_LLMTI_SHIFT (9U)
14557#define HSADC_STAT_LLMTI(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_LLMTI_SHIFT)) & HSADC_STAT_LLMTI_MASK)
14558#define HSADC_STAT_ZCI_MASK (0x400U)
14559#define HSADC_STAT_ZCI_SHIFT (10U)
14564#define HSADC_STAT_ZCI(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_ZCI_SHIFT)) & HSADC_STAT_ZCI_MASK)
14565#define HSADC_STAT_EOSIA_MASK (0x800U)
14566#define HSADC_STAT_EOSIA_SHIFT (11U)
14571#define HSADC_STAT_EOSIA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOSIA_SHIFT)) & HSADC_STAT_EOSIA_MASK)
14572#define HSADC_STAT_EOSIB_MASK (0x1000U)
14573#define HSADC_STAT_EOSIB_SHIFT (12U)
14578#define HSADC_STAT_EOSIB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOSIB_SHIFT)) & HSADC_STAT_EOSIB_MASK)
14579#define HSADC_STAT_CIPB_MASK (0x4000U)
14580#define HSADC_STAT_CIPB_SHIFT (14U)
14585#define HSADC_STAT_CIPB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CIPB_SHIFT)) & HSADC_STAT_CIPB_MASK)
14586#define HSADC_STAT_CIPA_MASK (0x8000U)
14587#define HSADC_STAT_CIPA_SHIFT (15U)
14592#define HSADC_STAT_CIPA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CIPA_SHIFT)) & HSADC_STAT_CIPA_MASK)
14597#define HSADC_RDY_RDY_MASK (0xFFFFU)
14598#define HSADC_RDY_RDY_SHIFT (0U)
14603#define HSADC_RDY_RDY(x) (((uint16_t)(((uint16_t)(x)) << HSADC_RDY_RDY_SHIFT)) & HSADC_RDY_RDY_MASK)
14608#define HSADC_LOLIMSTAT_LLS_MASK (0xFFFFU)
14609#define HSADC_LOLIMSTAT_LLS_SHIFT (0U)
14610#define HSADC_LOLIMSTAT_LLS(x) (((uint16_t)(((uint16_t)(x)) << HSADC_LOLIMSTAT_LLS_SHIFT)) & HSADC_LOLIMSTAT_LLS_MASK)
14615#define HSADC_HILIMSTAT_HLS_MASK (0xFFFFU)
14616#define HSADC_HILIMSTAT_HLS_SHIFT (0U)
14617#define HSADC_HILIMSTAT_HLS(x) (((uint16_t)(((uint16_t)(x)) << HSADC_HILIMSTAT_HLS_SHIFT)) & HSADC_HILIMSTAT_HLS_MASK)
14622#define HSADC_ZXSTAT_ZCS_MASK (0xFFFFU)
14623#define HSADC_ZXSTAT_ZCS_SHIFT (0U)
14628#define HSADC_ZXSTAT_ZCS(x) (((uint16_t)(((uint16_t)(x)) << HSADC_ZXSTAT_ZCS_SHIFT)) & HSADC_ZXSTAT_ZCS_MASK)
14633#define HSADC_RSLT_RSLT_MASK (0x7FF8U)
14634#define HSADC_RSLT_RSLT_SHIFT (3U)
14635#define HSADC_RSLT_RSLT(x) (((uint16_t)(((uint16_t)(x)) << HSADC_RSLT_RSLT_SHIFT)) & HSADC_RSLT_RSLT_MASK)
14636#define HSADC_RSLT_SEXT_MASK (0x8000U)
14637#define HSADC_RSLT_SEXT_SHIFT (15U)
14638#define HSADC_RSLT_SEXT(x) (((uint16_t)(((uint16_t)(x)) << HSADC_RSLT_SEXT_SHIFT)) & HSADC_RSLT_SEXT_MASK)
14641/* The count of HSADC_RSLT */
14642#define HSADC_RSLT_COUNT (16U)
14643
14646#define HSADC_LOLIM_LLMT_MASK (0x7FF8U)
14647#define HSADC_LOLIM_LLMT_SHIFT (3U)
14648#define HSADC_LOLIM_LLMT(x) (((uint16_t)(((uint16_t)(x)) << HSADC_LOLIM_LLMT_SHIFT)) & HSADC_LOLIM_LLMT_MASK)
14651/* The count of HSADC_LOLIM */
14652#define HSADC_LOLIM_COUNT (16U)
14653
14656#define HSADC_HILIM_HLMT_MASK (0x7FF8U)
14657#define HSADC_HILIM_HLMT_SHIFT (3U)
14658#define HSADC_HILIM_HLMT(x) (((uint16_t)(((uint16_t)(x)) << HSADC_HILIM_HLMT_SHIFT)) & HSADC_HILIM_HLMT_MASK)
14661/* The count of HSADC_HILIM */
14662#define HSADC_HILIM_COUNT (16U)
14663
14666#define HSADC_OFFST_OFFSET_MASK (0x7FF8U)
14667#define HSADC_OFFST_OFFSET_SHIFT (3U)
14668#define HSADC_OFFST_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << HSADC_OFFST_OFFSET_SHIFT)) & HSADC_OFFST_OFFSET_MASK)
14671/* The count of HSADC_OFFST */
14672#define HSADC_OFFST_COUNT (16U)
14673
14676#define HSADC_PWR_PDA_MASK (0x1U)
14677#define HSADC_PWR_PDA_SHIFT (0U)
14682#define HSADC_PWR_PDA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PDA_SHIFT)) & HSADC_PWR_PDA_MASK)
14683#define HSADC_PWR_PDB_MASK (0x2U)
14684#define HSADC_PWR_PDB_SHIFT (1U)
14689#define HSADC_PWR_PDB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PDB_SHIFT)) & HSADC_PWR_PDB_MASK)
14690#define HSADC_PWR_APD_MASK (0x8U)
14691#define HSADC_PWR_APD_SHIFT (3U)
14696#define HSADC_PWR_APD(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_APD_SHIFT)) & HSADC_PWR_APD_MASK)
14697#define HSADC_PWR_PUDELAY_MASK (0x3F0U)
14698#define HSADC_PWR_PUDELAY_SHIFT (4U)
14699#define HSADC_PWR_PUDELAY(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PUDELAY_SHIFT)) & HSADC_PWR_PUDELAY_MASK)
14700#define HSADC_PWR_PSTSA_MASK (0x400U)
14701#define HSADC_PWR_PSTSA_SHIFT (10U)
14706#define HSADC_PWR_PSTSA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PSTSA_SHIFT)) & HSADC_PWR_PSTSA_MASK)
14707#define HSADC_PWR_PSTSB_MASK (0x800U)
14708#define HSADC_PWR_PSTSB_SHIFT (11U)
14713#define HSADC_PWR_PSTSB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PSTSB_SHIFT)) & HSADC_PWR_PSTSB_MASK)
14714#define HSADC_PWR_ASB_MASK (0x8000U)
14715#define HSADC_PWR_ASB_SHIFT (15U)
14720#define HSADC_PWR_ASB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_ASB_SHIFT)) & HSADC_PWR_ASB_MASK)
14725#define HSADC_SCTRL_SC_MASK (0xFFFFU)
14726#define HSADC_SCTRL_SC_SHIFT (0U)
14731#define HSADC_SCTRL_SC(x) (((uint16_t)(((uint16_t)(x)) << HSADC_SCTRL_SC_SHIFT)) & HSADC_SCTRL_SC_MASK)
14736#define HSADC_PWR2_DIVB_MASK (0x3F00U)
14737#define HSADC_PWR2_DIVB_SHIFT (8U)
14738#define HSADC_PWR2_DIVB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_PWR2_DIVB_SHIFT)) & HSADC_PWR2_DIVB_MASK)
14743#define HSADC_CTRL3_DMASRC_MASK (0x40U)
14744#define HSADC_CTRL3_DMASRC_SHIFT (6U)
14749#define HSADC_CTRL3_DMASRC(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL3_DMASRC_SHIFT)) & HSADC_CTRL3_DMASRC_MASK)
14750#define HSADC_CTRL3_ADCRES_MASK (0x300U)
14751#define HSADC_CTRL3_ADCRES_SHIFT (8U)
14758#define HSADC_CTRL3_ADCRES(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL3_ADCRES_SHIFT)) & HSADC_CTRL3_ADCRES_MASK)
14763#define HSADC_SCINTEN_SCINTEN_MASK (0xFFFFU)
14764#define HSADC_SCINTEN_SCINTEN_SHIFT (0U)
14769#define HSADC_SCINTEN_SCINTEN(x) (((uint16_t)(((uint16_t)(x)) << HSADC_SCINTEN_SCINTEN_SHIFT)) & HSADC_SCINTEN_SCINTEN_MASK)
14774#define HSADC_SAMPTIM_SAMPT_A_MASK (0xFFU)
14775#define HSADC_SAMPTIM_SAMPT_A_SHIFT (0U)
14776#define HSADC_SAMPTIM_SAMPT_A(x) (((uint16_t)(((uint16_t)(x)) << HSADC_SAMPTIM_SAMPT_A_SHIFT)) & HSADC_SAMPTIM_SAMPT_A_MASK)
14777#define HSADC_SAMPTIM_SAMPT_B_MASK (0xFF00U)
14778#define HSADC_SAMPTIM_SAMPT_B_SHIFT (8U)
14779#define HSADC_SAMPTIM_SAMPT_B(x) (((uint16_t)(((uint16_t)(x)) << HSADC_SAMPTIM_SAMPT_B_SHIFT)) & HSADC_SAMPTIM_SAMPT_B_MASK)
14784#define HSADC_CALIB_REQSINGA_MASK (0x1U)
14785#define HSADC_CALIB_REQSINGA_SHIFT (0U)
14790#define HSADC_CALIB_REQSINGA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQSINGA_SHIFT)) & HSADC_CALIB_REQSINGA_MASK)
14791#define HSADC_CALIB_REQDIFA_MASK (0x2U)
14792#define HSADC_CALIB_REQDIFA_SHIFT (1U)
14797#define HSADC_CALIB_REQDIFA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQDIFA_SHIFT)) & HSADC_CALIB_REQDIFA_MASK)
14798#define HSADC_CALIB_BYPA_MASK (0x4U)
14799#define HSADC_CALIB_BYPA_SHIFT (2U)
14804#define HSADC_CALIB_BYPA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_BYPA_SHIFT)) & HSADC_CALIB_BYPA_MASK)
14805#define HSADC_CALIB_CAL_REQA_MASK (0x8U)
14806#define HSADC_CALIB_CAL_REQA_SHIFT (3U)
14811#define HSADC_CALIB_CAL_REQA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_CAL_REQA_SHIFT)) & HSADC_CALIB_CAL_REQA_MASK)
14812#define HSADC_CALIB_REQSINGB_MASK (0x10U)
14813#define HSADC_CALIB_REQSINGB_SHIFT (4U)
14818#define HSADC_CALIB_REQSINGB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQSINGB_SHIFT)) & HSADC_CALIB_REQSINGB_MASK)
14819#define HSADC_CALIB_REQDIFB_MASK (0x20U)
14820#define HSADC_CALIB_REQDIFB_SHIFT (5U)
14825#define HSADC_CALIB_REQDIFB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQDIFB_SHIFT)) & HSADC_CALIB_REQDIFB_MASK)
14826#define HSADC_CALIB_BYPB_MASK (0x40U)
14827#define HSADC_CALIB_BYPB_SHIFT (6U)
14832#define HSADC_CALIB_BYPB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_BYPB_SHIFT)) & HSADC_CALIB_BYPB_MASK)
14833#define HSADC_CALIB_CAL_REQB_MASK (0x80U)
14834#define HSADC_CALIB_CAL_REQB_SHIFT (7U)
14839#define HSADC_CALIB_CAL_REQB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_CAL_REQB_SHIFT)) & HSADC_CALIB_CAL_REQB_MASK)
14840#define HSADC_CALIB_EOCALIEA_MASK (0x100U)
14841#define HSADC_CALIB_EOCALIEA_SHIFT (8U)
14846#define HSADC_CALIB_EOCALIEA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_EOCALIEA_SHIFT)) & HSADC_CALIB_EOCALIEA_MASK)
14847#define HSADC_CALIB_EOCALIEB_MASK (0x200U)
14848#define HSADC_CALIB_EOCALIEB_SHIFT (9U)
14853#define HSADC_CALIB_EOCALIEB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_EOCALIEB_SHIFT)) & HSADC_CALIB_EOCALIEB_MASK)
14858#define HSADC_CALVAL_A_CALVSING_MASK (0x7FU)
14859#define HSADC_CALVAL_A_CALVSING_SHIFT (0U)
14860#define HSADC_CALVAL_A_CALVSING(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_A_CALVSING_SHIFT)) & HSADC_CALVAL_A_CALVSING_MASK)
14861#define HSADC_CALVAL_A_CALVDIF_MASK (0x7F00U)
14862#define HSADC_CALVAL_A_CALVDIF_SHIFT (8U)
14863#define HSADC_CALVAL_A_CALVDIF(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_A_CALVDIF_SHIFT)) & HSADC_CALVAL_A_CALVDIF_MASK)
14868#define HSADC_CALVAL_B_CALVSING_MASK (0x7FU)
14869#define HSADC_CALVAL_B_CALVSING_SHIFT (0U)
14870#define HSADC_CALVAL_B_CALVSING(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_B_CALVSING_SHIFT)) & HSADC_CALVAL_B_CALVSING_MASK)
14871#define HSADC_CALVAL_B_CALVDIF_MASK (0x7F00U)
14872#define HSADC_CALVAL_B_CALVDIF_SHIFT (8U)
14873#define HSADC_CALVAL_B_CALVDIF(x) (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_B_CALVDIF_SHIFT)) & HSADC_CALVAL_B_CALVDIF_MASK)
14878#define HSADC_MUX67_SEL_CH6_SELA_MASK (0x7U)
14879#define HSADC_MUX67_SEL_CH6_SELA_SHIFT (0U)
14880#define HSADC_MUX67_SEL_CH6_SELA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH6_SELA_SHIFT)) & HSADC_MUX67_SEL_CH6_SELA_MASK)
14881#define HSADC_MUX67_SEL_CH7_SELA_MASK (0x70U)
14882#define HSADC_MUX67_SEL_CH7_SELA_SHIFT (4U)
14883#define HSADC_MUX67_SEL_CH7_SELA(x) (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH7_SELA_SHIFT)) & HSADC_MUX67_SEL_CH7_SELA_MASK)
14884#define HSADC_MUX67_SEL_CH6_SELB_MASK (0x700U)
14885#define HSADC_MUX67_SEL_CH6_SELB_SHIFT (8U)
14886#define HSADC_MUX67_SEL_CH6_SELB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH6_SELB_SHIFT)) & HSADC_MUX67_SEL_CH6_SELB_MASK)
14887#define HSADC_MUX67_SEL_CH7_SELB_MASK (0x7000U)
14888#define HSADC_MUX67_SEL_CH7_SELB_SHIFT (12U)
14889#define HSADC_MUX67_SEL_CH7_SELB(x) (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH7_SELB_SHIFT)) & HSADC_MUX67_SEL_CH7_SELB_MASK)
14895 /* end of group HSADC_Register_Masks */
14896
14897
14898/* HSADC - Peripheral instance base addresses */
14900#define HSADC0_BASE (0x4005C000u)
14902#define HSADC0 ((HSADC_Type *)HSADC0_BASE)
14904#define HSADC1_BASE (0x400DC000u)
14906#define HSADC1 ((HSADC_Type *)HSADC1_BASE)
14908#define HSADC_BASE_ADDRS { HSADC0_BASE, HSADC1_BASE }
14910#define HSADC_BASE_PTRS { HSADC0, HSADC1 }
14912#define HSADC_IRQS { { HSADC0_CCA_IRQn, HSADC0_CCB_IRQn }, { HSADC1_CCA_IRQn, HSADC1_CCB_IRQn } }
14913#define HSADC_ERR_IRQS { HSADC_ERR_IRQn, HSADC_ERR_IRQn }
14914
14917 /* end of group HSADC_Peripheral_Access_Layer */
14918
14919
14920/* ----------------------------------------------------------------------------
14921 -- I2C Peripheral Access Layer
14922 ---------------------------------------------------------------------------- */
14923
14930typedef struct {
14931 __IO uint8_t A1;
14932 __IO uint8_t F;
14933 __IO uint8_t C1;
14934 __IO uint8_t S;
14935 __IO uint8_t D;
14936 __IO uint8_t C2;
14937 __IO uint8_t FLT;
14938 __IO uint8_t RA;
14939 __IO uint8_t SMB;
14940 __IO uint8_t A2;
14941 __IO uint8_t SLTH;
14942 __IO uint8_t SLTL;
14943} I2C_Type;
14944
14945/* ----------------------------------------------------------------------------
14946 -- I2C Register Masks
14947 ---------------------------------------------------------------------------- */
14948
14956#define I2C_A1_AD_MASK (0xFEU)
14957#define I2C_A1_AD_SHIFT (1U)
14958#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
14963#define I2C_F_ICR_MASK (0x3FU)
14964#define I2C_F_ICR_SHIFT (0U)
14965#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
14966#define I2C_F_MULT_MASK (0xC0U)
14967#define I2C_F_MULT_SHIFT (6U)
14974#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
14979#define I2C_C1_DMAEN_MASK (0x1U)
14980#define I2C_C1_DMAEN_SHIFT (0U)
14985#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
14986#define I2C_C1_WUEN_MASK (0x2U)
14987#define I2C_C1_WUEN_SHIFT (1U)
14992#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
14993#define I2C_C1_RSTA_MASK (0x4U)
14994#define I2C_C1_RSTA_SHIFT (2U)
14995#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
14996#define I2C_C1_TXAK_MASK (0x8U)
14997#define I2C_C1_TXAK_SHIFT (3U)
15002#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
15003#define I2C_C1_TX_MASK (0x10U)
15004#define I2C_C1_TX_SHIFT (4U)
15009#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
15010#define I2C_C1_MST_MASK (0x20U)
15011#define I2C_C1_MST_SHIFT (5U)
15016#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
15017#define I2C_C1_IICIE_MASK (0x40U)
15018#define I2C_C1_IICIE_SHIFT (6U)
15023#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
15024#define I2C_C1_IICEN_MASK (0x80U)
15025#define I2C_C1_IICEN_SHIFT (7U)
15030#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
15035#define I2C_S_RXAK_MASK (0x1U)
15036#define I2C_S_RXAK_SHIFT (0U)
15041#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
15042#define I2C_S_IICIF_MASK (0x2U)
15043#define I2C_S_IICIF_SHIFT (1U)
15048#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
15049#define I2C_S_SRW_MASK (0x4U)
15050#define I2C_S_SRW_SHIFT (2U)
15055#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
15056#define I2C_S_RAM_MASK (0x8U)
15057#define I2C_S_RAM_SHIFT (3U)
15062#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
15063#define I2C_S_ARBL_MASK (0x10U)
15064#define I2C_S_ARBL_SHIFT (4U)
15069#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
15070#define I2C_S_BUSY_MASK (0x20U)
15071#define I2C_S_BUSY_SHIFT (5U)
15076#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
15077#define I2C_S_IAAS_MASK (0x40U)
15078#define I2C_S_IAAS_SHIFT (6U)
15083#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
15084#define I2C_S_TCF_MASK (0x80U)
15085#define I2C_S_TCF_SHIFT (7U)
15090#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
15095#define I2C_D_DATA_MASK (0xFFU)
15096#define I2C_D_DATA_SHIFT (0U)
15097#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
15102#define I2C_C2_AD_MASK (0x7U)
15103#define I2C_C2_AD_SHIFT (0U)
15104#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
15105#define I2C_C2_RMEN_MASK (0x8U)
15106#define I2C_C2_RMEN_SHIFT (3U)
15111#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
15112#define I2C_C2_SBRC_MASK (0x10U)
15113#define I2C_C2_SBRC_SHIFT (4U)
15118#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
15119#define I2C_C2_HDRS_MASK (0x20U)
15120#define I2C_C2_HDRS_SHIFT (5U)
15125#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
15126#define I2C_C2_ADEXT_MASK (0x40U)
15127#define I2C_C2_ADEXT_SHIFT (6U)
15132#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
15133#define I2C_C2_GCAEN_MASK (0x80U)
15134#define I2C_C2_GCAEN_SHIFT (7U)
15139#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
15144#define I2C_FLT_FLT_MASK (0xFU)
15145#define I2C_FLT_FLT_SHIFT (0U)
15149#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
15150#define I2C_FLT_STARTF_MASK (0x10U)
15151#define I2C_FLT_STARTF_SHIFT (4U)
15156#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
15157#define I2C_FLT_SSIE_MASK (0x20U)
15158#define I2C_FLT_SSIE_SHIFT (5U)
15163#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
15164#define I2C_FLT_STOPF_MASK (0x40U)
15165#define I2C_FLT_STOPF_SHIFT (6U)
15170#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
15171#define I2C_FLT_SHEN_MASK (0x80U)
15172#define I2C_FLT_SHEN_SHIFT (7U)
15177#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
15182#define I2C_RA_RAD_MASK (0xFEU)
15183#define I2C_RA_RAD_SHIFT (1U)
15184#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
15189#define I2C_SMB_SHTF2IE_MASK (0x1U)
15190#define I2C_SMB_SHTF2IE_SHIFT (0U)
15195#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
15196#define I2C_SMB_SHTF2_MASK (0x2U)
15197#define I2C_SMB_SHTF2_SHIFT (1U)
15202#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
15203#define I2C_SMB_SHTF1_MASK (0x4U)
15204#define I2C_SMB_SHTF1_SHIFT (2U)
15209#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
15210#define I2C_SMB_SLTF_MASK (0x8U)
15211#define I2C_SMB_SLTF_SHIFT (3U)
15216#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
15217#define I2C_SMB_TCKSEL_MASK (0x10U)
15218#define I2C_SMB_TCKSEL_SHIFT (4U)
15223#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
15224#define I2C_SMB_SIICAEN_MASK (0x20U)
15225#define I2C_SMB_SIICAEN_SHIFT (5U)
15230#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
15231#define I2C_SMB_ALERTEN_MASK (0x40U)
15232#define I2C_SMB_ALERTEN_SHIFT (6U)
15237#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
15238#define I2C_SMB_FACK_MASK (0x80U)
15239#define I2C_SMB_FACK_SHIFT (7U)
15244#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
15249#define I2C_A2_SAD_MASK (0xFEU)
15250#define I2C_A2_SAD_SHIFT (1U)
15251#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
15256#define I2C_SLTH_SSLT_MASK (0xFFU)
15257#define I2C_SLTH_SSLT_SHIFT (0U)
15258#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
15263#define I2C_SLTL_SSLT_MASK (0xFFU)
15264#define I2C_SLTL_SSLT_SHIFT (0U)
15265#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
15271 /* end of group I2C_Register_Masks */
15272
15273
15274/* I2C - Peripheral instance base addresses */
15276#define I2C0_BASE (0x40066000u)
15278#define I2C0 ((I2C_Type *)I2C0_BASE)
15280#define I2C1_BASE (0x40067000u)
15282#define I2C1 ((I2C_Type *)I2C1_BASE)
15284#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
15286#define I2C_BASE_PTRS { I2C0, I2C1 }
15288#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
15289
15292 /* end of group I2C_Peripheral_Access_Layer */
15293
15294
15295/* ----------------------------------------------------------------------------
15296 -- LLWU Peripheral Access Layer
15297 ---------------------------------------------------------------------------- */
15298
15305typedef struct {
15306 __IO uint8_t PE1;
15307 __IO uint8_t PE2;
15308 __IO uint8_t PE3;
15309 __IO uint8_t PE4;
15310 __IO uint8_t PE5;
15311 __IO uint8_t PE6;
15312 __IO uint8_t PE7;
15313 __IO uint8_t PE8;
15314 __IO uint8_t ME;
15315 __IO uint8_t PF1;
15316 __IO uint8_t PF2;
15317 __IO uint8_t PF3;
15318 __IO uint8_t PF4;
15319 __I uint8_t MF5;
15320 __IO uint8_t FILT1;
15321 __IO uint8_t FILT2;
15322} LLWU_Type;
15323
15324/* ----------------------------------------------------------------------------
15325 -- LLWU Register Masks
15326 ---------------------------------------------------------------------------- */
15327
15335#define LLWU_PE1_WUPE0_MASK (0x3U)
15336#define LLWU_PE1_WUPE0_SHIFT (0U)
15343#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
15344#define LLWU_PE1_WUPE1_MASK (0xCU)
15345#define LLWU_PE1_WUPE1_SHIFT (2U)
15352#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
15353#define LLWU_PE1_WUPE2_MASK (0x30U)
15354#define LLWU_PE1_WUPE2_SHIFT (4U)
15361#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
15362#define LLWU_PE1_WUPE3_MASK (0xC0U)
15363#define LLWU_PE1_WUPE3_SHIFT (6U)
15370#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
15375#define LLWU_PE2_WUPE4_MASK (0x3U)
15376#define LLWU_PE2_WUPE4_SHIFT (0U)
15383#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
15384#define LLWU_PE2_WUPE5_MASK (0xCU)
15385#define LLWU_PE2_WUPE5_SHIFT (2U)
15392#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
15393#define LLWU_PE2_WUPE6_MASK (0x30U)
15394#define LLWU_PE2_WUPE6_SHIFT (4U)
15401#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
15402#define LLWU_PE2_WUPE7_MASK (0xC0U)
15403#define LLWU_PE2_WUPE7_SHIFT (6U)
15410#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
15415#define LLWU_PE3_WUPE8_MASK (0x3U)
15416#define LLWU_PE3_WUPE8_SHIFT (0U)
15423#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
15424#define LLWU_PE3_WUPE9_MASK (0xCU)
15425#define LLWU_PE3_WUPE9_SHIFT (2U)
15432#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
15433#define LLWU_PE3_WUPE10_MASK (0x30U)
15434#define LLWU_PE3_WUPE10_SHIFT (4U)
15441#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
15442#define LLWU_PE3_WUPE11_MASK (0xC0U)
15443#define LLWU_PE3_WUPE11_SHIFT (6U)
15450#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
15455#define LLWU_PE4_WUPE12_MASK (0x3U)
15456#define LLWU_PE4_WUPE12_SHIFT (0U)
15463#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
15464#define LLWU_PE4_WUPE13_MASK (0xCU)
15465#define LLWU_PE4_WUPE13_SHIFT (2U)
15472#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
15473#define LLWU_PE4_WUPE14_MASK (0x30U)
15474#define LLWU_PE4_WUPE14_SHIFT (4U)
15481#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
15482#define LLWU_PE4_WUPE15_MASK (0xC0U)
15483#define LLWU_PE4_WUPE15_SHIFT (6U)
15490#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
15495#define LLWU_PE5_WUPE16_MASK (0x3U)
15496#define LLWU_PE5_WUPE16_SHIFT (0U)
15503#define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
15504#define LLWU_PE5_WUPE17_MASK (0xCU)
15505#define LLWU_PE5_WUPE17_SHIFT (2U)
15512#define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
15513#define LLWU_PE5_WUPE18_MASK (0x30U)
15514#define LLWU_PE5_WUPE18_SHIFT (4U)
15521#define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
15522#define LLWU_PE5_WUPE19_MASK (0xC0U)
15523#define LLWU_PE5_WUPE19_SHIFT (6U)
15530#define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
15535#define LLWU_PE6_WUPE20_MASK (0x3U)
15536#define LLWU_PE6_WUPE20_SHIFT (0U)
15543#define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
15544#define LLWU_PE6_WUPE21_MASK (0xCU)
15545#define LLWU_PE6_WUPE21_SHIFT (2U)
15552#define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
15553#define LLWU_PE6_WUPE22_MASK (0x30U)
15554#define LLWU_PE6_WUPE22_SHIFT (4U)
15561#define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
15562#define LLWU_PE6_WUPE23_MASK (0xC0U)
15563#define LLWU_PE6_WUPE23_SHIFT (6U)
15570#define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
15575#define LLWU_PE7_WUPE24_MASK (0x3U)
15576#define LLWU_PE7_WUPE24_SHIFT (0U)
15583#define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
15584#define LLWU_PE7_WUPE25_MASK (0xCU)
15585#define LLWU_PE7_WUPE25_SHIFT (2U)
15592#define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
15593#define LLWU_PE7_WUPE26_MASK (0x30U)
15594#define LLWU_PE7_WUPE26_SHIFT (4U)
15601#define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
15602#define LLWU_PE7_WUPE27_MASK (0xC0U)
15603#define LLWU_PE7_WUPE27_SHIFT (6U)
15610#define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
15615#define LLWU_PE8_WUPE28_MASK (0x3U)
15616#define LLWU_PE8_WUPE28_SHIFT (0U)
15623#define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
15624#define LLWU_PE8_WUPE29_MASK (0xCU)
15625#define LLWU_PE8_WUPE29_SHIFT (2U)
15632#define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
15633#define LLWU_PE8_WUPE30_MASK (0x30U)
15634#define LLWU_PE8_WUPE30_SHIFT (4U)
15641#define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
15642#define LLWU_PE8_WUPE31_MASK (0xC0U)
15643#define LLWU_PE8_WUPE31_SHIFT (6U)
15650#define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
15655#define LLWU_ME_WUME0_MASK (0x1U)
15656#define LLWU_ME_WUME0_SHIFT (0U)
15661#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
15662#define LLWU_ME_WUME1_MASK (0x2U)
15663#define LLWU_ME_WUME1_SHIFT (1U)
15668#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
15669#define LLWU_ME_WUME2_MASK (0x4U)
15670#define LLWU_ME_WUME2_SHIFT (2U)
15675#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
15676#define LLWU_ME_WUME3_MASK (0x8U)
15677#define LLWU_ME_WUME3_SHIFT (3U)
15682#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
15683#define LLWU_ME_WUME4_MASK (0x10U)
15684#define LLWU_ME_WUME4_SHIFT (4U)
15689#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
15690#define LLWU_ME_WUME5_MASK (0x20U)
15691#define LLWU_ME_WUME5_SHIFT (5U)
15696#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
15697#define LLWU_ME_WUME6_MASK (0x40U)
15698#define LLWU_ME_WUME6_SHIFT (6U)
15703#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
15704#define LLWU_ME_WUME7_MASK (0x80U)
15705#define LLWU_ME_WUME7_SHIFT (7U)
15710#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
15715#define LLWU_PF1_WUF0_MASK (0x1U)
15716#define LLWU_PF1_WUF0_SHIFT (0U)
15721#define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
15722#define LLWU_PF1_WUF1_MASK (0x2U)
15723#define LLWU_PF1_WUF1_SHIFT (1U)
15728#define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
15729#define LLWU_PF1_WUF2_MASK (0x4U)
15730#define LLWU_PF1_WUF2_SHIFT (2U)
15735#define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
15736#define LLWU_PF1_WUF3_MASK (0x8U)
15737#define LLWU_PF1_WUF3_SHIFT (3U)
15742#define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
15743#define LLWU_PF1_WUF4_MASK (0x10U)
15744#define LLWU_PF1_WUF4_SHIFT (4U)
15749#define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
15750#define LLWU_PF1_WUF5_MASK (0x20U)
15751#define LLWU_PF1_WUF5_SHIFT (5U)
15756#define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
15757#define LLWU_PF1_WUF6_MASK (0x40U)
15758#define LLWU_PF1_WUF6_SHIFT (6U)
15763#define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
15764#define LLWU_PF1_WUF7_MASK (0x80U)
15765#define LLWU_PF1_WUF7_SHIFT (7U)
15770#define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
15775#define LLWU_PF2_WUF8_MASK (0x1U)
15776#define LLWU_PF2_WUF8_SHIFT (0U)
15781#define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
15782#define LLWU_PF2_WUF9_MASK (0x2U)
15783#define LLWU_PF2_WUF9_SHIFT (1U)
15788#define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
15789#define LLWU_PF2_WUF10_MASK (0x4U)
15790#define LLWU_PF2_WUF10_SHIFT (2U)
15795#define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
15796#define LLWU_PF2_WUF11_MASK (0x8U)
15797#define LLWU_PF2_WUF11_SHIFT (3U)
15802#define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
15803#define LLWU_PF2_WUF12_MASK (0x10U)
15804#define LLWU_PF2_WUF12_SHIFT (4U)
15809#define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
15810#define LLWU_PF2_WUF13_MASK (0x20U)
15811#define LLWU_PF2_WUF13_SHIFT (5U)
15816#define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
15817#define LLWU_PF2_WUF14_MASK (0x40U)
15818#define LLWU_PF2_WUF14_SHIFT (6U)
15823#define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
15824#define LLWU_PF2_WUF15_MASK (0x80U)
15825#define LLWU_PF2_WUF15_SHIFT (7U)
15830#define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
15835#define LLWU_PF3_WUF16_MASK (0x1U)
15836#define LLWU_PF3_WUF16_SHIFT (0U)
15841#define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
15842#define LLWU_PF3_WUF17_MASK (0x2U)
15843#define LLWU_PF3_WUF17_SHIFT (1U)
15848#define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
15849#define LLWU_PF3_WUF18_MASK (0x4U)
15850#define LLWU_PF3_WUF18_SHIFT (2U)
15855#define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
15856#define LLWU_PF3_WUF19_MASK (0x8U)
15857#define LLWU_PF3_WUF19_SHIFT (3U)
15862#define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
15863#define LLWU_PF3_WUF20_MASK (0x10U)
15864#define LLWU_PF3_WUF20_SHIFT (4U)
15869#define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
15870#define LLWU_PF3_WUF21_MASK (0x20U)
15871#define LLWU_PF3_WUF21_SHIFT (5U)
15876#define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
15877#define LLWU_PF3_WUF22_MASK (0x40U)
15878#define LLWU_PF3_WUF22_SHIFT (6U)
15883#define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
15884#define LLWU_PF3_WUF23_MASK (0x80U)
15885#define LLWU_PF3_WUF23_SHIFT (7U)
15890#define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
15895#define LLWU_PF4_WUF24_MASK (0x1U)
15896#define LLWU_PF4_WUF24_SHIFT (0U)
15901#define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
15902#define LLWU_PF4_WUF25_MASK (0x2U)
15903#define LLWU_PF4_WUF25_SHIFT (1U)
15908#define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
15909#define LLWU_PF4_WUF26_MASK (0x4U)
15910#define LLWU_PF4_WUF26_SHIFT (2U)
15915#define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
15916#define LLWU_PF4_WUF27_MASK (0x8U)
15917#define LLWU_PF4_WUF27_SHIFT (3U)
15922#define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
15923#define LLWU_PF4_WUF28_MASK (0x10U)
15924#define LLWU_PF4_WUF28_SHIFT (4U)
15929#define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
15930#define LLWU_PF4_WUF29_MASK (0x20U)
15931#define LLWU_PF4_WUF29_SHIFT (5U)
15936#define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
15937#define LLWU_PF4_WUF30_MASK (0x40U)
15938#define LLWU_PF4_WUF30_SHIFT (6U)
15943#define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
15944#define LLWU_PF4_WUF31_MASK (0x80U)
15945#define LLWU_PF4_WUF31_SHIFT (7U)
15950#define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
15955#define LLWU_MF5_MWUF0_MASK (0x1U)
15956#define LLWU_MF5_MWUF0_SHIFT (0U)
15961#define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
15962#define LLWU_MF5_MWUF1_MASK (0x2U)
15963#define LLWU_MF5_MWUF1_SHIFT (1U)
15968#define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
15969#define LLWU_MF5_MWUF2_MASK (0x4U)
15970#define LLWU_MF5_MWUF2_SHIFT (2U)
15975#define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
15976#define LLWU_MF5_MWUF3_MASK (0x8U)
15977#define LLWU_MF5_MWUF3_SHIFT (3U)
15982#define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
15983#define LLWU_MF5_MWUF4_MASK (0x10U)
15984#define LLWU_MF5_MWUF4_SHIFT (4U)
15989#define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
15990#define LLWU_MF5_MWUF5_MASK (0x20U)
15991#define LLWU_MF5_MWUF5_SHIFT (5U)
15996#define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
15997#define LLWU_MF5_MWUF6_MASK (0x40U)
15998#define LLWU_MF5_MWUF6_SHIFT (6U)
16003#define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
16004#define LLWU_MF5_MWUF7_MASK (0x80U)
16005#define LLWU_MF5_MWUF7_SHIFT (7U)
16010#define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
16015#define LLWU_FILT1_FILTSEL_MASK (0x1FU)
16016#define LLWU_FILT1_FILTSEL_SHIFT (0U)
16021#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
16022#define LLWU_FILT1_FILTE_MASK (0x60U)
16023#define LLWU_FILT1_FILTE_SHIFT (5U)
16030#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
16031#define LLWU_FILT1_FILTF_MASK (0x80U)
16032#define LLWU_FILT1_FILTF_SHIFT (7U)
16037#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
16042#define LLWU_FILT2_FILTSEL_MASK (0x1FU)
16043#define LLWU_FILT2_FILTSEL_SHIFT (0U)
16048#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
16049#define LLWU_FILT2_FILTE_MASK (0x60U)
16050#define LLWU_FILT2_FILTE_SHIFT (5U)
16057#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
16058#define LLWU_FILT2_FILTF_MASK (0x80U)
16059#define LLWU_FILT2_FILTF_SHIFT (7U)
16064#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
16070 /* end of group LLWU_Register_Masks */
16071
16072
16073/* LLWU - Peripheral instance base addresses */
16075#define LLWU_BASE (0x4007C000u)
16077#define LLWU ((LLWU_Type *)LLWU_BASE)
16079#define LLWU_BASE_ADDRS { LLWU_BASE }
16081#define LLWU_BASE_PTRS { LLWU }
16083#define LLWU_IRQS { LLWU_IRQn }
16084
16087 /* end of group LLWU_Peripheral_Access_Layer */
16088
16089
16090/* ----------------------------------------------------------------------------
16091 -- LPTMR Peripheral Access Layer
16092 ---------------------------------------------------------------------------- */
16093
16100typedef struct {
16101 __IO uint32_t CSR;
16102 __IO uint32_t PSR;
16103 __IO uint32_t CMR;
16104 __IO uint32_t CNR;
16105} LPTMR_Type;
16106
16107/* ----------------------------------------------------------------------------
16108 -- LPTMR Register Masks
16109 ---------------------------------------------------------------------------- */
16110
16118#define LPTMR_CSR_TEN_MASK (0x1U)
16119#define LPTMR_CSR_TEN_SHIFT (0U)
16124#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
16125#define LPTMR_CSR_TMS_MASK (0x2U)
16126#define LPTMR_CSR_TMS_SHIFT (1U)
16131#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
16132#define LPTMR_CSR_TFC_MASK (0x4U)
16133#define LPTMR_CSR_TFC_SHIFT (2U)
16138#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
16139#define LPTMR_CSR_TPP_MASK (0x8U)
16140#define LPTMR_CSR_TPP_SHIFT (3U)
16145#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
16146#define LPTMR_CSR_TPS_MASK (0x30U)
16147#define LPTMR_CSR_TPS_SHIFT (4U)
16154#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
16155#define LPTMR_CSR_TIE_MASK (0x40U)
16156#define LPTMR_CSR_TIE_SHIFT (6U)
16161#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
16162#define LPTMR_CSR_TCF_MASK (0x80U)
16163#define LPTMR_CSR_TCF_SHIFT (7U)
16168#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
16173#define LPTMR_PSR_PCS_MASK (0x3U)
16174#define LPTMR_PSR_PCS_SHIFT (0U)
16181#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
16182#define LPTMR_PSR_PBYP_MASK (0x4U)
16183#define LPTMR_PSR_PBYP_SHIFT (2U)
16188#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
16189#define LPTMR_PSR_PRESCALE_MASK (0x78U)
16190#define LPTMR_PSR_PRESCALE_SHIFT (3U)
16209#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
16214#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
16215#define LPTMR_CMR_COMPARE_SHIFT (0U)
16216#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
16221#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
16222#define LPTMR_CNR_COUNTER_SHIFT (0U)
16223#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
16229 /* end of group LPTMR_Register_Masks */
16230
16231
16232/* LPTMR - Peripheral instance base addresses */
16234#define LPTMR0_BASE (0x40040000u)
16236#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
16238#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
16240#define LPTMR_BASE_PTRS { LPTMR0 }
16242#define LPTMR_IRQS { LPTMR0_IRQn }
16243
16246 /* end of group LPTMR_Peripheral_Access_Layer */
16247
16248
16249/* ----------------------------------------------------------------------------
16250 -- MCG Peripheral Access Layer
16251 ---------------------------------------------------------------------------- */
16252
16259typedef struct {
16260 __IO uint8_t C1;
16261 __IO uint8_t C2;
16262 __IO uint8_t C3;
16263 __IO uint8_t C4;
16264 __IO uint8_t C5;
16265 __IO uint8_t C6;
16266 __IO uint8_t S;
16267 uint8_t RESERVED_0[1];
16268 __IO uint8_t SC;
16269 uint8_t RESERVED_1[1];
16270 __IO uint8_t ATCVH;
16271 __IO uint8_t ATCVL;
16272 uint8_t RESERVED_2[1];
16273 __IO uint8_t C8;
16274} MCG_Type;
16275
16276/* ----------------------------------------------------------------------------
16277 -- MCG Register Masks
16278 ---------------------------------------------------------------------------- */
16279
16287#define MCG_C1_IREFSTEN_MASK (0x1U)
16288#define MCG_C1_IREFSTEN_SHIFT (0U)
16293#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
16294#define MCG_C1_IRCLKEN_MASK (0x2U)
16295#define MCG_C1_IRCLKEN_SHIFT (1U)
16300#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
16301#define MCG_C1_IREFS_MASK (0x4U)
16302#define MCG_C1_IREFS_SHIFT (2U)
16307#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
16308#define MCG_C1_FRDIV_MASK (0x38U)
16309#define MCG_C1_FRDIV_SHIFT (3U)
16320#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
16321#define MCG_C1_CLKS_MASK (0xC0U)
16322#define MCG_C1_CLKS_SHIFT (6U)
16329#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
16334#define MCG_C2_IRCS_MASK (0x1U)
16335#define MCG_C2_IRCS_SHIFT (0U)
16340#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
16341#define MCG_C2_LP_MASK (0x2U)
16342#define MCG_C2_LP_SHIFT (1U)
16347#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
16348#define MCG_C2_EREFS_MASK (0x4U)
16349#define MCG_C2_EREFS_SHIFT (2U)
16354#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
16355#define MCG_C2_HGO_MASK (0x8U)
16356#define MCG_C2_HGO_SHIFT (3U)
16361#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
16362#define MCG_C2_RANGE_MASK (0x30U)
16363#define MCG_C2_RANGE_SHIFT (4U)
16369#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
16370#define MCG_C2_FCFTRIM_MASK (0x40U)
16371#define MCG_C2_FCFTRIM_SHIFT (6U)
16372#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
16373#define MCG_C2_LOCRE0_MASK (0x80U)
16374#define MCG_C2_LOCRE0_SHIFT (7U)
16379#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
16384#define MCG_C3_SCTRIM_MASK (0xFFU)
16385#define MCG_C3_SCTRIM_SHIFT (0U)
16386#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
16391#define MCG_C4_SCFTRIM_MASK (0x1U)
16392#define MCG_C4_SCFTRIM_SHIFT (0U)
16393#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
16394#define MCG_C4_FCTRIM_MASK (0x1EU)
16395#define MCG_C4_FCTRIM_SHIFT (1U)
16396#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
16397#define MCG_C4_DRST_DRS_MASK (0x60U)
16398#define MCG_C4_DRST_DRS_SHIFT (5U)
16405#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
16406#define MCG_C4_DMX32_MASK (0x80U)
16407#define MCG_C4_DMX32_SHIFT (7U)
16412#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
16417#define MCG_C5_PRDIV_MASK (0x7U)
16418#define MCG_C5_PRDIV_SHIFT (0U)
16429#define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
16430#define MCG_C5_PLLSTEN_MASK (0x20U)
16431#define MCG_C5_PLLSTEN_SHIFT (5U)
16436#define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
16437#define MCG_C5_PLLCLKEN_MASK (0x40U)
16438#define MCG_C5_PLLCLKEN_SHIFT (6U)
16443#define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
16448#define MCG_C6_VDIV_MASK (0x1FU)
16449#define MCG_C6_VDIV_SHIFT (0U)
16484#define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
16485#define MCG_C6_CME0_MASK (0x20U)
16486#define MCG_C6_CME0_SHIFT (5U)
16491#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
16492#define MCG_C6_PLLS_MASK (0x40U)
16493#define MCG_C6_PLLS_SHIFT (6U)
16498#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
16499#define MCG_C6_LOLIE0_MASK (0x80U)
16500#define MCG_C6_LOLIE0_SHIFT (7U)
16505#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
16510#define MCG_S_IRCST_MASK (0x1U)
16511#define MCG_S_IRCST_SHIFT (0U)
16516#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
16517#define MCG_S_OSCINIT0_MASK (0x2U)
16518#define MCG_S_OSCINIT0_SHIFT (1U)
16519#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
16520#define MCG_S_CLKST_MASK (0xCU)
16521#define MCG_S_CLKST_SHIFT (2U)
16528#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
16529#define MCG_S_IREFST_MASK (0x10U)
16530#define MCG_S_IREFST_SHIFT (4U)
16535#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
16536#define MCG_S_PLLST_MASK (0x20U)
16537#define MCG_S_PLLST_SHIFT (5U)
16542#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
16543#define MCG_S_LOCK0_MASK (0x40U)
16544#define MCG_S_LOCK0_SHIFT (6U)
16549#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
16550#define MCG_S_LOLS0_MASK (0x80U)
16551#define MCG_S_LOLS0_SHIFT (7U)
16556#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
16561#define MCG_SC_LOCS0_MASK (0x1U)
16562#define MCG_SC_LOCS0_SHIFT (0U)
16567#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
16568#define MCG_SC_FCRDIV_MASK (0xEU)
16569#define MCG_SC_FCRDIV_SHIFT (1U)
16580#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
16581#define MCG_SC_FLTPRSRV_MASK (0x10U)
16582#define MCG_SC_FLTPRSRV_SHIFT (4U)
16587#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
16588#define MCG_SC_ATMF_MASK (0x20U)
16589#define MCG_SC_ATMF_SHIFT (5U)
16594#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
16595#define MCG_SC_ATMS_MASK (0x40U)
16596#define MCG_SC_ATMS_SHIFT (6U)
16601#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
16602#define MCG_SC_ATME_MASK (0x80U)
16603#define MCG_SC_ATME_SHIFT (7U)
16608#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
16613#define MCG_ATCVH_ATCVH_MASK (0xFFU)
16614#define MCG_ATCVH_ATCVH_SHIFT (0U)
16615#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
16620#define MCG_ATCVL_ATCVL_MASK (0xFFU)
16621#define MCG_ATCVL_ATCVL_SHIFT (0U)
16622#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
16627#define MCG_C8_LOLRE_MASK (0x40U)
16628#define MCG_C8_LOLRE_SHIFT (6U)
16633#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
16639 /* end of group MCG_Register_Masks */
16640
16641
16642/* MCG - Peripheral instance base addresses */
16644#define MCG_BASE (0x40064000u)
16646#define MCG ((MCG_Type *)MCG_BASE)
16648#define MCG_BASE_ADDRS { MCG_BASE }
16650#define MCG_BASE_PTRS { MCG }
16652#define MCG_IRQS { MCG_IRQn }
16653/* MCG C5[PLLCLKEN0] backward compatibility */
16654#define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
16655#define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
16656#define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
16657#define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
16658
16659/* MCG C5[PLLSTEN0] backward compatibility */
16660#define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
16661#define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
16662#define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
16663#define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
16664
16665/* MCG C5[PRDIV0] backward compatibility */
16666#define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
16667#define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
16668#define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
16669#define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
16670
16671/* MCG C6[VDIV0] backward compatibility */
16672#define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
16673#define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
16674#define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
16675#define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
16676
16677
16680 /* end of group MCG_Peripheral_Access_Layer */
16681
16682
16683/* ----------------------------------------------------------------------------
16684 -- MCM Peripheral Access Layer
16685 ---------------------------------------------------------------------------- */
16686
16693typedef struct {
16694 __I uint32_t PCT;
16695 uint8_t RESERVED_0[8];
16696 __IO uint32_t CR;
16697 __IO uint32_t ISCR;
16698 uint8_t RESERVED_1[32];
16699 __IO uint32_t CPO;
16700 uint8_t RESERVED_2[968];
16701 __I uint32_t LMEM[5];
16702} MCM_Type;
16703
16704/* ----------------------------------------------------------------------------
16705 -- MCM Register Masks
16706 ---------------------------------------------------------------------------- */
16707
16715#define MCM_PCT_PLREV_MASK (0xFFFFU)
16716#define MCM_PCT_PLREV_SHIFT (0U)
16717#define MCM_PCT_PLREV(x) (((uint32_t)(((uint32_t)(x)) << MCM_PCT_PLREV_SHIFT)) & MCM_PCT_PLREV_MASK)
16718#define MCM_PCT_PCT_MASK (0xFFFF0000U)
16719#define MCM_PCT_PCT_SHIFT (16U)
16720#define MCM_PCT_PCT(x) (((uint32_t)(((uint32_t)(x)) << MCM_PCT_PCT_SHIFT)) & MCM_PCT_PCT_MASK)
16725#define MCM_CR_AHBSPRI_MASK (0x8000000U)
16726#define MCM_CR_AHBSPRI_SHIFT (27U)
16731#define MCM_CR_AHBSPRI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_AHBSPRI_SHIFT)) & MCM_CR_AHBSPRI_MASK)
16736#define MCM_ISCR_FIOC_MASK (0x100U)
16737#define MCM_ISCR_FIOC_SHIFT (8U)
16742#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
16743#define MCM_ISCR_FDZC_MASK (0x200U)
16744#define MCM_ISCR_FDZC_SHIFT (9U)
16749#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
16750#define MCM_ISCR_FOFC_MASK (0x400U)
16751#define MCM_ISCR_FOFC_SHIFT (10U)
16756#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
16757#define MCM_ISCR_FUFC_MASK (0x800U)
16758#define MCM_ISCR_FUFC_SHIFT (11U)
16763#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
16764#define MCM_ISCR_FIXC_MASK (0x1000U)
16765#define MCM_ISCR_FIXC_SHIFT (12U)
16770#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
16771#define MCM_ISCR_FIDC_MASK (0x8000U)
16772#define MCM_ISCR_FIDC_SHIFT (15U)
16777#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
16778#define MCM_ISCR_FIOCE_MASK (0x1000000U)
16779#define MCM_ISCR_FIOCE_SHIFT (24U)
16784#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
16785#define MCM_ISCR_FDZCE_MASK (0x2000000U)
16786#define MCM_ISCR_FDZCE_SHIFT (25U)
16791#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
16792#define MCM_ISCR_FOFCE_MASK (0x4000000U)
16793#define MCM_ISCR_FOFCE_SHIFT (26U)
16798#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
16799#define MCM_ISCR_FUFCE_MASK (0x8000000U)
16800#define MCM_ISCR_FUFCE_SHIFT (27U)
16805#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
16806#define MCM_ISCR_FIXCE_MASK (0x10000000U)
16807#define MCM_ISCR_FIXCE_SHIFT (28U)
16812#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
16813#define MCM_ISCR_FIDCE_MASK (0x80000000U)
16814#define MCM_ISCR_FIDCE_SHIFT (31U)
16819#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
16824#define MCM_CPO_CPOREQ_MASK (0x1U)
16825#define MCM_CPO_CPOREQ_SHIFT (0U)
16830#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
16831#define MCM_CPO_CPOACK_MASK (0x2U)
16832#define MCM_CPO_CPOACK_SHIFT (1U)
16837#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
16842#define MCM_LMEM_LMEM_Type_MASK (0xE000U)
16843#define MCM_LMEM_LMEM_Type_SHIFT (13U)
16850#define MCM_LMEM_LMEM_Type(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Type_SHIFT)) & MCM_LMEM_LMEM_Type_MASK)
16851#define MCM_LMEM_LMEM_Width_MASK (0xE0000U)
16852#define MCM_LMEM_LMEM_Width_SHIFT (17U)
16857#define MCM_LMEM_LMEM_Width(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Width_SHIFT)) & MCM_LMEM_LMEM_Width_MASK)
16858#define MCM_LMEM_LMEM_Ways_MASK (0xF00000U)
16859#define MCM_LMEM_LMEM_Ways_SHIFT (20U)
16865#define MCM_LMEM_LMEM_Ways(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Ways_SHIFT)) & MCM_LMEM_LMEM_Ways_MASK)
16866#define MCM_LMEM_LMEM_Size_MASK (0xF000000U)
16867#define MCM_LMEM_LMEM_Size_SHIFT (24U)
16873#define MCM_LMEM_LMEM_Size(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Size_SHIFT)) & MCM_LMEM_LMEM_Size_MASK)
16874#define MCM_LMEM_LMEM_Valid_MASK (0x80000000U)
16875#define MCM_LMEM_LMEM_Valid_SHIFT (31U)
16880#define MCM_LMEM_LMEM_Valid(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMEM_LMEM_Valid_SHIFT)) & MCM_LMEM_LMEM_Valid_MASK)
16883/* The count of MCM_LMEM */
16884#define MCM_LMEM_COUNT (5U)
16885
16886
16889 /* end of group MCM_Register_Masks */
16890
16891
16892/* MCM - Peripheral instance base addresses */
16894#define MCM_BASE (0xE0080000u)
16896#define MCM ((MCM_Type *)MCM_BASE)
16898#define MCM_BASE_ADDRS { MCM_BASE }
16900#define MCM_BASE_PTRS { MCM }
16902#define MCM_IRQS { MCM_IRQn }
16903
16906 /* end of group MCM_Peripheral_Access_Layer */
16907
16908
16909/* ----------------------------------------------------------------------------
16910 -- MSCM Peripheral Access Layer
16911 ---------------------------------------------------------------------------- */
16912
16919typedef struct {
16920 __I uint32_t CPxTYPE;
16921 __I uint32_t CPxNUM;
16922 __I uint32_t CPxMASTER;
16923 __I uint32_t CPxCOUNT;
16924 uint8_t RESERVED_0[4];
16925 __I uint32_t CPxCFG1;
16926 uint8_t RESERVED_1[4];
16927 __I uint32_t CPxCFG3;
16928 struct { /* offset: 0x20, array step: 0x20 */
16929 __I uint32_t TYPE;
16930 __I uint32_t NUM;
16931 __I uint32_t MASTER;
16932 __I uint32_t COUNT;
16933 uint8_t RESERVED_0[4];
16934 __I uint32_t CFG1;
16935 uint8_t RESERVED_1[4];
16936 __I uint32_t CFG3;
16937 } CP[2];
16938 uint8_t RESERVED_2[928];
16939 __I uint32_t OCMDR[3];
16940} MSCM_Type;
16941
16942/* ----------------------------------------------------------------------------
16943 -- MSCM Register Masks
16944 ---------------------------------------------------------------------------- */
16945
16953#define MSCM_CPxTYPE_RYPZ_MASK (0xFFU)
16954#define MSCM_CPxTYPE_RYPZ_SHIFT (0U)
16955#define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_RYPZ_SHIFT)) & MSCM_CPxTYPE_RYPZ_MASK)
16956#define MSCM_CPxTYPE_PERSONALITY_MASK (0xFFFFFF00U)
16957#define MSCM_CPxTYPE_PERSONALITY_SHIFT (8U)
16958#define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_PERSONALITY_SHIFT)) & MSCM_CPxTYPE_PERSONALITY_MASK)
16963#define MSCM_CPxNUM_CPN_MASK (0x1U)
16964#define MSCM_CPxNUM_CPN_SHIFT (0U)
16965#define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxNUM_CPN_SHIFT)) & MSCM_CPxNUM_CPN_MASK)
16970#define MSCM_CPxMASTER_PPN_MASK (0x3FU)
16971#define MSCM_CPxMASTER_PPN_SHIFT (0U)
16972#define MSCM_CPxMASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxMASTER_PPN_SHIFT)) & MSCM_CPxMASTER_PPN_MASK)
16977#define MSCM_CPxCOUNT_PCNT_MASK (0x3U)
16978#define MSCM_CPxCOUNT_PCNT_SHIFT (0U)
16979#define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCOUNT_PCNT_SHIFT)) & MSCM_CPxCOUNT_PCNT_MASK)
16984#define MSCM_CPxCFG1_L2WY_MASK (0xFF0000U)
16985#define MSCM_CPxCFG1_L2WY_SHIFT (16U)
16986#define MSCM_CPxCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_L2WY_SHIFT)) & MSCM_CPxCFG1_L2WY_MASK)
16987#define MSCM_CPxCFG1_L2SZ_MASK (0xFF000000U)
16988#define MSCM_CPxCFG1_L2SZ_SHIFT (24U)
16989#define MSCM_CPxCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_L2SZ_SHIFT)) & MSCM_CPxCFG1_L2SZ_MASK)
16994#define MSCM_CPxCFG3_FPU_MASK (0x1U)
16995#define MSCM_CPxCFG3_FPU_SHIFT (0U)
16996#define MSCM_CPxCFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_FPU_SHIFT)) & MSCM_CPxCFG3_FPU_MASK)
16997#define MSCM_CPxCFG3_SIMD_MASK (0x2U)
16998#define MSCM_CPxCFG3_SIMD_SHIFT (1U)
16999#define MSCM_CPxCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_SIMD_SHIFT)) & MSCM_CPxCFG3_SIMD_MASK)
17000#define MSCM_CPxCFG3_JAZ_MASK (0x4U)
17001#define MSCM_CPxCFG3_JAZ_SHIFT (2U)
17002#define MSCM_CPxCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_JAZ_SHIFT)) & MSCM_CPxCFG3_JAZ_MASK)
17003#define MSCM_CPxCFG3_MMU_MASK (0x8U)
17004#define MSCM_CPxCFG3_MMU_SHIFT (3U)
17005#define MSCM_CPxCFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_MMU_SHIFT)) & MSCM_CPxCFG3_MMU_MASK)
17006#define MSCM_CPxCFG3_TZ_MASK (0x10U)
17007#define MSCM_CPxCFG3_TZ_SHIFT (4U)
17008#define MSCM_CPxCFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_TZ_SHIFT)) & MSCM_CPxCFG3_TZ_MASK)
17009#define MSCM_CPxCFG3_CMP_MASK (0x20U)
17010#define MSCM_CPxCFG3_CMP_SHIFT (5U)
17011#define MSCM_CPxCFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_CMP_SHIFT)) & MSCM_CPxCFG3_CMP_MASK)
17012#define MSCM_CPxCFG3_BB_MASK (0x40U)
17013#define MSCM_CPxCFG3_BB_SHIFT (6U)
17014#define MSCM_CPxCFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_BB_SHIFT)) & MSCM_CPxCFG3_BB_MASK)
17015#define MSCM_CPxCFG3_SBP_MASK (0x300U)
17016#define MSCM_CPxCFG3_SBP_SHIFT (8U)
17017#define MSCM_CPxCFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_SBP_SHIFT)) & MSCM_CPxCFG3_SBP_MASK)
17022#define MSCM_TYPE_RYPZ_MASK (0xFFU)
17023#define MSCM_TYPE_RYPZ_SHIFT (0U)
17024#define MSCM_TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_RYPZ_SHIFT)) & MSCM_TYPE_RYPZ_MASK)
17025#define MSCM_TYPE_PERSONALITY_MASK (0xFFFFFF00U)
17026#define MSCM_TYPE_PERSONALITY_SHIFT (8U)
17027#define MSCM_TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_PERSONALITY_SHIFT)) & MSCM_TYPE_PERSONALITY_MASK)
17030/* The count of MSCM_TYPE */
17031#define MSCM_TYPE_COUNT (2U)
17032
17035#define MSCM_NUM_CPN_MASK (0x1U)
17036#define MSCM_NUM_CPN_SHIFT (0U)
17037#define MSCM_NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_NUM_CPN_SHIFT)) & MSCM_NUM_CPN_MASK)
17040/* The count of MSCM_NUM */
17041#define MSCM_NUM_COUNT (2U)
17042
17045#define MSCM_MASTER_PPN_MASK (0x3FU)
17046#define MSCM_MASTER_PPN_SHIFT (0U)
17047#define MSCM_MASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_MASTER_PPN_SHIFT)) & MSCM_MASTER_PPN_MASK)
17050/* The count of MSCM_MASTER */
17051#define MSCM_MASTER_COUNT (2U)
17052
17055#define MSCM_COUNT_PCNT_MASK (0x3U)
17056#define MSCM_COUNT_PCNT_SHIFT (0U)
17057#define MSCM_COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_COUNT_PCNT_SHIFT)) & MSCM_COUNT_PCNT_MASK)
17060/* The count of MSCM_COUNT */
17061#define MSCM_COUNT_COUNT (2U)
17062
17065#define MSCM_CFG1_L2WY_MASK (0xFF0000U)
17066#define MSCM_CFG1_L2WY_SHIFT (16U)
17067#define MSCM_CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2WY_SHIFT)) & MSCM_CFG1_L2WY_MASK)
17068#define MSCM_CFG1_L2SZ_MASK (0xFF000000U)
17069#define MSCM_CFG1_L2SZ_SHIFT (24U)
17070#define MSCM_CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2SZ_SHIFT)) & MSCM_CFG1_L2SZ_MASK)
17073/* The count of MSCM_CFG1 */
17074#define MSCM_CFG1_COUNT (2U)
17075
17078#define MSCM_CFG3_FPU_MASK (0x1U)
17079#define MSCM_CFG3_FPU_SHIFT (0U)
17080#define MSCM_CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK)
17081#define MSCM_CFG3_SIMD_MASK (0x2U)
17082#define MSCM_CFG3_SIMD_SHIFT (1U)
17083#define MSCM_CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SIMD_SHIFT)) & MSCM_CFG3_SIMD_MASK)
17084#define MSCM_CFG3_JAZ_MASK (0x4U)
17085#define MSCM_CFG3_JAZ_SHIFT (2U)
17086#define MSCM_CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_JAZ_SHIFT)) & MSCM_CFG3_JAZ_MASK)
17087#define MSCM_CFG3_MMU_MASK (0x8U)
17088#define MSCM_CFG3_MMU_SHIFT (3U)
17089#define MSCM_CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_MMU_SHIFT)) & MSCM_CFG3_MMU_MASK)
17090#define MSCM_CFG3_TZ_MASK (0x10U)
17091#define MSCM_CFG3_TZ_SHIFT (4U)
17092#define MSCM_CFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_TZ_SHIFT)) & MSCM_CFG3_TZ_MASK)
17093#define MSCM_CFG3_CMP_MASK (0x20U)
17094#define MSCM_CFG3_CMP_SHIFT (5U)
17095#define MSCM_CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_CMP_SHIFT)) & MSCM_CFG3_CMP_MASK)
17096#define MSCM_CFG3_BB_MASK (0x40U)
17097#define MSCM_CFG3_BB_SHIFT (6U)
17098#define MSCM_CFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_BB_SHIFT)) & MSCM_CFG3_BB_MASK)
17099#define MSCM_CFG3_SBP_MASK (0x300U)
17100#define MSCM_CFG3_SBP_SHIFT (8U)
17101#define MSCM_CFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SBP_SHIFT)) & MSCM_CFG3_SBP_MASK)
17104/* The count of MSCM_CFG3 */
17105#define MSCM_CFG3_COUNT (2U)
17106
17109#define MSCM_OCMDR_OCMPU_MASK (0x1000U)
17110#define MSCM_OCMDR_OCMPU_SHIFT (12U)
17115#define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMPU_SHIFT)) & MSCM_OCMDR_OCMPU_MASK)
17116#define MSCM_OCMDR_OCMT_MASK (0xE000U)
17117#define MSCM_OCMDR_OCMT_SHIFT (13U)
17128#define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMT_SHIFT)) & MSCM_OCMDR_OCMT_MASK)
17129#define MSCM_OCMDR_OCMW_MASK (0xE0000U)
17130#define MSCM_OCMDR_OCMW_SHIFT (17U)
17137#define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMW_SHIFT)) & MSCM_OCMDR_OCMW_MASK)
17138#define MSCM_OCMDR_OCMSZ_MASK (0xF000000U)
17139#define MSCM_OCMDR_OCMSZ_SHIFT (24U)
17156#define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZ_SHIFT)) & MSCM_OCMDR_OCMSZ_MASK)
17157#define MSCM_OCMDR_OCMSZH_MASK (0x10000000U)
17158#define MSCM_OCMDR_OCMSZH_SHIFT (28U)
17163#define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZH_SHIFT)) & MSCM_OCMDR_OCMSZH_MASK)
17164#define MSCM_OCMDR_FMT_MASK (0x40000000U)
17165#define MSCM_OCMDR_FMT_SHIFT (30U)
17170#define MSCM_OCMDR_FMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_FMT_SHIFT)) & MSCM_OCMDR_FMT_MASK)
17171#define MSCM_OCMDR_V_MASK (0x80000000U)
17172#define MSCM_OCMDR_V_SHIFT (31U)
17177#define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_V_SHIFT)) & MSCM_OCMDR_V_MASK)
17180/* The count of MSCM_OCMDR */
17181#define MSCM_OCMDR_COUNT (3U)
17182
17183
17186 /* end of group MSCM_Register_Masks */
17187
17188
17189/* MSCM - Peripheral instance base addresses */
17191#define MSCM_BASE (0x40001000u)
17193#define MSCM ((MSCM_Type *)MSCM_BASE)
17195#define MSCM_BASE_ADDRS { MSCM_BASE }
17197#define MSCM_BASE_PTRS { MSCM }
17198
17201 /* end of group MSCM_Peripheral_Access_Layer */
17202
17203
17204/* ----------------------------------------------------------------------------
17205 -- NV Peripheral Access Layer
17206 ---------------------------------------------------------------------------- */
17207
17214typedef struct {
17215 __I uint8_t BACKKEY3;
17216 __I uint8_t BACKKEY2;
17217 __I uint8_t BACKKEY1;
17218 __I uint8_t BACKKEY0;
17219 __I uint8_t BACKKEY7;
17220 __I uint8_t BACKKEY6;
17221 __I uint8_t BACKKEY5;
17222 __I uint8_t BACKKEY4;
17223 __I uint8_t FPROT3;
17224 __I uint8_t FPROT2;
17225 __I uint8_t FPROT1;
17226 __I uint8_t FPROT0;
17227 __I uint8_t FSEC;
17228 __I uint8_t FOPT;
17229} NV_Type;
17230
17231/* ----------------------------------------------------------------------------
17232 -- NV Register Masks
17233 ---------------------------------------------------------------------------- */
17234
17242#define NV_BACKKEY3_KEY_MASK (0xFFU)
17243#define NV_BACKKEY3_KEY_SHIFT (0U)
17244#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
17249#define NV_BACKKEY2_KEY_MASK (0xFFU)
17250#define NV_BACKKEY2_KEY_SHIFT (0U)
17251#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
17256#define NV_BACKKEY1_KEY_MASK (0xFFU)
17257#define NV_BACKKEY1_KEY_SHIFT (0U)
17258#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
17263#define NV_BACKKEY0_KEY_MASK (0xFFU)
17264#define NV_BACKKEY0_KEY_SHIFT (0U)
17265#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
17270#define NV_BACKKEY7_KEY_MASK (0xFFU)
17271#define NV_BACKKEY7_KEY_SHIFT (0U)
17272#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
17277#define NV_BACKKEY6_KEY_MASK (0xFFU)
17278#define NV_BACKKEY6_KEY_SHIFT (0U)
17279#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
17284#define NV_BACKKEY5_KEY_MASK (0xFFU)
17285#define NV_BACKKEY5_KEY_SHIFT (0U)
17286#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
17291#define NV_BACKKEY4_KEY_MASK (0xFFU)
17292#define NV_BACKKEY4_KEY_SHIFT (0U)
17293#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
17298#define NV_FPROT3_PROT_MASK (0xFFU)
17299#define NV_FPROT3_PROT_SHIFT (0U)
17300#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
17305#define NV_FPROT2_PROT_MASK (0xFFU)
17306#define NV_FPROT2_PROT_SHIFT (0U)
17307#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
17312#define NV_FPROT1_PROT_MASK (0xFFU)
17313#define NV_FPROT1_PROT_SHIFT (0U)
17314#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
17319#define NV_FPROT0_PROT_MASK (0xFFU)
17320#define NV_FPROT0_PROT_SHIFT (0U)
17321#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
17326#define NV_FSEC_SEC_MASK (0x3U)
17327#define NV_FSEC_SEC_SHIFT (0U)
17332#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
17333#define NV_FSEC_FSLACC_MASK (0xCU)
17334#define NV_FSEC_FSLACC_SHIFT (2U)
17339#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
17340#define NV_FSEC_MEEN_MASK (0x30U)
17341#define NV_FSEC_MEEN_SHIFT (4U)
17346#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
17347#define NV_FSEC_KEYEN_MASK (0xC0U)
17348#define NV_FSEC_KEYEN_SHIFT (6U)
17353#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
17358#define NV_FOPT_LPBOOT_MASK (0x1U)
17359#define NV_FOPT_LPBOOT_SHIFT (0U)
17364#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
17365#define NV_FOPT_NMI_DIS_MASK (0x4U)
17366#define NV_FOPT_NMI_DIS_SHIFT (2U)
17371#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
17372#define NV_FOPT_FAST_INIT_MASK (0x20U)
17373#define NV_FOPT_FAST_INIT_SHIFT (5U)
17378#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
17384 /* end of group NV_Register_Masks */
17385
17386
17387/* NV - Peripheral instance base addresses */
17389#define FTFL_FlashConfig_BASE (0x400u)
17391#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
17393#define NV_BASE_ADDRS { FTFL_FlashConfig_BASE }
17395#define NV_BASE_PTRS { FTFL_FlashConfig }
17396
17399 /* end of group NV_Peripheral_Access_Layer */
17400
17401
17402/* ----------------------------------------------------------------------------
17403 -- OSC Peripheral Access Layer
17404 ---------------------------------------------------------------------------- */
17405
17412typedef struct {
17413 __IO uint8_t CR;
17414 uint8_t RESERVED_0[1];
17415 __IO uint8_t DIV;
17416} OSC_Type;
17417
17418/* ----------------------------------------------------------------------------
17419 -- OSC Register Masks
17420 ---------------------------------------------------------------------------- */
17421
17429#define OSC_CR_SC16P_MASK (0x1U)
17430#define OSC_CR_SC16P_SHIFT (0U)
17435#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
17436#define OSC_CR_SC8P_MASK (0x2U)
17437#define OSC_CR_SC8P_SHIFT (1U)
17442#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
17443#define OSC_CR_SC4P_MASK (0x4U)
17444#define OSC_CR_SC4P_SHIFT (2U)
17449#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
17450#define OSC_CR_SC2P_MASK (0x8U)
17451#define OSC_CR_SC2P_SHIFT (3U)
17456#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
17457#define OSC_CR_EREFSTEN_MASK (0x20U)
17458#define OSC_CR_EREFSTEN_SHIFT (5U)
17463#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
17464#define OSC_CR_ERCLKEN_MASK (0x80U)
17465#define OSC_CR_ERCLKEN_SHIFT (7U)
17470#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
17475#define OSC_DIV_ERPS_MASK (0xC0U)
17476#define OSC_DIV_ERPS_SHIFT (6U)
17483#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
17489 /* end of group OSC_Register_Masks */
17490
17491
17492/* OSC - Peripheral instance base addresses */
17494#define OSC0_BASE (0x40065000u)
17496#define OSC0 ((OSC_Type *)OSC0_BASE)
17498#define OSC_BASE_ADDRS { OSC0_BASE }
17500#define OSC_BASE_PTRS { OSC0 }
17501
17504 /* end of group OSC_Peripheral_Access_Layer */
17505
17506
17507/* ----------------------------------------------------------------------------
17508 -- PDB Peripheral Access Layer
17509 ---------------------------------------------------------------------------- */
17510
17517typedef struct {
17518 __IO uint32_t SC;
17519 __IO uint32_t MOD;
17520 __I uint32_t CNT;
17521 __IO uint32_t IDLY;
17522 struct { /* offset: 0x10, array step: 0x28 */
17523 __IO uint32_t C1;
17524 __IO uint32_t S;
17525 __IO uint32_t DLY[2];
17526 uint8_t RESERVED_0[24];
17527 } CH[2];
17528 uint8_t RESERVED_0[240];
17529 struct { /* offset: 0x150, array step: 0x8 */
17530 __IO uint32_t INTC;
17531 __IO uint32_t INT;
17532 } DAC[1];
17533 uint8_t RESERVED_1[56];
17534 __IO uint32_t POEN;
17535 __IO uint32_t PODLY[2];
17536} PDB_Type;
17537
17538/* ----------------------------------------------------------------------------
17539 -- PDB Register Masks
17540 ---------------------------------------------------------------------------- */
17541
17549#define PDB_SC_LDOK_MASK (0x1U)
17550#define PDB_SC_LDOK_SHIFT (0U)
17551#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
17552#define PDB_SC_CONT_MASK (0x2U)
17553#define PDB_SC_CONT_SHIFT (1U)
17558#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
17559#define PDB_SC_MULT_MASK (0xCU)
17560#define PDB_SC_MULT_SHIFT (2U)
17567#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
17568#define PDB_SC_PDBIE_MASK (0x20U)
17569#define PDB_SC_PDBIE_SHIFT (5U)
17574#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
17575#define PDB_SC_PDBIF_MASK (0x40U)
17576#define PDB_SC_PDBIF_SHIFT (6U)
17577#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
17578#define PDB_SC_PDBEN_MASK (0x80U)
17579#define PDB_SC_PDBEN_SHIFT (7U)
17584#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
17585#define PDB_SC_TRGSEL_MASK (0xF00U)
17586#define PDB_SC_TRGSEL_SHIFT (8U)
17605#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
17606#define PDB_SC_PRESCALER_MASK (0x7000U)
17607#define PDB_SC_PRESCALER_SHIFT (12U)
17618#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
17619#define PDB_SC_DMAEN_MASK (0x8000U)
17620#define PDB_SC_DMAEN_SHIFT (15U)
17625#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
17626#define PDB_SC_SWTRIG_MASK (0x10000U)
17627#define PDB_SC_SWTRIG_SHIFT (16U)
17628#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
17629#define PDB_SC_PDBEIE_MASK (0x20000U)
17630#define PDB_SC_PDBEIE_SHIFT (17U)
17635#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
17636#define PDB_SC_LDMOD_MASK (0xC0000U)
17637#define PDB_SC_LDMOD_SHIFT (18U)
17644#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
17649#define PDB_MOD_MOD_MASK (0xFFFFU)
17650#define PDB_MOD_MOD_SHIFT (0U)
17651#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
17656#define PDB_CNT_CNT_MASK (0xFFFFU)
17657#define PDB_CNT_CNT_SHIFT (0U)
17658#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
17663#define PDB_IDLY_IDLY_MASK (0xFFFFU)
17664#define PDB_IDLY_IDLY_SHIFT (0U)
17665#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
17670#define PDB_C1_EN_MASK (0xFFU)
17671#define PDB_C1_EN_SHIFT (0U)
17676#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
17677#define PDB_C1_TOS_MASK (0xFF00U)
17678#define PDB_C1_TOS_SHIFT (8U)
17683#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
17684#define PDB_C1_BB_MASK (0xFF0000U)
17685#define PDB_C1_BB_SHIFT (16U)
17690#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
17693/* The count of PDB_C1 */
17694#define PDB_C1_COUNT (2U)
17695
17698#define PDB_S_ERR_MASK (0xFFU)
17699#define PDB_S_ERR_SHIFT (0U)
17704#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
17705#define PDB_S_CF_MASK (0xFF0000U)
17706#define PDB_S_CF_SHIFT (16U)
17707#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
17710/* The count of PDB_S */
17711#define PDB_S_COUNT (2U)
17712
17715#define PDB_DLY_DLY_MASK (0xFFFFU)
17716#define PDB_DLY_DLY_SHIFT (0U)
17717#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
17720/* The count of PDB_DLY */
17721#define PDB_DLY_COUNT (2U)
17722
17723/* The count of PDB_DLY */
17724#define PDB_DLY_COUNT2 (2U)
17725
17728#define PDB_INTC_TOE_MASK (0x1U)
17729#define PDB_INTC_TOE_SHIFT (0U)
17734#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
17735#define PDB_INTC_EXT_MASK (0x2U)
17736#define PDB_INTC_EXT_SHIFT (1U)
17741#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
17744/* The count of PDB_INTC */
17745#define PDB_INTC_COUNT (1U)
17746
17749#define PDB_INT_INT_MASK (0xFFFFU)
17750#define PDB_INT_INT_SHIFT (0U)
17751#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
17754/* The count of PDB_INT */
17755#define PDB_INT_COUNT (1U)
17756
17759#define PDB_POEN_POEN_MASK (0xFFU)
17760#define PDB_POEN_POEN_SHIFT (0U)
17765#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
17770#define PDB_PODLY_DLY2_MASK (0xFFFFU)
17771#define PDB_PODLY_DLY2_SHIFT (0U)
17772#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
17773#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
17774#define PDB_PODLY_DLY1_SHIFT (16U)
17775#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
17778/* The count of PDB_PODLY */
17779#define PDB_PODLY_COUNT (2U)
17780
17781
17784 /* end of group PDB_Register_Masks */
17785
17786
17787/* PDB - Peripheral instance base addresses */
17789#define PDB0_BASE (0x40036000u)
17791#define PDB0 ((PDB_Type *)PDB0_BASE)
17793#define PDB1_BASE (0x40031000u)
17795#define PDB1 ((PDB_Type *)PDB1_BASE)
17797#define PDB_BASE_ADDRS { PDB0_BASE, PDB1_BASE }
17799#define PDB_BASE_PTRS { PDB0, PDB1 }
17801#define PDB_IRQS { PDB0_IRQn, PDB1_IRQn }
17802
17805 /* end of group PDB_Peripheral_Access_Layer */
17806
17807
17808/* ----------------------------------------------------------------------------
17809 -- PIT Peripheral Access Layer
17810 ---------------------------------------------------------------------------- */
17811
17818typedef struct {
17819 __IO uint32_t MCR;
17820 uint8_t RESERVED_0[220];
17821 __I uint32_t LTMR64H;
17822 __I uint32_t LTMR64L;
17823 uint8_t RESERVED_1[24];
17824 struct { /* offset: 0x100, array step: 0x10 */
17825 __IO uint32_t LDVAL;
17826 __I uint32_t CVAL;
17827 __IO uint32_t TCTRL;
17828 __IO uint32_t TFLG;
17829 } CHANNEL[4];
17830} PIT_Type;
17831
17832/* ----------------------------------------------------------------------------
17833 -- PIT Register Masks
17834 ---------------------------------------------------------------------------- */
17835
17843#define PIT_MCR_FRZ_MASK (0x1U)
17844#define PIT_MCR_FRZ_SHIFT (0U)
17849#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
17850#define PIT_MCR_MDIS_MASK (0x2U)
17851#define PIT_MCR_MDIS_SHIFT (1U)
17856#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
17861#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
17862#define PIT_LTMR64H_LTH_SHIFT (0U)
17863#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
17868#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
17869#define PIT_LTMR64L_LTL_SHIFT (0U)
17870#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
17875#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
17876#define PIT_LDVAL_TSV_SHIFT (0U)
17877#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
17880/* The count of PIT_LDVAL */
17881#define PIT_LDVAL_COUNT (4U)
17882
17885#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
17886#define PIT_CVAL_TVL_SHIFT (0U)
17887#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
17890/* The count of PIT_CVAL */
17891#define PIT_CVAL_COUNT (4U)
17892
17895#define PIT_TCTRL_TEN_MASK (0x1U)
17896#define PIT_TCTRL_TEN_SHIFT (0U)
17901#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
17902#define PIT_TCTRL_TIE_MASK (0x2U)
17903#define PIT_TCTRL_TIE_SHIFT (1U)
17908#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
17909#define PIT_TCTRL_CHN_MASK (0x4U)
17910#define PIT_TCTRL_CHN_SHIFT (2U)
17915#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
17918/* The count of PIT_TCTRL */
17919#define PIT_TCTRL_COUNT (4U)
17920
17923#define PIT_TFLG_TIF_MASK (0x1U)
17924#define PIT_TFLG_TIF_SHIFT (0U)
17929#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
17932/* The count of PIT_TFLG */
17933#define PIT_TFLG_COUNT (4U)
17934
17935
17938 /* end of group PIT_Register_Masks */
17939
17940
17941/* PIT - Peripheral instance base addresses */
17943#define PIT_BASE (0x40037000u)
17945#define PIT ((PIT_Type *)PIT_BASE)
17947#define PIT_BASE_ADDRS { PIT_BASE }
17949#define PIT_BASE_PTRS { PIT }
17951#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
17952
17955 /* end of group PIT_Peripheral_Access_Layer */
17956
17957
17958/* ----------------------------------------------------------------------------
17959 -- PMC Peripheral Access Layer
17960 ---------------------------------------------------------------------------- */
17961
17968typedef struct {
17969 __IO uint8_t LVDSC1;
17970 __IO uint8_t LVDSC2;
17971 __IO uint8_t REGSC;
17972 uint8_t RESERVED_0[8];
17973 __IO uint8_t HVDSC1;
17974} PMC_Type;
17975
17976/* ----------------------------------------------------------------------------
17977 -- PMC Register Masks
17978 ---------------------------------------------------------------------------- */
17979
17987#define PMC_LVDSC1_LVDV_MASK (0x3U)
17988#define PMC_LVDSC1_LVDV_SHIFT (0U)
17995#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
17996#define PMC_LVDSC1_LVDRE_MASK (0x10U)
17997#define PMC_LVDSC1_LVDRE_SHIFT (4U)
18002#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
18003#define PMC_LVDSC1_LVDIE_MASK (0x20U)
18004#define PMC_LVDSC1_LVDIE_SHIFT (5U)
18009#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
18010#define PMC_LVDSC1_LVDACK_MASK (0x40U)
18011#define PMC_LVDSC1_LVDACK_SHIFT (6U)
18012#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
18013#define PMC_LVDSC1_LVDF_MASK (0x80U)
18014#define PMC_LVDSC1_LVDF_SHIFT (7U)
18019#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
18024#define PMC_LVDSC2_LVWV_MASK (0x3U)
18025#define PMC_LVDSC2_LVWV_SHIFT (0U)
18032#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
18033#define PMC_LVDSC2_LVWIE_MASK (0x20U)
18034#define PMC_LVDSC2_LVWIE_SHIFT (5U)
18039#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
18040#define PMC_LVDSC2_LVWACK_MASK (0x40U)
18041#define PMC_LVDSC2_LVWACK_SHIFT (6U)
18042#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
18043#define PMC_LVDSC2_LVWF_MASK (0x80U)
18044#define PMC_LVDSC2_LVWF_SHIFT (7U)
18049#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
18054#define PMC_REGSC_BGBE_MASK (0x1U)
18055#define PMC_REGSC_BGBE_SHIFT (0U)
18060#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
18061#define PMC_REGSC_REGONS_MASK (0x4U)
18062#define PMC_REGSC_REGONS_SHIFT (2U)
18067#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
18068#define PMC_REGSC_ACKISO_MASK (0x8U)
18069#define PMC_REGSC_ACKISO_SHIFT (3U)
18074#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
18075#define PMC_REGSC_BGEN_MASK (0x10U)
18076#define PMC_REGSC_BGEN_SHIFT (4U)
18081#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
18086#define PMC_HVDSC1_HVDV_MASK (0x1U)
18087#define PMC_HVDSC1_HVDV_SHIFT (0U)
18092#define PMC_HVDSC1_HVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK)
18093#define PMC_HVDSC1_HVDRE_MASK (0x10U)
18094#define PMC_HVDSC1_HVDRE_SHIFT (4U)
18099#define PMC_HVDSC1_HVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK)
18100#define PMC_HVDSC1_HVDIE_MASK (0x20U)
18101#define PMC_HVDSC1_HVDIE_SHIFT (5U)
18106#define PMC_HVDSC1_HVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK)
18107#define PMC_HVDSC1_HVDACK_MASK (0x40U)
18108#define PMC_HVDSC1_HVDACK_SHIFT (6U)
18109#define PMC_HVDSC1_HVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK)
18110#define PMC_HVDSC1_HVDF_MASK (0x80U)
18111#define PMC_HVDSC1_HVDF_SHIFT (7U)
18116#define PMC_HVDSC1_HVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK)
18122 /* end of group PMC_Register_Masks */
18123
18124
18125/* PMC - Peripheral instance base addresses */
18127#define PMC_BASE (0x4007D000u)
18129#define PMC ((PMC_Type *)PMC_BASE)
18131#define PMC_BASE_ADDRS { PMC_BASE }
18133#define PMC_BASE_PTRS { PMC }
18135#define PMC_IRQS { PMC_IRQn }
18136
18139 /* end of group PMC_Peripheral_Access_Layer */
18140
18141
18142/* ----------------------------------------------------------------------------
18143 -- PORT Peripheral Access Layer
18144 ---------------------------------------------------------------------------- */
18145
18152typedef struct {
18153 __IO uint32_t PCR[32];
18154 __O uint32_t GPCLR;
18155 __O uint32_t GPCHR;
18156 uint8_t RESERVED_0[24];
18157 __IO uint32_t ISFR;
18158 uint8_t RESERVED_1[28];
18159 __IO uint32_t DFER;
18160 __IO uint32_t DFCR;
18161 __IO uint32_t DFWR;
18162} PORT_Type;
18163
18164/* ----------------------------------------------------------------------------
18165 -- PORT Register Masks
18166 ---------------------------------------------------------------------------- */
18167
18175#define PORT_PCR_PS_MASK (0x1U)
18176#define PORT_PCR_PS_SHIFT (0U)
18181#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
18182#define PORT_PCR_PE_MASK (0x2U)
18183#define PORT_PCR_PE_SHIFT (1U)
18188#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
18189#define PORT_PCR_SRE_MASK (0x4U)
18190#define PORT_PCR_SRE_SHIFT (2U)
18195#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
18196#define PORT_PCR_PFE_MASK (0x10U)
18197#define PORT_PCR_PFE_SHIFT (4U)
18202#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
18203#define PORT_PCR_ODE_MASK (0x20U)
18204#define PORT_PCR_ODE_SHIFT (5U)
18209#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
18210#define PORT_PCR_DSE_MASK (0x40U)
18211#define PORT_PCR_DSE_SHIFT (6U)
18216#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
18217#define PORT_PCR_MUX_MASK (0xF00U)
18218#define PORT_PCR_MUX_SHIFT (8U)
18237#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
18238#define PORT_PCR_LK_MASK (0x8000U)
18239#define PORT_PCR_LK_SHIFT (15U)
18244#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
18245#define PORT_PCR_IRQC_MASK (0xF0000U)
18246#define PORT_PCR_IRQC_SHIFT (16U)
18265#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
18266#define PORT_PCR_ISF_MASK (0x1000000U)
18267#define PORT_PCR_ISF_SHIFT (24U)
18272#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
18275/* The count of PORT_PCR */
18276#define PORT_PCR_COUNT (32U)
18277
18280#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
18281#define PORT_GPCLR_GPWD_SHIFT (0U)
18282#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
18283#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
18284#define PORT_GPCLR_GPWE_SHIFT (16U)
18289#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
18294#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
18295#define PORT_GPCHR_GPWD_SHIFT (0U)
18296#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
18297#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
18298#define PORT_GPCHR_GPWE_SHIFT (16U)
18303#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
18308#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
18309#define PORT_ISFR_ISF_SHIFT (0U)
18314#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
18319#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
18320#define PORT_DFER_DFE_SHIFT (0U)
18325#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
18330#define PORT_DFCR_CS_MASK (0x1U)
18331#define PORT_DFCR_CS_SHIFT (0U)
18336#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
18341#define PORT_DFWR_FILT_MASK (0x1FU)
18342#define PORT_DFWR_FILT_SHIFT (0U)
18343#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
18349 /* end of group PORT_Register_Masks */
18350
18351
18352/* PORT - Peripheral instance base addresses */
18354#define PORTA_BASE (0x40049000u)
18356#define PORTA ((PORT_Type *)PORTA_BASE)
18358#define PORTB_BASE (0x4004A000u)
18360#define PORTB ((PORT_Type *)PORTB_BASE)
18362#define PORTC_BASE (0x4004B000u)
18364#define PORTC ((PORT_Type *)PORTC_BASE)
18366#define PORTD_BASE (0x4004C000u)
18368#define PORTD ((PORT_Type *)PORTD_BASE)
18370#define PORTE_BASE (0x4004D000u)
18372#define PORTE ((PORT_Type *)PORTE_BASE)
18374#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
18376#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
18378#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
18379
18382 /* end of group PORT_Peripheral_Access_Layer */
18383
18384
18385/* ----------------------------------------------------------------------------
18386 -- PWM Peripheral Access Layer
18387 ---------------------------------------------------------------------------- */
18388
18395typedef struct {
18396 struct { /* offset: 0x0, array step: 0x60 */
18397 __I uint16_t CNT;
18398 __IO uint16_t INIT;
18399 __IO uint16_t CTRL2;
18400 __IO uint16_t CTRL;
18401 uint8_t RESERVED_0[2];
18402 __IO uint16_t VAL0;
18403 __IO uint16_t FRACVAL1;
18404 __IO uint16_t VAL1;
18405 __IO uint16_t FRACVAL2;
18406 __IO uint16_t VAL2;
18407 __IO uint16_t FRACVAL3;
18408 __IO uint16_t VAL3;
18409 __IO uint16_t FRACVAL4;
18410 __IO uint16_t VAL4;
18411 __IO uint16_t FRACVAL5;
18412 __IO uint16_t VAL5;
18413 __IO uint16_t FRCTRL;
18414 __IO uint16_t OCTRL;
18415 __IO uint16_t STS;
18416 __IO uint16_t INTEN;
18417 __IO uint16_t DMAEN;
18418 __IO uint16_t TCTRL;
18419 __IO uint16_t DISMAP[1];
18420 uint8_t RESERVED_1[2];
18421 __IO uint16_t DTCNT0;
18422 __IO uint16_t DTCNT1;
18423 __IO uint16_t CAPTCTRLA;
18424 __IO uint16_t CAPTCOMPA;
18425 __IO uint16_t CAPTCTRLB;
18426 __IO uint16_t CAPTCOMPB;
18427 __IO uint16_t CAPTCTRLX;
18428 __IO uint16_t CAPTCOMPX;
18429 __I uint16_t CVAL0;
18430 __I uint16_t CVAL0CYC;
18431 __I uint16_t CVAL1;
18432 __I uint16_t CVAL1CYC;
18433 __I uint16_t CVAL2;
18434 __I uint16_t CVAL2CYC;
18435 __I uint16_t CVAL3;
18436 __I uint16_t CVAL3CYC;
18437 __I uint16_t CVAL4;
18438 __I uint16_t CVAL4CYC;
18439 __I uint16_t CVAL5;
18440 __I uint16_t CVAL5CYC;
18441 uint8_t RESERVED_2[8];
18442 } SM[4];
18443 __IO uint16_t OUTEN;
18444 __IO uint16_t MASK;
18445 __IO uint16_t SWCOUT;
18446 __IO uint16_t DTSRCSEL;
18447 __IO uint16_t MCTRL;
18448 __IO uint16_t MCTRL2;
18449 __IO uint16_t FCTRL;
18450 __IO uint16_t FSTS;
18451 __IO uint16_t FFILT;
18452 __IO uint16_t FTST;
18453 __IO uint16_t FCTRL2;
18454} PWM_Type;
18455
18456/* ----------------------------------------------------------------------------
18457 -- PWM Register Masks
18458 ---------------------------------------------------------------------------- */
18459
18467#define PWM_CNT_CNT_MASK (0xFFFFU)
18468#define PWM_CNT_CNT_SHIFT (0U)
18469#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
18472/* The count of PWM_CNT */
18473#define PWM_CNT_COUNT (4U)
18474
18477#define PWM_INIT_INIT_MASK (0xFFFFU)
18478#define PWM_INIT_INIT_SHIFT (0U)
18479#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
18482/* The count of PWM_INIT */
18483#define PWM_INIT_COUNT (4U)
18484
18487#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
18488#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
18495#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
18496#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
18497#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
18502#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
18503#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
18504#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
18515#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
18516#define PWM_CTRL2_FORCE_MASK (0x40U)
18517#define PWM_CTRL2_FORCE_SHIFT (6U)
18518#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
18519#define PWM_CTRL2_FRCEN_MASK (0x80U)
18520#define PWM_CTRL2_FRCEN_SHIFT (7U)
18525#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
18526#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
18527#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
18534#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
18535#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
18536#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
18537#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
18538#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
18539#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
18540#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
18541#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
18542#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
18543#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
18544#define PWM_CTRL2_INDEP_MASK (0x2000U)
18545#define PWM_CTRL2_INDEP_SHIFT (13U)
18550#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
18551#define PWM_CTRL2_WAITEN_MASK (0x4000U)
18552#define PWM_CTRL2_WAITEN_SHIFT (14U)
18553#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
18554#define PWM_CTRL2_DBGEN_MASK (0x8000U)
18555#define PWM_CTRL2_DBGEN_SHIFT (15U)
18556#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
18559/* The count of PWM_CTRL2 */
18560#define PWM_CTRL2_COUNT (4U)
18561
18564#define PWM_CTRL_DBLEN_MASK (0x1U)
18565#define PWM_CTRL_DBLEN_SHIFT (0U)
18570#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
18571#define PWM_CTRL_DBLX_MASK (0x2U)
18572#define PWM_CTRL_DBLX_SHIFT (1U)
18577#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
18578#define PWM_CTRL_LDMOD_MASK (0x4U)
18579#define PWM_CTRL_LDMOD_SHIFT (2U)
18584#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
18585#define PWM_CTRL_PRSC_MASK (0x70U)
18586#define PWM_CTRL_PRSC_SHIFT (4U)
18597#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
18598#define PWM_CTRL_DT_MASK (0x300U)
18599#define PWM_CTRL_DT_SHIFT (8U)
18600#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
18601#define PWM_CTRL_FULL_MASK (0x400U)
18602#define PWM_CTRL_FULL_SHIFT (10U)
18607#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
18608#define PWM_CTRL_HALF_MASK (0x800U)
18609#define PWM_CTRL_HALF_SHIFT (11U)
18614#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
18615#define PWM_CTRL_LDFQ_MASK (0xF000U)
18616#define PWM_CTRL_LDFQ_SHIFT (12U)
18635#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
18638/* The count of PWM_CTRL */
18639#define PWM_CTRL_COUNT (4U)
18640
18643#define PWM_VAL0_VAL0_MASK (0xFFFFU)
18644#define PWM_VAL0_VAL0_SHIFT (0U)
18645#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
18648/* The count of PWM_VAL0 */
18649#define PWM_VAL0_COUNT (4U)
18650
18653#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
18654#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
18655#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
18658/* The count of PWM_FRACVAL1 */
18659#define PWM_FRACVAL1_COUNT (4U)
18660
18663#define PWM_VAL1_VAL1_MASK (0xFFFFU)
18664#define PWM_VAL1_VAL1_SHIFT (0U)
18665#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
18668/* The count of PWM_VAL1 */
18669#define PWM_VAL1_COUNT (4U)
18670
18673#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
18674#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
18675#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
18678/* The count of PWM_FRACVAL2 */
18679#define PWM_FRACVAL2_COUNT (4U)
18680
18683#define PWM_VAL2_VAL2_MASK (0xFFFFU)
18684#define PWM_VAL2_VAL2_SHIFT (0U)
18685#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
18688/* The count of PWM_VAL2 */
18689#define PWM_VAL2_COUNT (4U)
18690
18693#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
18694#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
18695#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
18698/* The count of PWM_FRACVAL3 */
18699#define PWM_FRACVAL3_COUNT (4U)
18700
18703#define PWM_VAL3_VAL3_MASK (0xFFFFU)
18704#define PWM_VAL3_VAL3_SHIFT (0U)
18705#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
18708/* The count of PWM_VAL3 */
18709#define PWM_VAL3_COUNT (4U)
18710
18713#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
18714#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
18715#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
18718/* The count of PWM_FRACVAL4 */
18719#define PWM_FRACVAL4_COUNT (4U)
18720
18723#define PWM_VAL4_VAL4_MASK (0xFFFFU)
18724#define PWM_VAL4_VAL4_SHIFT (0U)
18725#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
18728/* The count of PWM_VAL4 */
18729#define PWM_VAL4_COUNT (4U)
18730
18733#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
18734#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
18735#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
18738/* The count of PWM_FRACVAL5 */
18739#define PWM_FRACVAL5_COUNT (4U)
18740
18743#define PWM_VAL5_VAL5_MASK (0xFFFFU)
18744#define PWM_VAL5_VAL5_SHIFT (0U)
18745#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
18748/* The count of PWM_VAL5 */
18749#define PWM_VAL5_COUNT (4U)
18750
18753#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
18754#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
18759#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
18760#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
18761#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
18766#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
18767#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
18768#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
18773#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
18774#define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
18775#define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
18780#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
18781#define PWM_FRCTRL_TEST_MASK (0x8000U)
18782#define PWM_FRCTRL_TEST_SHIFT (15U)
18783#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
18786/* The count of PWM_FRCTRL */
18787#define PWM_FRCTRL_COUNT (4U)
18788
18791#define PWM_OCTRL_PWMXFS_MASK (0x3U)
18792#define PWM_OCTRL_PWMXFS_SHIFT (0U)
18799#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
18800#define PWM_OCTRL_PWMBFS_MASK (0xCU)
18801#define PWM_OCTRL_PWMBFS_SHIFT (2U)
18808#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
18809#define PWM_OCTRL_PWMAFS_MASK (0x30U)
18810#define PWM_OCTRL_PWMAFS_SHIFT (4U)
18817#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
18818#define PWM_OCTRL_POLX_MASK (0x100U)
18819#define PWM_OCTRL_POLX_SHIFT (8U)
18824#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
18825#define PWM_OCTRL_POLB_MASK (0x200U)
18826#define PWM_OCTRL_POLB_SHIFT (9U)
18831#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
18832#define PWM_OCTRL_POLA_MASK (0x400U)
18833#define PWM_OCTRL_POLA_SHIFT (10U)
18838#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
18839#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
18840#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
18841#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
18842#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
18843#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
18844#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
18845#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
18846#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
18847#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
18850/* The count of PWM_OCTRL */
18851#define PWM_OCTRL_COUNT (4U)
18852
18855#define PWM_STS_CMPF_MASK (0x3FU)
18856#define PWM_STS_CMPF_SHIFT (0U)
18861#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
18862#define PWM_STS_CFX0_MASK (0x40U)
18863#define PWM_STS_CFX0_SHIFT (6U)
18864#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
18865#define PWM_STS_CFX1_MASK (0x80U)
18866#define PWM_STS_CFX1_SHIFT (7U)
18867#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
18868#define PWM_STS_CFB0_MASK (0x100U)
18869#define PWM_STS_CFB0_SHIFT (8U)
18870#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
18871#define PWM_STS_CFB1_MASK (0x200U)
18872#define PWM_STS_CFB1_SHIFT (9U)
18873#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
18874#define PWM_STS_CFA0_MASK (0x400U)
18875#define PWM_STS_CFA0_SHIFT (10U)
18876#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
18877#define PWM_STS_CFA1_MASK (0x800U)
18878#define PWM_STS_CFA1_SHIFT (11U)
18879#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
18880#define PWM_STS_RF_MASK (0x1000U)
18881#define PWM_STS_RF_SHIFT (12U)
18886#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
18887#define PWM_STS_REF_MASK (0x2000U)
18888#define PWM_STS_REF_SHIFT (13U)
18893#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
18894#define PWM_STS_RUF_MASK (0x4000U)
18895#define PWM_STS_RUF_SHIFT (14U)
18900#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
18903/* The count of PWM_STS */
18904#define PWM_STS_COUNT (4U)
18905
18908#define PWM_INTEN_CMPIE_MASK (0x3FU)
18909#define PWM_INTEN_CMPIE_SHIFT (0U)
18914#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
18915#define PWM_INTEN_CX0IE_MASK (0x40U)
18916#define PWM_INTEN_CX0IE_SHIFT (6U)
18921#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
18922#define PWM_INTEN_CX1IE_MASK (0x80U)
18923#define PWM_INTEN_CX1IE_SHIFT (7U)
18928#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
18929#define PWM_INTEN_CB0IE_MASK (0x100U)
18930#define PWM_INTEN_CB0IE_SHIFT (8U)
18935#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
18936#define PWM_INTEN_CB1IE_MASK (0x200U)
18937#define PWM_INTEN_CB1IE_SHIFT (9U)
18942#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
18943#define PWM_INTEN_CA0IE_MASK (0x400U)
18944#define PWM_INTEN_CA0IE_SHIFT (10U)
18949#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
18950#define PWM_INTEN_CA1IE_MASK (0x800U)
18951#define PWM_INTEN_CA1IE_SHIFT (11U)
18956#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
18957#define PWM_INTEN_RIE_MASK (0x1000U)
18958#define PWM_INTEN_RIE_SHIFT (12U)
18963#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
18964#define PWM_INTEN_REIE_MASK (0x2000U)
18965#define PWM_INTEN_REIE_SHIFT (13U)
18970#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
18973/* The count of PWM_INTEN */
18974#define PWM_INTEN_COUNT (4U)
18975
18978#define PWM_DMAEN_CX0DE_MASK (0x1U)
18979#define PWM_DMAEN_CX0DE_SHIFT (0U)
18980#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
18981#define PWM_DMAEN_CX1DE_MASK (0x2U)
18982#define PWM_DMAEN_CX1DE_SHIFT (1U)
18983#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
18984#define PWM_DMAEN_CB0DE_MASK (0x4U)
18985#define PWM_DMAEN_CB0DE_SHIFT (2U)
18986#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
18987#define PWM_DMAEN_CB1DE_MASK (0x8U)
18988#define PWM_DMAEN_CB1DE_SHIFT (3U)
18989#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
18990#define PWM_DMAEN_CA0DE_MASK (0x10U)
18991#define PWM_DMAEN_CA0DE_SHIFT (4U)
18992#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
18993#define PWM_DMAEN_CA1DE_MASK (0x20U)
18994#define PWM_DMAEN_CA1DE_SHIFT (5U)
18995#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
18996#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
18997#define PWM_DMAEN_CAPTDE_SHIFT (6U)
19004#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
19005#define PWM_DMAEN_FAND_MASK (0x100U)
19006#define PWM_DMAEN_FAND_SHIFT (8U)
19011#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
19012#define PWM_DMAEN_VALDE_MASK (0x200U)
19013#define PWM_DMAEN_VALDE_SHIFT (9U)
19018#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
19021/* The count of PWM_DMAEN */
19022#define PWM_DMAEN_COUNT (4U)
19023
19026#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
19027#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
19032#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
19033#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
19034#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
19039#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
19040#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
19041#define PWM_TCTRL_PWBOT1_SHIFT (14U)
19046#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
19047#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
19048#define PWM_TCTRL_PWAOT0_SHIFT (15U)
19053#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
19056/* The count of PWM_TCTRL */
19057#define PWM_TCTRL_COUNT (4U)
19058
19061#define PWM_DISMAP_DIS0A_MASK (0xFU)
19062#define PWM_DISMAP_DIS0A_SHIFT (0U)
19063#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
19064#define PWM_DISMAP_DIS0B_MASK (0xF0U)
19065#define PWM_DISMAP_DIS0B_SHIFT (4U)
19066#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
19067#define PWM_DISMAP_DIS0X_MASK (0xF00U)
19068#define PWM_DISMAP_DIS0X_SHIFT (8U)
19069#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
19072/* The count of PWM_DISMAP */
19073#define PWM_DISMAP_COUNT (4U)
19074
19075/* The count of PWM_DISMAP */
19076#define PWM_DISMAP_COUNT2 (1U)
19077
19080#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
19081#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
19082#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
19085/* The count of PWM_DTCNT0 */
19086#define PWM_DTCNT0_COUNT (4U)
19087
19090#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
19091#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
19092#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
19095/* The count of PWM_DTCNT1 */
19096#define PWM_DTCNT1_COUNT (4U)
19097
19100#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
19101#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
19106#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
19107#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
19108#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
19113#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
19114#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
19115#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
19122#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
19123#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
19124#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
19131#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
19132#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
19133#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
19138#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
19139#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
19140#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
19145#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
19146#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
19147#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
19148#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
19149#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
19150#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
19151#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
19152#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
19153#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
19154#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
19157/* The count of PWM_CAPTCTRLA */
19158#define PWM_CAPTCTRLA_COUNT (4U)
19159
19162#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
19163#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
19164#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
19165#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
19166#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
19167#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
19170/* The count of PWM_CAPTCOMPA */
19171#define PWM_CAPTCOMPA_COUNT (4U)
19172
19175#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
19176#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
19181#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
19182#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
19183#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
19188#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
19189#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
19190#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
19197#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
19198#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
19199#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
19206#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
19207#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
19208#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
19213#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
19214#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
19215#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
19220#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
19221#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
19222#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
19223#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
19224#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
19225#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
19226#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
19227#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
19228#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
19229#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
19232/* The count of PWM_CAPTCTRLB */
19233#define PWM_CAPTCTRLB_COUNT (4U)
19234
19237#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
19238#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
19239#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
19240#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
19241#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
19242#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
19245/* The count of PWM_CAPTCOMPB */
19246#define PWM_CAPTCOMPB_COUNT (4U)
19247
19250#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
19251#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
19256#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
19257#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
19258#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
19263#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
19264#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
19265#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
19272#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
19273#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
19274#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
19281#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
19282#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
19283#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
19288#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
19289#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
19290#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
19295#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
19296#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
19297#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
19298#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
19299#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
19300#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
19301#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
19302#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
19303#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
19304#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
19307/* The count of PWM_CAPTCTRLX */
19308#define PWM_CAPTCTRLX_COUNT (4U)
19309
19312#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
19313#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
19314#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
19315#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
19316#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
19317#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
19320/* The count of PWM_CAPTCOMPX */
19321#define PWM_CAPTCOMPX_COUNT (4U)
19322
19325#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
19326#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
19327#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
19330/* The count of PWM_CVAL0 */
19331#define PWM_CVAL0_COUNT (4U)
19332
19335#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
19336#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
19337#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
19340/* The count of PWM_CVAL0CYC */
19341#define PWM_CVAL0CYC_COUNT (4U)
19342
19345#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
19346#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
19347#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
19350/* The count of PWM_CVAL1 */
19351#define PWM_CVAL1_COUNT (4U)
19352
19355#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
19356#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
19357#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
19360/* The count of PWM_CVAL1CYC */
19361#define PWM_CVAL1CYC_COUNT (4U)
19362
19365#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
19366#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
19367#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
19370/* The count of PWM_CVAL2 */
19371#define PWM_CVAL2_COUNT (4U)
19372
19375#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
19376#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
19377#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
19380/* The count of PWM_CVAL2CYC */
19381#define PWM_CVAL2CYC_COUNT (4U)
19382
19385#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
19386#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
19387#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
19390/* The count of PWM_CVAL3 */
19391#define PWM_CVAL3_COUNT (4U)
19392
19395#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
19396#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
19397#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
19400/* The count of PWM_CVAL3CYC */
19401#define PWM_CVAL3CYC_COUNT (4U)
19402
19405#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
19406#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
19407#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
19410/* The count of PWM_CVAL4 */
19411#define PWM_CVAL4_COUNT (4U)
19412
19415#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
19416#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
19417#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
19420/* The count of PWM_CVAL4CYC */
19421#define PWM_CVAL4CYC_COUNT (4U)
19422
19425#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
19426#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
19427#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
19430/* The count of PWM_CVAL5 */
19431#define PWM_CVAL5_COUNT (4U)
19432
19435#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
19436#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
19437#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
19440/* The count of PWM_CVAL5CYC */
19441#define PWM_CVAL5CYC_COUNT (4U)
19442
19445#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
19446#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
19451#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
19452#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
19453#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
19458#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
19459#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
19460#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
19465#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
19470#define PWM_MASK_MASKX_MASK (0xFU)
19471#define PWM_MASK_MASKX_SHIFT (0U)
19476#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
19477#define PWM_MASK_MASKB_MASK (0xF0U)
19478#define PWM_MASK_MASKB_SHIFT (4U)
19483#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
19484#define PWM_MASK_MASKA_MASK (0xF00U)
19485#define PWM_MASK_MASKA_SHIFT (8U)
19490#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
19491#define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
19492#define PWM_MASK_UPDATE_MASK_SHIFT (12U)
19497#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
19502#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
19503#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
19508#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
19509#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
19510#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
19515#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
19516#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
19517#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
19522#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
19523#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
19524#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
19529#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
19530#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
19531#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
19536#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
19537#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
19538#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
19543#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
19544#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
19545#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
19550#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
19551#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
19552#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
19557#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
19562#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
19563#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
19570#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
19571#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
19572#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
19579#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
19580#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
19581#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
19588#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
19589#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
19590#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
19597#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
19598#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
19599#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
19606#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
19607#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
19608#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
19615#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
19616#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
19617#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
19624#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
19625#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
19626#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
19633#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
19638#define PWM_MCTRL_LDOK_MASK (0xFU)
19639#define PWM_MCTRL_LDOK_SHIFT (0U)
19644#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
19645#define PWM_MCTRL_CLDOK_MASK (0xF0U)
19646#define PWM_MCTRL_CLDOK_SHIFT (4U)
19647#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
19648#define PWM_MCTRL_RUN_MASK (0xF00U)
19649#define PWM_MCTRL_RUN_SHIFT (8U)
19654#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
19655#define PWM_MCTRL_IPOL_MASK (0xF000U)
19656#define PWM_MCTRL_IPOL_SHIFT (12U)
19661#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
19666#define PWM_MCTRL2_MONPLL_MASK (0x3U)
19667#define PWM_MCTRL2_MONPLL_SHIFT (0U)
19674#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
19679#define PWM_FCTRL_FIE_MASK (0xFU)
19680#define PWM_FCTRL_FIE_SHIFT (0U)
19685#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
19686#define PWM_FCTRL_FSAFE_MASK (0xF0U)
19687#define PWM_FCTRL_FSAFE_SHIFT (4U)
19692#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
19693#define PWM_FCTRL_FAUTO_MASK (0xF00U)
19694#define PWM_FCTRL_FAUTO_SHIFT (8U)
19699#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
19700#define PWM_FCTRL_FLVL_MASK (0xF000U)
19701#define PWM_FCTRL_FLVL_SHIFT (12U)
19706#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
19711#define PWM_FSTS_FFLAG_MASK (0xFU)
19712#define PWM_FSTS_FFLAG_SHIFT (0U)
19717#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
19718#define PWM_FSTS_FFULL_MASK (0xF0U)
19719#define PWM_FSTS_FFULL_SHIFT (4U)
19724#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
19725#define PWM_FSTS_FFPIN_MASK (0xF00U)
19726#define PWM_FSTS_FFPIN_SHIFT (8U)
19727#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
19728#define PWM_FSTS_FHALF_MASK (0xF000U)
19729#define PWM_FSTS_FHALF_SHIFT (12U)
19734#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
19739#define PWM_FFILT_FILT_PER_MASK (0xFFU)
19740#define PWM_FFILT_FILT_PER_SHIFT (0U)
19741#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
19742#define PWM_FFILT_FILT_CNT_MASK (0x700U)
19743#define PWM_FFILT_FILT_CNT_SHIFT (8U)
19744#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
19745#define PWM_FFILT_GSTR_MASK (0x8000U)
19746#define PWM_FFILT_GSTR_SHIFT (15U)
19751#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
19756#define PWM_FTST_FTEST_MASK (0x1U)
19757#define PWM_FTST_FTEST_SHIFT (0U)
19762#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
19767#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
19768#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
19773#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
19779 /* end of group PWM_Register_Masks */
19780
19781
19782/* PWM - Peripheral instance base addresses */
19784#define PWM0_BASE (0x40033000u)
19786#define PWM0 ((PWM_Type *)PWM0_BASE)
19788#define PWM1_BASE (0x400B3000u)
19790#define PWM1 ((PWM_Type *)PWM1_BASE)
19792#define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE }
19794#define PWM_BASE_PTRS { PWM0, PWM1 }
19796#define PWM_CMP_IRQS { { PWM0_CMP0_IRQn, PWM0_CMP1_IRQn, PWM0_CMP2_IRQn, PWM0_CMP3_IRQn }, { PWM1_CMP0_IRQn, PWM1_CMP1_IRQn, PWM1_CMP2_IRQn, PWM1_CMP3_IRQn } }
19797#define PWM_RELOAD_IRQS { { PWM0_RELOAD0_IRQn, PWM0_RELOAD1_IRQn, PWM0_RELOAD2_IRQn, PWM0_RELOAD3_IRQn }, { PWM1_RELOAD0_IRQn, PWM1_RELOAD1_IRQn, PWM1_RELOAD2_IRQn, PWM1_RELOAD3_IRQn } }
19798#define PWM_CAP_IRQS { PWM0_CAP_IRQn, PWM1_CAP_IRQn }
19799#define PWM_RERR_IRQS { PWM0_RERR_IRQn, PWM1_RERR_IRQn }
19800#define PWM_FAULT_IRQS { PWM0_FAULT_IRQn, PWM1_FAULT_IRQn }
19801
19804 /* end of group PWM_Peripheral_Access_Layer */
19805
19806
19807/* ----------------------------------------------------------------------------
19808 -- RCM Peripheral Access Layer
19809 ---------------------------------------------------------------------------- */
19810
19817typedef struct {
19818 __I uint8_t SRS0;
19819 __I uint8_t SRS1;
19820 uint8_t RESERVED_0[2];
19821 __IO uint8_t RPFC;
19822 __IO uint8_t RPFW;
19823 uint8_t RESERVED_1[2];
19824 __IO uint8_t SSRS0;
19825 __IO uint8_t SSRS1;
19826} RCM_Type;
19827
19828/* ----------------------------------------------------------------------------
19829 -- RCM Register Masks
19830 ---------------------------------------------------------------------------- */
19831
19839#define RCM_SRS0_WAKEUP_MASK (0x1U)
19840#define RCM_SRS0_WAKEUP_SHIFT (0U)
19845#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
19846#define RCM_SRS0_LVD_MASK (0x2U)
19847#define RCM_SRS0_LVD_SHIFT (1U)
19852#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
19853#define RCM_SRS0_LOC_MASK (0x4U)
19854#define RCM_SRS0_LOC_SHIFT (2U)
19859#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
19860#define RCM_SRS0_LOL_MASK (0x8U)
19861#define RCM_SRS0_LOL_SHIFT (3U)
19866#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
19867#define RCM_SRS0_WDOG_MASK (0x20U)
19868#define RCM_SRS0_WDOG_SHIFT (5U)
19873#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
19874#define RCM_SRS0_PIN_MASK (0x40U)
19875#define RCM_SRS0_PIN_SHIFT (6U)
19880#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
19881#define RCM_SRS0_POR_MASK (0x80U)
19882#define RCM_SRS0_POR_SHIFT (7U)
19887#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
19892#define RCM_SRS1_JTAG_MASK (0x1U)
19893#define RCM_SRS1_JTAG_SHIFT (0U)
19898#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
19899#define RCM_SRS1_LOCKUP_MASK (0x2U)
19900#define RCM_SRS1_LOCKUP_SHIFT (1U)
19905#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
19906#define RCM_SRS1_SW_MASK (0x4U)
19907#define RCM_SRS1_SW_SHIFT (2U)
19912#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
19913#define RCM_SRS1_MDM_AP_MASK (0x8U)
19914#define RCM_SRS1_MDM_AP_SHIFT (3U)
19919#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
19920#define RCM_SRS1_SACKERR_MASK (0x20U)
19921#define RCM_SRS1_SACKERR_SHIFT (5U)
19926#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
19931#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
19932#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
19939#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
19940#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
19941#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
19946#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
19951#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
19952#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
19987#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
19992#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
19993#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
19998#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
19999#define RCM_SSRS0_SLVD_MASK (0x2U)
20000#define RCM_SSRS0_SLVD_SHIFT (1U)
20005#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
20006#define RCM_SSRS0_SLOC_MASK (0x4U)
20007#define RCM_SSRS0_SLOC_SHIFT (2U)
20012#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
20013#define RCM_SSRS0_SLOL_MASK (0x8U)
20014#define RCM_SSRS0_SLOL_SHIFT (3U)
20019#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
20020#define RCM_SSRS0_SWDOG_MASK (0x20U)
20021#define RCM_SSRS0_SWDOG_SHIFT (5U)
20026#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
20027#define RCM_SSRS0_SPIN_MASK (0x40U)
20028#define RCM_SSRS0_SPIN_SHIFT (6U)
20033#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
20034#define RCM_SSRS0_SPOR_MASK (0x80U)
20035#define RCM_SSRS0_SPOR_SHIFT (7U)
20040#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
20045#define RCM_SSRS1_SJTAG_MASK (0x1U)
20046#define RCM_SSRS1_SJTAG_SHIFT (0U)
20051#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
20052#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
20053#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
20058#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
20059#define RCM_SSRS1_SSW_MASK (0x4U)
20060#define RCM_SSRS1_SSW_SHIFT (2U)
20065#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
20066#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
20067#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
20072#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
20073#define RCM_SSRS1_SSACKERR_MASK (0x20U)
20074#define RCM_SSRS1_SSACKERR_SHIFT (5U)
20079#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
20085 /* end of group RCM_Register_Masks */
20086
20087
20088/* RCM - Peripheral instance base addresses */
20090#define RCM_BASE (0x4007F000u)
20092#define RCM ((RCM_Type *)RCM_BASE)
20094#define RCM_BASE_ADDRS { RCM_BASE }
20096#define RCM_BASE_PTRS { RCM }
20097
20100 /* end of group RCM_Peripheral_Access_Layer */
20101
20102
20103/* ----------------------------------------------------------------------------
20104 -- RFSYS Peripheral Access Layer
20105 ---------------------------------------------------------------------------- */
20106
20113typedef struct {
20114 __IO uint32_t REG[8];
20115} RFSYS_Type;
20116
20117/* ----------------------------------------------------------------------------
20118 -- RFSYS Register Masks
20119 ---------------------------------------------------------------------------- */
20120
20128#define RFSYS_REG_LL_MASK (0xFFU)
20129#define RFSYS_REG_LL_SHIFT (0U)
20130#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
20131#define RFSYS_REG_LH_MASK (0xFF00U)
20132#define RFSYS_REG_LH_SHIFT (8U)
20133#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
20134#define RFSYS_REG_HL_MASK (0xFF0000U)
20135#define RFSYS_REG_HL_SHIFT (16U)
20136#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
20137#define RFSYS_REG_HH_MASK (0xFF000000U)
20138#define RFSYS_REG_HH_SHIFT (24U)
20139#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
20142/* The count of RFSYS_REG */
20143#define RFSYS_REG_COUNT (8U)
20144
20145
20148 /* end of group RFSYS_Register_Masks */
20149
20150
20151/* RFSYS - Peripheral instance base addresses */
20153#define RFSYS_BASE (0x40041000u)
20155#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
20157#define RFSYS_BASE_ADDRS { RFSYS_BASE }
20159#define RFSYS_BASE_PTRS { RFSYS }
20160
20163 /* end of group RFSYS_Peripheral_Access_Layer */
20164
20165
20166/* ----------------------------------------------------------------------------
20167 -- RFVBAT Peripheral Access Layer
20168 ---------------------------------------------------------------------------- */
20169
20176typedef struct {
20177 __IO uint32_t REG[8];
20178} RFVBAT_Type;
20179
20180/* ----------------------------------------------------------------------------
20181 -- RFVBAT Register Masks
20182 ---------------------------------------------------------------------------- */
20183
20191#define RFVBAT_REG_LL_MASK (0xFFU)
20192#define RFVBAT_REG_LL_SHIFT (0U)
20193#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
20194#define RFVBAT_REG_LH_MASK (0xFF00U)
20195#define RFVBAT_REG_LH_SHIFT (8U)
20196#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
20197#define RFVBAT_REG_HL_MASK (0xFF0000U)
20198#define RFVBAT_REG_HL_SHIFT (16U)
20199#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
20200#define RFVBAT_REG_HH_MASK (0xFF000000U)
20201#define RFVBAT_REG_HH_SHIFT (24U)
20202#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
20205/* The count of RFVBAT_REG */
20206#define RFVBAT_REG_COUNT (8U)
20207
20208
20211 /* end of group RFVBAT_Register_Masks */
20212
20213
20214/* RFVBAT - Peripheral instance base addresses */
20216#define RFVBAT_BASE (0x4003E000u)
20218#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
20220#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
20222#define RFVBAT_BASE_PTRS { RFVBAT }
20223
20226 /* end of group RFVBAT_Peripheral_Access_Layer */
20227
20228
20229/* ----------------------------------------------------------------------------
20230 -- SIM Peripheral Access Layer
20231 ---------------------------------------------------------------------------- */
20232
20239typedef struct {
20240 __IO uint32_t SOPT1;
20241 uint8_t RESERVED_0[4096];
20242 __IO uint32_t SOPT2;
20243 uint8_t RESERVED_1[4];
20244 __IO uint32_t SOPT4;
20245 __IO uint32_t SOPT5;
20246 uint8_t RESERVED_2[4];
20247 __IO uint32_t SOPT7;
20248 __IO uint32_t SOPT8;
20249 __IO uint32_t SOPT9;
20250 __I uint32_t SDID;
20251 __IO uint32_t SCGC1;
20252 __IO uint32_t SCGC2;
20253 __IO uint32_t SCGC3;
20254 __IO uint32_t SCGC4;
20255 __IO uint32_t SCGC5;
20256 __IO uint32_t SCGC6;
20257 __IO uint32_t SCGC7;
20258 __IO uint32_t CLKDIV1;
20259 uint8_t RESERVED_3[4];
20260 __IO uint32_t FCFG1;
20261 __I uint32_t FCFG2;
20262 __I uint32_t UIDH;
20263 __I uint32_t UIDMH;
20264 __I uint32_t UIDML;
20265 __I uint32_t UIDL;
20266 uint8_t RESERVED_4[4];
20267 __IO uint32_t CLKDIV4;
20268 __IO uint32_t MISCTRL0;
20269 __IO uint32_t MISCTRL1;
20270 uint8_t RESERVED_5[140];
20271 __IO uint32_t WDOGC;
20272 __IO uint32_t PWRC;
20273 __IO uint32_t ADCOPT;
20274} SIM_Type;
20275
20276/* ----------------------------------------------------------------------------
20277 -- SIM Register Masks
20278 ---------------------------------------------------------------------------- */
20279
20287#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
20288#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
20300#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
20301#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
20302#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
20309#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
20314#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
20315#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
20326#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
20327#define SIM_SOPT2_FBSL_MASK (0x300U)
20328#define SIM_SOPT2_FBSL_SHIFT (8U)
20335#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
20336#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
20337#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
20342#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
20343#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
20344#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
20351#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
20352#define SIM_SOPT2_RMIISRC_MASK (0x80000U)
20353#define SIM_SOPT2_RMIISRC_SHIFT (19U)
20358#define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
20359#define SIM_SOPT2_TIMESRC_MASK (0x300000U)
20360#define SIM_SOPT2_TIMESRC_SHIFT (20U)
20367#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
20372#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
20373#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
20378#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
20379#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
20380#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
20385#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
20386#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
20387#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
20392#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
20393#define SIM_SOPT4_FTM0FLT3_MASK (0x8U)
20394#define SIM_SOPT4_FTM0FLT3_SHIFT (3U)
20399#define SIM_SOPT4_FTM0FLT3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
20400#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
20401#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
20406#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
20407#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
20408#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
20413#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
20414#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
20415#define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
20420#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
20421#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000U)
20422#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (16U)
20427#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
20428#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000U)
20429#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (17U)
20434#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
20435#define SIM_SOPT4_FTM0TRG2SRC_MASK (0x40000U)
20436#define SIM_SOPT4_FTM0TRG2SRC_SHIFT (18U)
20441#define SIM_SOPT4_FTM0TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG2SRC_SHIFT)) & SIM_SOPT4_FTM0TRG2SRC_MASK)
20442#define SIM_SOPT4_FTM1TRG0SRC_MASK (0x100000U)
20443#define SIM_SOPT4_FTM1TRG0SRC_SHIFT (20U)
20448#define SIM_SOPT4_FTM1TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG0SRC_SHIFT)) & SIM_SOPT4_FTM1TRG0SRC_MASK)
20449#define SIM_SOPT4_FTM1TRG2SRC_MASK (0x400000U)
20450#define SIM_SOPT4_FTM1TRG2SRC_SHIFT (22U)
20455#define SIM_SOPT4_FTM1TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG2SRC_SHIFT)) & SIM_SOPT4_FTM1TRG2SRC_MASK)
20456#define SIM_SOPT4_FTM2TRG0SRC_MASK (0x1000000U)
20457#define SIM_SOPT4_FTM2TRG0SRC_SHIFT (24U)
20462#define SIM_SOPT4_FTM2TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG0SRC_SHIFT)) & SIM_SOPT4_FTM2TRG0SRC_MASK)
20463#define SIM_SOPT4_FTM2TRG2SRC_MASK (0x4000000U)
20464#define SIM_SOPT4_FTM2TRG2SRC_SHIFT (26U)
20469#define SIM_SOPT4_FTM2TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG2SRC_SHIFT)) & SIM_SOPT4_FTM2TRG2SRC_MASK)
20470#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x10000000U)
20471#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (28U)
20476#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
20477#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x20000000U)
20478#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (29U)
20483#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
20484#define SIM_SOPT4_FTM3TRG2SRC_MASK (0x40000000U)
20485#define SIM_SOPT4_FTM3TRG2SRC_SHIFT (30U)
20490#define SIM_SOPT4_FTM3TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG2SRC_SHIFT)) & SIM_SOPT4_FTM3TRG2SRC_MASK)
20495#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
20496#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
20503#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
20504#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
20505#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
20512#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
20513#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
20514#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
20521#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
20522#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
20523#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
20530#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
20535#define SIM_SOPT7_HSADC0ATRGSEL_MASK (0xFU)
20536#define SIM_SOPT7_HSADC0ATRGSEL_SHIFT (0U)
20555#define SIM_SOPT7_HSADC0ATRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0ATRGSEL_SHIFT)) & SIM_SOPT7_HSADC0ATRGSEL_MASK)
20556#define SIM_SOPT7_HSADC0AALTTRGEN_MASK (0xC0U)
20557#define SIM_SOPT7_HSADC0AALTTRGEN_SHIFT (6U)
20562#define SIM_SOPT7_HSADC0AALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0AALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC0AALTTRGEN_MASK)
20563#define SIM_SOPT7_HSADC0BTRGSEL_MASK (0xF00U)
20564#define SIM_SOPT7_HSADC0BTRGSEL_SHIFT (8U)
20583#define SIM_SOPT7_HSADC0BTRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0BTRGSEL_SHIFT)) & SIM_SOPT7_HSADC0BTRGSEL_MASK)
20584#define SIM_SOPT7_HSADC0BALTTRGEN_MASK (0xC000U)
20585#define SIM_SOPT7_HSADC0BALTTRGEN_SHIFT (14U)
20590#define SIM_SOPT7_HSADC0BALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0BALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC0BALTTRGEN_MASK)
20591#define SIM_SOPT7_HSADC1ATRGSEL_MASK (0xF0000U)
20592#define SIM_SOPT7_HSADC1ATRGSEL_SHIFT (16U)
20611#define SIM_SOPT7_HSADC1ATRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1ATRGSEL_SHIFT)) & SIM_SOPT7_HSADC1ATRGSEL_MASK)
20612#define SIM_SOPT7_HSADC1AALTTRGEN_MASK (0xC00000U)
20613#define SIM_SOPT7_HSADC1AALTTRGEN_SHIFT (22U)
20618#define SIM_SOPT7_HSADC1AALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1AALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC1AALTTRGEN_MASK)
20619#define SIM_SOPT7_HSADC1BTRGSEL_MASK (0xF000000U)
20620#define SIM_SOPT7_HSADC1BTRGSEL_SHIFT (24U)
20639#define SIM_SOPT7_HSADC1BTRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1BTRGSEL_SHIFT)) & SIM_SOPT7_HSADC1BTRGSEL_MASK)
20640#define SIM_SOPT7_HSADC1BALTTRGEN_MASK (0xC0000000U)
20641#define SIM_SOPT7_HSADC1BALTTRGEN_SHIFT (30U)
20646#define SIM_SOPT7_HSADC1BALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1BALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC1BALTTRGEN_MASK)
20651#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
20652#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
20657#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
20658#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
20659#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
20664#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
20665#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
20666#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
20671#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
20672#define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
20673#define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
20678#define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
20679#define SIM_SOPT8_FTM0CFSEL_MASK (0x100U)
20680#define SIM_SOPT8_FTM0CFSEL_SHIFT (8U)
20685#define SIM_SOPT8_FTM0CFSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0CFSEL_SHIFT)) & SIM_SOPT8_FTM0CFSEL_MASK)
20686#define SIM_SOPT8_FTM3CFSEL_MASK (0x200U)
20687#define SIM_SOPT8_FTM3CFSEL_SHIFT (9U)
20692#define SIM_SOPT8_FTM3CFSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3CFSEL_SHIFT)) & SIM_SOPT8_FTM3CFSEL_MASK)
20693#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
20694#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
20699#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
20700#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
20701#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
20706#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
20707#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
20708#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
20713#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
20714#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
20715#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
20720#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
20721#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
20722#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
20727#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
20728#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
20729#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
20734#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
20735#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
20736#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
20741#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
20742#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
20743#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
20748#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
20749#define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
20750#define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
20755#define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
20756#define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
20757#define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
20762#define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
20763#define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
20764#define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
20769#define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
20770#define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
20771#define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
20776#define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
20777#define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
20778#define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
20783#define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
20784#define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
20785#define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
20790#define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
20791#define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
20792#define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
20797#define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
20798#define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
20799#define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
20804#define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
20809#define SIM_SOPT9_FTM1ICH0SRC_MASK (0x30U)
20810#define SIM_SOPT9_FTM1ICH0SRC_SHIFT (4U)
20817#define SIM_SOPT9_FTM1ICH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1ICH0SRC_SHIFT)) & SIM_SOPT9_FTM1ICH0SRC_MASK)
20818#define SIM_SOPT9_FTM1ICH1SRC_MASK (0x40U)
20819#define SIM_SOPT9_FTM1ICH1SRC_SHIFT (6U)
20824#define SIM_SOPT9_FTM1ICH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1ICH1SRC_SHIFT)) & SIM_SOPT9_FTM1ICH1SRC_MASK)
20825#define SIM_SOPT9_FTM2ICH0SRC_MASK (0x300U)
20826#define SIM_SOPT9_FTM2ICH0SRC_SHIFT (8U)
20833#define SIM_SOPT9_FTM2ICH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2ICH0SRC_SHIFT)) & SIM_SOPT9_FTM2ICH0SRC_MASK)
20834#define SIM_SOPT9_FTM2ICH1SRC_MASK (0x400U)
20835#define SIM_SOPT9_FTM2ICH1SRC_SHIFT (10U)
20840#define SIM_SOPT9_FTM2ICH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2ICH1SRC_SHIFT)) & SIM_SOPT9_FTM2ICH1SRC_MASK)
20841#define SIM_SOPT9_FTM0CLKSEL_MASK (0x3000000U)
20842#define SIM_SOPT9_FTM0CLKSEL_SHIFT (24U)
20849#define SIM_SOPT9_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM0CLKSEL_SHIFT)) & SIM_SOPT9_FTM0CLKSEL_MASK)
20850#define SIM_SOPT9_FTM1CLKSEL_MASK (0xC000000U)
20851#define SIM_SOPT9_FTM1CLKSEL_SHIFT (26U)
20858#define SIM_SOPT9_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1CLKSEL_SHIFT)) & SIM_SOPT9_FTM1CLKSEL_MASK)
20859#define SIM_SOPT9_FTM2CLKSEL_MASK (0x30000000U)
20860#define SIM_SOPT9_FTM2CLKSEL_SHIFT (28U)
20867#define SIM_SOPT9_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2CLKSEL_SHIFT)) & SIM_SOPT9_FTM2CLKSEL_MASK)
20868#define SIM_SOPT9_FTM3CLKSEL_MASK (0xC0000000U)
20869#define SIM_SOPT9_FTM3CLKSEL_SHIFT (30U)
20876#define SIM_SOPT9_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3CLKSEL_SHIFT)) & SIM_SOPT9_FTM3CLKSEL_MASK)
20881#define SIM_SDID_PINID_MASK (0xFU)
20882#define SIM_SDID_PINID_SHIFT (0U)
20888#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
20889#define SIM_SDID_DIEID_MASK (0xF80U)
20890#define SIM_SDID_DIEID_SHIFT (7U)
20894#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
20895#define SIM_SDID_REVID_MASK (0xF000U)
20896#define SIM_SDID_REVID_SHIFT (12U)
20897#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
20898#define SIM_SDID_SERIESID_MASK (0xF00000U)
20899#define SIM_SDID_SERIESID_SHIFT (20U)
20903#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
20904#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
20905#define SIM_SDID_SUBFAMID_SHIFT (24U)
20911#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
20912#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
20913#define SIM_SDID_FAMILYID_SHIFT (28U)
20917#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
20922#define SIM_SCGC1_UART4_MASK (0x400U)
20923#define SIM_SCGC1_UART4_SHIFT (10U)
20928#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
20929#define SIM_SCGC1_UART5_MASK (0x800U)
20930#define SIM_SCGC1_UART5_SHIFT (11U)
20935#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
20936#define SIM_SCGC1_PWM1_SM0_MASK (0x1000000U)
20937#define SIM_SCGC1_PWM1_SM0_SHIFT (24U)
20942#define SIM_SCGC1_PWM1_SM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM0_SHIFT)) & SIM_SCGC1_PWM1_SM0_MASK)
20943#define SIM_SCGC1_PWM1_SM1_MASK (0x2000000U)
20944#define SIM_SCGC1_PWM1_SM1_SHIFT (25U)
20949#define SIM_SCGC1_PWM1_SM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM1_SHIFT)) & SIM_SCGC1_PWM1_SM1_MASK)
20950#define SIM_SCGC1_PWM1_SM2_MASK (0x4000000U)
20951#define SIM_SCGC1_PWM1_SM2_SHIFT (26U)
20956#define SIM_SCGC1_PWM1_SM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM2_SHIFT)) & SIM_SCGC1_PWM1_SM2_MASK)
20957#define SIM_SCGC1_PWM1_SM3_MASK (0x8000000U)
20958#define SIM_SCGC1_PWM1_SM3_SHIFT (27U)
20963#define SIM_SCGC1_PWM1_SM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM3_SHIFT)) & SIM_SCGC1_PWM1_SM3_MASK)
20968#define SIM_SCGC2_ENET_MASK (0x1U)
20969#define SIM_SCGC2_ENET_SHIFT (0U)
20974#define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
20975#define SIM_SCGC2_HSADC1_MASK (0x10000000U)
20976#define SIM_SCGC2_HSADC1_SHIFT (28U)
20981#define SIM_SCGC2_HSADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_HSADC1_SHIFT)) & SIM_SCGC2_HSADC1_MASK)
20986#define SIM_SCGC3_TRNG_MASK (0x1U)
20987#define SIM_SCGC3_TRNG_SHIFT (0U)
20992#define SIM_SCGC3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_TRNG_SHIFT)) & SIM_SCGC3_TRNG_MASK)
20993#define SIM_SCGC3_FLEXCAN2_MASK (0x10U)
20994#define SIM_SCGC3_FLEXCAN2_SHIFT (4U)
20999#define SIM_SCGC3_FLEXCAN2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN2_SHIFT)) & SIM_SCGC3_FLEXCAN2_MASK)
21000#define SIM_SCGC3_SPI2_MASK (0x1000U)
21001#define SIM_SCGC3_SPI2_SHIFT (12U)
21006#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
21011#define SIM_SCGC4_EWM_MASK (0x2U)
21012#define SIM_SCGC4_EWM_SHIFT (1U)
21017#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
21018#define SIM_SCGC4_I2C0_MASK (0x40U)
21019#define SIM_SCGC4_I2C0_SHIFT (6U)
21024#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
21025#define SIM_SCGC4_I2C1_MASK (0x80U)
21026#define SIM_SCGC4_I2C1_SHIFT (7U)
21027#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
21028#define SIM_SCGC4_UART0_MASK (0x400U)
21029#define SIM_SCGC4_UART0_SHIFT (10U)
21034#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
21035#define SIM_SCGC4_UART1_MASK (0x800U)
21036#define SIM_SCGC4_UART1_SHIFT (11U)
21041#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
21042#define SIM_SCGC4_UART2_MASK (0x1000U)
21043#define SIM_SCGC4_UART2_SHIFT (12U)
21048#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
21049#define SIM_SCGC4_UART3_MASK (0x2000U)
21050#define SIM_SCGC4_UART3_SHIFT (13U)
21055#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
21056#define SIM_SCGC4_CMP_MASK (0x80000U)
21057#define SIM_SCGC4_CMP_SHIFT (19U)
21062#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
21063#define SIM_SCGC4_PWM0_SM0_MASK (0x1000000U)
21064#define SIM_SCGC4_PWM0_SM0_SHIFT (24U)
21069#define SIM_SCGC4_PWM0_SM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM0_SHIFT)) & SIM_SCGC4_PWM0_SM0_MASK)
21070#define SIM_SCGC4_PWM0_SM1_MASK (0x2000000U)
21071#define SIM_SCGC4_PWM0_SM1_SHIFT (25U)
21076#define SIM_SCGC4_PWM0_SM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM1_SHIFT)) & SIM_SCGC4_PWM0_SM1_MASK)
21077#define SIM_SCGC4_PWM0_SM2_MASK (0x4000000U)
21078#define SIM_SCGC4_PWM0_SM2_SHIFT (26U)
21083#define SIM_SCGC4_PWM0_SM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM2_SHIFT)) & SIM_SCGC4_PWM0_SM2_MASK)
21084#define SIM_SCGC4_PWM0_SM3_MASK (0x8000000U)
21085#define SIM_SCGC4_PWM0_SM3_SHIFT (27U)
21090#define SIM_SCGC4_PWM0_SM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM3_SHIFT)) & SIM_SCGC4_PWM0_SM3_MASK)
21095#define SIM_SCGC5_LPTMR_MASK (0x1U)
21096#define SIM_SCGC5_LPTMR_SHIFT (0U)
21101#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
21102#define SIM_SCGC5_PORTA_MASK (0x200U)
21103#define SIM_SCGC5_PORTA_SHIFT (9U)
21108#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
21109#define SIM_SCGC5_PORTB_MASK (0x400U)
21110#define SIM_SCGC5_PORTB_SHIFT (10U)
21115#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
21116#define SIM_SCGC5_PORTC_MASK (0x800U)
21117#define SIM_SCGC5_PORTC_SHIFT (11U)
21122#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
21123#define SIM_SCGC5_PORTD_MASK (0x1000U)
21124#define SIM_SCGC5_PORTD_SHIFT (12U)
21129#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
21130#define SIM_SCGC5_PORTE_MASK (0x2000U)
21131#define SIM_SCGC5_PORTE_SHIFT (13U)
21136#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
21137#define SIM_SCGC5_ENC_MASK (0x200000U)
21138#define SIM_SCGC5_ENC_SHIFT (21U)
21143#define SIM_SCGC5_ENC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ENC_SHIFT)) & SIM_SCGC5_ENC_MASK)
21144#define SIM_SCGC5_XBARA_MASK (0x2000000U)
21145#define SIM_SCGC5_XBARA_SHIFT (25U)
21150#define SIM_SCGC5_XBARA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBARA_SHIFT)) & SIM_SCGC5_XBARA_MASK)
21151#define SIM_SCGC5_XBARB_MASK (0x4000000U)
21152#define SIM_SCGC5_XBARB_SHIFT (26U)
21157#define SIM_SCGC5_XBARB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBARB_SHIFT)) & SIM_SCGC5_XBARB_MASK)
21158#define SIM_SCGC5_AOI_MASK (0x8000000U)
21159#define SIM_SCGC5_AOI_SHIFT (27U)
21164#define SIM_SCGC5_AOI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_AOI_SHIFT)) & SIM_SCGC5_AOI_MASK)
21165#define SIM_SCGC5_HSADC0_MASK (0x10000000U)
21166#define SIM_SCGC5_HSADC0_SHIFT (28U)
21171#define SIM_SCGC5_HSADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_HSADC0_SHIFT)) & SIM_SCGC5_HSADC0_MASK)
21176#define SIM_SCGC6_FTF_MASK (0x1U)
21177#define SIM_SCGC6_FTF_SHIFT (0U)
21182#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
21183#define SIM_SCGC6_DMAMUX_MASK (0x2U)
21184#define SIM_SCGC6_DMAMUX_SHIFT (1U)
21189#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
21190#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
21191#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
21196#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
21197#define SIM_SCGC6_FLEXCAN1_MASK (0x20U)
21198#define SIM_SCGC6_FLEXCAN1_SHIFT (5U)
21203#define SIM_SCGC6_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN1_SHIFT)) & SIM_SCGC6_FLEXCAN1_MASK)
21204#define SIM_SCGC6_FTM3_MASK (0x40U)
21205#define SIM_SCGC6_FTM3_SHIFT (6U)
21210#define SIM_SCGC6_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM3_SHIFT)) & SIM_SCGC6_FTM3_MASK)
21211#define SIM_SCGC6_SPI0_MASK (0x1000U)
21212#define SIM_SCGC6_SPI0_SHIFT (12U)
21217#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
21218#define SIM_SCGC6_SPI1_MASK (0x2000U)
21219#define SIM_SCGC6_SPI1_SHIFT (13U)
21224#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
21225#define SIM_SCGC6_PDB1_MASK (0x20000U)
21226#define SIM_SCGC6_PDB1_SHIFT (17U)
21231#define SIM_SCGC6_PDB1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB1_SHIFT)) & SIM_SCGC6_PDB1_MASK)
21232#define SIM_SCGC6_CRC_MASK (0x40000U)
21233#define SIM_SCGC6_CRC_SHIFT (18U)
21238#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
21239#define SIM_SCGC6_PDB0_MASK (0x400000U)
21240#define SIM_SCGC6_PDB0_SHIFT (22U)
21245#define SIM_SCGC6_PDB0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB0_SHIFT)) & SIM_SCGC6_PDB0_MASK)
21246#define SIM_SCGC6_PIT_MASK (0x800000U)
21247#define SIM_SCGC6_PIT_SHIFT (23U)
21252#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
21253#define SIM_SCGC6_FTM0_MASK (0x1000000U)
21254#define SIM_SCGC6_FTM0_SHIFT (24U)
21259#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
21260#define SIM_SCGC6_FTM1_MASK (0x2000000U)
21261#define SIM_SCGC6_FTM1_SHIFT (25U)
21266#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
21267#define SIM_SCGC6_FTM2_MASK (0x4000000U)
21268#define SIM_SCGC6_FTM2_SHIFT (26U)
21273#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
21274#define SIM_SCGC6_ADC0_MASK (0x8000000U)
21275#define SIM_SCGC6_ADC0_SHIFT (27U)
21280#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
21281#define SIM_SCGC6_DAC0_MASK (0x80000000U)
21282#define SIM_SCGC6_DAC0_SHIFT (31U)
21287#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
21292#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
21293#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
21298#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
21299#define SIM_SCGC7_SMPU_MASK (0x4U)
21300#define SIM_SCGC7_SMPU_SHIFT (2U)
21305#define SIM_SCGC7_SMPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SMPU_SHIFT)) & SIM_SCGC7_SMPU_MASK)
21306#define SIM_SCGC7_DMA_MASK (0x100U)
21307#define SIM_SCGC7_DMA_SHIFT (8U)
21312#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
21317#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
21318#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
21337#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
21338#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
21339#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
21358#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
21359#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
21360#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
21379#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
21380#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
21381#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
21400#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
21405#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
21406#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
21411#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
21412#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
21413#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
21418#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
21419#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
21420#define SIM_FCFG1_PFSIZE_SHIFT (24U)
21425#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
21430#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
21431#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
21432#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
21437#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
21438#define SIM_UIDH_UID_SHIFT (0U)
21439#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
21444#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
21445#define SIM_UIDMH_UID_SHIFT (0U)
21446#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
21451#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
21452#define SIM_UIDML_UID_SHIFT (0U)
21453#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
21458#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
21459#define SIM_UIDL_UID_SHIFT (0U)
21460#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
21465#define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
21466#define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
21467#define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
21468#define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
21469#define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
21470#define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
21471#define SIM_CLKDIV4_TRACEDIVEN_MASK (0x10000000U)
21472#define SIM_CLKDIV4_TRACEDIVEN_SHIFT (28U)
21477#define SIM_CLKDIV4_TRACEDIVEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIVEN_SHIFT)) & SIM_CLKDIV4_TRACEDIVEN_MASK)
21482#define SIM_MISCTRL0_CMPWIN0SRC_MASK (0x300U)
21483#define SIM_MISCTRL0_CMPWIN0SRC_SHIFT (8U)
21490#define SIM_MISCTRL0_CMPWIN0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN0SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN0SRC_MASK)
21491#define SIM_MISCTRL0_CMPWIN1SRC_MASK (0xC00U)
21492#define SIM_MISCTRL0_CMPWIN1SRC_SHIFT (10U)
21499#define SIM_MISCTRL0_CMPWIN1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN1SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN1SRC_MASK)
21500#define SIM_MISCTRL0_CMPWIN2SRC_MASK (0x3000U)
21501#define SIM_MISCTRL0_CMPWIN2SRC_SHIFT (12U)
21508#define SIM_MISCTRL0_CMPWIN2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN2SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN2SRC_MASK)
21509#define SIM_MISCTRL0_CMPWIN3SRC_MASK (0xC000U)
21510#define SIM_MISCTRL0_CMPWIN3SRC_SHIFT (14U)
21517#define SIM_MISCTRL0_CMPWIN3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN3SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN3SRC_MASK)
21518#define SIM_MISCTRL0_EWMINSRC_MASK (0x10000U)
21519#define SIM_MISCTRL0_EWMINSRC_SHIFT (16U)
21524#define SIM_MISCTRL0_EWMINSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_EWMINSRC_SHIFT)) & SIM_MISCTRL0_EWMINSRC_MASK)
21525#define SIM_MISCTRL0_DACTRIGSRC_MASK (0xC0000U)
21526#define SIM_MISCTRL0_DACTRIGSRC_SHIFT (18U)
21533#define SIM_MISCTRL0_DACTRIGSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_DACTRIGSRC_SHIFT)) & SIM_MISCTRL0_DACTRIGSRC_MASK)
21538#define SIM_MISCTRL1_SYNCXBARAPITTRIG0_MASK (0x100U)
21539#define SIM_MISCTRL1_SYNCXBARAPITTRIG0_SHIFT (8U)
21544#define SIM_MISCTRL1_SYNCXBARAPITTRIG0(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG0_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG0_MASK)
21545#define SIM_MISCTRL1_SYNCXBARAPITTRIG1_MASK (0x200U)
21546#define SIM_MISCTRL1_SYNCXBARAPITTRIG1_SHIFT (9U)
21551#define SIM_MISCTRL1_SYNCXBARAPITTRIG1(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG1_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG1_MASK)
21552#define SIM_MISCTRL1_SYNCXBARAPITTRIG2_MASK (0x400U)
21553#define SIM_MISCTRL1_SYNCXBARAPITTRIG2_SHIFT (10U)
21558#define SIM_MISCTRL1_SYNCXBARAPITTRIG2(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG2_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG2_MASK)
21559#define SIM_MISCTRL1_SYNCXBARAPITTRIG3_MASK (0x800U)
21560#define SIM_MISCTRL1_SYNCXBARAPITTRIG3_SHIFT (11U)
21565#define SIM_MISCTRL1_SYNCXBARAPITTRIG3(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG3_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG3_MASK)
21566#define SIM_MISCTRL1_SYNCXBARBPITTRIG0_MASK (0x1000U)
21567#define SIM_MISCTRL1_SYNCXBARBPITTRIG0_SHIFT (12U)
21572#define SIM_MISCTRL1_SYNCXBARBPITTRIG0(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARBPITTRIG0_SHIFT)) & SIM_MISCTRL1_SYNCXBARBPITTRIG0_MASK)
21573#define SIM_MISCTRL1_SYNCXBARBPITTRIG1_MASK (0x2000U)
21574#define SIM_MISCTRL1_SYNCXBARBPITTRIG1_SHIFT (13U)
21579#define SIM_MISCTRL1_SYNCXBARBPITTRIG1(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARBPITTRIG1_SHIFT)) & SIM_MISCTRL1_SYNCXBARBPITTRIG1_MASK)
21580#define SIM_MISCTRL1_SYNCDACHWTRIG_MASK (0x10000U)
21581#define SIM_MISCTRL1_SYNCDACHWTRIG_SHIFT (16U)
21586#define SIM_MISCTRL1_SYNCDACHWTRIG(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCDACHWTRIG_SHIFT)) & SIM_MISCTRL1_SYNCDACHWTRIG_MASK)
21587#define SIM_MISCTRL1_SYNCEWMIN_MASK (0x20000U)
21588#define SIM_MISCTRL1_SYNCEWMIN_SHIFT (17U)
21593#define SIM_MISCTRL1_SYNCEWMIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCEWMIN_SHIFT)) & SIM_MISCTRL1_SYNCEWMIN_MASK)
21594#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_MASK (0x100000U)
21595#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_SHIFT (20U)
21600#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_MASK)
21601#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_MASK (0x200000U)
21602#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_SHIFT (21U)
21607#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_MASK)
21608#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_MASK (0x400000U)
21609#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_SHIFT (22U)
21614#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_MASK)
21615#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_MASK (0x800000U)
21616#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_SHIFT (23U)
21621#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_MASK)
21626#define SIM_WDOGC_WDOGCLKS_MASK (0x2U)
21627#define SIM_WDOGC_WDOGCLKS_SHIFT (1U)
21632#define SIM_WDOGC_WDOGCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_WDOGC_WDOGCLKS_SHIFT)) & SIM_WDOGC_WDOGCLKS_MASK)
21637#define SIM_PWRC_SRPDN_MASK (0x3U)
21638#define SIM_PWRC_SRPDN_SHIFT (0U)
21645#define SIM_PWRC_SRPDN(x) (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPDN_SHIFT)) & SIM_PWRC_SRPDN_MASK)
21646#define SIM_PWRC_SR27STDBY_MASK (0xCU)
21647#define SIM_PWRC_SR27STDBY_SHIFT (2U)
21654#define SIM_PWRC_SR27STDBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SR27STDBY_SHIFT)) & SIM_PWRC_SR27STDBY_MASK)
21655#define SIM_PWRC_SR12STDBY_MASK (0xC0U)
21656#define SIM_PWRC_SR12STDBY_SHIFT (6U)
21663#define SIM_PWRC_SR12STDBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SR12STDBY_SHIFT)) & SIM_PWRC_SR12STDBY_MASK)
21664#define SIM_PWRC_SRPWRDETEN_MASK (0x100U)
21665#define SIM_PWRC_SRPWRDETEN_SHIFT (8U)
21670#define SIM_PWRC_SRPWRDETEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWRDETEN_SHIFT)) & SIM_PWRC_SRPWRDETEN_MASK)
21671#define SIM_PWRC_SRPWRRDY_MASK (0x200U)
21672#define SIM_PWRC_SRPWRRDY_SHIFT (9U)
21677#define SIM_PWRC_SRPWRRDY(x) (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWRRDY_SHIFT)) & SIM_PWRC_SRPWRRDY_MASK)
21678#define SIM_PWRC_SRPWROK_MASK (0x10000U)
21679#define SIM_PWRC_SRPWROK_SHIFT (16U)
21684#define SIM_PWRC_SRPWROK(x) (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWROK_SHIFT)) & SIM_PWRC_SRPWROK_MASK)
21689#define SIM_ADCOPT_ADC0TRGSEL_MASK (0xF0000U)
21690#define SIM_ADCOPT_ADC0TRGSEL_SHIFT (16U)
21709#define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK)
21710#define SIM_ADCOPT_ADC0PRETRGSEL_MASK (0x100000U)
21711#define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT (20U)
21716#define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK)
21717#define SIM_ADCOPT_ADC0ALTTRGEN_MASK (0xC00000U)
21718#define SIM_ADCOPT_ADC0ALTTRGEN_SHIFT (22U)
21725#define SIM_ADCOPT_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0ALTTRGEN_SHIFT)) & SIM_ADCOPT_ADC0ALTTRGEN_MASK)
21726#define SIM_ADCOPT_HSADCIRCLK_MASK (0x2000000U)
21727#define SIM_ADCOPT_HSADCIRCLK_SHIFT (25U)
21732#define SIM_ADCOPT_HSADCIRCLK(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_HSADCIRCLK_SHIFT)) & SIM_ADCOPT_HSADCIRCLK_MASK)
21733#define SIM_ADCOPT_HSADCSTOPEN_MASK (0x4000000U)
21734#define SIM_ADCOPT_HSADCSTOPEN_SHIFT (26U)
21739#define SIM_ADCOPT_HSADCSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_HSADCSTOPEN_SHIFT)) & SIM_ADCOPT_HSADCSTOPEN_MASK)
21745 /* end of group SIM_Register_Masks */
21746
21747
21748/* SIM - Peripheral instance base addresses */
21750#define SIM_BASE (0x40047000u)
21752#define SIM ((SIM_Type *)SIM_BASE)
21754#define SIM_BASE_ADDRS { SIM_BASE }
21756#define SIM_BASE_PTRS { SIM }
21757
21760 /* end of group SIM_Peripheral_Access_Layer */
21761
21762
21763/* ----------------------------------------------------------------------------
21764 -- SMC Peripheral Access Layer
21765 ---------------------------------------------------------------------------- */
21766
21773typedef struct {
21774 __IO uint8_t PMPROT;
21775 __IO uint8_t PMCTRL;
21776 __IO uint8_t STOPCTRL;
21777 __I uint8_t PMSTAT;
21778} SMC_Type;
21779
21780/* ----------------------------------------------------------------------------
21781 -- SMC Register Masks
21782 ---------------------------------------------------------------------------- */
21783
21791#define SMC_PMPROT_AVLLS_MASK (0x2U)
21792#define SMC_PMPROT_AVLLS_SHIFT (1U)
21797#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
21798#define SMC_PMPROT_AVLP_MASK (0x20U)
21799#define SMC_PMPROT_AVLP_SHIFT (5U)
21804#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
21805#define SMC_PMPROT_AHSRUN_MASK (0x80U)
21806#define SMC_PMPROT_AHSRUN_SHIFT (7U)
21811#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
21816#define SMC_PMCTRL_STOPM_MASK (0x7U)
21817#define SMC_PMCTRL_STOPM_SHIFT (0U)
21828#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
21829#define SMC_PMCTRL_STOPA_MASK (0x8U)
21830#define SMC_PMCTRL_STOPA_SHIFT (3U)
21835#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
21836#define SMC_PMCTRL_RUNM_MASK (0x60U)
21837#define SMC_PMCTRL_RUNM_SHIFT (5U)
21844#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
21849#define SMC_STOPCTRL_VLLSM_MASK (0x7U)
21850#define SMC_STOPCTRL_VLLSM_SHIFT (0U)
21861#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
21862#define SMC_STOPCTRL_LPOPO_MASK (0x8U)
21863#define SMC_STOPCTRL_LPOPO_SHIFT (3U)
21868#define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
21869#define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
21870#define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
21875#define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
21876#define SMC_STOPCTRL_PORPO_MASK (0x20U)
21877#define SMC_STOPCTRL_PORPO_SHIFT (5U)
21882#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
21883#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
21884#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
21891#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
21896#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
21897#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
21898#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
21904 /* end of group SMC_Register_Masks */
21905
21906
21907/* SMC - Peripheral instance base addresses */
21909#define SMC_BASE (0x4007E000u)
21911#define SMC ((SMC_Type *)SMC_BASE)
21913#define SMC_BASE_ADDRS { SMC_BASE }
21915#define SMC_BASE_PTRS { SMC }
21916
21919 /* end of group SMC_Peripheral_Access_Layer */
21920
21921
21922/* ----------------------------------------------------------------------------
21923 -- SPI Peripheral Access Layer
21924 ---------------------------------------------------------------------------- */
21925
21932typedef struct {
21933 __IO uint32_t MCR;
21934 uint8_t RESERVED_0[4];
21935 __IO uint32_t TCR;
21936 union { /* offset: 0xC */
21937 __IO uint32_t CTAR[2];
21938 __IO uint32_t CTAR_SLAVE[1];
21939 };
21940 uint8_t RESERVED_1[24];
21941 __IO uint32_t SR;
21942 __IO uint32_t RSER;
21943 union { /* offset: 0x34 */
21944 __IO uint32_t PUSHR;
21945 __IO uint32_t PUSHR_SLAVE;
21946 };
21947 __I uint32_t POPR;
21948 __I uint32_t TXFR0;
21949 __I uint32_t TXFR1;
21950 __I uint32_t TXFR2;
21951 __I uint32_t TXFR3;
21952 uint8_t RESERVED_2[48];
21953 __I uint32_t RXFR0;
21954 __I uint32_t RXFR1;
21955 __I uint32_t RXFR2;
21956 __I uint32_t RXFR3;
21957} SPI_Type;
21958
21959/* ----------------------------------------------------------------------------
21960 -- SPI Register Masks
21961 ---------------------------------------------------------------------------- */
21962
21970#define SPI_MCR_HALT_MASK (0x1U)
21971#define SPI_MCR_HALT_SHIFT (0U)
21976#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
21977#define SPI_MCR_SMPL_PT_MASK (0x300U)
21978#define SPI_MCR_SMPL_PT_SHIFT (8U)
21985#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
21986#define SPI_MCR_CLR_RXF_MASK (0x400U)
21987#define SPI_MCR_CLR_RXF_SHIFT (10U)
21992#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
21993#define SPI_MCR_CLR_TXF_MASK (0x800U)
21994#define SPI_MCR_CLR_TXF_SHIFT (11U)
21999#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
22000#define SPI_MCR_DIS_RXF_MASK (0x1000U)
22001#define SPI_MCR_DIS_RXF_SHIFT (12U)
22006#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
22007#define SPI_MCR_DIS_TXF_MASK (0x2000U)
22008#define SPI_MCR_DIS_TXF_SHIFT (13U)
22013#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
22014#define SPI_MCR_MDIS_MASK (0x4000U)
22015#define SPI_MCR_MDIS_SHIFT (14U)
22020#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
22021#define SPI_MCR_DOZE_MASK (0x8000U)
22022#define SPI_MCR_DOZE_SHIFT (15U)
22027#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
22028#define SPI_MCR_PCSIS_MASK (0x3F0000U)
22029#define SPI_MCR_PCSIS_SHIFT (16U)
22034#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
22035#define SPI_MCR_ROOE_MASK (0x1000000U)
22036#define SPI_MCR_ROOE_SHIFT (24U)
22041#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
22042#define SPI_MCR_PCSSE_MASK (0x2000000U)
22043#define SPI_MCR_PCSSE_SHIFT (25U)
22048#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
22049#define SPI_MCR_MTFE_MASK (0x4000000U)
22050#define SPI_MCR_MTFE_SHIFT (26U)
22055#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
22056#define SPI_MCR_FRZ_MASK (0x8000000U)
22057#define SPI_MCR_FRZ_SHIFT (27U)
22062#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
22063#define SPI_MCR_DCONF_MASK (0x30000000U)
22064#define SPI_MCR_DCONF_SHIFT (28U)
22071#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
22072#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
22073#define SPI_MCR_CONT_SCKE_SHIFT (30U)
22078#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
22079#define SPI_MCR_MSTR_MASK (0x80000000U)
22080#define SPI_MCR_MSTR_SHIFT (31U)
22085#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
22090#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
22091#define SPI_TCR_SPI_TCNT_SHIFT (16U)
22092#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
22097#define SPI_CTAR_BR_MASK (0xFU)
22098#define SPI_CTAR_BR_SHIFT (0U)
22099#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
22100#define SPI_CTAR_DT_MASK (0xF0U)
22101#define SPI_CTAR_DT_SHIFT (4U)
22102#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
22103#define SPI_CTAR_ASC_MASK (0xF00U)
22104#define SPI_CTAR_ASC_SHIFT (8U)
22105#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
22106#define SPI_CTAR_CSSCK_MASK (0xF000U)
22107#define SPI_CTAR_CSSCK_SHIFT (12U)
22108#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
22109#define SPI_CTAR_PBR_MASK (0x30000U)
22110#define SPI_CTAR_PBR_SHIFT (16U)
22117#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
22118#define SPI_CTAR_PDT_MASK (0xC0000U)
22119#define SPI_CTAR_PDT_SHIFT (18U)
22126#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
22127#define SPI_CTAR_PASC_MASK (0x300000U)
22128#define SPI_CTAR_PASC_SHIFT (20U)
22135#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
22136#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
22137#define SPI_CTAR_PCSSCK_SHIFT (22U)
22144#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
22145#define SPI_CTAR_LSBFE_MASK (0x1000000U)
22146#define SPI_CTAR_LSBFE_SHIFT (24U)
22151#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
22152#define SPI_CTAR_CPHA_MASK (0x2000000U)
22153#define SPI_CTAR_CPHA_SHIFT (25U)
22158#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
22159#define SPI_CTAR_CPOL_MASK (0x4000000U)
22160#define SPI_CTAR_CPOL_SHIFT (26U)
22165#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
22166#define SPI_CTAR_FMSZ_MASK (0x78000000U)
22167#define SPI_CTAR_FMSZ_SHIFT (27U)
22168#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
22169#define SPI_CTAR_DBR_MASK (0x80000000U)
22170#define SPI_CTAR_DBR_SHIFT (31U)
22175#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
22178/* The count of SPI_CTAR */
22179#define SPI_CTAR_COUNT (2U)
22180
22183#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
22184#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
22189#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
22190#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
22191#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
22196#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
22197#define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
22198#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
22199#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
22202/* The count of SPI_CTAR_SLAVE */
22203#define SPI_CTAR_SLAVE_COUNT (1U)
22204
22207#define SPI_SR_POPNXTPTR_MASK (0xFU)
22208#define SPI_SR_POPNXTPTR_SHIFT (0U)
22209#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
22210#define SPI_SR_RXCTR_MASK (0xF0U)
22211#define SPI_SR_RXCTR_SHIFT (4U)
22212#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
22213#define SPI_SR_TXNXTPTR_MASK (0xF00U)
22214#define SPI_SR_TXNXTPTR_SHIFT (8U)
22215#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
22216#define SPI_SR_TXCTR_MASK (0xF000U)
22217#define SPI_SR_TXCTR_SHIFT (12U)
22218#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
22219#define SPI_SR_RFDF_MASK (0x20000U)
22220#define SPI_SR_RFDF_SHIFT (17U)
22225#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
22226#define SPI_SR_RFOF_MASK (0x80000U)
22227#define SPI_SR_RFOF_SHIFT (19U)
22232#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
22233#define SPI_SR_TFFF_MASK (0x2000000U)
22234#define SPI_SR_TFFF_SHIFT (25U)
22239#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
22240#define SPI_SR_TFUF_MASK (0x8000000U)
22241#define SPI_SR_TFUF_SHIFT (27U)
22246#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
22247#define SPI_SR_EOQF_MASK (0x10000000U)
22248#define SPI_SR_EOQF_SHIFT (28U)
22253#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
22254#define SPI_SR_TXRXS_MASK (0x40000000U)
22255#define SPI_SR_TXRXS_SHIFT (30U)
22260#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
22261#define SPI_SR_TCF_MASK (0x80000000U)
22262#define SPI_SR_TCF_SHIFT (31U)
22267#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
22272#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
22273#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
22278#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
22279#define SPI_RSER_RFDF_RE_MASK (0x20000U)
22280#define SPI_RSER_RFDF_RE_SHIFT (17U)
22285#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
22286#define SPI_RSER_RFOF_RE_MASK (0x80000U)
22287#define SPI_RSER_RFOF_RE_SHIFT (19U)
22292#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
22293#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
22294#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
22299#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
22300#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
22301#define SPI_RSER_TFFF_RE_SHIFT (25U)
22306#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
22307#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
22308#define SPI_RSER_TFUF_RE_SHIFT (27U)
22313#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
22314#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
22315#define SPI_RSER_EOQF_RE_SHIFT (28U)
22320#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
22321#define SPI_RSER_TCF_RE_MASK (0x80000000U)
22322#define SPI_RSER_TCF_RE_SHIFT (31U)
22327#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
22332#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
22333#define SPI_PUSHR_TXDATA_SHIFT (0U)
22334#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
22335#define SPI_PUSHR_PCS_MASK (0x3F0000U)
22336#define SPI_PUSHR_PCS_SHIFT (16U)
22341#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
22342#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
22343#define SPI_PUSHR_CTCNT_SHIFT (26U)
22348#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
22349#define SPI_PUSHR_EOQ_MASK (0x8000000U)
22350#define SPI_PUSHR_EOQ_SHIFT (27U)
22355#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
22356#define SPI_PUSHR_CTAS_MASK (0x70000000U)
22357#define SPI_PUSHR_CTAS_SHIFT (28U)
22368#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
22369#define SPI_PUSHR_CONT_MASK (0x80000000U)
22370#define SPI_PUSHR_CONT_SHIFT (31U)
22375#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
22380#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU)
22381#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
22382#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
22387#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
22388#define SPI_POPR_RXDATA_SHIFT (0U)
22389#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
22394#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
22395#define SPI_TXFR0_TXDATA_SHIFT (0U)
22396#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
22397#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
22398#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
22399#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
22404#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
22405#define SPI_TXFR1_TXDATA_SHIFT (0U)
22406#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
22407#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
22408#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
22409#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
22414#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
22415#define SPI_TXFR2_TXDATA_SHIFT (0U)
22416#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
22417#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
22418#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
22419#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
22424#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
22425#define SPI_TXFR3_TXDATA_SHIFT (0U)
22426#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
22427#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
22428#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
22429#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
22434#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
22435#define SPI_RXFR0_RXDATA_SHIFT (0U)
22436#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
22441#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
22442#define SPI_RXFR1_RXDATA_SHIFT (0U)
22443#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
22448#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
22449#define SPI_RXFR2_RXDATA_SHIFT (0U)
22450#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
22455#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
22456#define SPI_RXFR3_RXDATA_SHIFT (0U)
22457#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
22463 /* end of group SPI_Register_Masks */
22464
22465
22466/* SPI - Peripheral instance base addresses */
22468#define SPI0_BASE (0x4002C000u)
22470#define SPI0 ((SPI_Type *)SPI0_BASE)
22472#define SPI1_BASE (0x4002D000u)
22474#define SPI1 ((SPI_Type *)SPI1_BASE)
22476#define SPI2_BASE (0x400AC000u)
22478#define SPI2 ((SPI_Type *)SPI2_BASE)
22480#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
22482#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
22484#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
22485
22488 /* end of group SPI_Peripheral_Access_Layer */
22489
22490
22491/* ----------------------------------------------------------------------------
22492 -- SYSMPU Peripheral Access Layer
22493 ---------------------------------------------------------------------------- */
22494
22501typedef struct {
22502 __IO uint32_t CESR;
22503 uint8_t RESERVED_0[12];
22504 struct { /* offset: 0x10, array step: 0x8 */
22505 __I uint32_t EAR;
22506 __I uint32_t EDR;
22507 } SP[5];
22508 uint8_t RESERVED_1[968];
22509 __IO uint32_t WORD[12][4];
22510 uint8_t RESERVED_2[832];
22511 __IO uint32_t RGDAAC[12];
22512} SYSMPU_Type;
22513
22514/* ----------------------------------------------------------------------------
22515 -- SYSMPU Register Masks
22516 ---------------------------------------------------------------------------- */
22517
22525#define SYSMPU_CESR_VLD_MASK (0x1U)
22526#define SYSMPU_CESR_VLD_SHIFT (0U)
22531#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
22532#define SYSMPU_CESR_NRGD_MASK (0xF00U)
22533#define SYSMPU_CESR_NRGD_SHIFT (8U)
22539#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
22540#define SYSMPU_CESR_NSP_MASK (0xF000U)
22541#define SYSMPU_CESR_NSP_SHIFT (12U)
22542#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
22543#define SYSMPU_CESR_HRL_MASK (0xF0000U)
22544#define SYSMPU_CESR_HRL_SHIFT (16U)
22545#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
22546#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
22547#define SYSMPU_CESR_SPERR_SHIFT (27U)
22552#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
22557#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
22558#define SYSMPU_EAR_EADDR_SHIFT (0U)
22559#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
22562/* The count of SYSMPU_EAR */
22563#define SYSMPU_EAR_COUNT (5U)
22564
22567#define SYSMPU_EDR_ERW_MASK (0x1U)
22568#define SYSMPU_EDR_ERW_SHIFT (0U)
22573#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
22574#define SYSMPU_EDR_EATTR_MASK (0xEU)
22575#define SYSMPU_EDR_EATTR_SHIFT (1U)
22582#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
22583#define SYSMPU_EDR_EMN_MASK (0xF0U)
22584#define SYSMPU_EDR_EMN_SHIFT (4U)
22585#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
22586#define SYSMPU_EDR_EPID_MASK (0xFF00U)
22587#define SYSMPU_EDR_EPID_SHIFT (8U)
22588#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
22589#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
22590#define SYSMPU_EDR_EACD_SHIFT (16U)
22591#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
22594/* The count of SYSMPU_EDR */
22595#define SYSMPU_EDR_COUNT (5U)
22596
22599#define SYSMPU_WORD_M0UM_MASK (0x7U)
22600#define SYSMPU_WORD_M0UM_SHIFT (0U)
22601#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
22602#define SYSMPU_WORD_VLD_MASK (0x1U)
22603#define SYSMPU_WORD_VLD_SHIFT (0U)
22608#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
22609#define SYSMPU_WORD_M0SM_MASK (0x18U)
22610#define SYSMPU_WORD_M0SM_SHIFT (3U)
22611#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
22612#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
22613#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
22614#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
22615#define SYSMPU_WORD_M0PE_MASK (0x20U)
22616#define SYSMPU_WORD_M0PE_SHIFT (5U)
22617#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
22618#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
22619#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
22620#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
22621#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
22622#define SYSMPU_WORD_M1UM_SHIFT (6U)
22623#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
22624#define SYSMPU_WORD_M1SM_MASK (0x600U)
22625#define SYSMPU_WORD_M1SM_SHIFT (9U)
22626#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
22627#define SYSMPU_WORD_M1PE_MASK (0x800U)
22628#define SYSMPU_WORD_M1PE_SHIFT (11U)
22629#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
22630#define SYSMPU_WORD_M2UM_MASK (0x7000U)
22631#define SYSMPU_WORD_M2UM_SHIFT (12U)
22632#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
22633#define SYSMPU_WORD_M2SM_MASK (0x18000U)
22634#define SYSMPU_WORD_M2SM_SHIFT (15U)
22635#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
22636#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
22637#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
22638#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
22639#define SYSMPU_WORD_M2PE_MASK (0x20000U)
22640#define SYSMPU_WORD_M2PE_SHIFT (17U)
22641#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
22642#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
22643#define SYSMPU_WORD_M3UM_SHIFT (18U)
22648#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
22649#define SYSMPU_WORD_M3SM_MASK (0x600000U)
22650#define SYSMPU_WORD_M3SM_SHIFT (21U)
22657#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
22658#define SYSMPU_WORD_M3PE_MASK (0x800000U)
22659#define SYSMPU_WORD_M3PE_SHIFT (23U)
22664#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
22665#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
22666#define SYSMPU_WORD_M4WE_SHIFT (24U)
22671#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
22672#define SYSMPU_WORD_PID_MASK (0xFF000000U)
22673#define SYSMPU_WORD_PID_SHIFT (24U)
22674#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
22675#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
22676#define SYSMPU_WORD_M4RE_SHIFT (25U)
22681#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
22682#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
22683#define SYSMPU_WORD_M5WE_SHIFT (26U)
22688#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
22689#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
22690#define SYSMPU_WORD_M5RE_SHIFT (27U)
22695#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
22696#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
22697#define SYSMPU_WORD_M6WE_SHIFT (28U)
22702#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
22703#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
22704#define SYSMPU_WORD_M6RE_SHIFT (29U)
22709#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
22710#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
22711#define SYSMPU_WORD_M7WE_SHIFT (30U)
22716#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
22717#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
22718#define SYSMPU_WORD_M7RE_SHIFT (31U)
22723#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
22726/* The count of SYSMPU_WORD */
22727#define SYSMPU_WORD_COUNT (12U)
22728
22729/* The count of SYSMPU_WORD */
22730#define SYSMPU_WORD_COUNT2 (4U)
22731
22734#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
22735#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
22736#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
22737#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
22738#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
22739#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
22740#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
22741#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
22742#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
22743#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
22744#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
22745#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
22746#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
22747#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
22748#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
22749#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
22750#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
22751#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
22752#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
22753#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
22754#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
22755#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
22756#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
22757#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
22758#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
22759#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
22760#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
22761#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
22762#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
22767#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
22768#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
22769#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
22776#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
22777#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
22778#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
22783#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
22784#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
22785#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
22790#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
22791#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
22792#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
22797#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
22798#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
22799#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
22804#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
22805#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
22806#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
22811#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
22812#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
22813#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
22818#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
22819#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
22820#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
22825#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
22826#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
22827#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
22832#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
22833#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
22834#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
22839#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
22842/* The count of SYSMPU_RGDAAC */
22843#define SYSMPU_RGDAAC_COUNT (12U)
22844
22845
22848 /* end of group SYSMPU_Register_Masks */
22849
22850
22851/* SYSMPU - Peripheral instance base addresses */
22853#define SYSMPU_BASE (0x4000D000u)
22855#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
22857#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
22859#define SYSMPU_BASE_PTRS { SYSMPU }
22860
22863 /* end of group SYSMPU_Peripheral_Access_Layer */
22864
22865
22866/* ----------------------------------------------------------------------------
22867 -- TRNG Peripheral Access Layer
22868 ---------------------------------------------------------------------------- */
22869
22876typedef struct {
22877 __IO uint32_t MCTL;
22878 __IO uint32_t SCMISC;
22879 __IO uint32_t PKRRNG;
22880 union { /* offset: 0xC */
22881 __IO uint32_t PKRMAX;
22882 __I uint32_t PKRSQ;
22883 };
22884 __IO uint32_t SDCTL;
22885 union { /* offset: 0x14 */
22886 __IO uint32_t SBLIM;
22887 __I uint32_t TOTSAM;
22888 };
22889 __IO uint32_t FRQMIN;
22890 union { /* offset: 0x1C */
22891 __I uint32_t FRQCNT;
22892 __IO uint32_t FRQMAX;
22893 };
22894 union { /* offset: 0x20 */
22895 __I uint32_t SCMC;
22896 __IO uint32_t SCML;
22897 };
22898 union { /* offset: 0x24 */
22899 __I uint32_t SCR1C;
22900 __IO uint32_t SCR1L;
22901 };
22902 union { /* offset: 0x28 */
22903 __I uint32_t SCR2C;
22904 __IO uint32_t SCR2L;
22905 };
22906 union { /* offset: 0x2C */
22907 __I uint32_t SCR3C;
22908 __IO uint32_t SCR3L;
22909 };
22910 union { /* offset: 0x30 */
22911 __I uint32_t SCR4C;
22912 __IO uint32_t SCR4L;
22913 };
22914 union { /* offset: 0x34 */
22915 __I uint32_t SCR5C;
22916 __IO uint32_t SCR5L;
22917 };
22918 union { /* offset: 0x38 */
22919 __I uint32_t SCR6PC;
22920 __IO uint32_t SCR6PL;
22921 };
22922 __I uint32_t STATUS;
22923 __I uint32_t ENT[16];
22924 __I uint32_t PKRCNT10;
22925 __I uint32_t PKRCNT32;
22926 __I uint32_t PKRCNT54;
22927 __I uint32_t PKRCNT76;
22928 __I uint32_t PKRCNT98;
22929 __I uint32_t PKRCNTBA;
22930 __I uint32_t PKRCNTDC;
22931 __I uint32_t PKRCNTFE;
22932 uint8_t RESERVED_0[16];
22933 __IO uint32_t SEC_CFG;
22934 __IO uint32_t INT_CTRL;
22935 __IO uint32_t INT_MASK;
22936 __IO uint32_t INT_STATUS;
22937 uint8_t RESERVED_1[48];
22938 __I uint32_t VID1;
22939 __I uint32_t VID2;
22940} TRNG_Type;
22941
22942/* ----------------------------------------------------------------------------
22943 -- TRNG Register Masks
22944 ---------------------------------------------------------------------------- */
22945
22953#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
22954#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
22961#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
22962#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
22963#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
22970#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
22971#define TRNG_MCTL_UNUSED_MASK (0x10U)
22972#define TRNG_MCTL_UNUSED_SHIFT (4U)
22973#define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
22974#define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
22975#define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
22976#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
22977#define TRNG_MCTL_RST_DEF_MASK (0x40U)
22978#define TRNG_MCTL_RST_DEF_SHIFT (6U)
22979#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
22980#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
22981#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
22982#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
22983#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
22984#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
22985#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
22986#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
22987#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
22988#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
22989#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
22990#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
22991#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
22992#define TRNG_MCTL_TST_OUT_MASK (0x800U)
22993#define TRNG_MCTL_TST_OUT_SHIFT (11U)
22994#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
22995#define TRNG_MCTL_ERR_MASK (0x1000U)
22996#define TRNG_MCTL_ERR_SHIFT (12U)
22997#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
22998#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
22999#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
23000#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
23001#define TRNG_MCTL_PRGM_MASK (0x10000U)
23002#define TRNG_MCTL_PRGM_SHIFT (16U)
23003#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
23008#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
23009#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
23010#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
23011#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
23012#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
23013#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
23018#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
23019#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
23020#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
23025#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
23026#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
23027#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
23032#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
23033#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
23034#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
23039#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
23040#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
23041#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
23042#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
23043#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
23044#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
23049#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
23050#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
23051#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
23056#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
23057#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
23058#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
23063#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
23064#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
23065#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
23070#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
23071#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
23072#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
23077#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
23078#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
23079#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
23084#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
23085#define TRNG_SCMC_MONO_CT_SHIFT (0U)
23086#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
23091#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
23092#define TRNG_SCML_MONO_MAX_SHIFT (0U)
23093#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
23094#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
23095#define TRNG_SCML_MONO_RNG_SHIFT (16U)
23096#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
23101#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
23102#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
23103#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
23104#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
23105#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
23106#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
23111#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
23112#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
23113#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
23114#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
23115#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
23116#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
23121#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
23122#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
23123#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
23124#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
23125#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
23126#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
23131#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
23132#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
23133#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
23134#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
23135#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
23136#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
23141#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
23142#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
23143#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
23144#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
23145#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
23146#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
23151#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
23152#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
23153#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
23154#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
23155#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
23156#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
23161#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
23162#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
23163#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
23164#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
23165#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
23166#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
23171#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
23172#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
23173#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
23174#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
23175#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
23176#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
23181#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
23182#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
23183#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
23184#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
23185#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
23186#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
23191#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
23192#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
23193#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
23194#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
23195#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
23196#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
23201#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
23202#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
23203#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
23204#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
23205#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
23206#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
23211#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
23212#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
23213#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
23214#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
23215#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
23216#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
23221#define TRNG_STATUS_TF1BR0_MASK (0x1U)
23222#define TRNG_STATUS_TF1BR0_SHIFT (0U)
23223#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
23224#define TRNG_STATUS_TF1BR1_MASK (0x2U)
23225#define TRNG_STATUS_TF1BR1_SHIFT (1U)
23226#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
23227#define TRNG_STATUS_TF2BR0_MASK (0x4U)
23228#define TRNG_STATUS_TF2BR0_SHIFT (2U)
23229#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
23230#define TRNG_STATUS_TF2BR1_MASK (0x8U)
23231#define TRNG_STATUS_TF2BR1_SHIFT (3U)
23232#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
23233#define TRNG_STATUS_TF3BR0_MASK (0x10U)
23234#define TRNG_STATUS_TF3BR0_SHIFT (4U)
23235#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
23236#define TRNG_STATUS_TF3BR1_MASK (0x20U)
23237#define TRNG_STATUS_TF3BR1_SHIFT (5U)
23238#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
23239#define TRNG_STATUS_TF4BR0_MASK (0x40U)
23240#define TRNG_STATUS_TF4BR0_SHIFT (6U)
23241#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
23242#define TRNG_STATUS_TF4BR1_MASK (0x80U)
23243#define TRNG_STATUS_TF4BR1_SHIFT (7U)
23244#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
23245#define TRNG_STATUS_TF5BR0_MASK (0x100U)
23246#define TRNG_STATUS_TF5BR0_SHIFT (8U)
23247#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
23248#define TRNG_STATUS_TF5BR1_MASK (0x200U)
23249#define TRNG_STATUS_TF5BR1_SHIFT (9U)
23250#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
23251#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
23252#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
23253#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
23254#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
23255#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
23256#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
23257#define TRNG_STATUS_TFSB_MASK (0x1000U)
23258#define TRNG_STATUS_TFSB_SHIFT (12U)
23259#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
23260#define TRNG_STATUS_TFLR_MASK (0x2000U)
23261#define TRNG_STATUS_TFLR_SHIFT (13U)
23262#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
23263#define TRNG_STATUS_TFP_MASK (0x4000U)
23264#define TRNG_STATUS_TFP_SHIFT (14U)
23265#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
23266#define TRNG_STATUS_TFMB_MASK (0x8000U)
23267#define TRNG_STATUS_TFMB_SHIFT (15U)
23268#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
23269#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
23270#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
23271#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
23276#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
23277#define TRNG_ENT_ENT_SHIFT (0U)
23278#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
23281/* The count of TRNG_ENT */
23282#define TRNG_ENT_COUNT (16U)
23283
23286#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
23287#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
23288#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
23289#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
23290#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
23291#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
23296#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
23297#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
23298#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
23299#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
23300#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
23301#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
23306#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
23307#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
23308#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
23309#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
23310#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
23311#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
23316#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
23317#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
23318#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
23319#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
23320#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
23321#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
23326#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
23327#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
23328#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
23329#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
23330#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
23331#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
23336#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
23337#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
23338#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
23339#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
23340#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
23341#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
23346#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
23347#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
23348#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
23349#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
23350#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
23351#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
23356#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
23357#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
23358#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
23359#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
23360#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
23361#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
23366#define TRNG_SEC_CFG_SH0_MASK (0x1U)
23367#define TRNG_SEC_CFG_SH0_SHIFT (0U)
23372#define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
23373#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
23374#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
23379#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
23380#define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
23381#define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
23386#define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
23391#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
23392#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
23397#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
23398#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
23399#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
23404#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
23405#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
23406#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
23411#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
23412#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
23413#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
23414#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
23419#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
23420#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
23425#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
23426#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
23427#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
23432#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
23433#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
23434#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
23439#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
23444#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
23445#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
23450#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
23451#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
23452#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
23457#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
23458#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
23459#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
23464#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
23469#define TRNG_VID1_RNG_MIN_REV_MASK (0xFFU)
23470#define TRNG_VID1_RNG_MIN_REV_SHIFT (0U)
23474#define TRNG_VID1_RNG_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MIN_REV_SHIFT)) & TRNG_VID1_RNG_MIN_REV_MASK)
23475#define TRNG_VID1_RNG_MAJ_REV_MASK (0xFF00U)
23476#define TRNG_VID1_RNG_MAJ_REV_SHIFT (8U)
23480#define TRNG_VID1_RNG_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MAJ_REV_SHIFT)) & TRNG_VID1_RNG_MAJ_REV_MASK)
23481#define TRNG_VID1_RNG_IP_ID_MASK (0xFFFF0000U)
23482#define TRNG_VID1_RNG_IP_ID_SHIFT (16U)
23483#define TRNG_VID1_RNG_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_IP_ID_SHIFT)) & TRNG_VID1_RNG_IP_ID_MASK)
23488#define TRNG_VID2_RNG_CONFIG_OPT_MASK (0xFFU)
23489#define TRNG_VID2_RNG_CONFIG_OPT_SHIFT (0U)
23493#define TRNG_VID2_RNG_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_CONFIG_OPT_SHIFT)) & TRNG_VID2_RNG_CONFIG_OPT_MASK)
23494#define TRNG_VID2_RNG_ECO_REV_MASK (0xFF00U)
23495#define TRNG_VID2_RNG_ECO_REV_SHIFT (8U)
23499#define TRNG_VID2_RNG_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ECO_REV_SHIFT)) & TRNG_VID2_RNG_ECO_REV_MASK)
23500#define TRNG_VID2_RNG_INTG_OPT_MASK (0xFF0000U)
23501#define TRNG_VID2_RNG_INTG_OPT_SHIFT (16U)
23505#define TRNG_VID2_RNG_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_INTG_OPT_SHIFT)) & TRNG_VID2_RNG_INTG_OPT_MASK)
23506#define TRNG_VID2_RNG_ERA_MASK (0xFF000000U)
23507#define TRNG_VID2_RNG_ERA_SHIFT (24U)
23511#define TRNG_VID2_RNG_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ERA_SHIFT)) & TRNG_VID2_RNG_ERA_MASK)
23517 /* end of group TRNG_Register_Masks */
23518
23519
23520/* TRNG - Peripheral instance base addresses */
23522#define TRNG0_BASE (0x400A0000u)
23524#define TRNG0 ((TRNG_Type *)TRNG0_BASE)
23526#define TRNG_BASE_ADDRS { TRNG0_BASE }
23528#define TRNG_BASE_PTRS { TRNG0 }
23530#define TRNG_IRQS { TRNG0_IRQn }
23531
23534 /* end of group TRNG_Peripheral_Access_Layer */
23535
23536
23537/* ----------------------------------------------------------------------------
23538 -- UART Peripheral Access Layer
23539 ---------------------------------------------------------------------------- */
23540
23547typedef struct {
23548 __IO uint8_t BDH;
23549 __IO uint8_t BDL;
23550 __IO uint8_t C1;
23551 __IO uint8_t C2;
23552 __I uint8_t S1;
23553 __IO uint8_t S2;
23554 __IO uint8_t C3;
23555 __IO uint8_t D;
23556 __IO uint8_t MA1;
23557 __IO uint8_t MA2;
23558 __IO uint8_t C4;
23559 __IO uint8_t C5;
23560 __I uint8_t ED;
23561 __IO uint8_t MODEM;
23562 __IO uint8_t IR;
23563 uint8_t RESERVED_0[1];
23564 __IO uint8_t PFIFO;
23565 __IO uint8_t CFIFO;
23566 __IO uint8_t SFIFO;
23567 __IO uint8_t TWFIFO;
23568 __I uint8_t TCFIFO;
23569 __IO uint8_t RWFIFO;
23570 __I uint8_t RCFIFO;
23571 uint8_t RESERVED_1[1];
23572 __IO uint8_t C7816;
23573 __IO uint8_t IE7816;
23574 __IO uint8_t IS7816;
23575 __IO uint8_t WP7816;
23576 __IO uint8_t WN7816;
23577 __IO uint8_t WF7816;
23578 __IO uint8_t ET7816;
23579 __IO uint8_t TL7816;
23580 uint8_t RESERVED_2[26];
23581 __IO uint8_t AP7816A_T0;
23582 __IO uint8_t AP7816B_T0;
23583 union { /* offset: 0x3C */
23584 struct { /* offset: 0x3C */
23585 __IO uint8_t WP7816A_T0;
23586 __IO uint8_t WP7816B_T0;
23587 } TYPE0;
23588 struct { /* offset: 0x3C */
23589 __IO uint8_t WP7816A_T1;
23590 __IO uint8_t WP7816B_T1;
23591 } TYPE1;
23592 };
23593 __IO uint8_t WGP7816_T1;
23594 __IO uint8_t WP7816C_T1;
23595} UART_Type;
23596
23597/* ----------------------------------------------------------------------------
23598 -- UART Register Masks
23599 ---------------------------------------------------------------------------- */
23600
23608#define UART_BDH_SBR_MASK (0x1FU)
23609#define UART_BDH_SBR_SHIFT (0U)
23610#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
23611#define UART_BDH_SBNS_MASK (0x20U)
23612#define UART_BDH_SBNS_SHIFT (5U)
23617#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
23618#define UART_BDH_RXEDGIE_MASK (0x40U)
23619#define UART_BDH_RXEDGIE_SHIFT (6U)
23624#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
23625#define UART_BDH_LBKDIE_MASK (0x80U)
23626#define UART_BDH_LBKDIE_SHIFT (7U)
23631#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
23636#define UART_BDL_SBR_MASK (0xFFU)
23637#define UART_BDL_SBR_SHIFT (0U)
23638#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
23643#define UART_C1_PT_MASK (0x1U)
23644#define UART_C1_PT_SHIFT (0U)
23649#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
23650#define UART_C1_PE_MASK (0x2U)
23651#define UART_C1_PE_SHIFT (1U)
23656#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
23657#define UART_C1_ILT_MASK (0x4U)
23658#define UART_C1_ILT_SHIFT (2U)
23663#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
23664#define UART_C1_WAKE_MASK (0x8U)
23665#define UART_C1_WAKE_SHIFT (3U)
23670#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
23671#define UART_C1_M_MASK (0x10U)
23672#define UART_C1_M_SHIFT (4U)
23677#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
23678#define UART_C1_RSRC_MASK (0x20U)
23679#define UART_C1_RSRC_SHIFT (5U)
23684#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
23685#define UART_C1_UARTSWAI_MASK (0x40U)
23686#define UART_C1_UARTSWAI_SHIFT (6U)
23691#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
23692#define UART_C1_LOOPS_MASK (0x80U)
23693#define UART_C1_LOOPS_SHIFT (7U)
23698#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
23703#define UART_C2_SBK_MASK (0x1U)
23704#define UART_C2_SBK_SHIFT (0U)
23709#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
23710#define UART_C2_RWU_MASK (0x2U)
23711#define UART_C2_RWU_SHIFT (1U)
23716#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
23717#define UART_C2_RE_MASK (0x4U)
23718#define UART_C2_RE_SHIFT (2U)
23723#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
23724#define UART_C2_TE_MASK (0x8U)
23725#define UART_C2_TE_SHIFT (3U)
23730#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
23731#define UART_C2_ILIE_MASK (0x10U)
23732#define UART_C2_ILIE_SHIFT (4U)
23737#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
23738#define UART_C2_RIE_MASK (0x20U)
23739#define UART_C2_RIE_SHIFT (5U)
23744#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
23745#define UART_C2_TCIE_MASK (0x40U)
23746#define UART_C2_TCIE_SHIFT (6U)
23751#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
23752#define UART_C2_TIE_MASK (0x80U)
23753#define UART_C2_TIE_SHIFT (7U)
23758#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
23763#define UART_S1_PF_MASK (0x1U)
23764#define UART_S1_PF_SHIFT (0U)
23769#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
23770#define UART_S1_FE_MASK (0x2U)
23771#define UART_S1_FE_SHIFT (1U)
23776#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
23777#define UART_S1_NF_MASK (0x4U)
23778#define UART_S1_NF_SHIFT (2U)
23783#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
23784#define UART_S1_OR_MASK (0x8U)
23785#define UART_S1_OR_SHIFT (3U)
23790#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
23791#define UART_S1_IDLE_MASK (0x10U)
23792#define UART_S1_IDLE_SHIFT (4U)
23797#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
23798#define UART_S1_RDRF_MASK (0x20U)
23799#define UART_S1_RDRF_SHIFT (5U)
23804#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
23805#define UART_S1_TC_MASK (0x40U)
23806#define UART_S1_TC_SHIFT (6U)
23811#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
23812#define UART_S1_TDRE_MASK (0x80U)
23813#define UART_S1_TDRE_SHIFT (7U)
23818#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
23823#define UART_S2_RAF_MASK (0x1U)
23824#define UART_S2_RAF_SHIFT (0U)
23829#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
23830#define UART_S2_LBKDE_MASK (0x2U)
23831#define UART_S2_LBKDE_SHIFT (1U)
23836#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
23837#define UART_S2_BRK13_MASK (0x4U)
23838#define UART_S2_BRK13_SHIFT (2U)
23843#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
23844#define UART_S2_RWUID_MASK (0x8U)
23845#define UART_S2_RWUID_SHIFT (3U)
23850#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
23851#define UART_S2_RXINV_MASK (0x10U)
23852#define UART_S2_RXINV_SHIFT (4U)
23857#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
23858#define UART_S2_MSBF_MASK (0x20U)
23859#define UART_S2_MSBF_SHIFT (5U)
23864#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
23865#define UART_S2_RXEDGIF_MASK (0x40U)
23866#define UART_S2_RXEDGIF_SHIFT (6U)
23871#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
23872#define UART_S2_LBKDIF_MASK (0x80U)
23873#define UART_S2_LBKDIF_SHIFT (7U)
23878#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
23883#define UART_C3_PEIE_MASK (0x1U)
23884#define UART_C3_PEIE_SHIFT (0U)
23889#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
23890#define UART_C3_FEIE_MASK (0x2U)
23891#define UART_C3_FEIE_SHIFT (1U)
23896#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
23897#define UART_C3_NEIE_MASK (0x4U)
23898#define UART_C3_NEIE_SHIFT (2U)
23903#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
23904#define UART_C3_ORIE_MASK (0x8U)
23905#define UART_C3_ORIE_SHIFT (3U)
23910#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
23911#define UART_C3_TXINV_MASK (0x10U)
23912#define UART_C3_TXINV_SHIFT (4U)
23917#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
23918#define UART_C3_TXDIR_MASK (0x20U)
23919#define UART_C3_TXDIR_SHIFT (5U)
23924#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
23925#define UART_C3_T8_MASK (0x40U)
23926#define UART_C3_T8_SHIFT (6U)
23927#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
23928#define UART_C3_R8_MASK (0x80U)
23929#define UART_C3_R8_SHIFT (7U)
23930#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
23935#define UART_D_RT_MASK (0xFFU)
23936#define UART_D_RT_SHIFT (0U)
23937#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
23942#define UART_MA1_MA_MASK (0xFFU)
23943#define UART_MA1_MA_SHIFT (0U)
23944#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
23949#define UART_MA2_MA_MASK (0xFFU)
23950#define UART_MA2_MA_SHIFT (0U)
23951#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
23956#define UART_C4_BRFA_MASK (0x1FU)
23957#define UART_C4_BRFA_SHIFT (0U)
23958#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
23959#define UART_C4_M10_MASK (0x20U)
23960#define UART_C4_M10_SHIFT (5U)
23965#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
23966#define UART_C4_MAEN2_MASK (0x40U)
23967#define UART_C4_MAEN2_SHIFT (6U)
23972#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
23973#define UART_C4_MAEN1_MASK (0x80U)
23974#define UART_C4_MAEN1_SHIFT (7U)
23979#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
23984#define UART_C5_LBKDDMAS_MASK (0x8U)
23985#define UART_C5_LBKDDMAS_SHIFT (3U)
23990#define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK)
23991#define UART_C5_RDMAS_MASK (0x20U)
23992#define UART_C5_RDMAS_SHIFT (5U)
23997#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
23998#define UART_C5_TDMAS_MASK (0x80U)
23999#define UART_C5_TDMAS_SHIFT (7U)
24004#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
24009#define UART_ED_PARITYE_MASK (0x40U)
24010#define UART_ED_PARITYE_SHIFT (6U)
24015#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
24016#define UART_ED_NOISY_MASK (0x80U)
24017#define UART_ED_NOISY_SHIFT (7U)
24022#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
24027#define UART_MODEM_TXCTSE_MASK (0x1U)
24028#define UART_MODEM_TXCTSE_SHIFT (0U)
24033#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
24034#define UART_MODEM_TXRTSE_MASK (0x2U)
24035#define UART_MODEM_TXRTSE_SHIFT (1U)
24040#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
24041#define UART_MODEM_TXRTSPOL_MASK (0x4U)
24042#define UART_MODEM_TXRTSPOL_SHIFT (2U)
24047#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
24048#define UART_MODEM_RXRTSE_MASK (0x8U)
24049#define UART_MODEM_RXRTSE_SHIFT (3U)
24054#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
24059#define UART_IR_TNP_MASK (0x3U)
24060#define UART_IR_TNP_SHIFT (0U)
24067#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
24068#define UART_IR_IREN_MASK (0x4U)
24069#define UART_IR_IREN_SHIFT (2U)
24074#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
24079#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
24080#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
24091#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
24092#define UART_PFIFO_RXFE_MASK (0x8U)
24093#define UART_PFIFO_RXFE_SHIFT (3U)
24098#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
24099#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
24100#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
24111#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
24112#define UART_PFIFO_TXFE_MASK (0x80U)
24113#define UART_PFIFO_TXFE_SHIFT (7U)
24118#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
24123#define UART_CFIFO_RXUFE_MASK (0x1U)
24124#define UART_CFIFO_RXUFE_SHIFT (0U)
24129#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
24130#define UART_CFIFO_TXOFE_MASK (0x2U)
24131#define UART_CFIFO_TXOFE_SHIFT (1U)
24136#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
24137#define UART_CFIFO_RXOFE_MASK (0x4U)
24138#define UART_CFIFO_RXOFE_SHIFT (2U)
24143#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
24144#define UART_CFIFO_RXFLUSH_MASK (0x40U)
24145#define UART_CFIFO_RXFLUSH_SHIFT (6U)
24150#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
24151#define UART_CFIFO_TXFLUSH_MASK (0x80U)
24152#define UART_CFIFO_TXFLUSH_SHIFT (7U)
24157#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
24162#define UART_SFIFO_RXUF_MASK (0x1U)
24163#define UART_SFIFO_RXUF_SHIFT (0U)
24168#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
24169#define UART_SFIFO_TXOF_MASK (0x2U)
24170#define UART_SFIFO_TXOF_SHIFT (1U)
24175#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
24176#define UART_SFIFO_RXOF_MASK (0x4U)
24177#define UART_SFIFO_RXOF_SHIFT (2U)
24182#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
24183#define UART_SFIFO_RXEMPT_MASK (0x40U)
24184#define UART_SFIFO_RXEMPT_SHIFT (6U)
24189#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
24190#define UART_SFIFO_TXEMPT_MASK (0x80U)
24191#define UART_SFIFO_TXEMPT_SHIFT (7U)
24196#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
24201#define UART_TWFIFO_TXWATER_MASK (0xFFU)
24202#define UART_TWFIFO_TXWATER_SHIFT (0U)
24203#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
24208#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
24209#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
24210#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
24215#define UART_RWFIFO_RXWATER_MASK (0xFFU)
24216#define UART_RWFIFO_RXWATER_SHIFT (0U)
24217#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
24222#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
24223#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
24224#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
24229#define UART_C7816_ISO_7816E_MASK (0x1U)
24230#define UART_C7816_ISO_7816E_SHIFT (0U)
24235#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
24236#define UART_C7816_TTYPE_MASK (0x2U)
24237#define UART_C7816_TTYPE_SHIFT (1U)
24242#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
24243#define UART_C7816_INIT_MASK (0x4U)
24244#define UART_C7816_INIT_SHIFT (2U)
24249#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
24250#define UART_C7816_ANACK_MASK (0x8U)
24251#define UART_C7816_ANACK_SHIFT (3U)
24256#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
24257#define UART_C7816_ONACK_MASK (0x10U)
24258#define UART_C7816_ONACK_SHIFT (4U)
24263#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
24268#define UART_IE7816_RXTE_MASK (0x1U)
24269#define UART_IE7816_RXTE_SHIFT (0U)
24274#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
24275#define UART_IE7816_TXTE_MASK (0x2U)
24276#define UART_IE7816_TXTE_SHIFT (1U)
24281#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
24282#define UART_IE7816_GTVE_MASK (0x4U)
24283#define UART_IE7816_GTVE_SHIFT (2U)
24288#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
24289#define UART_IE7816_ADTE_MASK (0x8U)
24290#define UART_IE7816_ADTE_SHIFT (3U)
24295#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
24296#define UART_IE7816_INITDE_MASK (0x10U)
24297#define UART_IE7816_INITDE_SHIFT (4U)
24302#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
24303#define UART_IE7816_BWTE_MASK (0x20U)
24304#define UART_IE7816_BWTE_SHIFT (5U)
24309#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
24310#define UART_IE7816_CWTE_MASK (0x40U)
24311#define UART_IE7816_CWTE_SHIFT (6U)
24316#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
24317#define UART_IE7816_WTE_MASK (0x80U)
24318#define UART_IE7816_WTE_SHIFT (7U)
24323#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
24328#define UART_IS7816_RXT_MASK (0x1U)
24329#define UART_IS7816_RXT_SHIFT (0U)
24334#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
24335#define UART_IS7816_TXT_MASK (0x2U)
24336#define UART_IS7816_TXT_SHIFT (1U)
24341#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
24342#define UART_IS7816_GTV_MASK (0x4U)
24343#define UART_IS7816_GTV_SHIFT (2U)
24348#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
24349#define UART_IS7816_ADT_MASK (0x8U)
24350#define UART_IS7816_ADT_SHIFT (3U)
24355#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
24356#define UART_IS7816_INITD_MASK (0x10U)
24357#define UART_IS7816_INITD_SHIFT (4U)
24362#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
24363#define UART_IS7816_BWT_MASK (0x20U)
24364#define UART_IS7816_BWT_SHIFT (5U)
24369#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
24370#define UART_IS7816_CWT_MASK (0x40U)
24371#define UART_IS7816_CWT_SHIFT (6U)
24376#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
24377#define UART_IS7816_WT_MASK (0x80U)
24378#define UART_IS7816_WT_SHIFT (7U)
24383#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
24388#define UART_WP7816_WTX_MASK (0xFFU)
24389#define UART_WP7816_WTX_SHIFT (0U)
24390#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
24395#define UART_WN7816_GTN_MASK (0xFFU)
24396#define UART_WN7816_GTN_SHIFT (0U)
24397#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
24402#define UART_WF7816_GTFD_MASK (0xFFU)
24403#define UART_WF7816_GTFD_SHIFT (0U)
24404#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
24409#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
24410#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
24411#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
24412#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
24413#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
24418#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
24423#define UART_TL7816_TLEN_MASK (0xFFU)
24424#define UART_TL7816_TLEN_SHIFT (0U)
24425#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
24430#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
24431#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
24432#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
24437#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
24438#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
24439#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
24444#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
24445#define UART_WP7816A_T0_WI_H_SHIFT (0U)
24446#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
24451#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
24452#define UART_WP7816B_T0_WI_L_SHIFT (0U)
24453#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
24458#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
24459#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
24460#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
24465#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
24466#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
24467#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
24472#define UART_WGP7816_T1_BGI_MASK (0xFU)
24473#define UART_WGP7816_T1_BGI_SHIFT (0U)
24474#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
24475#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
24476#define UART_WGP7816_T1_CWI1_SHIFT (4U)
24477#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
24482#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
24483#define UART_WP7816C_T1_CWI2_SHIFT (0U)
24484#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
24490 /* end of group UART_Register_Masks */
24491
24492
24493/* UART - Peripheral instance base addresses */
24495#define UART0_BASE (0x4006A000u)
24497#define UART0 ((UART_Type *)UART0_BASE)
24499#define UART1_BASE (0x4006B000u)
24501#define UART1 ((UART_Type *)UART1_BASE)
24503#define UART2_BASE (0x4006C000u)
24505#define UART2 ((UART_Type *)UART2_BASE)
24507#define UART3_BASE (0x4006D000u)
24509#define UART3 ((UART_Type *)UART3_BASE)
24511#define UART4_BASE (0x400EA000u)
24513#define UART4 ((UART_Type *)UART4_BASE)
24515#define UART5_BASE (0x400EB000u)
24517#define UART5 ((UART_Type *)UART5_BASE)
24519#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
24521#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
24523#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
24524#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
24525
24528 /* end of group UART_Peripheral_Access_Layer */
24529
24530
24531/* ----------------------------------------------------------------------------
24532 -- WDOG Peripheral Access Layer
24533 ---------------------------------------------------------------------------- */
24534
24541typedef struct {
24542 __IO uint16_t STCTRLH;
24543 __IO uint16_t STCTRLL;
24544 __IO uint16_t TOVALH;
24545 __IO uint16_t TOVALL;
24546 __IO uint16_t WINH;
24547 __IO uint16_t WINL;
24548 __IO uint16_t REFRESH;
24549 __IO uint16_t UNLOCK;
24550 __IO uint16_t TMROUTH;
24551 __IO uint16_t TMROUTL;
24552 __IO uint16_t RSTCNT;
24553 __IO uint16_t PRESC;
24554} WDOG_Type;
24555
24556/* ----------------------------------------------------------------------------
24557 -- WDOG Register Masks
24558 ---------------------------------------------------------------------------- */
24559
24567#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
24568#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
24573#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
24574#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
24575#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
24580#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
24581#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
24582#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
24587#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
24588#define WDOG_STCTRLH_WINEN_MASK (0x8U)
24589#define WDOG_STCTRLH_WINEN_SHIFT (3U)
24594#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
24595#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
24596#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
24601#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
24602#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
24603#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
24608#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
24609#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
24610#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
24615#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
24616#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
24617#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
24622#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
24623#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
24624#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
24625#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
24626#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
24627#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
24632#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
24633#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
24634#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
24641#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
24642#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
24643#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
24648#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
24653#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
24654#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
24655#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
24660#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
24661#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
24662#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
24667#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
24668#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
24669#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
24674#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
24675#define WDOG_WINH_WINHIGH_SHIFT (0U)
24676#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
24681#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
24682#define WDOG_WINL_WINLOW_SHIFT (0U)
24683#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
24688#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
24689#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
24690#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
24695#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
24696#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
24697#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
24702#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
24703#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
24704#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
24709#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
24710#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
24711#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
24716#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
24717#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
24718#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
24723#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
24724#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
24725#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
24731 /* end of group WDOG_Register_Masks */
24732
24733
24734/* WDOG - Peripheral instance base addresses */
24736#define WDOG_BASE (0x40052000u)
24738#define WDOG ((WDOG_Type *)WDOG_BASE)
24740#define WDOG_BASE_ADDRS { WDOG_BASE }
24742#define WDOG_BASE_PTRS { WDOG }
24744#define WDOG_IRQS { WDOG_EWM_IRQn }
24745
24748 /* end of group WDOG_Peripheral_Access_Layer */
24749
24750
24751/* ----------------------------------------------------------------------------
24752 -- XBARA Peripheral Access Layer
24753 ---------------------------------------------------------------------------- */
24754
24761typedef struct {
24762 __IO uint16_t SEL0;
24763 __IO uint16_t SEL1;
24764 __IO uint16_t SEL2;
24765 __IO uint16_t SEL3;
24766 __IO uint16_t SEL4;
24767 __IO uint16_t SEL5;
24768 __IO uint16_t SEL6;
24769 __IO uint16_t SEL7;
24770 __IO uint16_t SEL8;
24771 __IO uint16_t SEL9;
24772 __IO uint16_t SEL10;
24773 __IO uint16_t SEL11;
24774 __IO uint16_t SEL12;
24775 __IO uint16_t SEL13;
24776 __IO uint16_t SEL14;
24777 __IO uint16_t SEL15;
24778 __IO uint16_t SEL16;
24779 __IO uint16_t SEL17;
24780 __IO uint16_t SEL18;
24781 __IO uint16_t SEL19;
24782 __IO uint16_t SEL20;
24783 __IO uint16_t SEL21;
24784 __IO uint16_t SEL22;
24785 __IO uint16_t SEL23;
24786 __IO uint16_t SEL24;
24787 __IO uint16_t SEL25;
24788 __IO uint16_t SEL26;
24789 __IO uint16_t SEL27;
24790 __IO uint16_t SEL28;
24791 __IO uint16_t SEL29;
24792 __IO uint16_t CTRL0;
24793 __IO uint16_t CTRL1;
24794} XBARA_Type;
24795
24796/* ----------------------------------------------------------------------------
24797 -- XBARA Register Masks
24798 ---------------------------------------------------------------------------- */
24799
24807#define XBARA_SEL0_SEL0_MASK (0x3FU)
24808#define XBARA_SEL0_SEL0_SHIFT (0U)
24869#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
24870#define XBARA_SEL0_SEL1_MASK (0x3F00U)
24871#define XBARA_SEL0_SEL1_SHIFT (8U)
24932#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
24937#define XBARA_SEL1_SEL2_MASK (0x3FU)
24938#define XBARA_SEL1_SEL2_SHIFT (0U)
24999#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
25000#define XBARA_SEL1_SEL3_MASK (0x3F00U)
25001#define XBARA_SEL1_SEL3_SHIFT (8U)
25062#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
25067#define XBARA_SEL2_SEL4_MASK (0x3FU)
25068#define XBARA_SEL2_SEL4_SHIFT (0U)
25129#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
25130#define XBARA_SEL2_SEL5_MASK (0x3F00U)
25131#define XBARA_SEL2_SEL5_SHIFT (8U)
25192#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
25197#define XBARA_SEL3_SEL6_MASK (0x3FU)
25198#define XBARA_SEL3_SEL6_SHIFT (0U)
25259#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
25260#define XBARA_SEL3_SEL7_MASK (0x3F00U)
25261#define XBARA_SEL3_SEL7_SHIFT (8U)
25322#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
25327#define XBARA_SEL4_SEL8_MASK (0x3FU)
25328#define XBARA_SEL4_SEL8_SHIFT (0U)
25389#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
25390#define XBARA_SEL4_SEL9_MASK (0x3F00U)
25391#define XBARA_SEL4_SEL9_SHIFT (8U)
25452#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
25457#define XBARA_SEL5_SEL10_MASK (0x3FU)
25458#define XBARA_SEL5_SEL10_SHIFT (0U)
25519#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
25520#define XBARA_SEL5_SEL11_MASK (0x3F00U)
25521#define XBARA_SEL5_SEL11_SHIFT (8U)
25582#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
25587#define XBARA_SEL6_SEL12_MASK (0x3FU)
25588#define XBARA_SEL6_SEL12_SHIFT (0U)
25649#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
25650#define XBARA_SEL6_SEL13_MASK (0x3F00U)
25651#define XBARA_SEL6_SEL13_SHIFT (8U)
25712#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
25717#define XBARA_SEL7_SEL14_MASK (0x3FU)
25718#define XBARA_SEL7_SEL14_SHIFT (0U)
25719#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
25720#define XBARA_SEL7_SEL15_MASK (0x3F00U)
25721#define XBARA_SEL7_SEL15_SHIFT (8U)
25782#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
25787#define XBARA_SEL8_SEL16_MASK (0x3FU)
25788#define XBARA_SEL8_SEL16_SHIFT (0U)
25849#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
25850#define XBARA_SEL8_SEL17_MASK (0x3F00U)
25851#define XBARA_SEL8_SEL17_SHIFT (8U)
25912#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
25917#define XBARA_SEL9_SEL18_MASK (0x3FU)
25918#define XBARA_SEL9_SEL18_SHIFT (0U)
25979#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
25980#define XBARA_SEL9_SEL19_MASK (0x3F00U)
25981#define XBARA_SEL9_SEL19_SHIFT (8U)
26042#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
26047#define XBARA_SEL10_SEL20_MASK (0x3FU)
26048#define XBARA_SEL10_SEL20_SHIFT (0U)
26109#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
26110#define XBARA_SEL10_SEL21_MASK (0x3F00U)
26111#define XBARA_SEL10_SEL21_SHIFT (8U)
26172#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
26177#define XBARA_SEL11_SEL22_MASK (0x3FU)
26178#define XBARA_SEL11_SEL22_SHIFT (0U)
26239#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
26240#define XBARA_SEL11_SEL23_MASK (0x3F00U)
26241#define XBARA_SEL11_SEL23_SHIFT (8U)
26302#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
26307#define XBARA_SEL12_SEL24_MASK (0x3FU)
26308#define XBARA_SEL12_SEL24_SHIFT (0U)
26369#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
26370#define XBARA_SEL12_SEL25_MASK (0x3F00U)
26371#define XBARA_SEL12_SEL25_SHIFT (8U)
26432#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
26437#define XBARA_SEL13_SEL26_MASK (0x3FU)
26438#define XBARA_SEL13_SEL26_SHIFT (0U)
26499#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
26500#define XBARA_SEL13_SEL27_MASK (0x3F00U)
26501#define XBARA_SEL13_SEL27_SHIFT (8U)
26562#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
26567#define XBARA_SEL14_SEL28_MASK (0x3FU)
26568#define XBARA_SEL14_SEL28_SHIFT (0U)
26629#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
26630#define XBARA_SEL14_SEL29_MASK (0x3F00U)
26631#define XBARA_SEL14_SEL29_SHIFT (8U)
26692#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
26697#define XBARA_SEL15_SEL30_MASK (0x3FU)
26698#define XBARA_SEL15_SEL30_SHIFT (0U)
26759#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
26760#define XBARA_SEL15_SEL31_MASK (0x3F00U)
26761#define XBARA_SEL15_SEL31_SHIFT (8U)
26822#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
26827#define XBARA_SEL16_SEL32_MASK (0x3FU)
26828#define XBARA_SEL16_SEL32_SHIFT (0U)
26889#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
26890#define XBARA_SEL16_SEL33_MASK (0x3F00U)
26891#define XBARA_SEL16_SEL33_SHIFT (8U)
26952#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
26957#define XBARA_SEL17_SEL34_MASK (0x3FU)
26958#define XBARA_SEL17_SEL34_SHIFT (0U)
27019#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
27020#define XBARA_SEL17_SEL35_MASK (0x3F00U)
27021#define XBARA_SEL17_SEL35_SHIFT (8U)
27082#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
27087#define XBARA_SEL18_SEL36_MASK (0x3FU)
27088#define XBARA_SEL18_SEL36_SHIFT (0U)
27149#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
27150#define XBARA_SEL18_SEL37_MASK (0x3F00U)
27151#define XBARA_SEL18_SEL37_SHIFT (8U)
27212#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
27217#define XBARA_SEL19_SEL38_MASK (0x3FU)
27218#define XBARA_SEL19_SEL38_SHIFT (0U)
27279#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
27280#define XBARA_SEL19_SEL39_MASK (0x3F00U)
27281#define XBARA_SEL19_SEL39_SHIFT (8U)
27342#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
27347#define XBARA_SEL20_SEL40_MASK (0x3FU)
27348#define XBARA_SEL20_SEL40_SHIFT (0U)
27349#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
27350#define XBARA_SEL20_SEL41_MASK (0x3F00U)
27351#define XBARA_SEL20_SEL41_SHIFT (8U)
27412#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
27417#define XBARA_SEL21_SEL42_MASK (0x3FU)
27418#define XBARA_SEL21_SEL42_SHIFT (0U)
27479#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
27480#define XBARA_SEL21_SEL43_MASK (0x3F00U)
27481#define XBARA_SEL21_SEL43_SHIFT (8U)
27542#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
27547#define XBARA_SEL22_SEL44_MASK (0x3FU)
27548#define XBARA_SEL22_SEL44_SHIFT (0U)
27609#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
27610#define XBARA_SEL22_SEL45_MASK (0x3F00U)
27611#define XBARA_SEL22_SEL45_SHIFT (8U)
27672#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
27677#define XBARA_SEL23_SEL46_MASK (0x3FU)
27678#define XBARA_SEL23_SEL46_SHIFT (0U)
27739#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
27740#define XBARA_SEL23_SEL47_MASK (0x3F00U)
27741#define XBARA_SEL23_SEL47_SHIFT (8U)
27802#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
27807#define XBARA_SEL24_SEL48_MASK (0x3FU)
27808#define XBARA_SEL24_SEL48_SHIFT (0U)
27869#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
27870#define XBARA_SEL24_SEL49_MASK (0x3F00U)
27871#define XBARA_SEL24_SEL49_SHIFT (8U)
27932#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
27937#define XBARA_SEL25_SEL50_MASK (0x3FU)
27938#define XBARA_SEL25_SEL50_SHIFT (0U)
27999#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
28000#define XBARA_SEL25_SEL51_MASK (0x3F00U)
28001#define XBARA_SEL25_SEL51_SHIFT (8U)
28062#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
28067#define XBARA_SEL26_SEL52_MASK (0x3FU)
28068#define XBARA_SEL26_SEL52_SHIFT (0U)
28129#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
28130#define XBARA_SEL26_SEL53_MASK (0x3F00U)
28131#define XBARA_SEL26_SEL53_SHIFT (8U)
28192#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
28197#define XBARA_SEL27_SEL54_MASK (0x3FU)
28198#define XBARA_SEL27_SEL54_SHIFT (0U)
28259#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
28260#define XBARA_SEL27_SEL55_MASK (0x3F00U)
28261#define XBARA_SEL27_SEL55_SHIFT (8U)
28322#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
28327#define XBARA_SEL28_SEL56_MASK (0x3FU)
28328#define XBARA_SEL28_SEL56_SHIFT (0U)
28389#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
28390#define XBARA_SEL28_SEL57_MASK (0x3F00U)
28391#define XBARA_SEL28_SEL57_SHIFT (8U)
28452#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
28457#define XBARA_SEL29_SEL58_MASK (0x3FU)
28458#define XBARA_SEL29_SEL58_SHIFT (0U)
28519#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
28524#define XBARA_CTRL0_DEN0_MASK (0x1U)
28525#define XBARA_CTRL0_DEN0_SHIFT (0U)
28530#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
28531#define XBARA_CTRL0_IEN0_MASK (0x2U)
28532#define XBARA_CTRL0_IEN0_SHIFT (1U)
28537#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
28538#define XBARA_CTRL0_EDGE0_MASK (0xCU)
28539#define XBARA_CTRL0_EDGE0_SHIFT (2U)
28546#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
28547#define XBARA_CTRL0_STS0_MASK (0x10U)
28548#define XBARA_CTRL0_STS0_SHIFT (4U)
28553#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
28554#define XBARA_CTRL0_DEN1_MASK (0x100U)
28555#define XBARA_CTRL0_DEN1_SHIFT (8U)
28560#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
28561#define XBARA_CTRL0_IEN1_MASK (0x200U)
28562#define XBARA_CTRL0_IEN1_SHIFT (9U)
28567#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
28568#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
28569#define XBARA_CTRL0_EDGE1_SHIFT (10U)
28576#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
28577#define XBARA_CTRL0_STS1_MASK (0x1000U)
28578#define XBARA_CTRL0_STS1_SHIFT (12U)
28583#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
28588#define XBARA_CTRL1_DEN2_MASK (0x1U)
28589#define XBARA_CTRL1_DEN2_SHIFT (0U)
28594#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
28595#define XBARA_CTRL1_IEN2_MASK (0x2U)
28596#define XBARA_CTRL1_IEN2_SHIFT (1U)
28601#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
28602#define XBARA_CTRL1_EDGE2_MASK (0xCU)
28603#define XBARA_CTRL1_EDGE2_SHIFT (2U)
28610#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
28611#define XBARA_CTRL1_STS2_MASK (0x10U)
28612#define XBARA_CTRL1_STS2_SHIFT (4U)
28617#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
28618#define XBARA_CTRL1_DEN3_MASK (0x100U)
28619#define XBARA_CTRL1_DEN3_SHIFT (8U)
28624#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
28625#define XBARA_CTRL1_IEN3_MASK (0x200U)
28626#define XBARA_CTRL1_IEN3_SHIFT (9U)
28631#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
28632#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
28633#define XBARA_CTRL1_EDGE3_SHIFT (10U)
28640#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
28641#define XBARA_CTRL1_STS3_MASK (0x1000U)
28642#define XBARA_CTRL1_STS3_SHIFT (12U)
28647#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
28653 /* end of group XBARA_Register_Masks */
28654
28655
28656/* XBARA - Peripheral instance base addresses */
28658#define XBARA_BASE (0x40059000u)
28660#define XBARA ((XBARA_Type *)XBARA_BASE)
28662#define XBARA_BASE_ADDRS { XBARA_BASE }
28664#define XBARA_BASE_PTRS { XBARA }
28666#define XBARA_IRQS { XBARA_IRQn }
28667
28670 /* end of group XBARA_Peripheral_Access_Layer */
28671
28672
28673/* ----------------------------------------------------------------------------
28674 -- XBARB Peripheral Access Layer
28675 ---------------------------------------------------------------------------- */
28676
28683typedef struct {
28684 __IO uint16_t SEL0;
28685 __IO uint16_t SEL1;
28686 __IO uint16_t SEL2;
28687 __IO uint16_t SEL3;
28688 __IO uint16_t SEL4;
28689 __IO uint16_t SEL5;
28690 __IO uint16_t SEL6;
28691 __IO uint16_t SEL7;
28692} XBARB_Type;
28693
28694/* ----------------------------------------------------------------------------
28695 -- XBARB Register Masks
28696 ---------------------------------------------------------------------------- */
28697
28705#define XBARB_SEL0_SEL0_MASK (0x3FU)
28706#define XBARB_SEL0_SEL0_SHIFT (0U)
28748#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
28749#define XBARB_SEL0_SEL1_MASK (0x3F00U)
28750#define XBARB_SEL0_SEL1_SHIFT (8U)
28792#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
28797#define XBARB_SEL1_SEL2_MASK (0x3FU)
28798#define XBARB_SEL1_SEL2_SHIFT (0U)
28840#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
28841#define XBARB_SEL1_SEL3_MASK (0x3F00U)
28842#define XBARB_SEL1_SEL3_SHIFT (8U)
28884#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
28889#define XBARB_SEL2_SEL4_MASK (0x3FU)
28890#define XBARB_SEL2_SEL4_SHIFT (0U)
28932#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
28933#define XBARB_SEL2_SEL5_MASK (0x3F00U)
28934#define XBARB_SEL2_SEL5_SHIFT (8U)
28976#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
28981#define XBARB_SEL3_SEL6_MASK (0x3FU)
28982#define XBARB_SEL3_SEL6_SHIFT (0U)
29024#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
29025#define XBARB_SEL3_SEL7_MASK (0x3F00U)
29026#define XBARB_SEL3_SEL7_SHIFT (8U)
29068#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
29073#define XBARB_SEL4_SEL8_MASK (0x3FU)
29074#define XBARB_SEL4_SEL8_SHIFT (0U)
29116#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
29117#define XBARB_SEL4_SEL9_MASK (0x3F00U)
29118#define XBARB_SEL4_SEL9_SHIFT (8U)
29160#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
29165#define XBARB_SEL5_SEL10_MASK (0x3FU)
29166#define XBARB_SEL5_SEL10_SHIFT (0U)
29208#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
29209#define XBARB_SEL5_SEL11_MASK (0x3F00U)
29210#define XBARB_SEL5_SEL11_SHIFT (8U)
29252#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
29257#define XBARB_SEL6_SEL12_MASK (0x3FU)
29258#define XBARB_SEL6_SEL12_SHIFT (0U)
29300#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
29301#define XBARB_SEL6_SEL13_MASK (0x3F00U)
29302#define XBARB_SEL6_SEL13_SHIFT (8U)
29344#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
29349#define XBARB_SEL7_SEL14_MASK (0x3FU)
29350#define XBARB_SEL7_SEL14_SHIFT (0U)
29392#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
29393#define XBARB_SEL7_SEL15_MASK (0x3F00U)
29394#define XBARB_SEL7_SEL15_SHIFT (8U)
29436#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
29442 /* end of group XBARB_Register_Masks */
29443
29444
29445/* XBARB - Peripheral instance base addresses */
29447#define XBARB_BASE (0x4005A000u)
29449#define XBARB ((XBARB_Type *)XBARB_BASE)
29451#define XBARB_BASE_ADDRS { XBARB_BASE }
29453#define XBARB_BASE_PTRS { XBARB }
29454
29457 /* end of group XBARB_Peripheral_Access_Layer */
29458
29459
29460/*
29461** End of section using anonymous unions
29462*/
29463
29464#if defined(__ARMCC_VERSION)
29465 #if (__ARMCC_VERSION >= 6010050)
29466 #pragma clang diagnostic pop
29467 #else
29468 #pragma pop
29469 #endif
29470#elif defined(__CWCC__)
29471 #pragma pop
29472#elif defined(__GNUC__)
29473 /* leave anonymous unions enabled */
29474#elif defined(__IAR_SYSTEMS_ICC__)
29475 #pragma language=default
29476#else
29477 #error Not supported compiler type
29478#endif
29479
29482 /* end of group Peripheral_access_layer */
29483
29484
29485/* ----------------------------------------------------------------------------
29486 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
29487 ---------------------------------------------------------------------------- */
29488
29494#if defined(__ARMCC_VERSION)
29495 #if (__ARMCC_VERSION >= 6010050)
29496 #pragma clang system_header
29497 #endif
29498#elif defined(__IAR_SYSTEMS_ICC__)
29499 #pragma system_include
29500#endif
29501
29508#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
29515#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
29516
29519 /* end of group Bit_Field_Generic_Macros */
29520
29521
29522/* ----------------------------------------------------------------------------
29523 -- SDK Compatibility
29524 ---------------------------------------------------------------------------- */
29525
29531#define DSPI0 SPI0
29532#define DSPI1 SPI1
29533#define DSPI2 SPI2
29534#define FLEXCAN0 CAN0
29535#define FLEXCAN1 CAN1
29536#define FLEXCAN2 CAN2
29537#define DMAMUX0 DMAMUX
29538
29541 /* end of group SDK_Compatibility_Symbols */
29542
29543
29544#endif /* _MKV58F24_H_ */
__O
#define __O
Definition core_cm3.h:169
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn
IRQn
Definition MK60D10.h:157
MCM_IRQn
@ MCM_IRQn
Definition MKV58F24.h:144
CAN2_Tx_Warning_IRQn
@ CAN2_Tx_Warning_IRQn
Definition MKV58F24.h:245
PendSV_IRQn
@ PendSV_IRQn
Definition MKV58F24.h:123
CAN1_ORed_Message_buffer_IRQn
@ CAN1_ORed_Message_buffer_IRQn
Definition MKV58F24.h:221
FTM0_IRQn
@ FTM0_IRQn
Definition MKV58F24.h:169
ADC0_IRQn
@ ADC0_IRQn
Definition MKV58F24.h:164
WDOG_EWM_IRQn
@ WDOG_EWM_IRQn
Definition MKV58F24.h:149
PORTE_IRQn
@ PORTE_IRQn
Definition MKV58F24.h:190
CAN2_Wake_Up_IRQn
@ CAN2_Wake_Up_IRQn
Definition MKV58F24.h:247
I2C0_IRQn
@ I2C0_IRQn
Definition MKV58F24.h:151
PWM1_RELOAD0_IRQn
@ PWM1_RELOAD0_IRQn
Definition MKV58F24.h:232
Reserved46_IRQn
@ Reserved46_IRQn
Definition MKV58F24.h:157
MCG_IRQn
@ MCG_IRQn
Definition MKV58F24.h:184
PWM0_CMP3_IRQn
@ PWM0_CMP3_IRQn
Definition MKV58F24.h:214
DMA0_DMA16_IRQn
@ DMA0_DMA16_IRQn
Definition MKV58F24.h:127
HSADC1_CCA_IRQn
@ HSADC1_CCA_IRQn
Definition MKV58F24.h:201
PWM0_RELOAD2_IRQn
@ PWM0_RELOAD2_IRQn
Definition MKV58F24.h:213
ENC_HOME_IRQn
@ ENC_HOME_IRQn
Definition MKV58F24.h:194
DMA14_DMA30_IRQn
@ DMA14_DMA30_IRQn
Definition MKV58F24.h:141
CAN1_Bus_Off_IRQn
@ CAN1_Bus_Off_IRQn
Definition MKV58F24.h:222
CAN2_Bus_Off_IRQn
@ CAN2_Bus_Off_IRQn
Definition MKV58F24.h:243
NotAvail_IRQn
@ NotAvail_IRQn
Definition MKV58F24.h:113
DMA13_DMA29_IRQn
@ DMA13_DMA29_IRQn
Definition MKV58F24.h:140
UART4_RX_TX_IRQn
@ UART4_RX_TX_IRQn
Definition MKV58F24.h:173
PWM1_CMP2_IRQn
@ PWM1_CMP2_IRQn
Definition MKV58F24.h:235
CAN1_Error_IRQn
@ CAN1_Error_IRQn
Definition MKV58F24.h:223
PORTD_IRQn
@ PORTD_IRQn
Definition MKV58F24.h:189
PWM1_CMP1_IRQn
@ PWM1_CMP1_IRQn
Definition MKV58F24.h:233
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition MKV58F24.h:118
CAN0_ORed_Message_buffer_IRQn
@ CAN0_ORed_Message_buffer_IRQn
Definition MKV58F24.h:202
DMA15_DMA31_IRQn
@ DMA15_DMA31_IRQn
Definition MKV58F24.h:142
UART5_ERR_IRQn
@ UART5_ERR_IRQn
Definition MKV58F24.h:156
PWM0_RELOAD1_IRQn
@ PWM0_RELOAD1_IRQn
Definition MKV58F24.h:211
FTM1_IRQn
@ FTM1_IRQn
Definition MKV58F24.h:170
PWM0_RELOAD3_IRQn
@ PWM0_RELOAD3_IRQn
Definition MKV58F24.h:215
CAN0_Wake_Up_IRQn
@ CAN0_Wake_Up_IRQn
Definition MKV58F24.h:207
PWM1_FAULT_IRQn
@ PWM1_FAULT_IRQn
Definition MKV58F24.h:241
SWI_IRQn
@ SWI_IRQn
Definition MKV58F24.h:191
SVCall_IRQn
@ SVCall_IRQn
Definition MKV58F24.h:121
CAN0_Tx_Warning_IRQn
@ CAN0_Tx_Warning_IRQn
Definition MKV58F24.h:205
TRNG0_IRQn
@ TRNG0_IRQn
Definition MKV58F24.h:150
PWM1_CMP3_IRQn
@ PWM1_CMP3_IRQn
Definition MKV58F24.h:237
DMA10_DMA26_IRQn
@ DMA10_DMA26_IRQn
Definition MKV58F24.h:137
SPI2_IRQn
@ SPI2_IRQn
Definition MKV58F24.h:192
PWM0_FAULT_IRQn
@ PWM0_FAULT_IRQn
Definition MKV58F24.h:218
DMA_Error_IRQn
@ DMA_Error_IRQn
Definition MKV58F24.h:143
DMA5_DMA21_IRQn
@ DMA5_DMA21_IRQn
Definition MKV58F24.h:132
UART0_RX_TX_IRQn
@ UART0_RX_TX_IRQn
Definition MKV58F24.h:158
DAC0_IRQn
@ DAC0_IRQn
Definition MKV58F24.h:183
DMA3_DMA19_IRQn
@ DMA3_DMA19_IRQn
Definition MKV58F24.h:130
FTM2_IRQn
@ FTM2_IRQn
Definition MKV58F24.h:180
UsageFault_IRQn
@ UsageFault_IRQn
Definition MKV58F24.h:120
UART4_ERR_IRQn
@ UART4_ERR_IRQn
Definition MKV58F24.h:174
HSADC0_CCA_IRQn
@ HSADC0_CCA_IRQn
Definition MKV58F24.h:166
SysTick_IRQn
@ SysTick_IRQn
Definition MKV58F24.h:124
CAN0_Error_IRQn
@ CAN0_Error_IRQn
Definition MKV58F24.h:204
UART5_RX_TX_IRQn
@ UART5_RX_TX_IRQn
Definition MKV58F24.h:155
PMC_IRQn
@ PMC_IRQn
Definition MKV58F24.h:147
UART0_ERR_IRQn
@ UART0_ERR_IRQn
Definition MKV58F24.h:159
CAN1_Rx_Warning_IRQn
@ CAN1_Rx_Warning_IRQn
Definition MKV58F24.h:225
CMP2_IRQn
@ CMP2_IRQn
Definition MKV58F24.h:197
DMA4_DMA20_IRQn
@ DMA4_DMA20_IRQn
Definition MKV58F24.h:131
PDB1_IRQn
@ PDB1_IRQn
Definition MKV58F24.h:182
CAN1_Wake_Up_IRQn
@ CAN1_Wake_Up_IRQn
Definition MKV58F24.h:226
CAN2_ORed_Message_buffer_IRQn
@ CAN2_ORed_Message_buffer_IRQn
Definition MKV58F24.h:242
BusFault_IRQn
@ BusFault_IRQn
Definition MKV58F24.h:119
CMP0_IRQn
@ CMP0_IRQn
Definition MKV58F24.h:167
ENET_Receive_IRQn
@ ENET_Receive_IRQn
Definition MKV58F24.h:229
PDB0_IRQn
@ PDB0_IRQn
Definition MKV58F24.h:179
UART2_RX_TX_IRQn
@ UART2_RX_TX_IRQn
Definition MKV58F24.h:162
LLWU_IRQn
@ LLWU_IRQn
Definition MKV58F24.h:148
PWM0_CMP1_IRQn
@ PWM0_CMP1_IRQn
Definition MKV58F24.h:210
DMA7_DMA23_IRQn
@ DMA7_DMA23_IRQn
Definition MKV58F24.h:134
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition MKV58F24.h:122
Reserved88_IRQn
@ Reserved88_IRQn
Definition MKV58F24.h:199
ENC_INDEX_IRQn
@ ENC_INDEX_IRQn
Definition MKV58F24.h:196
PWM1_RELOAD3_IRQn
@ PWM1_RELOAD3_IRQn
Definition MKV58F24.h:238
UART1_ERR_IRQn
@ UART1_ERR_IRQn
Definition MKV58F24.h:161
LPTMR0_IRQn
@ LPTMR0_IRQn
Definition MKV58F24.h:185
DMA8_DMA24_IRQn
@ DMA8_DMA24_IRQn
Definition MKV58F24.h:135
Read_Collision_IRQn
@ Read_Collision_IRQn
Definition MKV58F24.h:146
DMA6_DMA22_IRQn
@ DMA6_DMA22_IRQn
Definition MKV58F24.h:133
PWM1_RERR_IRQn
@ PWM1_RERR_IRQn
Definition MKV58F24.h:240
ENC_COMPARE_IRQn
@ ENC_COMPARE_IRQn
Definition MKV58F24.h:193
PIT3_IRQn
@ PIT3_IRQn
Definition MKV58F24.h:178
PWM1_RELOAD1_IRQn
@ PWM1_RELOAD1_IRQn
Definition MKV58F24.h:234
PWM0_CAP_IRQn
@ PWM0_CAP_IRQn
Definition MKV58F24.h:216
UART2_ERR_IRQn
@ UART2_ERR_IRQn
Definition MKV58F24.h:163
SPI1_IRQn
@ SPI1_IRQn
Definition MKV58F24.h:154
PWM0_RERR_IRQn
@ PWM0_RERR_IRQn
Definition MKV58F24.h:217
PWM1_CMP0_IRQn
@ PWM1_CMP0_IRQn
Definition MKV58F24.h:231
HardFault_IRQn
@ HardFault_IRQn
Definition MKV58F24.h:117
CAN0_Rx_Warning_IRQn
@ CAN0_Rx_Warning_IRQn
Definition MKV58F24.h:206
PIT0_IRQn
@ PIT0_IRQn
Definition MKV58F24.h:175
UART3_RX_TX_IRQn
@ UART3_RX_TX_IRQn
Definition MKV58F24.h:171
ENET_Error_IRQn
@ ENET_Error_IRQn
Definition MKV58F24.h:230
PWM0_RELOAD0_IRQn
@ PWM0_RELOAD0_IRQn
Definition MKV58F24.h:209
PWM0_CMP0_IRQn
@ PWM0_CMP0_IRQn
Definition MKV58F24.h:208
PORTA_IRQn
@ PORTA_IRQn
Definition MKV58F24.h:186
FTFE_IRQn
@ FTFE_IRQn
Definition MKV58F24.h:145
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition MKV58F24.h:227
CMP1_IRQn
@ CMP1_IRQn
Definition MKV58F24.h:168
DMA11_DMA27_IRQn
@ DMA11_DMA27_IRQn
Definition MKV58F24.h:138
HSADC_ERR_IRQn
@ HSADC_ERR_IRQn
Definition MKV58F24.h:165
PORTC_IRQn
@ PORTC_IRQn
Definition MKV58F24.h:188
ENET_Transmit_IRQn
@ ENET_Transmit_IRQn
Definition MKV58F24.h:228
HSADC0_CCB_IRQn
@ HSADC0_CCB_IRQn
Definition MKV58F24.h:200
PWM1_CAP_IRQn
@ PWM1_CAP_IRQn
Definition MKV58F24.h:239
PORTB_IRQn
@ PORTB_IRQn
Definition MKV58F24.h:187
UART3_ERR_IRQn
@ UART3_ERR_IRQn
Definition MKV58F24.h:172
PWM0_CMP2_IRQn
@ PWM0_CMP2_IRQn
Definition MKV58F24.h:212
FTM3_IRQn
@ FTM3_IRQn
Definition MKV58F24.h:198
UART1_RX_TX_IRQn
@ UART1_RX_TX_IRQn
Definition MKV58F24.h:160
DMA2_DMA18_IRQn
@ DMA2_DMA18_IRQn
Definition MKV58F24.h:129
PWM1_RELOAD2_IRQn
@ PWM1_RELOAD2_IRQn
Definition MKV58F24.h:236
CMP3_IRQn
@ CMP3_IRQn
Definition MKV58F24.h:219
CAN0_Bus_Off_IRQn
@ CAN0_Bus_Off_IRQn
Definition MKV58F24.h:203
CAN1_Tx_Warning_IRQn
@ CAN1_Tx_Warning_IRQn
Definition MKV58F24.h:224
CAN2_Rx_Warning_IRQn
@ CAN2_Rx_Warning_IRQn
Definition MKV58F24.h:246
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition MKV58F24.h:116
ENC_WDOG_SAB_IRQn
@ ENC_WDOG_SAB_IRQn
Definition MKV58F24.h:195
XBARA_IRQn
@ XBARA_IRQn
Definition MKV58F24.h:181
CAN2_Error_IRQn
@ CAN2_Error_IRQn
Definition MKV58F24.h:244
HSADC1_CCB_IRQn
@ HSADC1_CCB_IRQn
Definition MKV58F24.h:220
PIT1_IRQn
@ PIT1_IRQn
Definition MKV58F24.h:176
DMA9_DMA25_IRQn
@ DMA9_DMA25_IRQn
Definition MKV58F24.h:136
DMA12_DMA28_IRQn
@ DMA12_DMA28_IRQn
Definition MKV58F24.h:139
I2C1_IRQn
@ I2C1_IRQn
Definition MKV58F24.h:152
SPI0_IRQn
@ SPI0_IRQn
Definition MKV58F24.h:153
PIT2_IRQn
@ PIT2_IRQn
Definition MKV58F24.h:177
DMA1_DMA17_IRQn
@ DMA1_DMA17_IRQn
Definition MKV58F24.h:128
LMEM
#define LMEM
Definition MK65F18.h:16067
TRNG_Type::SEC_CFG
__IO uint32_t SEC_CFG
Definition MKV58F24.h:22933
HSADC_Type::ZXCTRL2
__IO uint16_t ZXCTRL2
Definition MKV58F24.h:13802
TRNG_Type::PKRCNT76
__I uint32_t PKRCNT76
Definition MKV58F24.h:22927
PWM_Type::CVAL5
__I uint16_t CVAL5
Definition MKV58F24.h:18439
XBARA_Type::CTRL1
__IO uint16_t CTRL1
Definition MKV58F24.h:24793
PIT_Type::@174::TFLG
__IO uint32_t TFLG
Definition MKV58F24.h:17828
MSCM_Type::CPxCOUNT
__I uint32_t CPxCOUNT
Definition MKV58F24.h:16923
CAN_Type::@148::ID
__IO uint32_t ID
Definition MKV58F24.h:4493
TRNG_Type::VID1
__I uint32_t VID1
Definition MKV58F24.h:22938
TRNG_Type::SCMC
__I uint32_t SCMC
Definition MKV58F24.h:22895
UART_Type::@201::@203::WP7816B_T0
__IO uint8_t WP7816B_T0
Definition MKV58F24.h:23586
TRNG_Type::SCR5L
__IO uint32_t SCR5L
Definition MKV58F24.h:22916
AOI_Type::BFCRT01
__IO uint16_t BFCRT01
Definition MKV58F24.h:4030
PWM_Type::OUTEN
__IO uint16_t OUTEN
Definition MKV58F24.h:18443
EWM_Type::CLKCTRL
__IO uint8_t CLKCTRL
Definition MKV58F24.h:11459
FB_Type::@169::CSCR
__IO uint32_t CSCR
Definition MKV58F24.h:11560
MSCM_Type::CPxNUM
__I uint32_t CPxNUM
Definition MKV58F24.h:16921
PWM_Type::DTCNT0
__IO uint16_t DTCNT0
Definition MKV58F24.h:18421
ENC_Type::LMOD
__IO uint16_t LMOD
Definition MKV58F24.h:9690
PWM_Type::MCTRL2
__IO uint16_t MCTRL2
Definition MKV58F24.h:18448
PWM_Type::STS
__IO uint16_t STS
Definition MKV58F24.h:18415
SYSMPU_Type::@180::EDR
__I uint32_t EDR
Definition MKV58F24.h:22506
CRC_Type::@151::@157::GPOLYL
__IO uint16_t GPOLYL
Definition MKV58F24.h:6197
PIT_Type::@174::CVAL
__I uint32_t CVAL
Definition MKV58F24.h:17826
TRNG_Type::PKRRNG
__IO uint32_t PKRRNG
Definition MKV58F24.h:22879
XBARA_Type::SEL26
__IO uint16_t SEL26
Definition MKV58F24.h:24788
FB_Type::@169::CSMR
__IO uint32_t CSMR
Definition MKV58F24.h:11559
DMA_Type::@161::@164::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition MKV58F24.h:6728
TRNG_Type::SBLIM
__IO uint32_t SBLIM
Definition MKV58F24.h:22886
PWM_Type::CVAL2
__I uint16_t CVAL2
Definition MKV58F24.h:18433
ENC_Type::REV
__IO uint16_t REV
Definition MKV58F24.h:9678
DMA_Type::@161::DADDR
__IO uint32_t DADDR
Definition MKV58F24.h:6724
HSADC_Type::CLIST3
__IO uint16_t CLIST3
Definition MKV58F24.h:13805
PIT_Type::@174::LDVAL
__IO uint32_t LDVAL
Definition MKV58F24.h:17825
TRNG_Type::SCR2L
__IO uint32_t SCR2L
Definition MKV58F24.h:22904
DMA_Type::@161::@162::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition MKV58F24.h:6721
MSCM_Type::CFG3
__I uint32_t CFG3
Definition MKV58F24.h:16936
PWM_Type::VAL1
__IO uint16_t VAL1
Definition MKV58F24.h:18404
ENC_Type::POSDH
__I uint16_t POSDH
Definition MKV58F24.h:9677
XBARA_Type::SEL15
__IO uint16_t SEL15
Definition MKV58F24.h:24777
CRC_Type::@151::@158::GPOLYHL
__IO uint8_t GPOLYHL
Definition MKV58F24.h:6204
TRNG_Type::PKRCNT32
__I uint32_t PKRCNT32
Definition MKV58F24.h:22925
XBARA_Type::SEL0
__IO uint16_t SEL0
Definition MKV58F24.h:24762
TRNG_Type::INT_MASK
__IO uint32_t INT_MASK
Definition MKV58F24.h:22935
HSADC_Type::CTRL1
__IO uint16_t CTRL1
Definition MKV58F24.h:13799
XBARA_Type::SEL7
__IO uint16_t SEL7
Definition MKV58F24.h:24769
PWM_Type::CAPTCOMPX
__IO uint16_t CAPTCOMPX
Definition MKV58F24.h:18428
TRNG_Type::SCR4C
__I uint32_t SCR4C
Definition MKV58F24.h:22911
HSADC_Type::SDIS
__IO uint16_t SDIS
Definition MKV58F24.h:13807
XBARA_Type::SEL29
__IO uint16_t SEL29
Definition MKV58F24.h:24791
MSCM_Type::MASTER
__I uint32_t MASTER
Definition MKV58F24.h:16931
CRC_Type::@149::@155::DATAH
__IO uint16_t DATAH
Definition MKV58F24.h:6185
CRC_Type::@153::@159::CTRLHU
__IO uint8_t CTRLHU
Definition MKV58F24.h:6212
HSADC_Type::CLIST1
__IO uint16_t CLIST1
Definition MKV58F24.h:13803
MSCM_Type::CPxCFG1
__I uint32_t CPxCFG1
Definition MKV58F24.h:16925
XBARB_Type::SEL2
__IO uint16_t SEL2
Definition MKV58F24.h:28686
CRC_Type::@151::@158::GPOLYHU
__IO uint8_t GPOLYHU
Definition MKV58F24.h:6205
PWM_Type::FTST
__IO uint16_t FTST
Definition MKV58F24.h:18452
DMA_Type::@161::DOFF
__IO uint16_t DOFF
Definition MKV58F24.h:6725
HSADC_Type::STAT
__IO uint16_t STAT
Definition MKV58F24.h:13808
AXBS_Type::@147::CRS
__IO uint32_t CRS
Definition MKV58F24.h:4237
TRNG_Type::PKRCNTDC
__I uint32_t PKRCNTDC
Definition MKV58F24.h:22930
SIM_Type::WDOGC
__IO uint32_t WDOGC
Definition MKV58F24.h:20271
HSADC_Type::MUX67_SEL
__IO uint16_t MUX67_SEL
Definition MKV58F24.h:13828
PWM_Type::CVAL3CYC
__I uint16_t CVAL3CYC
Definition MKV58F24.h:18436
XBARA_Type::SEL12
__IO uint16_t SEL12
Definition MKV58F24.h:24774
XBARA_Type::SEL5
__IO uint16_t SEL5
Definition MKV58F24.h:24767
TRNG_Type::MCTL
__IO uint32_t MCTL
Definition MKV58F24.h:22877
CRC_Type::@151::@158::GPOLYLU
__IO uint8_t GPOLYLU
Definition MKV58F24.h:6203
ENC_Type::CTRL
__IO uint16_t CTRL
Definition MKV58F24.h:9673
SPI_Type::@178::PUSHR_SLAVE
__IO uint32_t PUSHR_SLAVE
Definition MKV58F24.h:21945
PWM_Type::OCTRL
__IO uint16_t OCTRL
Definition MKV58F24.h:18414
XBARA_Type::SEL1
__IO uint16_t SEL1
Definition MKV58F24.h:24763
PWM_Type::FCTRL2
__IO uint16_t FCTRL2
Definition MKV58F24.h:18453
MSCM_Type::TYPE
__I uint32_t TYPE
Definition MKV58F24.h:16929
PWM_Type::FRACVAL4
__IO uint16_t FRACVAL4
Definition MKV58F24.h:18409
XBARB_Type::SEL3
__IO uint16_t SEL3
Definition MKV58F24.h:28687
DMA_Type::@161::SOFF
__IO uint16_t SOFF
Definition MKV58F24.h:6716
DMA_Type::@161::DLAST_SGA
__IO uint32_t DLAST_SGA
Definition MKV58F24.h:6730
PWM_Type::CNT
__I uint16_t CNT
Definition MKV58F24.h:18397
XBARA_Type::SEL9
__IO uint16_t SEL9
Definition MKV58F24.h:24771
HSADC_Type::CTRL2
__IO uint16_t CTRL2
Definition MKV58F24.h:13800
XBARA_Type::SEL17
__IO uint16_t SEL17
Definition MKV58F24.h:24779
HSADC_Type::SCINTEN
__IO uint16_t SCINTEN
Definition MKV58F24.h:13822
TRNG_Type::SCR1L
__IO uint32_t SCR1L
Definition MKV58F24.h:22900
CRC_Type::@151::GPOLY
__IO uint32_t GPOLY
Definition MKV58F24.h:6200
XBARB_Type::SEL1
__IO uint16_t SEL1
Definition MKV58F24.h:28685
PWM_Type::CVAL1CYC
__I uint16_t CVAL1CYC
Definition MKV58F24.h:18432
HSADC_Type::SCTRL
__IO uint16_t SCTRL
Definition MKV58F24.h:13819
XBARA_Type::SEL16
__IO uint16_t SEL16
Definition MKV58F24.h:24778
TRNG_Type::SCR2C
__I uint32_t SCR2C
Definition MKV58F24.h:22903
TRNG_Type::SCMISC
__IO uint32_t SCMISC
Definition MKV58F24.h:22878
SYSMPU_Type::@180::EAR
__I uint32_t EAR
Definition MKV58F24.h:22505
PWM_Type::CAPTCTRLB
__IO uint16_t CAPTCTRLB
Definition MKV58F24.h:18425
XBARA_Type::SEL4
__IO uint16_t SEL4
Definition MKV58F24.h:24766
MSCM_Type::CPxTYPE
__I uint32_t CPxTYPE
Definition MKV58F24.h:16920
HSADC_Type::LOLIMSTAT
__IO uint16_t LOLIMSTAT
Definition MKV58F24.h:13810
FTM_Type::@170::CnV
__IO uint32_t CnV
Definition MKV58F24.h:12266
TRNG_Type::FRQMAX
__IO uint32_t FRQMAX
Definition MKV58F24.h:22892
CRC_Type::@149::@155::DATAL
__IO uint16_t DATAL
Definition MKV58F24.h:6184
PWM_Type::DMAEN
__IO uint16_t DMAEN
Definition MKV58F24.h:18417
XBARA_Type::SEL28
__IO uint16_t SEL28
Definition MKV58F24.h:24790
HSADC_Type::RDY
__I uint16_t RDY
Definition MKV58F24.h:13809
TRNG_Type::PKRCNTFE
__I uint32_t PKRCNTFE
Definition MKV58F24.h:22931
MSCM_Type::COUNT
__I uint32_t COUNT
Definition MKV58F24.h:16932
HSADC_Type::CALIB
__IO uint16_t CALIB
Definition MKV58F24.h:13824
TRNG_Type::SCR1C
__I uint32_t SCR1C
Definition MKV58F24.h:22899
UART_Type::@201::@204::WP7816B_T1
__IO uint8_t WP7816B_T1
Definition MKV58F24.h:23590
PWM_Type::VAL0
__IO uint16_t VAL0
Definition MKV58F24.h:18402
PWM_Type::VAL2
__IO uint16_t VAL2
Definition MKV58F24.h:18406
ENC_Type::WTR
__IO uint16_t WTR
Definition MKV58F24.h:9675
XBARA_Type::SEL13
__IO uint16_t SEL13
Definition MKV58F24.h:24775
ENC_Type::IMR
__I uint16_t IMR
Definition MKV58F24.h:9686
HSADC_Type::ZXSTAT
__IO uint16_t ZXSTAT
Definition MKV58F24.h:13812
ENC_Type::UMOD
__IO uint16_t UMOD
Definition MKV58F24.h:9689
DMA_Type::@161::@166::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition MKV58F24.h:6733
SIM_Type::PWRC
__IO uint32_t PWRC
Definition MKV58F24.h:20272
XBARA_Type::CTRL0
__IO uint16_t CTRL0
Definition MKV58F24.h:24792
CRC_Type::@153::CTRL
__IO uint32_t CTRL
Definition MKV58F24.h:6209
PWM_Type::FRACVAL5
__IO uint16_t FRACVAL5
Definition MKV58F24.h:18411
CRC_Type::@151::@158::GPOLYLL
__IO uint8_t GPOLYLL
Definition MKV58F24.h:6202
SIM_Type::ADCOPT
__IO uint32_t ADCOPT
Definition MKV58F24.h:20273
ENC_Type::FILT
__IO uint16_t FILT
Definition MKV58F24.h:9674
TRNG_Type::SCR4L
__IO uint32_t SCR4L
Definition MKV58F24.h:22912
XBARB_Type::SEL5
__IO uint16_t SEL5
Definition MKV58F24.h:28689
ENC_Type::LPOSH
__I uint16_t LPOSH
Definition MKV58F24.h:9683
ENC_Type::TST
__IO uint16_t TST
Definition MKV58F24.h:9687
PWM_Type::FFILT
__IO uint16_t FFILT
Definition MKV58F24.h:18451
DAC_Type::@160::DATL
__IO uint8_t DATL
Definition MKV58F24.h:6455
XBARA_Type::SEL2
__IO uint16_t SEL2
Definition MKV58F24.h:24764
PWM_Type::FRACVAL3
__IO uint16_t FRACVAL3
Definition MKV58F24.h:18407
XBARA_Type::SEL19
__IO uint16_t SEL19
Definition MKV58F24.h:24781
PWM_Type::INIT
__IO uint16_t INIT
Definition MKV58F24.h:18398
HSADC_Type::PWR2
__IO uint16_t PWR2
Definition MKV58F24.h:13820
DMA_Type::@161::@166::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition MKV58F24.h:6734
XBARB_Type::SEL6
__IO uint16_t SEL6
Definition MKV58F24.h:28690
PWM_Type::SWCOUT
__IO uint16_t SWCOUT
Definition MKV58F24.h:18445
PWM_Type::CVAL1
__I uint16_t CVAL1
Definition MKV58F24.h:18431
CAN_Type::@148::WORD0
__IO uint32_t WORD0
Definition MKV58F24.h:4494
PWM_Type::MCTRL
__IO uint16_t MCTRL
Definition MKV58F24.h:18447
TRNG_Type::SCR5C
__I uint32_t SCR5C
Definition MKV58F24.h:22915
MSCM_Type::CPxCFG3
__I uint32_t CPxCFG3
Definition MKV58F24.h:16927
PDB_Type::@173::INTC
__IO uint32_t INTC
Definition MKV58F24.h:17530
HSADC_Type::SAMPTIM
__IO uint16_t SAMPTIM
Definition MKV58F24.h:13823
DMA_Type::@161::SLAST
__IO uint32_t SLAST
Definition MKV58F24.h:6723
XBARA_Type::SEL25
__IO uint16_t SEL25
Definition MKV58F24.h:24787
CRC_Type::@149::@156::DATAHL
__IO uint8_t DATAHL
Definition MKV58F24.h:6191
PWM_Type::CVAL0CYC
__I uint16_t CVAL0CYC
Definition MKV58F24.h:18430
TRNG_Type::VID2
__I uint32_t VID2
Definition MKV58F24.h:22939
PWM_Type::VAL5
__IO uint16_t VAL5
Definition MKV58F24.h:18412
PWM_Type::CVAL3
__I uint16_t CVAL3
Definition MKV58F24.h:18435
PDB_Type::@172::S
__IO uint32_t S
Definition MKV58F24.h:17524
TRNG_Type::PKRSQ
__I uint32_t PKRSQ
Definition MKV58F24.h:22882
XBARB_Type::SEL7
__IO uint16_t SEL7
Definition MKV58F24.h:28691
CAN_Type::CBT
__IO uint32_t CBT
Definition MKV58F24.h:4489
DMA_Type::@161::@162::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition MKV58F24.h:6719
CAN_Type::@148::WORD1
__IO uint32_t WORD1
Definition MKV58F24.h:4495
HSADC_Type::CLIST4
__IO uint16_t CLIST4
Definition MKV58F24.h:13806
CRC_Type::@149::@156::DATALU
__IO uint8_t DATALU
Definition MKV58F24.h:6190
HSADC_Type::HILIMSTAT
__IO uint16_t HILIMSTAT
Definition MKV58F24.h:13811
UART_Type::@201::@203::WP7816A_T0
__IO uint8_t WP7816A_T0
Definition MKV58F24.h:23585
PWM_Type::DTCNT1
__IO uint16_t DTCNT1
Definition MKV58F24.h:18422
SIM_Type::MISCTRL1
__IO uint32_t MISCTRL1
Definition MKV58F24.h:20269
XBARA_Type::SEL18
__IO uint16_t SEL18
Definition MKV58F24.h:24780
TRNG_Type::SCML
__IO uint32_t SCML
Definition MKV58F24.h:22896
TRNG_Type::FRQCNT
__I uint32_t FRQCNT
Definition MKV58F24.h:22891
SIM_Type::MISCTRL0
__IO uint32_t MISCTRL0
Definition MKV58F24.h:20268
PIT_Type::@174::TCTRL
__IO uint32_t TCTRL
Definition MKV58F24.h:17827
HSADC_Type::PWR
__IO uint16_t PWR
Definition MKV58F24.h:13817
ENC_Type::REVH
__I uint16_t REVH
Definition MKV58F24.h:9679
TRNG_Type::SDCTL
__IO uint32_t SDCTL
Definition MKV58F24.h:22884
CRC_Type::@149::DATA
__IO uint32_t DATA
Definition MKV58F24.h:6187
MSCM_Type::CFG1
__I uint32_t CFG1
Definition MKV58F24.h:16934
PWM_Type::CTRL2
__IO uint16_t CTRL2
Definition MKV58F24.h:18399
HSADC_Type::CLIST2
__IO uint16_t CLIST2
Definition MKV58F24.h:13804
XBARA_Type::SEL20
__IO uint16_t SEL20
Definition MKV58F24.h:24782
XBARA_Type::SEL10
__IO uint16_t SEL10
Definition MKV58F24.h:24772
DMA_Type::@161::ATTR
__IO uint16_t ATTR
Definition MKV58F24.h:6717
PWM_Type::CVAL2CYC
__I uint16_t CVAL2CYC
Definition MKV58F24.h:18434
PDB_Type::@173::INT
__IO uint32_t INT
Definition MKV58F24.h:17531
PWM_Type::FSTS
__IO uint16_t FSTS
Definition MKV58F24.h:18450
XBARA_Type::SEL8
__IO uint16_t SEL8
Definition MKV58F24.h:24770
ENC_Type::UPOS
__IO uint16_t UPOS
Definition MKV58F24.h:9680
HSADC_Type::ZXCTRL1
__IO uint16_t ZXCTRL1
Definition MKV58F24.h:13801
DAC_Type::@160::DATH
__IO uint8_t DATH
Definition MKV58F24.h:6456
TRNG_Type::PKRMAX
__IO uint32_t PKRMAX
Definition MKV58F24.h:22881
PWM_Type::CVAL4CYC
__I uint16_t CVAL4CYC
Definition MKV58F24.h:18438
FTM_Type::@170::CnSC
__IO uint32_t CnSC
Definition MKV58F24.h:12265
SPI_Type::@178::PUSHR
__IO uint32_t PUSHR
Definition MKV58F24.h:21944
PDB_Type::@172::C1
__IO uint32_t C1
Definition MKV58F24.h:17523
AOI_Type::BFCRT23
__IO uint16_t BFCRT23
Definition MKV58F24.h:4031
XBARB_Type::SEL4
__IO uint16_t SEL4
Definition MKV58F24.h:28688
PWM_Type::VAL3
__IO uint16_t VAL3
Definition MKV58F24.h:18408
PWM_Type::TCTRL
__IO uint16_t TCTRL
Definition MKV58F24.h:18418
TRNG_Type::TOTSAM
__I uint32_t TOTSAM
Definition MKV58F24.h:22887
XBARA_Type::SEL21
__IO uint16_t SEL21
Definition MKV58F24.h:24783
ENC_Type::UINIT
__IO uint16_t UINIT
Definition MKV58F24.h:9684
TRNG_Type::STATUS
__I uint32_t STATUS
Definition MKV58F24.h:22922
PWM_Type::CVAL4
__I uint16_t CVAL4
Definition MKV58F24.h:18437
PWM_Type::DTSRCSEL
__IO uint16_t DTSRCSEL
Definition MKV58F24.h:18446
ENET_Type::@168::TCSR
__IO uint32_t TCSR
Definition MKV58F24.h:10231
MSCM_Type::CPxMASTER
__I uint32_t CPxMASTER
Definition MKV58F24.h:16922
PWM_Type::VAL4
__IO uint16_t VAL4
Definition MKV58F24.h:18410
XBARA_Type::SEL3
__IO uint16_t SEL3
Definition MKV58F24.h:24765
TRNG_Type::PKRCNT98
__I uint32_t PKRCNT98
Definition MKV58F24.h:22928
TRNG_Type::PKRCNT10
__I uint32_t PKRCNT10
Definition MKV58F24.h:22924
TRNG_Type::SCR6PC
__I uint32_t SCR6PC
Definition MKV58F24.h:22919
DMA_Type::@161::SADDR
__IO uint32_t SADDR
Definition MKV58F24.h:6715
PWM_Type::CVAL5CYC
__I uint16_t CVAL5CYC
Definition MKV58F24.h:18440
PWM_Type::FCTRL
__IO uint16_t FCTRL
Definition MKV58F24.h:18449
DMA_Type::@161::CSR
__IO uint16_t CSR
Definition MKV58F24.h:6731
PWM_Type::CAPTCOMPB
__IO uint16_t CAPTCOMPB
Definition MKV58F24.h:18426
XBARA_Type::SEL24
__IO uint16_t SEL24
Definition MKV58F24.h:24786
TRNG_Type::INT_CTRL
__IO uint32_t INT_CTRL
Definition MKV58F24.h:22934
HSADC_Type::CALVAL_A
__IO uint16_t CALVAL_A
Definition MKV58F24.h:13825
ENC_Type::POSD
__IO uint16_t POSD
Definition MKV58F24.h:9676
TRNG_Type::PKRCNT54
__I uint32_t PKRCNT54
Definition MKV58F24.h:22926
XBARA_Type::SEL6
__IO uint16_t SEL6
Definition MKV58F24.h:24768
FB_Type::@169::CSAR
__IO uint32_t CSAR
Definition MKV58F24.h:11558
TRNG_Type::SCR3C
__I uint32_t SCR3C
Definition MKV58F24.h:22907
TRNG_Type::SCR6PL
__IO uint32_t SCR6PL
Definition MKV58F24.h:22920
UART_Type::@201::@204::WP7816A_T1
__IO uint8_t WP7816A_T1
Definition MKV58F24.h:23589
DMA_Type::@161::@162::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition MKV58F24.h:6720
TRNG_Type::PKRCNTBA
__I uint32_t PKRCNTBA
Definition MKV58F24.h:22929
MSCM_Type::NUM
__I uint32_t NUM
Definition MKV58F24.h:16930
PWM_Type::CTRL
__IO uint16_t CTRL
Definition MKV58F24.h:18400
TRNG_Type::SCR3L
__IO uint32_t SCR3L
Definition MKV58F24.h:22908
PWM_Type::CAPTCTRLX
__IO uint16_t CAPTCTRLX
Definition MKV58F24.h:18427
TRNG_Type::FRQMIN
__IO uint32_t FRQMIN
Definition MKV58F24.h:22889
ENC_Type::CTRL2
__IO uint16_t CTRL2
Definition MKV58F24.h:9688
HSADC_Type::CTRL3
__IO uint16_t CTRL3
Definition MKV58F24.h:13821
XBARA_Type::SEL11
__IO uint16_t SEL11
Definition MKV58F24.h:24773
ENC_Type::LPOS
__IO uint16_t LPOS
Definition MKV58F24.h:9681
PWM_Type::CVAL0
__I uint16_t CVAL0
Definition MKV58F24.h:18429
PWM_Type::FRACVAL1
__IO uint16_t FRACVAL1
Definition MKV58F24.h:18403
PWM_Type::FRACVAL2
__IO uint16_t FRACVAL2
Definition MKV58F24.h:18405
ENET_Type::@168::TCCR
__IO uint32_t TCCR
Definition MKV58F24.h:10232
XBARA_Type::SEL22
__IO uint16_t SEL22
Definition MKV58F24.h:24784
PMC_Type::HVDSC1
__IO uint8_t HVDSC1
Definition MKV58F24.h:17973
ENC_Type::LINIT
__IO uint16_t LINIT
Definition MKV58F24.h:9685
CAN_Type::@148::CS
__IO uint32_t CS
Definition MKV58F24.h:4492
MCM_Type::PCT
__I uint32_t PCT
Definition MKV58F24.h:16694
AXBS_Type::@147::PRS
__IO uint32_t PRS
Definition MKV58F24.h:4235
ENC_Type::LCOMP
__IO uint16_t LCOMP
Definition MKV58F24.h:9692
PWM_Type::FRCTRL
__IO uint16_t FRCTRL
Definition MKV58F24.h:18413
XBARA_Type::SEL14
__IO uint16_t SEL14
Definition MKV58F24.h:24776
PWM_Type::CAPTCTRLA
__IO uint16_t CAPTCTRLA
Definition MKV58F24.h:18423
XBARA_Type::SEL23
__IO uint16_t SEL23
Definition MKV58F24.h:24785
CRC_Type::@149::@156::DATALL
__IO uint8_t DATALL
Definition MKV58F24.h:6189
DMA_Type::@161::@164::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition MKV58F24.h:6727
TRNG_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition MKV58F24.h:22936
XBARB_Type::SEL0
__IO uint16_t SEL0
Definition MKV58F24.h:28684
HSADC_Type::CALVAL_B
__IO uint16_t CALVAL_B
Definition MKV58F24.h:13826
CRC_Type::@149::@156::DATAHU
__IO uint8_t DATAHU
Definition MKV58F24.h:6192
PWM_Type::CAPTCOMPA
__IO uint16_t CAPTCOMPA
Definition MKV58F24.h:18424
ENC_Type::UPOSH
__I uint16_t UPOSH
Definition MKV58F24.h:9682
XBARA_Type::SEL27
__IO uint16_t SEL27
Definition MKV58F24.h:24789
ENC_Type::UCOMP
__IO uint16_t UCOMP
Definition MKV58F24.h:9691
PWM_Type::INTEN
__IO uint16_t INTEN
Definition MKV58F24.h:18416
CRC_Type::@151::@157::GPOLYH
__IO uint16_t GPOLYH
Definition MKV58F24.h:6198
PWM_Type::MASK
__IO uint16_t MASK
Definition MKV58F24.h:18444
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70
_xbar_input_signal
_xbar_input_signal
Definition MKV58F24.h:445
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_xbar_output_signal
_xbar_output_signal
Definition MKV58F24.h:546
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition MK60D10.h:336
kXBARA_InputAndOrInvert1
@ kXBARA_InputAndOrInvert1
Definition MKV58F24.h:493
kXBARB_InputFtm0Match
@ kXBARB_InputFtm0Match
Definition MKV58F24.h:508
kXBARB_InputCmp1Output
@ kXBARB_InputCmp1Output
Definition MKV58F24.h:505
kXBARA_InputCmp1Output
@ kXBARA_InputCmp1Output
Definition MKV58F24.h:459
kXBARB_InputDmaCh6Done
@ kXBARB_InputDmaCh6Done
Definition MKV58F24.h:526
kXBARB_InputPwm1Ch1Trg0OrTrg1
@ kXBARB_InputPwm1Ch1Trg0OrTrg1
Definition MKV58F24.h:533
kXBARB_InputFtm2Extrig
@ kXBARB_InputFtm2Extrig
Definition MKV58F24.h:537
kXBARB_InputPitTrigger0
@ kXBARB_InputPitTrigger0
Definition MKV58F24.h:528
kXBARA_InputFtm2Extrig
@ kXBARA_InputFtm2Extrig
Definition MKV58F24.h:503
kXBARB_InputXbarIn11
@ kXBARB_InputXbarIn11
Definition MKV58F24.h:525
kXBARB_InputHsadc0Ccb
@ kXBARB_InputHsadc0Ccb
Definition MKV58F24.h:531
kXBARB_InputCmp3Output
@ kXBARB_InputCmp3Output
Definition MKV58F24.h:507
kXBARA_InputPwm0Ch2Trg0
@ kXBARA_InputPwm0Ch2Trg0
Definition MKV58F24.h:470
kXBARB_InputPwm0Ch1Trg0
@ kXBARB_InputPwm0Ch1Trg0
Definition MKV58F24.h:513
kXBARA_InputPitTrigger1
@ kXBARA_InputPitTrigger1
Definition MKV58F24.h:489
kXBARA_InputPwm0Ch3Trg1
@ kXBARA_InputPwm0Ch3Trg1
Definition MKV58F24.h:473
kXBARA_InputHsadc1Cca
@ kXBARA_InputHsadc1Cca
Definition MKV58F24.h:478
kXBARA_InputDmaCh7Done
@ kXBARA_InputDmaCh7Done
Definition MKV58F24.h:487
kXBARA_InputXbarIn6
@ kXBARA_InputXbarIn6
Definition MKV58F24.h:452
kXBARB_InputXbarIn10
@ kXBARB_InputXbarIn10
Definition MKV58F24.h:524
kXBARA_InputPwm0Ch1Trg1
@ kXBARA_InputPwm0Ch1Trg1
Definition MKV58F24.h:469
kXBARA_InputFtm0Match
@ kXBARA_InputFtm0Match
Definition MKV58F24.h:462
kXBARA_InputPwm0Ch1Trg0
@ kXBARA_InputPwm0Ch1Trg0
Definition MKV58F24.h:468
kXBARB_InputAdc0Coco
@ kXBARB_InputAdc0Coco
Definition MKV58F24.h:542
kXBARA_InputEnc0CmpPosMatch
@ kXBARA_InputEnc0CmpPosMatch
Definition MKV58F24.h:491
kXBARA_InputCmp2Output
@ kXBARA_InputCmp2Output
Definition MKV58F24.h:460
kXBARA_InputPwm1Ch0Trg0OrTrg1
@ kXBARA_InputPwm1Ch0Trg0OrTrg1
Definition MKV58F24.h:498
kXBARB_InputDmaCh0Done
@ kXBARB_InputDmaCh0Done
Definition MKV58F24.h:522
kXBARA_InputPwm1Ch3Trg0OrTrg1
@ kXBARA_InputPwm1Ch3Trg0OrTrg1
Definition MKV58F24.h:501
kXBARA_InputPdb1Ch1Output
@ kXBARA_InputPdb1Ch1Output
Definition MKV58F24.h:476
kXBARA_InputHsadc1Ccb
@ kXBARA_InputHsadc1Ccb
Definition MKV58F24.h:480
kXBARB_InputFtm1Match
@ kXBARB_InputFtm1Match
Definition MKV58F24.h:520
kXBARB_InputFtm2Match
@ kXBARB_InputFtm2Match
Definition MKV58F24.h:536
kXBARA_InputFtm3Match
@ kXBARA_InputFtm3Match
Definition MKV58F24.h:464
kXBARA_InputXbarIn2
@ kXBARA_InputXbarIn2
Definition MKV58F24.h:448
kXBARB_InputCmp0Output
@ kXBARB_InputCmp0Output
Definition MKV58F24.h:504
kXBARB_InputPwm0Ch0Trg0
@ kXBARB_InputPwm0Ch0Trg0
Definition MKV58F24.h:512
kXBARB_InputDmaCh7Done
@ kXBARB_InputDmaCh7Done
Definition MKV58F24.h:527
kXBARA_InputPdb0Ch0Output
@ kXBARA_InputPdb0Ch0Output
Definition MKV58F24.h:475
kXBARA_InputXbarIn8
@ kXBARA_InputXbarIn8
Definition MKV58F24.h:454
kXBARA_InputPdb0Ch1Output
@ kXBARA_InputPdb0Ch1Output
Definition MKV58F24.h:474
kXBARA_InputFtm1Match
@ kXBARA_InputFtm1Match
Definition MKV58F24.h:482
kXBARB_InputPdb1Ch1Output
@ kXBARB_InputPdb1Ch1Output
Definition MKV58F24.h:539
kXBARA_InputXbarIn7
@ kXBARA_InputXbarIn7
Definition MKV58F24.h:453
kXBARA_InputAdc0Coco
@ kXBARA_InputAdc0Coco
Definition MKV58F24.h:490
kXBARB_InputPdb1Ch0Output
@ kXBARB_InputPdb1Ch0Output
Definition MKV58F24.h:530
kXBARA_InputVss
@ kXBARA_InputVss
Definition MKV58F24.h:446
kXBARA_InputFtm2Match
@ kXBARA_InputFtm2Match
Definition MKV58F24.h:502
kXBARB_InputFtm3Match
@ kXBARB_InputFtm3Match
Definition MKV58F24.h:510
kXBARA_InputPwm0Ch0Trg1
@ kXBARA_InputPwm0Ch0Trg1
Definition MKV58F24.h:467
kXBARA_InputPwm0Ch3Trg0
@ kXBARA_InputPwm0Ch3Trg0
Definition MKV58F24.h:472
kXBARB_InputFtm0Extrig
@ kXBARB_InputFtm0Extrig
Definition MKV58F24.h:509
kXBARA_InputPitTrigger0
@ kXBARA_InputPitTrigger0
Definition MKV58F24.h:488
kXBARB_InputPwm1Ch2Trg0OrTrg1
@ kXBARB_InputPwm1Ch2Trg0OrTrg1
Definition MKV58F24.h:534
kXBARA_InputCmp3Output
@ kXBARA_InputCmp3Output
Definition MKV58F24.h:461
kXBARB_InputHsadc1Ccb
@ kXBARB_InputHsadc1Ccb
Definition MKV58F24.h:541
kXBARA_InputXbarIn4
@ kXBARA_InputXbarIn4
Definition MKV58F24.h:450
kXBARA_InputPdb1Ch0Output
@ kXBARA_InputPdb1Ch0Output
Definition MKV58F24.h:477
kXBARA_InputDmaCh0Done
@ kXBARA_InputDmaCh0Done
Definition MKV58F24.h:484
kXBARA_InputPwm1Ch1Trg0OrTrg1
@ kXBARA_InputPwm1Ch1Trg0OrTrg1
Definition MKV58F24.h:499
kXBARB_InputPwm1Ch3Trg0OrTrg1
@ kXBARB_InputPwm1Ch3Trg0OrTrg1
Definition MKV58F24.h:535
kXBARB_InputFtm1Extrig
@ kXBARB_InputFtm1Extrig
Definition MKV58F24.h:521
kXBARA_InputPwm1Ch2Trg0OrTrg1
@ kXBARA_InputPwm1Ch2Trg0OrTrg1
Definition MKV58F24.h:500
kXBARA_InputAndOrInvert2
@ kXBARA_InputAndOrInvert2
Definition MKV58F24.h:494
kXBARA_InputXbarIn11
@ kXBARA_InputXbarIn11
Definition MKV58F24.h:457
kXBARB_InputXbarIn3
@ kXBARB_InputXbarIn3
Definition MKV58F24.h:519
kXBARB_InputPitTrigger1
@ kXBARB_InputPitTrigger1
Definition MKV58F24.h:529
kXBARA_InputPitTrigger3
@ kXBARA_InputPitTrigger3
Definition MKV58F24.h:497
kXBARA_InputAndOrInvert0
@ kXBARA_InputAndOrInvert0
Definition MKV58F24.h:492
kXBARB_InputHsadc0Cca
@ kXBARB_InputHsadc0Cca
Definition MKV58F24.h:517
kXBARB_InputPdb0Ch0Output
@ kXBARB_InputPdb0Ch0Output
Definition MKV58F24.h:516
kXBARB_InputXbarIn2
@ kXBARB_InputXbarIn2
Definition MKV58F24.h:518
kXBARA_InputPitTrigger2
@ kXBARA_InputPitTrigger2
Definition MKV58F24.h:496
kXBARA_InputDmaCh6Done
@ kXBARA_InputDmaCh6Done
Definition MKV58F24.h:486
kXBARA_InputXbarIn3
@ kXBARA_InputXbarIn3
Definition MKV58F24.h:449
kXBARA_InputAndOrInvert3
@ kXBARA_InputAndOrInvert3
Definition MKV58F24.h:495
kXBARA_InputDmaCh1Done
@ kXBARA_InputDmaCh1Done
Definition MKV58F24.h:485
kXBARB_InputCmp2Output
@ kXBARB_InputCmp2Output
Definition MKV58F24.h:506
kXBARA_InputFtm3Extrig
@ kXBARA_InputFtm3Extrig
Definition MKV58F24.h:465
kXBARB_InputFtm3Extrig
@ kXBARB_InputFtm3Extrig
Definition MKV58F24.h:511
kXBARA_InputHsadc0Cca
@ kXBARA_InputHsadc0Cca
Definition MKV58F24.h:479
kXBARA_InputVdd
@ kXBARA_InputVdd
Definition MKV58F24.h:447
kXBARB_InputPwm1Ch0Trg0OrTrg1
@ kXBARB_InputPwm1Ch0Trg0OrTrg1
Definition MKV58F24.h:532
kXBARA_InputCmp0Output
@ kXBARA_InputCmp0Output
Definition MKV58F24.h:458
kXBARA_InputXbarIn5
@ kXBARA_InputXbarIn5
Definition MKV58F24.h:451
kXBARB_InputPwm0Ch3Trg0
@ kXBARB_InputPwm0Ch3Trg0
Definition MKV58F24.h:515
kXBARA_InputXbarIn10
@ kXBARA_InputXbarIn10
Definition MKV58F24.h:456
kXBARA_InputXbarIn9
@ kXBARA_InputXbarIn9
Definition MKV58F24.h:455
kXBARB_InputHsadc1Cca
@ kXBARB_InputHsadc1Cca
Definition MKV58F24.h:540
kXBARB_InputDmaCh1Done
@ kXBARB_InputDmaCh1Done
Definition MKV58F24.h:523
kXBARA_InputFtm0Extrig
@ kXBARA_InputFtm0Extrig
Definition MKV58F24.h:463
kXBARA_InputPwm0Ch2Trg1
@ kXBARA_InputPwm0Ch2Trg1
Definition MKV58F24.h:471
kXBARA_InputPwm0Ch0Trg0
@ kXBARA_InputPwm0Ch0Trg0
Definition MKV58F24.h:466
kXBARB_InputPdb0Ch1Output
@ kXBARB_InputPdb0Ch1Output
Definition MKV58F24.h:538
kXBARA_InputHsadc0Ccb
@ kXBARA_InputHsadc0Ccb
Definition MKV58F24.h:481
kXBARA_InputFtm1Extrig
@ kXBARA_InputFtm1Extrig
Definition MKV58F24.h:483
kXBARB_InputPwm0Ch2Trg0
@ kXBARB_InputPwm0Ch2Trg0
Definition MKV58F24.h:514
kXBARA_OutputDmamux21
@ kXBARA_OutputDmamux21
Definition MKV58F24.h:550
kXBARB_OutputAoiIn9
@ kXBARB_OutputAoiIn9
Definition MKV58F24.h:615
kXBARA_OutputCmp3
@ kXBARA_OutputCmp3
Definition MKV58F24.h:566
kXBARA_OutputFtm0Fault3
@ kXBARA_OutputFtm0Fault3
Definition MKV58F24.h:596
kXBARA_OutputDmamux20
@ kXBARA_OutputDmamux20
Definition MKV58F24.h:549
kXBARA_OutputDac12bSync
@ kXBARA_OutputDac12bSync
Definition MKV58F24.h:562
kXBARA_OutputEncPhA
@ kXBARA_OutputEncPhA
Definition MKV58F24.h:591
kXBARB_OutputAoiIn14
@ kXBARB_OutputAoiIn14
Definition MKV58F24.h:620
kXBARA_OutputXbOut9
@ kXBARA_OutputXbOut9
Definition MKV58F24.h:556
kXBARB_OutputAoiIn7
@ kXBARB_OutputAoiIn7
Definition MKV58F24.h:613
kXBARA_OutputHsadc1BTrig
@ kXBARA_OutputHsadc1BTrig
Definition MKV58F24.h:590
kXBARA_OutputDmamux19
@ kXBARA_OutputDmamux19
Definition MKV58F24.h:548
kXBARB_OutputAoiIn3
@ kXBARB_OutputAoiIn3
Definition MKV58F24.h:609
kXBARA_OutputFtm2Fault1
@ kXBARA_OutputFtm2Fault1
Definition MKV58F24.h:598
kXBARA_OutputPwm0Ch2ExtSync
@ kXBARA_OutputPwm0Ch2ExtSync
Definition MKV58F24.h:573
kXBARA_OutputXbOut4
@ kXBARA_OutputXbOut4
Definition MKV58F24.h:551
kXBARA_OutputCmp0
@ kXBARA_OutputCmp0
Definition MKV58F24.h:563
kXBARA_OutputXbOut5
@ kXBARA_OutputXbOut5
Definition MKV58F24.h:552
kXBARA_OutputPwm1Ch2ExtSync
@ kXBARA_OutputPwm1Ch2ExtSync
Definition MKV58F24.h:602
kXBARA_OutputFtm1Trig2
@ kXBARA_OutputFtm1Trig2
Definition MKV58F24.h:582
kXBARB_OutputAoiIn8
@ kXBARB_OutputAoiIn8
Definition MKV58F24.h:614
kXBARA_OutputEncIndex
@ kXBARA_OutputEncIndex
Definition MKV58F24.h:593
kXBARB_OutputAoiIn0
@ kXBARB_OutputAoiIn0
Definition MKV58F24.h:606
kXBARA_OutputAdc0Hdwt
@ kXBARA_OutputAdc0Hdwt
Definition MKV58F24.h:586
kXBARA_OutputPwm1Ch3ExtSync
@ kXBARA_OutputPwm1Ch3ExtSync
Definition MKV58F24.h:603
kXBARA_OutputCmp1
@ kXBARA_OutputCmp1
Definition MKV58F24.h:564
kXBARA_OutputHsadc0ATrig
@ kXBARA_OutputHsadc0ATrig
Definition MKV58F24.h:559
kXBARA_OutputPwm0Fault1
@ kXBARA_OutputPwm0Fault1
Definition MKV58F24.h:577
kXBARA_OutputDmamux18
@ kXBARA_OutputDmamux18
Definition MKV58F24.h:547
kXBARB_OutputAoiIn11
@ kXBARB_OutputAoiIn11
Definition MKV58F24.h:617
kXBARA_OutputPwmCh3ExtA
@ kXBARA_OutputPwmCh3ExtA
Definition MKV58F24.h:570
kXBARA_OutputRESERVED14
@ kXBARA_OutputRESERVED14
Definition MKV58F24.h:561
kXBARA_OutputPwmCh0ExtA
@ kXBARA_OutputPwmCh0ExtA
Definition MKV58F24.h:567
kXBARA_OutputXbOut8
@ kXBARA_OutputXbOut8
Definition MKV58F24.h:555
kXBARB_OutputAoiIn6
@ kXBARB_OutputAoiIn6
Definition MKV58F24.h:612
kXBARA_OutputEncPhB
@ kXBARA_OutputEncPhB
Definition MKV58F24.h:592
kXBARA_OutputXbOut7
@ kXBARA_OutputXbOut7
Definition MKV58F24.h:554
kXBARA_OutputPwm0Ch1ExtSync
@ kXBARA_OutputPwm0Ch1ExtSync
Definition MKV58F24.h:572
kXBARA_OutputHsadc1ATrig
@ kXBARA_OutputHsadc1ATrig
Definition MKV58F24.h:589
kXBARA_OutputXbOut6
@ kXBARA_OutputXbOut6
Definition MKV58F24.h:553
kXBARA_OutputPwm0Ch3ExtSync
@ kXBARA_OutputPwm0Ch3ExtSync
Definition MKV58F24.h:574
kXBARA_OutputPwmCh1ExtA
@ kXBARA_OutputPwmCh1ExtA
Definition MKV58F24.h:568
kXBARA_OutputPdb1InCh12
@ kXBARA_OutputPdb1InCh12
Definition MKV58F24.h:588
kXBARA_OutputRESERVED40
@ kXBARA_OutputRESERVED40
Definition MKV58F24.h:587
kXBARA_OutputEncHome
@ kXBARA_OutputEncHome
Definition MKV58F24.h:594
kXBARA_OutputXbOut11
@ kXBARA_OutputXbOut11
Definition MKV58F24.h:558
kXBARA_OutputCmp2
@ kXBARA_OutputCmp2
Definition MKV58F24.h:565
kXBARB_OutputAoiIn2
@ kXBARB_OutputAoiIn2
Definition MKV58F24.h:608
kXBARA_OutputFtm3Trig2
@ kXBARA_OutputFtm3Trig2
Definition MKV58F24.h:584
kXBARB_OutputAoiIn12
@ kXBARB_OutputAoiIn12
Definition MKV58F24.h:618
kXBARA_OutputPwm0Force
@ kXBARA_OutputPwm0Force
Definition MKV58F24.h:580
kXBARA_OutputPwm0Fault0
@ kXBARA_OutputPwm0Fault0
Definition MKV58F24.h:576
kXBARB_OutputAoiIn1
@ kXBARB_OutputAoiIn1
Definition MKV58F24.h:607
kXBARA_OutputEwmIn
@ kXBARA_OutputEwmIn
Definition MKV58F24.h:605
kXBARA_OutputFtm1Fault1
@ kXBARA_OutputFtm1Fault1
Definition MKV58F24.h:597
kXBARA_OutputPwm1Force
@ kXBARA_OutputPwm1Force
Definition MKV58F24.h:604
kXBARA_OutputFtm2Trig2
@ kXBARA_OutputFtm2Trig2
Definition MKV58F24.h:583
kXBARA_OutputPwm1Ch0ExtSync
@ kXBARA_OutputPwm1Ch0ExtSync
Definition MKV58F24.h:600
kXBARA_OutputPdb0InCh12
@ kXBARA_OutputPdb0InCh12
Definition MKV58F24.h:585
kXBARB_OutputAoiIn13
@ kXBARB_OutputAoiIn13
Definition MKV58F24.h:619
kXBARB_OutputAoiIn10
@ kXBARB_OutputAoiIn10
Definition MKV58F24.h:616
kXBARB_OutputAoiIn5
@ kXBARB_OutputAoiIn5
Definition MKV58F24.h:611
kXBARA_OutputFtm3Fault3
@ kXBARA_OutputFtm3Fault3
Definition MKV58F24.h:599
kXBARA_OutputEncCapTrigger
@ kXBARA_OutputEncCapTrigger
Definition MKV58F24.h:595
kXBARA_OutputPwm0Ch0ExtSync
@ kXBARA_OutputPwm0Ch0ExtSync
Definition MKV58F24.h:571
kXBARA_OutputPwmCh2ExtA
@ kXBARA_OutputPwmCh2ExtA
Definition MKV58F24.h:569
kXBARA_OutputPwm0Fault2
@ kXBARA_OutputPwm0Fault2
Definition MKV58F24.h:578
kXBARB_OutputAoiIn4
@ kXBARB_OutputAoiIn4
Definition MKV58F24.h:610
kXBARA_OutputPwm0Fault3
@ kXBARA_OutputPwm0Fault3
Definition MKV58F24.h:579
kXBARA_OutputFtm0Trig2
@ kXBARA_OutputFtm0Trig2
Definition MKV58F24.h:581
kXBARA_OutputPwm1Ch1ExtSync
@ kXBARA_OutputPwm1Ch1ExtSync
Definition MKV58F24.h:601
kXBARA_OutputXbOut10
@ kXBARA_OutputXbOut10
Definition MKV58F24.h:557
kXBARA_OutputHsadc0BTrig
@ kXBARA_OutputHsadc0BTrig
Definition MKV58F24.h:560
kXBARA_OutputPwmExtClk
@ kXBARA_OutputPwmExtClk
Definition MKV58F24.h:575
kXBARB_OutputAoiIn15
@ kXBARB_OutputAoiIn15
Definition MKV58F24.h:621
kDmaRequestMux0FTM1Channel0
@ kDmaRequestMux0FTM1Channel0
Definition MKV58F24.h:344
kDmaRequestMux0Group1UART4Tx
@ kDmaRequestMux0Group1UART4Tx
Definition MKV58F24.h:431
kDmaRequestMux0Group1Reserved23
@ kDmaRequestMux0Group1Reserved23
Definition MKV58F24.h:399
kDmaRequestMux0DAC0
@ kDmaRequestMux0DAC0
Definition MKV58F24.h:357
kDmaRequestMux0FTM0Channel7
@ kDmaRequestMux0FTM0Channel7
Definition MKV58F24.h:343
kDmaRequestMux0Group1Reserved49
@ kDmaRequestMux0Group1Reserved49
Definition MKV58F24.h:425
kDmaRequestMux0I2C0
@ kDmaRequestMux0I2C0
Definition MKV58F24.h:334
kDmaRequestMux0CMP0
@ kDmaRequestMux0CMP0
Definition MKV58F24.h:354
kDmaRequestMux0FTM3Channel1
@ kDmaRequestMux0FTM3Channel1
Definition MKV58F24.h:349
kDmaRequestMux0Group1UART3Rx
@ kDmaRequestMux0Group1UART3Rx
Definition MKV58F24.h:380
kDmaRequestMux0PWM0CP2
@ kDmaRequestMux0PWM0CP2
Definition MKV58F24.h:324
kDmaRequestMux0Reserved35
@ kDmaRequestMux0Reserved35
Definition MKV58F24.h:347
kDmaRequestMux0PWM0CP3
@ kDmaRequestMux0PWM0CP3
Definition MKV58F24.h:325
kDmaRequestMux0Group1Reserved47
@ kDmaRequestMux0Group1Reserved47
Definition MKV58F24.h:423
kDmaRequestMux0Group1Reserved20
@ kDmaRequestMux0Group1Reserved20
Definition MKV58F24.h:396
kDmaRequestMux0Group1Reserved53
@ kDmaRequestMux0Group1Reserved53
Definition MKV58F24.h:429
kDmaRequestMux0PWM0WR3
@ kDmaRequestMux0PWM0WR3
Definition MKV58F24.h:321
kDmaRequestMux0Group1IEEE1588Timer2
@ kDmaRequestMux0Group1IEEE1588Timer2
Definition MKV58F24.h:414
kDmaRequestMux0CMP1
@ kDmaRequestMux0CMP1
Definition MKV58F24.h:355
kDmaRequestMux0FTM3Channel7
@ kDmaRequestMux0FTM3Channel7
Definition MKV58F24.h:369
kDmaRequestMux0Group1Reserved50
@ kDmaRequestMux0Group1Reserved50
Definition MKV58F24.h:426
kDmaRequestMux0XBARAOUT2
@ kDmaRequestMux0XBARAOUT2
Definition MKV58F24.h:332
kDmaRequestMux0Group1HSADC1A
@ kDmaRequestMux0Group1HSADC1A
Definition MKV58F24.h:416
kDmaRequestMux0Group1UART3Tx
@ kDmaRequestMux0Group1UART3Tx
Definition MKV58F24.h:381
kDmaRequestMux0Group1SPI2Tx
@ kDmaRequestMux0Group1SPI2Tx
Definition MKV58F24.h:411
kDmaRequestMux0Reserved58
@ kDmaRequestMux0Reserved58
Definition MKV58F24.h:370
kDmaRequestMux0PortE
@ kDmaRequestMux0PortE
Definition MKV58F24.h:365
kDmaRequestMux0AlwaysOn63
@ kDmaRequestMux0AlwaysOn63
Definition MKV58F24.h:375
kDmaRequestMux0Group1AlwaysOn63
@ kDmaRequestMux0Group1AlwaysOn63
Definition MKV58F24.h:439
kDmaRequestMux0Group1Reserved28
@ kDmaRequestMux0Group1Reserved28
Definition MKV58F24.h:404
kDmaRequestMux0Group1UART5Rx
@ kDmaRequestMux0Group1UART5Rx
Definition MKV58F24.h:432
kDmaRequestMux0Group1PWM1CP1
@ kDmaRequestMux0Group1PWM1CP1
Definition MKV58F24.h:387
kDmaRequestMux0Group1Disable
@ kDmaRequestMux0Group1Disable
Definition MKV58F24.h:376
kDmaRequestMux0SPI0Tx
@ kDmaRequestMux0SPI0Tx
Definition MKV58F24.h:329
kDmaRequestMux0Group1Reserved18
@ kDmaRequestMux0Group1Reserved18
Definition MKV58F24.h:394
kDmaRequestMux0FTM0Channel1
@ kDmaRequestMux0FTM0Channel1
Definition MKV58F24.h:337
kDmaRequestMux0Group1Reserved59
@ kDmaRequestMux0Group1Reserved59
Definition MKV58F24.h:435
kDmaRequestMux0FTM0Channel5
@ kDmaRequestMux0FTM0Channel5
Definition MKV58F24.h:341
kDmaRequestMux0AlwaysOn61
@ kDmaRequestMux0AlwaysOn61
Definition MKV58F24.h:373
kDmaRequestMux0Group1ADC0
@ kDmaRequestMux0Group1ADC0
Definition MKV58F24.h:421
kDmaRequestMux0Group1Reserved30
@ kDmaRequestMux0Group1Reserved30
Definition MKV58F24.h:406
kDmaRequestMux0UART1Tx
@ kDmaRequestMux0UART1Tx
Definition MKV58F24.h:317
kDmaRequestMux0Group1UART2Rx
@ kDmaRequestMux0Group1UART2Rx
Definition MKV58F24.h:378
kDmaRequestMux0Group1I2C1
@ kDmaRequestMux0Group1I2C1
Definition MKV58F24.h:398
kDmaRequestMux0PWM0WR1
@ kDmaRequestMux0PWM0WR1
Definition MKV58F24.h:319
kDmaRequestMux0FTM0Channel6
@ kDmaRequestMux0FTM0Channel6
Definition MKV58F24.h:342
kDmaRequestMux0Group1PWM1CP0
@ kDmaRequestMux0Group1PWM1CP0
Definition MKV58F24.h:386
kDmaRequestMux0Group1Reserved31
@ kDmaRequestMux0Group1Reserved31
Definition MKV58F24.h:407
kDmaRequestMux0Group1Reserved19
@ kDmaRequestMux0Group1Reserved19
Definition MKV58F24.h:395
kDmaRequestMux0Group1Reserved51
@ kDmaRequestMux0Group1Reserved51
Definition MKV58F24.h:427
kDmaRequestMux0PDB0
@ kDmaRequestMux0PDB0
Definition MKV58F24.h:360
kDmaRequestMux0Group1IEEE1588Timer3
@ kDmaRequestMux0Group1IEEE1588Timer3
Definition MKV58F24.h:415
kDmaRequestMux0UART1Rx
@ kDmaRequestMux0UART1Rx
Definition MKV58F24.h:316
kDmaRequestMux0Group1Reserved42
@ kDmaRequestMux0Group1Reserved42
Definition MKV58F24.h:418
kDmaRequestMux0XBARAOUT3
@ kDmaRequestMux0XBARAOUT3
Definition MKV58F24.h:333
kDmaRequestMux0PortB
@ kDmaRequestMux0PortB
Definition MKV58F24.h:362
kDmaRequestMux0Group1Reserved52
@ kDmaRequestMux0Group1Reserved52
Definition MKV58F24.h:428
kDmaRequestMux0CMP3
@ kDmaRequestMux0CMP3
Definition MKV58F24.h:346
kDmaRequestMux0Group1SPI1Rx
@ kDmaRequestMux0Group1SPI1Rx
Definition MKV58F24.h:392
kDmaRequestMux0PortC
@ kDmaRequestMux0PortC
Definition MKV58F24.h:363
kDmaRequestMux0Group1PWM1WR2
@ kDmaRequestMux0Group1PWM1WR2
Definition MKV58F24.h:384
kDmaRequestMux0FTM3Channel0
@ kDmaRequestMux0FTM3Channel0
Definition MKV58F24.h:348
kDmaRequestMux0CAN0
@ kDmaRequestMux0CAN0
Definition MKV58F24.h:326
kDmaRequestMux0XBARAOUT0
@ kDmaRequestMux0XBARAOUT0
Definition MKV58F24.h:330
kDmaRequestMux0FTM1Channel1
@ kDmaRequestMux0FTM1Channel1
Definition MKV58F24.h:345
kDmaRequestMux0CMP2
@ kDmaRequestMux0CMP2
Definition MKV58F24.h:356
kDmaRequestMux0Reserved1
@ kDmaRequestMux0Reserved1
Definition MKV58F24.h:313
kDmaRequestMux0Group1Reserved44
@ kDmaRequestMux0Group1Reserved44
Definition MKV58F24.h:420
kDmaRequestMux0Group1Reserved46
@ kDmaRequestMux0Group1Reserved46
Definition MKV58F24.h:422
kDmaRequestMux0Group1IEEE1588Timer0
@ kDmaRequestMux0Group1IEEE1588Timer0
Definition MKV58F24.h:412
kDmaRequestMux0HSADC0B
@ kDmaRequestMux0HSADC0B
Definition MKV58F24.h:353
kDmaRequestMux0FTM0Channel4
@ kDmaRequestMux0FTM0Channel4
Definition MKV58F24.h:340
kDmaRequestMux0Group1PWM1CP3
@ kDmaRequestMux0Group1PWM1CP3
Definition MKV58F24.h:389
kDmaRequestMux0Group1Reserved26
@ kDmaRequestMux0Group1Reserved26
Definition MKV58F24.h:402
kDmaRequestMux0Group1AlwaysOn60
@ kDmaRequestMux0Group1AlwaysOn60
Definition MKV58F24.h:436
kDmaRequestMux0Group1Reserved29
@ kDmaRequestMux0Group1Reserved29
Definition MKV58F24.h:405
kDmaRequestMux0AlwaysOn60
@ kDmaRequestMux0AlwaysOn60
Definition MKV58F24.h:372
kDmaRequestMux0FTM3Channel2
@ kDmaRequestMux0FTM3Channel2
Definition MKV58F24.h:350
kDmaRequestMux0Group1FTM2Channel1
@ kDmaRequestMux0Group1FTM2Channel1
Definition MKV58F24.h:409
kDmaRequestMux0Group1UART4Rx
@ kDmaRequestMux0Group1UART4Rx
Definition MKV58F24.h:430
kDmaRequestMux0PWM0WR2
@ kDmaRequestMux0PWM0WR2
Definition MKV58F24.h:320
kDmaRequestMux0Group1PWM1WR0
@ kDmaRequestMux0Group1PWM1WR0
Definition MKV58F24.h:382
kDmaRequestMux0Group1Reserved21
@ kDmaRequestMux0Group1Reserved21
Definition MKV58F24.h:397
kDmaRequestMux0FTM3Channel4
@ kDmaRequestMux0FTM3Channel4
Definition MKV58F24.h:366
kDmaRequestMux0FTM3Channel5
@ kDmaRequestMux0FTM3Channel5
Definition MKV58F24.h:367
kDmaRequestMux0Disable
@ kDmaRequestMux0Disable
Definition MKV58F24.h:312
kDmaRequestMux0Group1SPI2Rx
@ kDmaRequestMux0Group1SPI2Rx
Definition MKV58F24.h:410
kDmaRequestMux0Group1Reserved24
@ kDmaRequestMux0Group1Reserved24
Definition MKV58F24.h:400
kDmaRequestMux0Group1CAN2
@ kDmaRequestMux0Group1CAN2
Definition MKV58F24.h:390
kDmaRequestMux0Reserved23
@ kDmaRequestMux0Reserved23
Definition MKV58F24.h:335
kDmaRequestMux0PortA
@ kDmaRequestMux0PortA
Definition MKV58F24.h:361
kDmaRequestMux0PortD
@ kDmaRequestMux0PortD
Definition MKV58F24.h:364
kDmaRequestMux0Group1Reserved58
@ kDmaRequestMux0Group1Reserved58
Definition MKV58F24.h:434
kDmaRequestMux0Group1SPI1Tx
@ kDmaRequestMux0Group1SPI1Tx
Definition MKV58F24.h:393
kDmaRequestMux0Group1UART5Tx
@ kDmaRequestMux0Group1UART5Tx
Definition MKV58F24.h:433
kDmaRequestMux0Group1Reserved27
@ kDmaRequestMux0Group1Reserved27
Definition MKV58F24.h:403
kDmaRequestMux0Group1Reserved1
@ kDmaRequestMux0Group1Reserved1
Definition MKV58F24.h:377
kDmaRequestMux0Group1UART2Tx
@ kDmaRequestMux0Group1UART2Tx
Definition MKV58F24.h:379
kDmaRequestMux0PWM0CP0
@ kDmaRequestMux0PWM0CP0
Definition MKV58F24.h:322
kDmaRequestMux0Group1FTM2Channel0
@ kDmaRequestMux0Group1FTM2Channel0
Definition MKV58F24.h:408
kDmaRequestMux0FTM3Channel3
@ kDmaRequestMux0FTM3Channel3
Definition MKV58F24.h:351
kDmaRequestMux0FTM0Channel3
@ kDmaRequestMux0FTM0Channel3
Definition MKV58F24.h:339
kDmaRequestMux0Group1AlwaysOn62
@ kDmaRequestMux0Group1AlwaysOn62
Definition MKV58F24.h:438
kDmaRequestMux0CAN1
@ kDmaRequestMux0CAN1
Definition MKV58F24.h:327
kDmaRequestMux0HSADC0A
@ kDmaRequestMux0HSADC0A
Definition MKV58F24.h:352
kDmaRequestMux0Reserved59
@ kDmaRequestMux0Reserved59
Definition MKV58F24.h:371
kDmaRequestMux0Group1PWM1WR1
@ kDmaRequestMux0Group1PWM1WR1
Definition MKV58F24.h:383
kDmaRequestMux0UART0Rx
@ kDmaRequestMux0UART0Rx
Definition MKV58F24.h:314
kDmaRequestMux0Group1PWM1WR3
@ kDmaRequestMux0Group1PWM1WR3
Definition MKV58F24.h:385
kDmaRequestMux0FTM0Channel0
@ kDmaRequestMux0FTM0Channel0
Definition MKV58F24.h:336
kDmaRequestMux0FTM3Channel6
@ kDmaRequestMux0FTM3Channel6
Definition MKV58F24.h:368
kDmaRequestMux0Group1AlwaysOn61
@ kDmaRequestMux0Group1AlwaysOn61
Definition MKV58F24.h:437
kDmaRequestMux0Group1Reserved43
@ kDmaRequestMux0Group1Reserved43
Definition MKV58F24.h:419
kDmaRequestMux0Reserved46
@ kDmaRequestMux0Reserved46
Definition MKV58F24.h:358
kDmaRequestMux0PWM0WR0
@ kDmaRequestMux0PWM0WR0
Definition MKV58F24.h:318
kDmaRequestMux0AlwaysOn62
@ kDmaRequestMux0AlwaysOn62
Definition MKV58F24.h:374
kDmaRequestMux0PWM0CP1
@ kDmaRequestMux0PWM0CP1
Definition MKV58F24.h:323
kDmaRequestMux0PDB1
@ kDmaRequestMux0PDB1
Definition MKV58F24.h:359
kDmaRequestMux0Group1Reserved25
@ kDmaRequestMux0Group1Reserved25
Definition MKV58F24.h:401
kDmaRequestMux0Group1Reserved15
@ kDmaRequestMux0Group1Reserved15
Definition MKV58F24.h:391
kDmaRequestMux0Group1PWM1CP2
@ kDmaRequestMux0Group1PWM1CP2
Definition MKV58F24.h:388
kDmaRequestMux0FTM0Channel2
@ kDmaRequestMux0FTM0Channel2
Definition MKV58F24.h:338
kDmaRequestMux0UART0Tx
@ kDmaRequestMux0UART0Tx
Definition MKV58F24.h:315
kDmaRequestMux0SPI0Rx
@ kDmaRequestMux0SPI0Rx
Definition MKV58F24.h:328
kDmaRequestMux0Group1IEEE1588Timer1
@ kDmaRequestMux0Group1IEEE1588Timer1
Definition MKV58F24.h:413
kDmaRequestMux0Group1HSADC1B
@ kDmaRequestMux0Group1HSADC1B
Definition MKV58F24.h:417
kDmaRequestMux0XBARAOUT1
@ kDmaRequestMux0XBARAOUT1
Definition MKV58F24.h:331
kDmaRequestMux0Group1Reserved48
@ kDmaRequestMux0Group1Reserved48
Definition MKV58F24.h:424
ADC_Type
Definition MK60D10.h:449
AIPS_Type
Definition MK60D10.h:726
AOI_Type
Definition MKV58F24.h:4028
AXBS_Type
Definition MK60D10.h:2032
CAN_Type
Definition MK60D10.h:2166
CAU_Type
Definition MK60D10.h:2591
CMP_Type
Definition MK60D10.h:3104
CRC_Type
Definition MK60D10.h:3382
DAC_Type
Definition MK60D10.h:3574
DMAMUX_Type
Definition MK60D10.h:4580
DMA_Type
Definition MK60D10.h:3706
ENC_Type
Definition MKV58F24.h:9672
ENET_Type
Definition MK60D10.h:4638
EWM_Type
Definition MK60D10.h:5537
FB_Type
Definition MK60D10.h:5622
FMC_Type
Definition MK60D10.h:5755
FTFE_Type
Definition MK64F12.h:10306
FTM_Type
Definition MK60D10.h:6173
GPIO_Type
Definition MK60D10.h:6852
HSADC_Type
Definition MKV58F24.h:13798
I2C_Type
Definition MK60D10.h:6947
LLWU_Type
Definition MK60D10.h:7536
LPTMR_Type
Definition MK60D10.h:7782
MCG_Type
Definition MK60D10.h:7875
MCM_Type
Definition MK60D10.h:8113
MSCM_Type
Definition MKV58F24.h:16919
NV_Type
Definition MK60D10.h:8235
OSC_Type
Definition MK60D10.h:8389
PDB_Type
Definition MK60D10.h:8453
PIT_Type
Definition MK60D10.h:8640
PMC_Type
Definition MK60D10.h:8739
PORT_Type
Definition MK60D10.h:8832
PWM_Type
Definition MKV58F24.h:18395
RCM_Type
Definition MK60D10.h:8973
RFSYS_Type
Definition MK60D10.h:9084
RFVBAT_Type
Definition MK60D10.h:9145
SIM_Type
Definition MK60D10.h:10117
SMC_Type
Definition MK60D10.h:10560
SPI_Type
Definition MK60D10.h:10645
SYSMPU_Type
Definition MK60D10.h:10978
TRNG_Type
Definition MKV58F24.h:22876
UART_Type
Definition MK60D10.h:11447
WDOG_Type
Definition MK60D10.h:12726
XBARA_Type
Definition MKV58F24.h:24761
XBARB_Type
Definition MKV58F24.h:28683