mikroSDK Reference Manual
MK66F18.h
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1/*
2** ###################################################################
3** Processors: MK66FN2M0VLQ18
4** MK66FN2M0VMD18
5** MK66FX1M0VLQ18
6** MK66FX1M0VMD18
7**
8** Compilers: Keil ARM C/C++ Compiler
9** Freescale C/C++ for Embedded ARM
10** GNU C Compiler
11** IAR ANSI C/C++ Compiler for ARM
12** MCUXpresso Compiler
13**
14** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
15** Version: rev. 3.0, 2015-03-25
16** Build: b180801
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MK66F18
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2018 NXP
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: support@nxp.com
28**
29** Revisions:
30** - rev. 1.0 (2013-09-02)
31** Initial version.
32** - rev. 2.0 (2014-02-17)
33** Register accessor macros added to the memory map.
34** Symbols for Processor Expert memory map compatibility added to the memory map.
35** Startup file for gcc has been updated according to CMSIS 3.2.
36** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
37** Update according to reference manual rev. 2
38** - rev. 2.1 (2014-04-16)
39** Update of SystemInit() and SystemCoreClockUpdate() functions.
40** - rev. 2.2 (2014-10-14)
41** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
42** - rev. 2.3 (2014-11-20)
43** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
44** Update of SystemInit() to use 16MHz external crystal.
45** - rev. 2.4 (2015-02-19)
46** Renamed interrupt vector LLW to LLWU.
47** - rev. 3.0 (2015-03-25)
48** Registers updated according to the reference manual revision 1, March 2015
49**
50** ###################################################################
51*/
52
62#ifndef _MK66F18_H_
63#define _MK66F18_H_
67#define MCU_MEM_MAP_VERSION 0x0300U
69#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
70
79#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
88#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
89#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
98#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
107#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
108
109/* ----------------------------------------------------------------------------
110 -- Interrupt vector numbers
111 ---------------------------------------------------------------------------- */
112
119#define NUMBER_OF_INT_VECTORS 116
121typedef enum IRQn {
122 /* Auxiliary constants */
123 NotAvail_IRQn = -128,
125 /* Core interrupts */
126 NonMaskableInt_IRQn = -14,
127 HardFault_IRQn = -13,
128 MemoryManagement_IRQn = -12,
129 BusFault_IRQn = -11,
130 UsageFault_IRQn = -10,
131 SVCall_IRQn = -5,
132 DebugMonitor_IRQn = -4,
133 PendSV_IRQn = -2,
134 SysTick_IRQn = -1,
136 /* Device specific interrupts */
137 DMA0_DMA16_IRQn = 0,
138 DMA1_DMA17_IRQn = 1,
139 DMA2_DMA18_IRQn = 2,
140 DMA3_DMA19_IRQn = 3,
141 DMA4_DMA20_IRQn = 4,
142 DMA5_DMA21_IRQn = 5,
143 DMA6_DMA22_IRQn = 6,
144 DMA7_DMA23_IRQn = 7,
145 DMA8_DMA24_IRQn = 8,
146 DMA9_DMA25_IRQn = 9,
147 DMA10_DMA26_IRQn = 10,
148 DMA11_DMA27_IRQn = 11,
149 DMA12_DMA28_IRQn = 12,
150 DMA13_DMA29_IRQn = 13,
151 DMA14_DMA30_IRQn = 14,
152 DMA15_DMA31_IRQn = 15,
153 DMA_Error_IRQn = 16,
154 MCM_IRQn = 17,
155 FTFE_IRQn = 18,
156 Read_Collision_IRQn = 19,
157 LVD_LVW_IRQn = 20,
158 LLWU_IRQn = 21,
159 WDOG_EWM_IRQn = 22,
160 RNG_IRQn = 23,
161 I2C0_IRQn = 24,
162 I2C1_IRQn = 25,
163 SPI0_IRQn = 26,
164 SPI1_IRQn = 27,
165 I2S0_Tx_IRQn = 28,
166 I2S0_Rx_IRQn = 29,
167 Reserved46_IRQn = 30,
168 UART0_RX_TX_IRQn = 31,
169 UART0_ERR_IRQn = 32,
170 UART1_RX_TX_IRQn = 33,
171 UART1_ERR_IRQn = 34,
172 UART2_RX_TX_IRQn = 35,
173 UART2_ERR_IRQn = 36,
174 UART3_RX_TX_IRQn = 37,
175 UART3_ERR_IRQn = 38,
176 ADC0_IRQn = 39,
177 CMP0_IRQn = 40,
178 CMP1_IRQn = 41,
179 FTM0_IRQn = 42,
180 FTM1_IRQn = 43,
181 FTM2_IRQn = 44,
182 CMT_IRQn = 45,
183 RTC_IRQn = 46,
184 RTC_Seconds_IRQn = 47,
185 PIT0_IRQn = 48,
186 PIT1_IRQn = 49,
187 PIT2_IRQn = 50,
188 PIT3_IRQn = 51,
189 PDB0_IRQn = 52,
190 USB0_IRQn = 53,
191 USBDCD_IRQn = 54,
192 Reserved71_IRQn = 55,
193 DAC0_IRQn = 56,
194 MCG_IRQn = 57,
195 LPTMR0_IRQn = 58,
196 PORTA_IRQn = 59,
197 PORTB_IRQn = 60,
198 PORTC_IRQn = 61,
199 PORTD_IRQn = 62,
200 PORTE_IRQn = 63,
201 SWI_IRQn = 64,
202 SPI2_IRQn = 65,
203 UART4_RX_TX_IRQn = 66,
204 UART4_ERR_IRQn = 67,
205 Reserved84_IRQn = 68,
206 Reserved85_IRQn = 69,
207 CMP2_IRQn = 70,
208 FTM3_IRQn = 71,
209 DAC1_IRQn = 72,
210 ADC1_IRQn = 73,
211 I2C2_IRQn = 74,
212 CAN0_ORed_Message_buffer_IRQn = 75,
213 CAN0_Bus_Off_IRQn = 76,
214 CAN0_Error_IRQn = 77,
215 CAN0_Tx_Warning_IRQn = 78,
216 CAN0_Rx_Warning_IRQn = 79,
217 CAN0_Wake_Up_IRQn = 80,
218 SDHC_IRQn = 81,
219 ENET_1588_Timer_IRQn = 82,
220 ENET_Transmit_IRQn = 83,
221 ENET_Receive_IRQn = 84,
222 ENET_Error_IRQn = 85,
223 LPUART0_IRQn = 86,
224 TSI0_IRQn = 87,
225 TPM1_IRQn = 88,
226 TPM2_IRQn = 89,
227 USBHSDCD_IRQn = 90,
228 I2C3_IRQn = 91,
229 CMP3_IRQn = 92,
230 USBHS_IRQn = 93,
231 CAN1_ORed_Message_buffer_IRQn = 94,
232 CAN1_Bus_Off_IRQn = 95,
233 CAN1_Error_IRQn = 96,
234 CAN1_Tx_Warning_IRQn = 97,
235 CAN1_Rx_Warning_IRQn = 98,
236 CAN1_Wake_Up_IRQn = 99
237} IRQn_Type;
238
241 /* end of group Interrupt_vector_numbers */
242
243
244/* ----------------------------------------------------------------------------
245 -- Cortex M4 Core Configuration
246 ---------------------------------------------------------------------------- */
247
253#define __MPU_PRESENT 0
254#define __NVIC_PRIO_BITS 4
255#define __Vendor_SysTickConfig 0
256#define __FPU_PRESENT 1
258#include "core_cm4.h" /* Core Peripheral Access Layer */
259// Note: Added for MikroE implementation.
260#ifndef __PROJECT_MIKROSDK_MIKROE__
261#include "system_MK66F18.h" /* Device specific configuration file */
262#endif
263
266 /* end of group Cortex_Core_Configuration */
267
268
269/* ----------------------------------------------------------------------------
270 -- Mapping Information
271 ---------------------------------------------------------------------------- */
272
284/*******************************************************************************
285 * Definitions
286 ******************************************************************************/
287
295typedef enum _dma_request_source
296{
297 kDmaRequestMux0Disable = 0|0x100U,
298 kDmaRequestMux0TSI0 = 1|0x100U,
299 kDmaRequestMux0UART0Rx = 2|0x100U,
300 kDmaRequestMux0UART0Tx = 3|0x100U,
301 kDmaRequestMux0UART1Rx = 4|0x100U,
302 kDmaRequestMux0UART1Tx = 5|0x100U,
303 kDmaRequestMux0UART2Rx = 6|0x100U,
304 kDmaRequestMux0UART2Tx = 7|0x100U,
305 kDmaRequestMux0UART3Rx = 8|0x100U,
306 kDmaRequestMux0UART3Tx = 9|0x100U,
307 kDmaRequestMux0UART4 = 10|0x100U,
308 kDmaRequestMux0Reserved11 = 11|0x100U,
309 kDmaRequestMux0I2S0Rx = 12|0x100U,
310 kDmaRequestMux0I2S0Tx = 13|0x100U,
311 kDmaRequestMux0SPI0Rx = 14|0x100U,
312 kDmaRequestMux0SPI0Tx = 15|0x100U,
313 kDmaRequestMux0SPI1Rx = 16|0x100U,
314 kDmaRequestMux0SPI1Tx = 17|0x100U,
315 kDmaRequestMux0I2C0I2C3 = 18|0x100U,
316 kDmaRequestMux0I2C0 = 18|0x100U,
317 kDmaRequestMux0I2C3 = 18|0x100U,
318 kDmaRequestMux0I2C1I2C2 = 19|0x100U,
319 kDmaRequestMux0I2C1 = 19|0x100U,
320 kDmaRequestMux0I2C2 = 19|0x100U,
321 kDmaRequestMux0FTM0Channel0 = 20|0x100U,
322 kDmaRequestMux0FTM0Channel1 = 21|0x100U,
323 kDmaRequestMux0FTM0Channel2 = 22|0x100U,
324 kDmaRequestMux0FTM0Channel3 = 23|0x100U,
325 kDmaRequestMux0FTM0Channel4 = 24|0x100U,
326 kDmaRequestMux0FTM0Channel5 = 25|0x100U,
327 kDmaRequestMux0FTM0Channel6 = 26|0x100U,
328 kDmaRequestMux0FTM0Channel7 = 27|0x100U,
329 kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U,
330 kDmaRequestMux0FTM1Channel0 = 28|0x100U,
331 kDmaRequestMux0TPM1Channel0 = 28|0x100U,
332 kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U,
333 kDmaRequestMux0FTM1Channel1 = 29|0x100U,
334 kDmaRequestMux0TPM1Channel1 = 29|0x100U,
335 kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U,
336 kDmaRequestMux0FTM2Channel0 = 30|0x100U,
337 kDmaRequestMux0TPM2Channel0 = 30|0x100U,
338 kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U,
339 kDmaRequestMux0FTM2Channel1 = 31|0x100U,
340 kDmaRequestMux0TPM2Channel1 = 31|0x100U,
341 kDmaRequestMux0FTM3Channel0 = 32|0x100U,
342 kDmaRequestMux0FTM3Channel1 = 33|0x100U,
343 kDmaRequestMux0FTM3Channel2 = 34|0x100U,
344 kDmaRequestMux0FTM3Channel3 = 35|0x100U,
345 kDmaRequestMux0FTM3Channel4 = 36|0x100U,
346 kDmaRequestMux0FTM3Channel5 = 37|0x100U,
347 kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U,
348 kDmaRequestMux0FTM3Channel6 = 38|0x100U,
349 kDmaRequestMux0SPI2Rx = 38|0x100U,
350 kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U,
351 kDmaRequestMux0FTM3Channel7 = 39|0x100U,
352 kDmaRequestMux0SPI2Tx = 39|0x100U,
353 kDmaRequestMux0ADC0 = 40|0x100U,
354 kDmaRequestMux0ADC1 = 41|0x100U,
355 kDmaRequestMux0CMP0 = 42|0x100U,
356 kDmaRequestMux0CMP1 = 43|0x100U,
357 kDmaRequestMux0CMP2CMP3 = 44|0x100U,
358 kDmaRequestMux0CMP2 = 44|0x100U,
359 kDmaRequestMux0CMP3 = 44|0x100U,
360 kDmaRequestMux0DAC0 = 45|0x100U,
361 kDmaRequestMux0DAC1 = 46|0x100U,
362 kDmaRequestMux0CMT = 47|0x100U,
363 kDmaRequestMux0PDB = 48|0x100U,
364 kDmaRequestMux0PortA = 49|0x100U,
365 kDmaRequestMux0PortB = 50|0x100U,
366 kDmaRequestMux0PortC = 51|0x100U,
367 kDmaRequestMux0PortD = 52|0x100U,
368 kDmaRequestMux0PortE = 53|0x100U,
369 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U,
370 kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U,
371 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U,
372 kDmaRequestMux0TPM1Overflow = 55|0x100U,
373 kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U,
374 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U,
375 kDmaRequestMux0TPM2Overflow = 56|0x100U,
376 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U,
377 kDmaRequestMux0LPUART0Rx = 58|0x100U,
378 kDmaRequestMux0LPUART0Tx = 59|0x100U,
379 kDmaRequestMux0AlwaysOn60 = 60|0x100U,
380 kDmaRequestMux0AlwaysOn61 = 61|0x100U,
381 kDmaRequestMux0AlwaysOn62 = 62|0x100U,
382 kDmaRequestMux0AlwaysOn63 = 63|0x100U,
383} dma_request_source_t;
384
385/* @} */
386
387
390 /* end of group Mapping_Information */
391
392
393/* ----------------------------------------------------------------------------
394 -- Device Peripheral Access Layer
395 ---------------------------------------------------------------------------- */
396
403/*
404** Start of section using anonymous unions
405*/
406
407#if defined(__ARMCC_VERSION)
408 #if (__ARMCC_VERSION >= 6010050)
409 #pragma clang diagnostic push
410 #else
411 #pragma push
412 #pragma anon_unions
413 #endif
414#elif defined(__CWCC__)
415 #pragma push
416 #pragma cpp_extensions on
417#elif defined(__GNUC__)
418 /* anonymous unions are enabled by default */
419#elif defined(__IAR_SYSTEMS_ICC__)
420 #pragma language=extended
421#else
422 #error Not supported compiler type
423#endif
424
425/* ----------------------------------------------------------------------------
426 -- ADC Peripheral Access Layer
427 ---------------------------------------------------------------------------- */
428
435typedef struct {
436 __IO uint32_t SC1[2];
437 __IO uint32_t CFG1;
438 __IO uint32_t CFG2;
439 __I uint32_t R[2];
440 __IO uint32_t CV1;
441 __IO uint32_t CV2;
442 __IO uint32_t SC2;
443 __IO uint32_t SC3;
444 __IO uint32_t OFS;
445 __IO uint32_t PG;
446 __IO uint32_t MG;
447 __IO uint32_t CLPD;
448 __IO uint32_t CLPS;
449 __IO uint32_t CLP4;
450 __IO uint32_t CLP3;
451 __IO uint32_t CLP2;
452 __IO uint32_t CLP1;
453 __IO uint32_t CLP0;
454 uint8_t RESERVED_0[4];
455 __IO uint32_t CLMD;
456 __IO uint32_t CLMS;
457 __IO uint32_t CLM4;
458 __IO uint32_t CLM3;
459 __IO uint32_t CLM2;
460 __IO uint32_t CLM1;
461 __IO uint32_t CLM0;
462} ADC_Type;
463
464/* ----------------------------------------------------------------------------
465 -- ADC Register Masks
466 ---------------------------------------------------------------------------- */
467
475#define ADC_SC1_ADCH_MASK (0x1FU)
476#define ADC_SC1_ADCH_SHIFT (0U)
511#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
512#define ADC_SC1_DIFF_MASK (0x20U)
513#define ADC_SC1_DIFF_SHIFT (5U)
518#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
519#define ADC_SC1_AIEN_MASK (0x40U)
520#define ADC_SC1_AIEN_SHIFT (6U)
525#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
526#define ADC_SC1_COCO_MASK (0x80U)
527#define ADC_SC1_COCO_SHIFT (7U)
532#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
535/* The count of ADC_SC1 */
536#define ADC_SC1_COUNT (2U)
537
540#define ADC_CFG1_ADICLK_MASK (0x3U)
541#define ADC_CFG1_ADICLK_SHIFT (0U)
548#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
549#define ADC_CFG1_MODE_MASK (0xCU)
550#define ADC_CFG1_MODE_SHIFT (2U)
557#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
558#define ADC_CFG1_ADLSMP_MASK (0x10U)
559#define ADC_CFG1_ADLSMP_SHIFT (4U)
564#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
565#define ADC_CFG1_ADIV_MASK (0x60U)
566#define ADC_CFG1_ADIV_SHIFT (5U)
573#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
574#define ADC_CFG1_ADLPC_MASK (0x80U)
575#define ADC_CFG1_ADLPC_SHIFT (7U)
580#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
585#define ADC_CFG2_ADLSTS_MASK (0x3U)
586#define ADC_CFG2_ADLSTS_SHIFT (0U)
593#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
594#define ADC_CFG2_ADHSC_MASK (0x4U)
595#define ADC_CFG2_ADHSC_SHIFT (2U)
600#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
601#define ADC_CFG2_ADACKEN_MASK (0x8U)
602#define ADC_CFG2_ADACKEN_SHIFT (3U)
607#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
608#define ADC_CFG2_MUXSEL_MASK (0x10U)
609#define ADC_CFG2_MUXSEL_SHIFT (4U)
614#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
619#define ADC_R_D_MASK (0xFFFFU)
620#define ADC_R_D_SHIFT (0U)
621#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
624/* The count of ADC_R */
625#define ADC_R_COUNT (2U)
626
629#define ADC_CV1_CV_MASK (0xFFFFU)
630#define ADC_CV1_CV_SHIFT (0U)
631#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
636#define ADC_CV2_CV_MASK (0xFFFFU)
637#define ADC_CV2_CV_SHIFT (0U)
638#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
643#define ADC_SC2_REFSEL_MASK (0x3U)
644#define ADC_SC2_REFSEL_SHIFT (0U)
651#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
652#define ADC_SC2_DMAEN_MASK (0x4U)
653#define ADC_SC2_DMAEN_SHIFT (2U)
658#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
659#define ADC_SC2_ACREN_MASK (0x8U)
660#define ADC_SC2_ACREN_SHIFT (3U)
665#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
666#define ADC_SC2_ACFGT_MASK (0x10U)
667#define ADC_SC2_ACFGT_SHIFT (4U)
672#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
673#define ADC_SC2_ACFE_MASK (0x20U)
674#define ADC_SC2_ACFE_SHIFT (5U)
679#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
680#define ADC_SC2_ADTRG_MASK (0x40U)
681#define ADC_SC2_ADTRG_SHIFT (6U)
686#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
687#define ADC_SC2_ADACT_MASK (0x80U)
688#define ADC_SC2_ADACT_SHIFT (7U)
693#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
698#define ADC_SC3_AVGS_MASK (0x3U)
699#define ADC_SC3_AVGS_SHIFT (0U)
706#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
707#define ADC_SC3_AVGE_MASK (0x4U)
708#define ADC_SC3_AVGE_SHIFT (2U)
713#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
714#define ADC_SC3_ADCO_MASK (0x8U)
715#define ADC_SC3_ADCO_SHIFT (3U)
720#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
721#define ADC_SC3_CALF_MASK (0x40U)
722#define ADC_SC3_CALF_SHIFT (6U)
727#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
728#define ADC_SC3_CAL_MASK (0x80U)
729#define ADC_SC3_CAL_SHIFT (7U)
730#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
735#define ADC_OFS_OFS_MASK (0xFFFFU)
736#define ADC_OFS_OFS_SHIFT (0U)
737#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
742#define ADC_PG_PG_MASK (0xFFFFU)
743#define ADC_PG_PG_SHIFT (0U)
744#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
749#define ADC_MG_MG_MASK (0xFFFFU)
750#define ADC_MG_MG_SHIFT (0U)
751#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
756#define ADC_CLPD_CLPD_MASK (0x3FU)
757#define ADC_CLPD_CLPD_SHIFT (0U)
758#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
763#define ADC_CLPS_CLPS_MASK (0x3FU)
764#define ADC_CLPS_CLPS_SHIFT (0U)
765#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
770#define ADC_CLP4_CLP4_MASK (0x3FFU)
771#define ADC_CLP4_CLP4_SHIFT (0U)
772#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
777#define ADC_CLP3_CLP3_MASK (0x1FFU)
778#define ADC_CLP3_CLP3_SHIFT (0U)
779#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
784#define ADC_CLP2_CLP2_MASK (0xFFU)
785#define ADC_CLP2_CLP2_SHIFT (0U)
786#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
791#define ADC_CLP1_CLP1_MASK (0x7FU)
792#define ADC_CLP1_CLP1_SHIFT (0U)
793#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
798#define ADC_CLP0_CLP0_MASK (0x3FU)
799#define ADC_CLP0_CLP0_SHIFT (0U)
800#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
805#define ADC_CLMD_CLMD_MASK (0x3FU)
806#define ADC_CLMD_CLMD_SHIFT (0U)
807#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
812#define ADC_CLMS_CLMS_MASK (0x3FU)
813#define ADC_CLMS_CLMS_SHIFT (0U)
814#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
819#define ADC_CLM4_CLM4_MASK (0x3FFU)
820#define ADC_CLM4_CLM4_SHIFT (0U)
821#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
826#define ADC_CLM3_CLM3_MASK (0x1FFU)
827#define ADC_CLM3_CLM3_SHIFT (0U)
828#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
833#define ADC_CLM2_CLM2_MASK (0xFFU)
834#define ADC_CLM2_CLM2_SHIFT (0U)
835#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
840#define ADC_CLM1_CLM1_MASK (0x7FU)
841#define ADC_CLM1_CLM1_SHIFT (0U)
842#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
847#define ADC_CLM0_CLM0_MASK (0x3FU)
848#define ADC_CLM0_CLM0_SHIFT (0U)
849#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
855 /* end of group ADC_Register_Masks */
856
857
858/* ADC - Peripheral instance base addresses */
860#define ADC0_BASE (0x4003B000u)
862#define ADC0 ((ADC_Type *)ADC0_BASE)
864#define ADC1_BASE (0x400BB000u)
866#define ADC1 ((ADC_Type *)ADC1_BASE)
868#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
870#define ADC_BASE_PTRS { ADC0, ADC1 }
872#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
873
876 /* end of group ADC_Peripheral_Access_Layer */
877
878
879/* ----------------------------------------------------------------------------
880 -- AIPS Peripheral Access Layer
881 ---------------------------------------------------------------------------- */
882
889typedef struct {
890 __IO uint32_t MPRA;
891 uint8_t RESERVED_0[28];
892 __IO uint32_t PACRA;
893 __IO uint32_t PACRB;
894 __IO uint32_t PACRC;
895 __IO uint32_t PACRD;
896 uint8_t RESERVED_1[16];
897 __IO uint32_t PACRE;
898 __IO uint32_t PACRF;
899 __IO uint32_t PACRG;
900 __IO uint32_t PACRH;
901 __IO uint32_t PACRI;
902 __IO uint32_t PACRJ;
903 __IO uint32_t PACRK;
904 __IO uint32_t PACRL;
905 __IO uint32_t PACRM;
906 __IO uint32_t PACRN;
907 __IO uint32_t PACRO;
908 __IO uint32_t PACRP;
909} AIPS_Type;
910
911/* ----------------------------------------------------------------------------
912 -- AIPS Register Masks
913 ---------------------------------------------------------------------------- */
914
922#define AIPS_MPRA_MPL6_MASK (0x10U)
923#define AIPS_MPRA_MPL6_SHIFT (4U)
928#define AIPS_MPRA_MPL6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
929#define AIPS_MPRA_MTW6_MASK (0x20U)
930#define AIPS_MPRA_MTW6_SHIFT (5U)
935#define AIPS_MPRA_MTW6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
936#define AIPS_MPRA_MTR6_MASK (0x40U)
937#define AIPS_MPRA_MTR6_SHIFT (6U)
942#define AIPS_MPRA_MTR6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
943#define AIPS_MPRA_MPL5_MASK (0x100U)
944#define AIPS_MPRA_MPL5_SHIFT (8U)
949#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
950#define AIPS_MPRA_MTW5_MASK (0x200U)
951#define AIPS_MPRA_MTW5_SHIFT (9U)
956#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
957#define AIPS_MPRA_MTR5_MASK (0x400U)
958#define AIPS_MPRA_MTR5_SHIFT (10U)
963#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
964#define AIPS_MPRA_MPL4_MASK (0x1000U)
965#define AIPS_MPRA_MPL4_SHIFT (12U)
970#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
971#define AIPS_MPRA_MTW4_MASK (0x2000U)
972#define AIPS_MPRA_MTW4_SHIFT (13U)
977#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
978#define AIPS_MPRA_MTR4_MASK (0x4000U)
979#define AIPS_MPRA_MTR4_SHIFT (14U)
984#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
985#define AIPS_MPRA_MPL3_MASK (0x10000U)
986#define AIPS_MPRA_MPL3_SHIFT (16U)
991#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
992#define AIPS_MPRA_MTW3_MASK (0x20000U)
993#define AIPS_MPRA_MTW3_SHIFT (17U)
998#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
999#define AIPS_MPRA_MTR3_MASK (0x40000U)
1000#define AIPS_MPRA_MTR3_SHIFT (18U)
1005#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
1006#define AIPS_MPRA_MPL2_MASK (0x100000U)
1007#define AIPS_MPRA_MPL2_SHIFT (20U)
1012#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
1013#define AIPS_MPRA_MTW2_MASK (0x200000U)
1014#define AIPS_MPRA_MTW2_SHIFT (21U)
1019#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
1020#define AIPS_MPRA_MTR2_MASK (0x400000U)
1021#define AIPS_MPRA_MTR2_SHIFT (22U)
1026#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
1027#define AIPS_MPRA_MPL1_MASK (0x1000000U)
1028#define AIPS_MPRA_MPL1_SHIFT (24U)
1033#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1034#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1035#define AIPS_MPRA_MTW1_SHIFT (25U)
1040#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1041#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1042#define AIPS_MPRA_MTR1_SHIFT (26U)
1047#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1048#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1049#define AIPS_MPRA_MPL0_SHIFT (28U)
1054#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1055#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1056#define AIPS_MPRA_MTW0_SHIFT (29U)
1061#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1062#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1063#define AIPS_MPRA_MTR0_SHIFT (30U)
1068#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1073#define AIPS_PACRA_TP7_MASK (0x1U)
1074#define AIPS_PACRA_TP7_SHIFT (0U)
1079#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1080#define AIPS_PACRA_WP7_MASK (0x2U)
1081#define AIPS_PACRA_WP7_SHIFT (1U)
1086#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1087#define AIPS_PACRA_SP7_MASK (0x4U)
1088#define AIPS_PACRA_SP7_SHIFT (2U)
1093#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1094#define AIPS_PACRA_TP6_MASK (0x10U)
1095#define AIPS_PACRA_TP6_SHIFT (4U)
1100#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1101#define AIPS_PACRA_WP6_MASK (0x20U)
1102#define AIPS_PACRA_WP6_SHIFT (5U)
1107#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1108#define AIPS_PACRA_SP6_MASK (0x40U)
1109#define AIPS_PACRA_SP6_SHIFT (6U)
1114#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1115#define AIPS_PACRA_TP5_MASK (0x100U)
1116#define AIPS_PACRA_TP5_SHIFT (8U)
1121#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1122#define AIPS_PACRA_WP5_MASK (0x200U)
1123#define AIPS_PACRA_WP5_SHIFT (9U)
1128#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1129#define AIPS_PACRA_SP5_MASK (0x400U)
1130#define AIPS_PACRA_SP5_SHIFT (10U)
1135#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1136#define AIPS_PACRA_TP4_MASK (0x1000U)
1137#define AIPS_PACRA_TP4_SHIFT (12U)
1142#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1143#define AIPS_PACRA_WP4_MASK (0x2000U)
1144#define AIPS_PACRA_WP4_SHIFT (13U)
1149#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1150#define AIPS_PACRA_SP4_MASK (0x4000U)
1151#define AIPS_PACRA_SP4_SHIFT (14U)
1156#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1157#define AIPS_PACRA_TP3_MASK (0x10000U)
1158#define AIPS_PACRA_TP3_SHIFT (16U)
1163#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1164#define AIPS_PACRA_WP3_MASK (0x20000U)
1165#define AIPS_PACRA_WP3_SHIFT (17U)
1170#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1171#define AIPS_PACRA_SP3_MASK (0x40000U)
1172#define AIPS_PACRA_SP3_SHIFT (18U)
1177#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1178#define AIPS_PACRA_TP2_MASK (0x100000U)
1179#define AIPS_PACRA_TP2_SHIFT (20U)
1184#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1185#define AIPS_PACRA_WP2_MASK (0x200000U)
1186#define AIPS_PACRA_WP2_SHIFT (21U)
1191#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1192#define AIPS_PACRA_SP2_MASK (0x400000U)
1193#define AIPS_PACRA_SP2_SHIFT (22U)
1198#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1199#define AIPS_PACRA_TP1_MASK (0x1000000U)
1200#define AIPS_PACRA_TP1_SHIFT (24U)
1205#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1206#define AIPS_PACRA_WP1_MASK (0x2000000U)
1207#define AIPS_PACRA_WP1_SHIFT (25U)
1212#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1213#define AIPS_PACRA_SP1_MASK (0x4000000U)
1214#define AIPS_PACRA_SP1_SHIFT (26U)
1219#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1220#define AIPS_PACRA_TP0_MASK (0x10000000U)
1221#define AIPS_PACRA_TP0_SHIFT (28U)
1226#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1227#define AIPS_PACRA_WP0_MASK (0x20000000U)
1228#define AIPS_PACRA_WP0_SHIFT (29U)
1233#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1234#define AIPS_PACRA_SP0_MASK (0x40000000U)
1235#define AIPS_PACRA_SP0_SHIFT (30U)
1240#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1245#define AIPS_PACRB_TP7_MASK (0x1U)
1246#define AIPS_PACRB_TP7_SHIFT (0U)
1251#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1252#define AIPS_PACRB_WP7_MASK (0x2U)
1253#define AIPS_PACRB_WP7_SHIFT (1U)
1258#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1259#define AIPS_PACRB_SP7_MASK (0x4U)
1260#define AIPS_PACRB_SP7_SHIFT (2U)
1265#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1266#define AIPS_PACRB_TP6_MASK (0x10U)
1267#define AIPS_PACRB_TP6_SHIFT (4U)
1272#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1273#define AIPS_PACRB_WP6_MASK (0x20U)
1274#define AIPS_PACRB_WP6_SHIFT (5U)
1279#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1280#define AIPS_PACRB_SP6_MASK (0x40U)
1281#define AIPS_PACRB_SP6_SHIFT (6U)
1286#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1287#define AIPS_PACRB_TP5_MASK (0x100U)
1288#define AIPS_PACRB_TP5_SHIFT (8U)
1293#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1294#define AIPS_PACRB_WP5_MASK (0x200U)
1295#define AIPS_PACRB_WP5_SHIFT (9U)
1300#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1301#define AIPS_PACRB_SP5_MASK (0x400U)
1302#define AIPS_PACRB_SP5_SHIFT (10U)
1307#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1308#define AIPS_PACRB_TP4_MASK (0x1000U)
1309#define AIPS_PACRB_TP4_SHIFT (12U)
1314#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1315#define AIPS_PACRB_WP4_MASK (0x2000U)
1316#define AIPS_PACRB_WP4_SHIFT (13U)
1321#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1322#define AIPS_PACRB_SP4_MASK (0x4000U)
1323#define AIPS_PACRB_SP4_SHIFT (14U)
1328#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1329#define AIPS_PACRB_TP3_MASK (0x10000U)
1330#define AIPS_PACRB_TP3_SHIFT (16U)
1335#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1336#define AIPS_PACRB_WP3_MASK (0x20000U)
1337#define AIPS_PACRB_WP3_SHIFT (17U)
1342#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1343#define AIPS_PACRB_SP3_MASK (0x40000U)
1344#define AIPS_PACRB_SP3_SHIFT (18U)
1349#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1350#define AIPS_PACRB_TP2_MASK (0x100000U)
1351#define AIPS_PACRB_TP2_SHIFT (20U)
1356#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1357#define AIPS_PACRB_WP2_MASK (0x200000U)
1358#define AIPS_PACRB_WP2_SHIFT (21U)
1363#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1364#define AIPS_PACRB_SP2_MASK (0x400000U)
1365#define AIPS_PACRB_SP2_SHIFT (22U)
1370#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1371#define AIPS_PACRB_TP1_MASK (0x1000000U)
1372#define AIPS_PACRB_TP1_SHIFT (24U)
1377#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1378#define AIPS_PACRB_WP1_MASK (0x2000000U)
1379#define AIPS_PACRB_WP1_SHIFT (25U)
1384#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1385#define AIPS_PACRB_SP1_MASK (0x4000000U)
1386#define AIPS_PACRB_SP1_SHIFT (26U)
1391#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1392#define AIPS_PACRB_TP0_MASK (0x10000000U)
1393#define AIPS_PACRB_TP0_SHIFT (28U)
1398#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1399#define AIPS_PACRB_WP0_MASK (0x20000000U)
1400#define AIPS_PACRB_WP0_SHIFT (29U)
1405#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1406#define AIPS_PACRB_SP0_MASK (0x40000000U)
1407#define AIPS_PACRB_SP0_SHIFT (30U)
1412#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1417#define AIPS_PACRC_TP7_MASK (0x1U)
1418#define AIPS_PACRC_TP7_SHIFT (0U)
1423#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1424#define AIPS_PACRC_WP7_MASK (0x2U)
1425#define AIPS_PACRC_WP7_SHIFT (1U)
1430#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1431#define AIPS_PACRC_SP7_MASK (0x4U)
1432#define AIPS_PACRC_SP7_SHIFT (2U)
1437#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1438#define AIPS_PACRC_TP6_MASK (0x10U)
1439#define AIPS_PACRC_TP6_SHIFT (4U)
1444#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1445#define AIPS_PACRC_WP6_MASK (0x20U)
1446#define AIPS_PACRC_WP6_SHIFT (5U)
1451#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1452#define AIPS_PACRC_SP6_MASK (0x40U)
1453#define AIPS_PACRC_SP6_SHIFT (6U)
1458#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1459#define AIPS_PACRC_TP5_MASK (0x100U)
1460#define AIPS_PACRC_TP5_SHIFT (8U)
1465#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1466#define AIPS_PACRC_WP5_MASK (0x200U)
1467#define AIPS_PACRC_WP5_SHIFT (9U)
1472#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1473#define AIPS_PACRC_SP5_MASK (0x400U)
1474#define AIPS_PACRC_SP5_SHIFT (10U)
1479#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1480#define AIPS_PACRC_TP4_MASK (0x1000U)
1481#define AIPS_PACRC_TP4_SHIFT (12U)
1486#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1487#define AIPS_PACRC_WP4_MASK (0x2000U)
1488#define AIPS_PACRC_WP4_SHIFT (13U)
1493#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1494#define AIPS_PACRC_SP4_MASK (0x4000U)
1495#define AIPS_PACRC_SP4_SHIFT (14U)
1500#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1501#define AIPS_PACRC_TP3_MASK (0x10000U)
1502#define AIPS_PACRC_TP3_SHIFT (16U)
1507#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1508#define AIPS_PACRC_WP3_MASK (0x20000U)
1509#define AIPS_PACRC_WP3_SHIFT (17U)
1514#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1515#define AIPS_PACRC_SP3_MASK (0x40000U)
1516#define AIPS_PACRC_SP3_SHIFT (18U)
1521#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1522#define AIPS_PACRC_TP2_MASK (0x100000U)
1523#define AIPS_PACRC_TP2_SHIFT (20U)
1528#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1529#define AIPS_PACRC_WP2_MASK (0x200000U)
1530#define AIPS_PACRC_WP2_SHIFT (21U)
1535#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1536#define AIPS_PACRC_SP2_MASK (0x400000U)
1537#define AIPS_PACRC_SP2_SHIFT (22U)
1542#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1543#define AIPS_PACRC_TP1_MASK (0x1000000U)
1544#define AIPS_PACRC_TP1_SHIFT (24U)
1549#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1550#define AIPS_PACRC_WP1_MASK (0x2000000U)
1551#define AIPS_PACRC_WP1_SHIFT (25U)
1556#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1557#define AIPS_PACRC_SP1_MASK (0x4000000U)
1558#define AIPS_PACRC_SP1_SHIFT (26U)
1563#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1564#define AIPS_PACRC_TP0_MASK (0x10000000U)
1565#define AIPS_PACRC_TP0_SHIFT (28U)
1570#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1571#define AIPS_PACRC_WP0_MASK (0x20000000U)
1572#define AIPS_PACRC_WP0_SHIFT (29U)
1577#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1578#define AIPS_PACRC_SP0_MASK (0x40000000U)
1579#define AIPS_PACRC_SP0_SHIFT (30U)
1584#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1589#define AIPS_PACRD_TP7_MASK (0x1U)
1590#define AIPS_PACRD_TP7_SHIFT (0U)
1595#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1596#define AIPS_PACRD_WP7_MASK (0x2U)
1597#define AIPS_PACRD_WP7_SHIFT (1U)
1602#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1603#define AIPS_PACRD_SP7_MASK (0x4U)
1604#define AIPS_PACRD_SP7_SHIFT (2U)
1609#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1610#define AIPS_PACRD_TP6_MASK (0x10U)
1611#define AIPS_PACRD_TP6_SHIFT (4U)
1616#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1617#define AIPS_PACRD_WP6_MASK (0x20U)
1618#define AIPS_PACRD_WP6_SHIFT (5U)
1623#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1624#define AIPS_PACRD_SP6_MASK (0x40U)
1625#define AIPS_PACRD_SP6_SHIFT (6U)
1630#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1631#define AIPS_PACRD_TP5_MASK (0x100U)
1632#define AIPS_PACRD_TP5_SHIFT (8U)
1637#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1638#define AIPS_PACRD_WP5_MASK (0x200U)
1639#define AIPS_PACRD_WP5_SHIFT (9U)
1644#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1645#define AIPS_PACRD_SP5_MASK (0x400U)
1646#define AIPS_PACRD_SP5_SHIFT (10U)
1651#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1652#define AIPS_PACRD_TP4_MASK (0x1000U)
1653#define AIPS_PACRD_TP4_SHIFT (12U)
1658#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1659#define AIPS_PACRD_WP4_MASK (0x2000U)
1660#define AIPS_PACRD_WP4_SHIFT (13U)
1665#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1666#define AIPS_PACRD_SP4_MASK (0x4000U)
1667#define AIPS_PACRD_SP4_SHIFT (14U)
1672#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1673#define AIPS_PACRD_TP3_MASK (0x10000U)
1674#define AIPS_PACRD_TP3_SHIFT (16U)
1679#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1680#define AIPS_PACRD_WP3_MASK (0x20000U)
1681#define AIPS_PACRD_WP3_SHIFT (17U)
1686#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1687#define AIPS_PACRD_SP3_MASK (0x40000U)
1688#define AIPS_PACRD_SP3_SHIFT (18U)
1693#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1694#define AIPS_PACRD_TP2_MASK (0x100000U)
1695#define AIPS_PACRD_TP2_SHIFT (20U)
1700#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1701#define AIPS_PACRD_WP2_MASK (0x200000U)
1702#define AIPS_PACRD_WP2_SHIFT (21U)
1707#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1708#define AIPS_PACRD_SP2_MASK (0x400000U)
1709#define AIPS_PACRD_SP2_SHIFT (22U)
1714#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1715#define AIPS_PACRD_TP1_MASK (0x1000000U)
1716#define AIPS_PACRD_TP1_SHIFT (24U)
1721#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1722#define AIPS_PACRD_WP1_MASK (0x2000000U)
1723#define AIPS_PACRD_WP1_SHIFT (25U)
1728#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1729#define AIPS_PACRD_SP1_MASK (0x4000000U)
1730#define AIPS_PACRD_SP1_SHIFT (26U)
1735#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1736#define AIPS_PACRD_TP0_MASK (0x10000000U)
1737#define AIPS_PACRD_TP0_SHIFT (28U)
1742#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1743#define AIPS_PACRD_WP0_MASK (0x20000000U)
1744#define AIPS_PACRD_WP0_SHIFT (29U)
1749#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1750#define AIPS_PACRD_SP0_MASK (0x40000000U)
1751#define AIPS_PACRD_SP0_SHIFT (30U)
1756#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1761#define AIPS_PACRE_TP7_MASK (0x1U)
1762#define AIPS_PACRE_TP7_SHIFT (0U)
1767#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1768#define AIPS_PACRE_WP7_MASK (0x2U)
1769#define AIPS_PACRE_WP7_SHIFT (1U)
1774#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1775#define AIPS_PACRE_SP7_MASK (0x4U)
1776#define AIPS_PACRE_SP7_SHIFT (2U)
1781#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1782#define AIPS_PACRE_TP6_MASK (0x10U)
1783#define AIPS_PACRE_TP6_SHIFT (4U)
1788#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1789#define AIPS_PACRE_WP6_MASK (0x20U)
1790#define AIPS_PACRE_WP6_SHIFT (5U)
1795#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1796#define AIPS_PACRE_SP6_MASK (0x40U)
1797#define AIPS_PACRE_SP6_SHIFT (6U)
1802#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1803#define AIPS_PACRE_TP5_MASK (0x100U)
1804#define AIPS_PACRE_TP5_SHIFT (8U)
1809#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1810#define AIPS_PACRE_WP5_MASK (0x200U)
1811#define AIPS_PACRE_WP5_SHIFT (9U)
1816#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1817#define AIPS_PACRE_SP5_MASK (0x400U)
1818#define AIPS_PACRE_SP5_SHIFT (10U)
1823#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1824#define AIPS_PACRE_TP4_MASK (0x1000U)
1825#define AIPS_PACRE_TP4_SHIFT (12U)
1830#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1831#define AIPS_PACRE_WP4_MASK (0x2000U)
1832#define AIPS_PACRE_WP4_SHIFT (13U)
1837#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1838#define AIPS_PACRE_SP4_MASK (0x4000U)
1839#define AIPS_PACRE_SP4_SHIFT (14U)
1844#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1845#define AIPS_PACRE_TP3_MASK (0x10000U)
1846#define AIPS_PACRE_TP3_SHIFT (16U)
1851#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1852#define AIPS_PACRE_WP3_MASK (0x20000U)
1853#define AIPS_PACRE_WP3_SHIFT (17U)
1858#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1859#define AIPS_PACRE_SP3_MASK (0x40000U)
1860#define AIPS_PACRE_SP3_SHIFT (18U)
1865#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1866#define AIPS_PACRE_TP2_MASK (0x100000U)
1867#define AIPS_PACRE_TP2_SHIFT (20U)
1872#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1873#define AIPS_PACRE_WP2_MASK (0x200000U)
1874#define AIPS_PACRE_WP2_SHIFT (21U)
1879#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1880#define AIPS_PACRE_SP2_MASK (0x400000U)
1881#define AIPS_PACRE_SP2_SHIFT (22U)
1886#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1887#define AIPS_PACRE_TP1_MASK (0x1000000U)
1888#define AIPS_PACRE_TP1_SHIFT (24U)
1893#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1894#define AIPS_PACRE_WP1_MASK (0x2000000U)
1895#define AIPS_PACRE_WP1_SHIFT (25U)
1900#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1901#define AIPS_PACRE_SP1_MASK (0x4000000U)
1902#define AIPS_PACRE_SP1_SHIFT (26U)
1907#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1908#define AIPS_PACRE_TP0_MASK (0x10000000U)
1909#define AIPS_PACRE_TP0_SHIFT (28U)
1914#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1915#define AIPS_PACRE_WP0_MASK (0x20000000U)
1916#define AIPS_PACRE_WP0_SHIFT (29U)
1921#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1922#define AIPS_PACRE_SP0_MASK (0x40000000U)
1923#define AIPS_PACRE_SP0_SHIFT (30U)
1928#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1933#define AIPS_PACRF_TP7_MASK (0x1U)
1934#define AIPS_PACRF_TP7_SHIFT (0U)
1939#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1940#define AIPS_PACRF_WP7_MASK (0x2U)
1941#define AIPS_PACRF_WP7_SHIFT (1U)
1946#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1947#define AIPS_PACRF_SP7_MASK (0x4U)
1948#define AIPS_PACRF_SP7_SHIFT (2U)
1953#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1954#define AIPS_PACRF_TP6_MASK (0x10U)
1955#define AIPS_PACRF_TP6_SHIFT (4U)
1960#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1961#define AIPS_PACRF_WP6_MASK (0x20U)
1962#define AIPS_PACRF_WP6_SHIFT (5U)
1967#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1968#define AIPS_PACRF_SP6_MASK (0x40U)
1969#define AIPS_PACRF_SP6_SHIFT (6U)
1974#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1975#define AIPS_PACRF_TP5_MASK (0x100U)
1976#define AIPS_PACRF_TP5_SHIFT (8U)
1981#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1982#define AIPS_PACRF_WP5_MASK (0x200U)
1983#define AIPS_PACRF_WP5_SHIFT (9U)
1988#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1989#define AIPS_PACRF_SP5_MASK (0x400U)
1990#define AIPS_PACRF_SP5_SHIFT (10U)
1995#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1996#define AIPS_PACRF_TP4_MASK (0x1000U)
1997#define AIPS_PACRF_TP4_SHIFT (12U)
2002#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
2003#define AIPS_PACRF_WP4_MASK (0x2000U)
2004#define AIPS_PACRF_WP4_SHIFT (13U)
2009#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
2010#define AIPS_PACRF_SP4_MASK (0x4000U)
2011#define AIPS_PACRF_SP4_SHIFT (14U)
2016#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
2017#define AIPS_PACRF_TP3_MASK (0x10000U)
2018#define AIPS_PACRF_TP3_SHIFT (16U)
2023#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
2024#define AIPS_PACRF_WP3_MASK (0x20000U)
2025#define AIPS_PACRF_WP3_SHIFT (17U)
2030#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
2031#define AIPS_PACRF_SP3_MASK (0x40000U)
2032#define AIPS_PACRF_SP3_SHIFT (18U)
2037#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2038#define AIPS_PACRF_TP2_MASK (0x100000U)
2039#define AIPS_PACRF_TP2_SHIFT (20U)
2044#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2045#define AIPS_PACRF_WP2_MASK (0x200000U)
2046#define AIPS_PACRF_WP2_SHIFT (21U)
2051#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2052#define AIPS_PACRF_SP2_MASK (0x400000U)
2053#define AIPS_PACRF_SP2_SHIFT (22U)
2058#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2059#define AIPS_PACRF_TP1_MASK (0x1000000U)
2060#define AIPS_PACRF_TP1_SHIFT (24U)
2065#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2066#define AIPS_PACRF_WP1_MASK (0x2000000U)
2067#define AIPS_PACRF_WP1_SHIFT (25U)
2072#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2073#define AIPS_PACRF_SP1_MASK (0x4000000U)
2074#define AIPS_PACRF_SP1_SHIFT (26U)
2079#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2080#define AIPS_PACRF_TP0_MASK (0x10000000U)
2081#define AIPS_PACRF_TP0_SHIFT (28U)
2086#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2087#define AIPS_PACRF_WP0_MASK (0x20000000U)
2088#define AIPS_PACRF_WP0_SHIFT (29U)
2093#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2094#define AIPS_PACRF_SP0_MASK (0x40000000U)
2095#define AIPS_PACRF_SP0_SHIFT (30U)
2100#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2105#define AIPS_PACRG_TP7_MASK (0x1U)
2106#define AIPS_PACRG_TP7_SHIFT (0U)
2111#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2112#define AIPS_PACRG_WP7_MASK (0x2U)
2113#define AIPS_PACRG_WP7_SHIFT (1U)
2118#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2119#define AIPS_PACRG_SP7_MASK (0x4U)
2120#define AIPS_PACRG_SP7_SHIFT (2U)
2125#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2126#define AIPS_PACRG_TP6_MASK (0x10U)
2127#define AIPS_PACRG_TP6_SHIFT (4U)
2132#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2133#define AIPS_PACRG_WP6_MASK (0x20U)
2134#define AIPS_PACRG_WP6_SHIFT (5U)
2139#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2140#define AIPS_PACRG_SP6_MASK (0x40U)
2141#define AIPS_PACRG_SP6_SHIFT (6U)
2146#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2147#define AIPS_PACRG_TP5_MASK (0x100U)
2148#define AIPS_PACRG_TP5_SHIFT (8U)
2153#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2154#define AIPS_PACRG_WP5_MASK (0x200U)
2155#define AIPS_PACRG_WP5_SHIFT (9U)
2160#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2161#define AIPS_PACRG_SP5_MASK (0x400U)
2162#define AIPS_PACRG_SP5_SHIFT (10U)
2167#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2168#define AIPS_PACRG_TP4_MASK (0x1000U)
2169#define AIPS_PACRG_TP4_SHIFT (12U)
2174#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2175#define AIPS_PACRG_WP4_MASK (0x2000U)
2176#define AIPS_PACRG_WP4_SHIFT (13U)
2181#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2182#define AIPS_PACRG_SP4_MASK (0x4000U)
2183#define AIPS_PACRG_SP4_SHIFT (14U)
2188#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2189#define AIPS_PACRG_TP3_MASK (0x10000U)
2190#define AIPS_PACRG_TP3_SHIFT (16U)
2195#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2196#define AIPS_PACRG_WP3_MASK (0x20000U)
2197#define AIPS_PACRG_WP3_SHIFT (17U)
2202#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2203#define AIPS_PACRG_SP3_MASK (0x40000U)
2204#define AIPS_PACRG_SP3_SHIFT (18U)
2209#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2210#define AIPS_PACRG_TP2_MASK (0x100000U)
2211#define AIPS_PACRG_TP2_SHIFT (20U)
2216#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2217#define AIPS_PACRG_WP2_MASK (0x200000U)
2218#define AIPS_PACRG_WP2_SHIFT (21U)
2223#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2224#define AIPS_PACRG_SP2_MASK (0x400000U)
2225#define AIPS_PACRG_SP2_SHIFT (22U)
2230#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2231#define AIPS_PACRG_TP1_MASK (0x1000000U)
2232#define AIPS_PACRG_TP1_SHIFT (24U)
2237#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2238#define AIPS_PACRG_WP1_MASK (0x2000000U)
2239#define AIPS_PACRG_WP1_SHIFT (25U)
2244#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2245#define AIPS_PACRG_SP1_MASK (0x4000000U)
2246#define AIPS_PACRG_SP1_SHIFT (26U)
2251#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2252#define AIPS_PACRG_TP0_MASK (0x10000000U)
2253#define AIPS_PACRG_TP0_SHIFT (28U)
2258#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2259#define AIPS_PACRG_WP0_MASK (0x20000000U)
2260#define AIPS_PACRG_WP0_SHIFT (29U)
2265#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2266#define AIPS_PACRG_SP0_MASK (0x40000000U)
2267#define AIPS_PACRG_SP0_SHIFT (30U)
2272#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2277#define AIPS_PACRH_TP7_MASK (0x1U)
2278#define AIPS_PACRH_TP7_SHIFT (0U)
2283#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2284#define AIPS_PACRH_WP7_MASK (0x2U)
2285#define AIPS_PACRH_WP7_SHIFT (1U)
2290#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2291#define AIPS_PACRH_SP7_MASK (0x4U)
2292#define AIPS_PACRH_SP7_SHIFT (2U)
2297#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2298#define AIPS_PACRH_TP6_MASK (0x10U)
2299#define AIPS_PACRH_TP6_SHIFT (4U)
2304#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2305#define AIPS_PACRH_WP6_MASK (0x20U)
2306#define AIPS_PACRH_WP6_SHIFT (5U)
2311#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2312#define AIPS_PACRH_SP6_MASK (0x40U)
2313#define AIPS_PACRH_SP6_SHIFT (6U)
2318#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2319#define AIPS_PACRH_TP5_MASK (0x100U)
2320#define AIPS_PACRH_TP5_SHIFT (8U)
2325#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2326#define AIPS_PACRH_WP5_MASK (0x200U)
2327#define AIPS_PACRH_WP5_SHIFT (9U)
2332#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2333#define AIPS_PACRH_SP5_MASK (0x400U)
2334#define AIPS_PACRH_SP5_SHIFT (10U)
2339#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2340#define AIPS_PACRH_TP4_MASK (0x1000U)
2341#define AIPS_PACRH_TP4_SHIFT (12U)
2346#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2347#define AIPS_PACRH_WP4_MASK (0x2000U)
2348#define AIPS_PACRH_WP4_SHIFT (13U)
2353#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2354#define AIPS_PACRH_SP4_MASK (0x4000U)
2355#define AIPS_PACRH_SP4_SHIFT (14U)
2360#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2361#define AIPS_PACRH_TP3_MASK (0x10000U)
2362#define AIPS_PACRH_TP3_SHIFT (16U)
2367#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2368#define AIPS_PACRH_WP3_MASK (0x20000U)
2369#define AIPS_PACRH_WP3_SHIFT (17U)
2374#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2375#define AIPS_PACRH_SP3_MASK (0x40000U)
2376#define AIPS_PACRH_SP3_SHIFT (18U)
2381#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2382#define AIPS_PACRH_TP2_MASK (0x100000U)
2383#define AIPS_PACRH_TP2_SHIFT (20U)
2388#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2389#define AIPS_PACRH_WP2_MASK (0x200000U)
2390#define AIPS_PACRH_WP2_SHIFT (21U)
2395#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2396#define AIPS_PACRH_SP2_MASK (0x400000U)
2397#define AIPS_PACRH_SP2_SHIFT (22U)
2402#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2403#define AIPS_PACRH_TP1_MASK (0x1000000U)
2404#define AIPS_PACRH_TP1_SHIFT (24U)
2409#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2410#define AIPS_PACRH_WP1_MASK (0x2000000U)
2411#define AIPS_PACRH_WP1_SHIFT (25U)
2416#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2417#define AIPS_PACRH_SP1_MASK (0x4000000U)
2418#define AIPS_PACRH_SP1_SHIFT (26U)
2423#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2424#define AIPS_PACRH_TP0_MASK (0x10000000U)
2425#define AIPS_PACRH_TP0_SHIFT (28U)
2430#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2431#define AIPS_PACRH_WP0_MASK (0x20000000U)
2432#define AIPS_PACRH_WP0_SHIFT (29U)
2437#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2438#define AIPS_PACRH_SP0_MASK (0x40000000U)
2439#define AIPS_PACRH_SP0_SHIFT (30U)
2444#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2449#define AIPS_PACRI_TP7_MASK (0x1U)
2450#define AIPS_PACRI_TP7_SHIFT (0U)
2455#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2456#define AIPS_PACRI_WP7_MASK (0x2U)
2457#define AIPS_PACRI_WP7_SHIFT (1U)
2462#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2463#define AIPS_PACRI_SP7_MASK (0x4U)
2464#define AIPS_PACRI_SP7_SHIFT (2U)
2469#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2470#define AIPS_PACRI_TP6_MASK (0x10U)
2471#define AIPS_PACRI_TP6_SHIFT (4U)
2476#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2477#define AIPS_PACRI_WP6_MASK (0x20U)
2478#define AIPS_PACRI_WP6_SHIFT (5U)
2483#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2484#define AIPS_PACRI_SP6_MASK (0x40U)
2485#define AIPS_PACRI_SP6_SHIFT (6U)
2490#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2491#define AIPS_PACRI_TP5_MASK (0x100U)
2492#define AIPS_PACRI_TP5_SHIFT (8U)
2497#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2498#define AIPS_PACRI_WP5_MASK (0x200U)
2499#define AIPS_PACRI_WP5_SHIFT (9U)
2504#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2505#define AIPS_PACRI_SP5_MASK (0x400U)
2506#define AIPS_PACRI_SP5_SHIFT (10U)
2511#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2512#define AIPS_PACRI_TP4_MASK (0x1000U)
2513#define AIPS_PACRI_TP4_SHIFT (12U)
2518#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2519#define AIPS_PACRI_WP4_MASK (0x2000U)
2520#define AIPS_PACRI_WP4_SHIFT (13U)
2525#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2526#define AIPS_PACRI_SP4_MASK (0x4000U)
2527#define AIPS_PACRI_SP4_SHIFT (14U)
2532#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2533#define AIPS_PACRI_TP3_MASK (0x10000U)
2534#define AIPS_PACRI_TP3_SHIFT (16U)
2539#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2540#define AIPS_PACRI_WP3_MASK (0x20000U)
2541#define AIPS_PACRI_WP3_SHIFT (17U)
2546#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2547#define AIPS_PACRI_SP3_MASK (0x40000U)
2548#define AIPS_PACRI_SP3_SHIFT (18U)
2553#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2554#define AIPS_PACRI_TP2_MASK (0x100000U)
2555#define AIPS_PACRI_TP2_SHIFT (20U)
2560#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2561#define AIPS_PACRI_WP2_MASK (0x200000U)
2562#define AIPS_PACRI_WP2_SHIFT (21U)
2567#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2568#define AIPS_PACRI_SP2_MASK (0x400000U)
2569#define AIPS_PACRI_SP2_SHIFT (22U)
2574#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2575#define AIPS_PACRI_TP1_MASK (0x1000000U)
2576#define AIPS_PACRI_TP1_SHIFT (24U)
2581#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2582#define AIPS_PACRI_WP1_MASK (0x2000000U)
2583#define AIPS_PACRI_WP1_SHIFT (25U)
2588#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2589#define AIPS_PACRI_SP1_MASK (0x4000000U)
2590#define AIPS_PACRI_SP1_SHIFT (26U)
2595#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2596#define AIPS_PACRI_TP0_MASK (0x10000000U)
2597#define AIPS_PACRI_TP0_SHIFT (28U)
2602#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2603#define AIPS_PACRI_WP0_MASK (0x20000000U)
2604#define AIPS_PACRI_WP0_SHIFT (29U)
2609#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2610#define AIPS_PACRI_SP0_MASK (0x40000000U)
2611#define AIPS_PACRI_SP0_SHIFT (30U)
2616#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2621#define AIPS_PACRJ_TP7_MASK (0x1U)
2622#define AIPS_PACRJ_TP7_SHIFT (0U)
2627#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2628#define AIPS_PACRJ_WP7_MASK (0x2U)
2629#define AIPS_PACRJ_WP7_SHIFT (1U)
2634#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2635#define AIPS_PACRJ_SP7_MASK (0x4U)
2636#define AIPS_PACRJ_SP7_SHIFT (2U)
2641#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2642#define AIPS_PACRJ_TP6_MASK (0x10U)
2643#define AIPS_PACRJ_TP6_SHIFT (4U)
2648#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2649#define AIPS_PACRJ_WP6_MASK (0x20U)
2650#define AIPS_PACRJ_WP6_SHIFT (5U)
2655#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2656#define AIPS_PACRJ_SP6_MASK (0x40U)
2657#define AIPS_PACRJ_SP6_SHIFT (6U)
2662#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2663#define AIPS_PACRJ_TP5_MASK (0x100U)
2664#define AIPS_PACRJ_TP5_SHIFT (8U)
2669#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2670#define AIPS_PACRJ_WP5_MASK (0x200U)
2671#define AIPS_PACRJ_WP5_SHIFT (9U)
2676#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2677#define AIPS_PACRJ_SP5_MASK (0x400U)
2678#define AIPS_PACRJ_SP5_SHIFT (10U)
2683#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2684#define AIPS_PACRJ_TP4_MASK (0x1000U)
2685#define AIPS_PACRJ_TP4_SHIFT (12U)
2690#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2691#define AIPS_PACRJ_WP4_MASK (0x2000U)
2692#define AIPS_PACRJ_WP4_SHIFT (13U)
2697#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2698#define AIPS_PACRJ_SP4_MASK (0x4000U)
2699#define AIPS_PACRJ_SP4_SHIFT (14U)
2704#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2705#define AIPS_PACRJ_TP3_MASK (0x10000U)
2706#define AIPS_PACRJ_TP3_SHIFT (16U)
2711#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2712#define AIPS_PACRJ_WP3_MASK (0x20000U)
2713#define AIPS_PACRJ_WP3_SHIFT (17U)
2718#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2719#define AIPS_PACRJ_SP3_MASK (0x40000U)
2720#define AIPS_PACRJ_SP3_SHIFT (18U)
2725#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2726#define AIPS_PACRJ_TP2_MASK (0x100000U)
2727#define AIPS_PACRJ_TP2_SHIFT (20U)
2732#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2733#define AIPS_PACRJ_WP2_MASK (0x200000U)
2734#define AIPS_PACRJ_WP2_SHIFT (21U)
2739#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2740#define AIPS_PACRJ_SP2_MASK (0x400000U)
2741#define AIPS_PACRJ_SP2_SHIFT (22U)
2746#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2747#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2748#define AIPS_PACRJ_TP1_SHIFT (24U)
2753#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2754#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2755#define AIPS_PACRJ_WP1_SHIFT (25U)
2760#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2761#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2762#define AIPS_PACRJ_SP1_SHIFT (26U)
2767#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2768#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2769#define AIPS_PACRJ_TP0_SHIFT (28U)
2774#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2775#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2776#define AIPS_PACRJ_WP0_SHIFT (29U)
2781#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2782#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2783#define AIPS_PACRJ_SP0_SHIFT (30U)
2788#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2793#define AIPS_PACRK_TP7_MASK (0x1U)
2794#define AIPS_PACRK_TP7_SHIFT (0U)
2799#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2800#define AIPS_PACRK_WP7_MASK (0x2U)
2801#define AIPS_PACRK_WP7_SHIFT (1U)
2806#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2807#define AIPS_PACRK_SP7_MASK (0x4U)
2808#define AIPS_PACRK_SP7_SHIFT (2U)
2813#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2814#define AIPS_PACRK_TP6_MASK (0x10U)
2815#define AIPS_PACRK_TP6_SHIFT (4U)
2820#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2821#define AIPS_PACRK_WP6_MASK (0x20U)
2822#define AIPS_PACRK_WP6_SHIFT (5U)
2827#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2828#define AIPS_PACRK_SP6_MASK (0x40U)
2829#define AIPS_PACRK_SP6_SHIFT (6U)
2834#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
2835#define AIPS_PACRK_TP5_MASK (0x100U)
2836#define AIPS_PACRK_TP5_SHIFT (8U)
2841#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
2842#define AIPS_PACRK_WP5_MASK (0x200U)
2843#define AIPS_PACRK_WP5_SHIFT (9U)
2848#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
2849#define AIPS_PACRK_SP5_MASK (0x400U)
2850#define AIPS_PACRK_SP5_SHIFT (10U)
2855#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
2856#define AIPS_PACRK_TP4_MASK (0x1000U)
2857#define AIPS_PACRK_TP4_SHIFT (12U)
2862#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
2863#define AIPS_PACRK_WP4_MASK (0x2000U)
2864#define AIPS_PACRK_WP4_SHIFT (13U)
2869#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
2870#define AIPS_PACRK_SP4_MASK (0x4000U)
2871#define AIPS_PACRK_SP4_SHIFT (14U)
2876#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
2877#define AIPS_PACRK_TP3_MASK (0x10000U)
2878#define AIPS_PACRK_TP3_SHIFT (16U)
2883#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
2884#define AIPS_PACRK_WP3_MASK (0x20000U)
2885#define AIPS_PACRK_WP3_SHIFT (17U)
2890#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
2891#define AIPS_PACRK_SP3_MASK (0x40000U)
2892#define AIPS_PACRK_SP3_SHIFT (18U)
2897#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
2898#define AIPS_PACRK_TP2_MASK (0x100000U)
2899#define AIPS_PACRK_TP2_SHIFT (20U)
2904#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
2905#define AIPS_PACRK_WP2_MASK (0x200000U)
2906#define AIPS_PACRK_WP2_SHIFT (21U)
2911#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
2912#define AIPS_PACRK_SP2_MASK (0x400000U)
2913#define AIPS_PACRK_SP2_SHIFT (22U)
2918#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
2919#define AIPS_PACRK_TP1_MASK (0x1000000U)
2920#define AIPS_PACRK_TP1_SHIFT (24U)
2925#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
2926#define AIPS_PACRK_WP1_MASK (0x2000000U)
2927#define AIPS_PACRK_WP1_SHIFT (25U)
2932#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
2933#define AIPS_PACRK_SP1_MASK (0x4000000U)
2934#define AIPS_PACRK_SP1_SHIFT (26U)
2939#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
2940#define AIPS_PACRK_TP0_MASK (0x10000000U)
2941#define AIPS_PACRK_TP0_SHIFT (28U)
2946#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
2947#define AIPS_PACRK_WP0_MASK (0x20000000U)
2948#define AIPS_PACRK_WP0_SHIFT (29U)
2953#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
2954#define AIPS_PACRK_SP0_MASK (0x40000000U)
2955#define AIPS_PACRK_SP0_SHIFT (30U)
2960#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
2965#define AIPS_PACRL_TP7_MASK (0x1U)
2966#define AIPS_PACRL_TP7_SHIFT (0U)
2971#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
2972#define AIPS_PACRL_WP7_MASK (0x2U)
2973#define AIPS_PACRL_WP7_SHIFT (1U)
2978#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
2979#define AIPS_PACRL_SP7_MASK (0x4U)
2980#define AIPS_PACRL_SP7_SHIFT (2U)
2985#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
2986#define AIPS_PACRL_TP6_MASK (0x10U)
2987#define AIPS_PACRL_TP6_SHIFT (4U)
2992#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
2993#define AIPS_PACRL_WP6_MASK (0x20U)
2994#define AIPS_PACRL_WP6_SHIFT (5U)
2999#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
3000#define AIPS_PACRL_SP6_MASK (0x40U)
3001#define AIPS_PACRL_SP6_SHIFT (6U)
3006#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
3007#define AIPS_PACRL_TP5_MASK (0x100U)
3008#define AIPS_PACRL_TP5_SHIFT (8U)
3013#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
3014#define AIPS_PACRL_WP5_MASK (0x200U)
3015#define AIPS_PACRL_WP5_SHIFT (9U)
3020#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
3021#define AIPS_PACRL_SP5_MASK (0x400U)
3022#define AIPS_PACRL_SP5_SHIFT (10U)
3027#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
3028#define AIPS_PACRL_TP4_MASK (0x1000U)
3029#define AIPS_PACRL_TP4_SHIFT (12U)
3034#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3035#define AIPS_PACRL_WP4_MASK (0x2000U)
3036#define AIPS_PACRL_WP4_SHIFT (13U)
3041#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3042#define AIPS_PACRL_SP4_MASK (0x4000U)
3043#define AIPS_PACRL_SP4_SHIFT (14U)
3048#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3049#define AIPS_PACRL_TP3_MASK (0x10000U)
3050#define AIPS_PACRL_TP3_SHIFT (16U)
3055#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3056#define AIPS_PACRL_WP3_MASK (0x20000U)
3057#define AIPS_PACRL_WP3_SHIFT (17U)
3062#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3063#define AIPS_PACRL_SP3_MASK (0x40000U)
3064#define AIPS_PACRL_SP3_SHIFT (18U)
3069#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3070#define AIPS_PACRL_TP2_MASK (0x100000U)
3071#define AIPS_PACRL_TP2_SHIFT (20U)
3076#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3077#define AIPS_PACRL_WP2_MASK (0x200000U)
3078#define AIPS_PACRL_WP2_SHIFT (21U)
3083#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3084#define AIPS_PACRL_SP2_MASK (0x400000U)
3085#define AIPS_PACRL_SP2_SHIFT (22U)
3090#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3091#define AIPS_PACRL_TP1_MASK (0x1000000U)
3092#define AIPS_PACRL_TP1_SHIFT (24U)
3097#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3098#define AIPS_PACRL_WP1_MASK (0x2000000U)
3099#define AIPS_PACRL_WP1_SHIFT (25U)
3104#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3105#define AIPS_PACRL_SP1_MASK (0x4000000U)
3106#define AIPS_PACRL_SP1_SHIFT (26U)
3111#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3112#define AIPS_PACRL_TP0_MASK (0x10000000U)
3113#define AIPS_PACRL_TP0_SHIFT (28U)
3118#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3119#define AIPS_PACRL_WP0_MASK (0x20000000U)
3120#define AIPS_PACRL_WP0_SHIFT (29U)
3125#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3126#define AIPS_PACRL_SP0_MASK (0x40000000U)
3127#define AIPS_PACRL_SP0_SHIFT (30U)
3132#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3137#define AIPS_PACRM_TP7_MASK (0x1U)
3138#define AIPS_PACRM_TP7_SHIFT (0U)
3143#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3144#define AIPS_PACRM_WP7_MASK (0x2U)
3145#define AIPS_PACRM_WP7_SHIFT (1U)
3150#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3151#define AIPS_PACRM_SP7_MASK (0x4U)
3152#define AIPS_PACRM_SP7_SHIFT (2U)
3157#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3158#define AIPS_PACRM_TP6_MASK (0x10U)
3159#define AIPS_PACRM_TP6_SHIFT (4U)
3164#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3165#define AIPS_PACRM_WP6_MASK (0x20U)
3166#define AIPS_PACRM_WP6_SHIFT (5U)
3171#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3172#define AIPS_PACRM_SP6_MASK (0x40U)
3173#define AIPS_PACRM_SP6_SHIFT (6U)
3178#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3179#define AIPS_PACRM_TP5_MASK (0x100U)
3180#define AIPS_PACRM_TP5_SHIFT (8U)
3185#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3186#define AIPS_PACRM_WP5_MASK (0x200U)
3187#define AIPS_PACRM_WP5_SHIFT (9U)
3192#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3193#define AIPS_PACRM_SP5_MASK (0x400U)
3194#define AIPS_PACRM_SP5_SHIFT (10U)
3199#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3200#define AIPS_PACRM_TP4_MASK (0x1000U)
3201#define AIPS_PACRM_TP4_SHIFT (12U)
3206#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3207#define AIPS_PACRM_WP4_MASK (0x2000U)
3208#define AIPS_PACRM_WP4_SHIFT (13U)
3213#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3214#define AIPS_PACRM_SP4_MASK (0x4000U)
3215#define AIPS_PACRM_SP4_SHIFT (14U)
3220#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3221#define AIPS_PACRM_TP3_MASK (0x10000U)
3222#define AIPS_PACRM_TP3_SHIFT (16U)
3227#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3228#define AIPS_PACRM_WP3_MASK (0x20000U)
3229#define AIPS_PACRM_WP3_SHIFT (17U)
3234#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3235#define AIPS_PACRM_SP3_MASK (0x40000U)
3236#define AIPS_PACRM_SP3_SHIFT (18U)
3241#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3242#define AIPS_PACRM_TP2_MASK (0x100000U)
3243#define AIPS_PACRM_TP2_SHIFT (20U)
3248#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3249#define AIPS_PACRM_WP2_MASK (0x200000U)
3250#define AIPS_PACRM_WP2_SHIFT (21U)
3255#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3256#define AIPS_PACRM_SP2_MASK (0x400000U)
3257#define AIPS_PACRM_SP2_SHIFT (22U)
3262#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3263#define AIPS_PACRM_TP1_MASK (0x1000000U)
3264#define AIPS_PACRM_TP1_SHIFT (24U)
3269#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3270#define AIPS_PACRM_WP1_MASK (0x2000000U)
3271#define AIPS_PACRM_WP1_SHIFT (25U)
3276#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3277#define AIPS_PACRM_SP1_MASK (0x4000000U)
3278#define AIPS_PACRM_SP1_SHIFT (26U)
3283#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3284#define AIPS_PACRM_TP0_MASK (0x10000000U)
3285#define AIPS_PACRM_TP0_SHIFT (28U)
3290#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3291#define AIPS_PACRM_WP0_MASK (0x20000000U)
3292#define AIPS_PACRM_WP0_SHIFT (29U)
3297#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3298#define AIPS_PACRM_SP0_MASK (0x40000000U)
3299#define AIPS_PACRM_SP0_SHIFT (30U)
3304#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3309#define AIPS_PACRN_TP7_MASK (0x1U)
3310#define AIPS_PACRN_TP7_SHIFT (0U)
3315#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3316#define AIPS_PACRN_WP7_MASK (0x2U)
3317#define AIPS_PACRN_WP7_SHIFT (1U)
3322#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3323#define AIPS_PACRN_SP7_MASK (0x4U)
3324#define AIPS_PACRN_SP7_SHIFT (2U)
3329#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3330#define AIPS_PACRN_TP6_MASK (0x10U)
3331#define AIPS_PACRN_TP6_SHIFT (4U)
3336#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3337#define AIPS_PACRN_WP6_MASK (0x20U)
3338#define AIPS_PACRN_WP6_SHIFT (5U)
3343#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3344#define AIPS_PACRN_SP6_MASK (0x40U)
3345#define AIPS_PACRN_SP6_SHIFT (6U)
3350#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3351#define AIPS_PACRN_TP5_MASK (0x100U)
3352#define AIPS_PACRN_TP5_SHIFT (8U)
3357#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3358#define AIPS_PACRN_WP5_MASK (0x200U)
3359#define AIPS_PACRN_WP5_SHIFT (9U)
3364#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3365#define AIPS_PACRN_SP5_MASK (0x400U)
3366#define AIPS_PACRN_SP5_SHIFT (10U)
3371#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3372#define AIPS_PACRN_TP4_MASK (0x1000U)
3373#define AIPS_PACRN_TP4_SHIFT (12U)
3378#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3379#define AIPS_PACRN_WP4_MASK (0x2000U)
3380#define AIPS_PACRN_WP4_SHIFT (13U)
3385#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3386#define AIPS_PACRN_SP4_MASK (0x4000U)
3387#define AIPS_PACRN_SP4_SHIFT (14U)
3392#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3393#define AIPS_PACRN_TP3_MASK (0x10000U)
3394#define AIPS_PACRN_TP3_SHIFT (16U)
3399#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3400#define AIPS_PACRN_WP3_MASK (0x20000U)
3401#define AIPS_PACRN_WP3_SHIFT (17U)
3406#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3407#define AIPS_PACRN_SP3_MASK (0x40000U)
3408#define AIPS_PACRN_SP3_SHIFT (18U)
3413#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3414#define AIPS_PACRN_TP2_MASK (0x100000U)
3415#define AIPS_PACRN_TP2_SHIFT (20U)
3420#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3421#define AIPS_PACRN_WP2_MASK (0x200000U)
3422#define AIPS_PACRN_WP2_SHIFT (21U)
3427#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3428#define AIPS_PACRN_SP2_MASK (0x400000U)
3429#define AIPS_PACRN_SP2_SHIFT (22U)
3434#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3435#define AIPS_PACRN_TP1_MASK (0x1000000U)
3436#define AIPS_PACRN_TP1_SHIFT (24U)
3441#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3442#define AIPS_PACRN_WP1_MASK (0x2000000U)
3443#define AIPS_PACRN_WP1_SHIFT (25U)
3448#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3449#define AIPS_PACRN_SP1_MASK (0x4000000U)
3450#define AIPS_PACRN_SP1_SHIFT (26U)
3455#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3456#define AIPS_PACRN_TP0_MASK (0x10000000U)
3457#define AIPS_PACRN_TP0_SHIFT (28U)
3462#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3463#define AIPS_PACRN_WP0_MASK (0x20000000U)
3464#define AIPS_PACRN_WP0_SHIFT (29U)
3469#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3470#define AIPS_PACRN_SP0_MASK (0x40000000U)
3471#define AIPS_PACRN_SP0_SHIFT (30U)
3476#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3481#define AIPS_PACRO_TP7_MASK (0x1U)
3482#define AIPS_PACRO_TP7_SHIFT (0U)
3487#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3488#define AIPS_PACRO_WP7_MASK (0x2U)
3489#define AIPS_PACRO_WP7_SHIFT (1U)
3494#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3495#define AIPS_PACRO_SP7_MASK (0x4U)
3496#define AIPS_PACRO_SP7_SHIFT (2U)
3501#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3502#define AIPS_PACRO_TP6_MASK (0x10U)
3503#define AIPS_PACRO_TP6_SHIFT (4U)
3508#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3509#define AIPS_PACRO_WP6_MASK (0x20U)
3510#define AIPS_PACRO_WP6_SHIFT (5U)
3515#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3516#define AIPS_PACRO_SP6_MASK (0x40U)
3517#define AIPS_PACRO_SP6_SHIFT (6U)
3522#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3523#define AIPS_PACRO_TP5_MASK (0x100U)
3524#define AIPS_PACRO_TP5_SHIFT (8U)
3529#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3530#define AIPS_PACRO_WP5_MASK (0x200U)
3531#define AIPS_PACRO_WP5_SHIFT (9U)
3536#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3537#define AIPS_PACRO_SP5_MASK (0x400U)
3538#define AIPS_PACRO_SP5_SHIFT (10U)
3543#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3544#define AIPS_PACRO_TP4_MASK (0x1000U)
3545#define AIPS_PACRO_TP4_SHIFT (12U)
3550#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3551#define AIPS_PACRO_WP4_MASK (0x2000U)
3552#define AIPS_PACRO_WP4_SHIFT (13U)
3557#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3558#define AIPS_PACRO_SP4_MASK (0x4000U)
3559#define AIPS_PACRO_SP4_SHIFT (14U)
3564#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3565#define AIPS_PACRO_TP3_MASK (0x10000U)
3566#define AIPS_PACRO_TP3_SHIFT (16U)
3571#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3572#define AIPS_PACRO_WP3_MASK (0x20000U)
3573#define AIPS_PACRO_WP3_SHIFT (17U)
3578#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3579#define AIPS_PACRO_SP3_MASK (0x40000U)
3580#define AIPS_PACRO_SP3_SHIFT (18U)
3585#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3586#define AIPS_PACRO_TP2_MASK (0x100000U)
3587#define AIPS_PACRO_TP2_SHIFT (20U)
3592#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3593#define AIPS_PACRO_WP2_MASK (0x200000U)
3594#define AIPS_PACRO_WP2_SHIFT (21U)
3599#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3600#define AIPS_PACRO_SP2_MASK (0x400000U)
3601#define AIPS_PACRO_SP2_SHIFT (22U)
3606#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3607#define AIPS_PACRO_TP1_MASK (0x1000000U)
3608#define AIPS_PACRO_TP1_SHIFT (24U)
3613#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3614#define AIPS_PACRO_WP1_MASK (0x2000000U)
3615#define AIPS_PACRO_WP1_SHIFT (25U)
3620#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3621#define AIPS_PACRO_SP1_MASK (0x4000000U)
3622#define AIPS_PACRO_SP1_SHIFT (26U)
3627#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3628#define AIPS_PACRO_TP0_MASK (0x10000000U)
3629#define AIPS_PACRO_TP0_SHIFT (28U)
3634#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3635#define AIPS_PACRO_WP0_MASK (0x20000000U)
3636#define AIPS_PACRO_WP0_SHIFT (29U)
3641#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3642#define AIPS_PACRO_SP0_MASK (0x40000000U)
3643#define AIPS_PACRO_SP0_SHIFT (30U)
3648#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3653#define AIPS_PACRP_TP7_MASK (0x1U)
3654#define AIPS_PACRP_TP7_SHIFT (0U)
3659#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3660#define AIPS_PACRP_WP7_MASK (0x2U)
3661#define AIPS_PACRP_WP7_SHIFT (1U)
3666#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3667#define AIPS_PACRP_SP7_MASK (0x4U)
3668#define AIPS_PACRP_SP7_SHIFT (2U)
3673#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3674#define AIPS_PACRP_TP6_MASK (0x10U)
3675#define AIPS_PACRP_TP6_SHIFT (4U)
3680#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3681#define AIPS_PACRP_WP6_MASK (0x20U)
3682#define AIPS_PACRP_WP6_SHIFT (5U)
3687#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3688#define AIPS_PACRP_SP6_MASK (0x40U)
3689#define AIPS_PACRP_SP6_SHIFT (6U)
3694#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3695#define AIPS_PACRP_TP5_MASK (0x100U)
3696#define AIPS_PACRP_TP5_SHIFT (8U)
3701#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3702#define AIPS_PACRP_WP5_MASK (0x200U)
3703#define AIPS_PACRP_WP5_SHIFT (9U)
3708#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3709#define AIPS_PACRP_SP5_MASK (0x400U)
3710#define AIPS_PACRP_SP5_SHIFT (10U)
3715#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3716#define AIPS_PACRP_TP4_MASK (0x1000U)
3717#define AIPS_PACRP_TP4_SHIFT (12U)
3722#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3723#define AIPS_PACRP_WP4_MASK (0x2000U)
3724#define AIPS_PACRP_WP4_SHIFT (13U)
3729#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3730#define AIPS_PACRP_SP4_MASK (0x4000U)
3731#define AIPS_PACRP_SP4_SHIFT (14U)
3736#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3737#define AIPS_PACRP_TP3_MASK (0x10000U)
3738#define AIPS_PACRP_TP3_SHIFT (16U)
3743#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3744#define AIPS_PACRP_WP3_MASK (0x20000U)
3745#define AIPS_PACRP_WP3_SHIFT (17U)
3750#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3751#define AIPS_PACRP_SP3_MASK (0x40000U)
3752#define AIPS_PACRP_SP3_SHIFT (18U)
3757#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3758#define AIPS_PACRP_TP2_MASK (0x100000U)
3759#define AIPS_PACRP_TP2_SHIFT (20U)
3764#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3765#define AIPS_PACRP_WP2_MASK (0x200000U)
3766#define AIPS_PACRP_WP2_SHIFT (21U)
3771#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3772#define AIPS_PACRP_SP2_MASK (0x400000U)
3773#define AIPS_PACRP_SP2_SHIFT (22U)
3778#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3779#define AIPS_PACRP_TP1_MASK (0x1000000U)
3780#define AIPS_PACRP_TP1_SHIFT (24U)
3785#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3786#define AIPS_PACRP_WP1_MASK (0x2000000U)
3787#define AIPS_PACRP_WP1_SHIFT (25U)
3792#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3793#define AIPS_PACRP_SP1_MASK (0x4000000U)
3794#define AIPS_PACRP_SP1_SHIFT (26U)
3799#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3800#define AIPS_PACRP_TP0_MASK (0x10000000U)
3801#define AIPS_PACRP_TP0_SHIFT (28U)
3806#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3807#define AIPS_PACRP_WP0_MASK (0x20000000U)
3808#define AIPS_PACRP_WP0_SHIFT (29U)
3813#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3814#define AIPS_PACRP_SP0_MASK (0x40000000U)
3815#define AIPS_PACRP_SP0_SHIFT (30U)
3820#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3826 /* end of group AIPS_Register_Masks */
3827
3828
3829/* AIPS - Peripheral instance base addresses */
3831#define AIPS0_BASE (0x40000000u)
3833#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
3835#define AIPS1_BASE (0x40080000u)
3837#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
3839#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
3841#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
3842
3845 /* end of group AIPS_Peripheral_Access_Layer */
3846
3847
3848/* ----------------------------------------------------------------------------
3849 -- AXBS Peripheral Access Layer
3850 ---------------------------------------------------------------------------- */
3851
3858typedef struct {
3859 struct { /* offset: 0x0, array step: 0x100 */
3860 __IO uint32_t PRS;
3861 uint8_t RESERVED_0[12];
3862 __IO uint32_t CRS;
3863 uint8_t RESERVED_1[236];
3864 } SLAVE[5];
3865 uint8_t RESERVED_0[768];
3866 __IO uint32_t MGPCR0;
3867 uint8_t RESERVED_1[252];
3868 __IO uint32_t MGPCR1;
3869 uint8_t RESERVED_2[252];
3870 __IO uint32_t MGPCR2;
3871 uint8_t RESERVED_3[252];
3872 __IO uint32_t MGPCR3;
3873 uint8_t RESERVED_4[252];
3874 __IO uint32_t MGPCR4;
3875 uint8_t RESERVED_5[252];
3876 __IO uint32_t MGPCR5;
3877 uint8_t RESERVED_6[252];
3878 __IO uint32_t MGPCR6;
3879} AXBS_Type;
3880
3881/* ----------------------------------------------------------------------------
3882 -- AXBS Register Masks
3883 ---------------------------------------------------------------------------- */
3884
3892#define AXBS_PRS_M0_MASK (0x7U)
3893#define AXBS_PRS_M0_SHIFT (0U)
3904#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
3905#define AXBS_PRS_M1_MASK (0x70U)
3906#define AXBS_PRS_M1_SHIFT (4U)
3917#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
3918#define AXBS_PRS_M2_MASK (0x700U)
3919#define AXBS_PRS_M2_SHIFT (8U)
3930#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
3931#define AXBS_PRS_M3_MASK (0x7000U)
3932#define AXBS_PRS_M3_SHIFT (12U)
3943#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
3944#define AXBS_PRS_M4_MASK (0x70000U)
3945#define AXBS_PRS_M4_SHIFT (16U)
3956#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
3957#define AXBS_PRS_M5_MASK (0x700000U)
3958#define AXBS_PRS_M5_SHIFT (20U)
3969#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
3970#define AXBS_PRS_M6_MASK (0x7000000U)
3971#define AXBS_PRS_M6_SHIFT (24U)
3982#define AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
3985/* The count of AXBS_PRS */
3986#define AXBS_PRS_COUNT (5U)
3987
3990#define AXBS_CRS_PARK_MASK (0x7U)
3991#define AXBS_CRS_PARK_SHIFT (0U)
4002#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
4003#define AXBS_CRS_PCTL_MASK (0x30U)
4004#define AXBS_CRS_PCTL_SHIFT (4U)
4011#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
4012#define AXBS_CRS_ARB_MASK (0x300U)
4013#define AXBS_CRS_ARB_SHIFT (8U)
4020#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
4021#define AXBS_CRS_HLP_MASK (0x40000000U)
4022#define AXBS_CRS_HLP_SHIFT (30U)
4027#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
4028#define AXBS_CRS_RO_MASK (0x80000000U)
4029#define AXBS_CRS_RO_SHIFT (31U)
4034#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4037/* The count of AXBS_CRS */
4038#define AXBS_CRS_COUNT (5U)
4039
4042#define AXBS_MGPCR0_AULB_MASK (0x7U)
4043#define AXBS_MGPCR0_AULB_SHIFT (0U)
4054#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4059#define AXBS_MGPCR1_AULB_MASK (0x7U)
4060#define AXBS_MGPCR1_AULB_SHIFT (0U)
4071#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4076#define AXBS_MGPCR2_AULB_MASK (0x7U)
4077#define AXBS_MGPCR2_AULB_SHIFT (0U)
4088#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4093#define AXBS_MGPCR3_AULB_MASK (0x7U)
4094#define AXBS_MGPCR3_AULB_SHIFT (0U)
4105#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
4110#define AXBS_MGPCR4_AULB_MASK (0x7U)
4111#define AXBS_MGPCR4_AULB_SHIFT (0U)
4122#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
4127#define AXBS_MGPCR5_AULB_MASK (0x7U)
4128#define AXBS_MGPCR5_AULB_SHIFT (0U)
4139#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
4144#define AXBS_MGPCR6_AULB_MASK (0x7U)
4145#define AXBS_MGPCR6_AULB_SHIFT (0U)
4156#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
4162 /* end of group AXBS_Register_Masks */
4163
4164
4165/* AXBS - Peripheral instance base addresses */
4167#define AXBS_BASE (0x40004000u)
4169#define AXBS ((AXBS_Type *)AXBS_BASE)
4171#define AXBS_BASE_ADDRS { AXBS_BASE }
4173#define AXBS_BASE_PTRS { AXBS }
4174
4177 /* end of group AXBS_Peripheral_Access_Layer */
4178
4179
4180/* ----------------------------------------------------------------------------
4181 -- CAN Peripheral Access Layer
4182 ---------------------------------------------------------------------------- */
4183
4190typedef struct {
4191 __IO uint32_t MCR;
4192 __IO uint32_t CTRL1;
4193 __IO uint32_t TIMER;
4194 uint8_t RESERVED_0[4];
4195 __IO uint32_t RXMGMASK;
4196 __IO uint32_t RX14MASK;
4197 __IO uint32_t RX15MASK;
4198 __IO uint32_t ECR;
4199 __IO uint32_t ESR1;
4200 uint8_t RESERVED_1[4];
4201 __IO uint32_t IMASK1;
4202 uint8_t RESERVED_2[4];
4203 __IO uint32_t IFLAG1;
4204 __IO uint32_t CTRL2;
4205 __I uint32_t ESR2;
4206 uint8_t RESERVED_3[8];
4207 __I uint32_t CRCR;
4208 __IO uint32_t RXFGMASK;
4209 __I uint32_t RXFIR;
4210 uint8_t RESERVED_4[48];
4211 struct { /* offset: 0x80, array step: 0x10 */
4212 __IO uint32_t CS;
4213 __IO uint32_t ID;
4214 __IO uint32_t WORD0;
4215 __IO uint32_t WORD1;
4216 } MB[16];
4217 uint8_t RESERVED_5[1792];
4218 __IO uint32_t RXIMR[16];
4219} CAN_Type;
4220
4221/* ----------------------------------------------------------------------------
4222 -- CAN Register Masks
4223 ---------------------------------------------------------------------------- */
4224
4232#define CAN_MCR_MAXMB_MASK (0x7FU)
4233#define CAN_MCR_MAXMB_SHIFT (0U)
4234#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4235#define CAN_MCR_IDAM_MASK (0x300U)
4236#define CAN_MCR_IDAM_SHIFT (8U)
4243#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4244#define CAN_MCR_AEN_MASK (0x1000U)
4245#define CAN_MCR_AEN_SHIFT (12U)
4250#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4251#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4252#define CAN_MCR_LPRIOEN_SHIFT (13U)
4257#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4258#define CAN_MCR_IRMQ_MASK (0x10000U)
4259#define CAN_MCR_IRMQ_SHIFT (16U)
4264#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4265#define CAN_MCR_SRXDIS_MASK (0x20000U)
4266#define CAN_MCR_SRXDIS_SHIFT (17U)
4271#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4272#define CAN_MCR_WAKSRC_MASK (0x80000U)
4273#define CAN_MCR_WAKSRC_SHIFT (19U)
4278#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4279#define CAN_MCR_LPMACK_MASK (0x100000U)
4280#define CAN_MCR_LPMACK_SHIFT (20U)
4285#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4286#define CAN_MCR_WRNEN_MASK (0x200000U)
4287#define CAN_MCR_WRNEN_SHIFT (21U)
4292#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4293#define CAN_MCR_SLFWAK_MASK (0x400000U)
4294#define CAN_MCR_SLFWAK_SHIFT (22U)
4299#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4300#define CAN_MCR_SUPV_MASK (0x800000U)
4301#define CAN_MCR_SUPV_SHIFT (23U)
4306#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4307#define CAN_MCR_FRZACK_MASK (0x1000000U)
4308#define CAN_MCR_FRZACK_SHIFT (24U)
4313#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4314#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4315#define CAN_MCR_SOFTRST_SHIFT (25U)
4320#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4321#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4322#define CAN_MCR_WAKMSK_SHIFT (26U)
4327#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4328#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4329#define CAN_MCR_NOTRDY_SHIFT (27U)
4334#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4335#define CAN_MCR_HALT_MASK (0x10000000U)
4336#define CAN_MCR_HALT_SHIFT (28U)
4341#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4342#define CAN_MCR_RFEN_MASK (0x20000000U)
4343#define CAN_MCR_RFEN_SHIFT (29U)
4348#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4349#define CAN_MCR_FRZ_MASK (0x40000000U)
4350#define CAN_MCR_FRZ_SHIFT (30U)
4355#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4356#define CAN_MCR_MDIS_MASK (0x80000000U)
4357#define CAN_MCR_MDIS_SHIFT (31U)
4362#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4367#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4368#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4369#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4370#define CAN_CTRL1_LOM_MASK (0x8U)
4371#define CAN_CTRL1_LOM_SHIFT (3U)
4376#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4377#define CAN_CTRL1_LBUF_MASK (0x10U)
4378#define CAN_CTRL1_LBUF_SHIFT (4U)
4383#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4384#define CAN_CTRL1_TSYN_MASK (0x20U)
4385#define CAN_CTRL1_TSYN_SHIFT (5U)
4390#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4391#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4392#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4397#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4398#define CAN_CTRL1_SMP_MASK (0x80U)
4399#define CAN_CTRL1_SMP_SHIFT (7U)
4404#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4405#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4406#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4411#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4412#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4413#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4418#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4419#define CAN_CTRL1_LPB_MASK (0x1000U)
4420#define CAN_CTRL1_LPB_SHIFT (12U)
4425#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4426#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4427#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4432#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4433#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4434#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4439#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4440#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4441#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4446#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4447#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4448#define CAN_CTRL1_PSEG2_SHIFT (16U)
4449#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4450#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4451#define CAN_CTRL1_PSEG1_SHIFT (19U)
4452#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4453#define CAN_CTRL1_RJW_MASK (0xC00000U)
4454#define CAN_CTRL1_RJW_SHIFT (22U)
4455#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4456#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4457#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4458#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4463#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4464#define CAN_TIMER_TIMER_SHIFT (0U)
4465#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4470#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4471#define CAN_RXMGMASK_MG_SHIFT (0U)
4476#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4481#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4482#define CAN_RX14MASK_RX14M_SHIFT (0U)
4487#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4492#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4493#define CAN_RX15MASK_RX15M_SHIFT (0U)
4498#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4503#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4504#define CAN_ECR_TXERRCNT_SHIFT (0U)
4505#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4506#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4507#define CAN_ECR_RXERRCNT_SHIFT (8U)
4508#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4513#define CAN_ESR1_WAKINT_MASK (0x1U)
4514#define CAN_ESR1_WAKINT_SHIFT (0U)
4519#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4520#define CAN_ESR1_ERRINT_MASK (0x2U)
4521#define CAN_ESR1_ERRINT_SHIFT (1U)
4526#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4527#define CAN_ESR1_BOFFINT_MASK (0x4U)
4528#define CAN_ESR1_BOFFINT_SHIFT (2U)
4533#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4534#define CAN_ESR1_RX_MASK (0x8U)
4535#define CAN_ESR1_RX_SHIFT (3U)
4540#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4541#define CAN_ESR1_FLTCONF_MASK (0x30U)
4542#define CAN_ESR1_FLTCONF_SHIFT (4U)
4548#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4549#define CAN_ESR1_TX_MASK (0x40U)
4550#define CAN_ESR1_TX_SHIFT (6U)
4555#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4556#define CAN_ESR1_IDLE_MASK (0x80U)
4557#define CAN_ESR1_IDLE_SHIFT (7U)
4562#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4563#define CAN_ESR1_RXWRN_MASK (0x100U)
4564#define CAN_ESR1_RXWRN_SHIFT (8U)
4569#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4570#define CAN_ESR1_TXWRN_MASK (0x200U)
4571#define CAN_ESR1_TXWRN_SHIFT (9U)
4576#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4577#define CAN_ESR1_STFERR_MASK (0x400U)
4578#define CAN_ESR1_STFERR_SHIFT (10U)
4583#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4584#define CAN_ESR1_FRMERR_MASK (0x800U)
4585#define CAN_ESR1_FRMERR_SHIFT (11U)
4590#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4591#define CAN_ESR1_CRCERR_MASK (0x1000U)
4592#define CAN_ESR1_CRCERR_SHIFT (12U)
4597#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4598#define CAN_ESR1_ACKERR_MASK (0x2000U)
4599#define CAN_ESR1_ACKERR_SHIFT (13U)
4604#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4605#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4606#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4611#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4612#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4613#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4618#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4619#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4620#define CAN_ESR1_RWRNINT_SHIFT (16U)
4625#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4626#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4627#define CAN_ESR1_TWRNINT_SHIFT (17U)
4632#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4633#define CAN_ESR1_SYNCH_MASK (0x40000U)
4634#define CAN_ESR1_SYNCH_SHIFT (18U)
4639#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4644#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4645#define CAN_IMASK1_BUFLM_SHIFT (0U)
4650#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4655#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4656#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4661#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4662#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4663#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4668#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4669#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4670#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4675#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4676#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4677#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4682#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4683#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4684#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4689#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4690#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4691#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4696#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4701#define CAN_CTRL2_EACEN_MASK (0x10000U)
4702#define CAN_CTRL2_EACEN_SHIFT (16U)
4707#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4708#define CAN_CTRL2_RRS_MASK (0x20000U)
4709#define CAN_CTRL2_RRS_SHIFT (17U)
4714#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4715#define CAN_CTRL2_MRP_MASK (0x40000U)
4716#define CAN_CTRL2_MRP_SHIFT (18U)
4721#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4722#define CAN_CTRL2_TASD_MASK (0xF80000U)
4723#define CAN_CTRL2_TASD_SHIFT (19U)
4724#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4725#define CAN_CTRL2_RFFN_MASK (0xF000000U)
4726#define CAN_CTRL2_RFFN_SHIFT (24U)
4727#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4728#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4729#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4734#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4739#define CAN_ESR2_IMB_MASK (0x2000U)
4740#define CAN_ESR2_IMB_SHIFT (13U)
4745#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4746#define CAN_ESR2_VPS_MASK (0x4000U)
4747#define CAN_ESR2_VPS_SHIFT (14U)
4752#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4753#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4754#define CAN_ESR2_LPTM_SHIFT (16U)
4755#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4760#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4761#define CAN_CRCR_TXCRC_SHIFT (0U)
4762#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4763#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4764#define CAN_CRCR_MBCRC_SHIFT (16U)
4765#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4770#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4771#define CAN_RXFGMASK_FGM_SHIFT (0U)
4776#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4781#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4782#define CAN_RXFIR_IDHIT_SHIFT (0U)
4783#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4788#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4789#define CAN_CS_TIME_STAMP_SHIFT (0U)
4790#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4791#define CAN_CS_DLC_MASK (0xF0000U)
4792#define CAN_CS_DLC_SHIFT (16U)
4793#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4794#define CAN_CS_RTR_MASK (0x100000U)
4795#define CAN_CS_RTR_SHIFT (20U)
4796#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4797#define CAN_CS_IDE_MASK (0x200000U)
4798#define CAN_CS_IDE_SHIFT (21U)
4799#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4800#define CAN_CS_SRR_MASK (0x400000U)
4801#define CAN_CS_SRR_SHIFT (22U)
4802#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4803#define CAN_CS_CODE_MASK (0xF000000U)
4804#define CAN_CS_CODE_SHIFT (24U)
4805#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4808/* The count of CAN_CS */
4809#define CAN_CS_COUNT (16U)
4810
4813#define CAN_ID_EXT_MASK (0x3FFFFU)
4814#define CAN_ID_EXT_SHIFT (0U)
4815#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4816#define CAN_ID_STD_MASK (0x1FFC0000U)
4817#define CAN_ID_STD_SHIFT (18U)
4818#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4819#define CAN_ID_PRIO_MASK (0xE0000000U)
4820#define CAN_ID_PRIO_SHIFT (29U)
4821#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4824/* The count of CAN_ID */
4825#define CAN_ID_COUNT (16U)
4826
4829#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4830#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4831#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4832#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4833#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4834#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4835#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4836#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4837#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4838#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4839#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4840#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4843/* The count of CAN_WORD0 */
4844#define CAN_WORD0_COUNT (16U)
4845
4848#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4849#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4850#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4851#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4852#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4853#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4854#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4855#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4856#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4857#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4858#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4859#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4862/* The count of CAN_WORD1 */
4863#define CAN_WORD1_COUNT (16U)
4864
4867#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4868#define CAN_RXIMR_MI_SHIFT (0U)
4873#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4876/* The count of CAN_RXIMR */
4877#define CAN_RXIMR_COUNT (16U)
4878
4879
4882 /* end of group CAN_Register_Masks */
4883
4884
4885/* CAN - Peripheral instance base addresses */
4887#define CAN0_BASE (0x40024000u)
4889#define CAN0 ((CAN_Type *)CAN0_BASE)
4891#define CAN1_BASE (0x400A4000u)
4893#define CAN1 ((CAN_Type *)CAN1_BASE)
4895#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
4897#define CAN_BASE_PTRS { CAN0, CAN1 }
4899#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
4900#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
4901#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
4902#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
4903#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
4904#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
4905
4908 /* end of group CAN_Peripheral_Access_Layer */
4909
4910
4911/* ----------------------------------------------------------------------------
4912 -- CAU Peripheral Access Layer
4913 ---------------------------------------------------------------------------- */
4914
4921typedef struct {
4922 __O uint32_t DIRECT[16];
4923 uint8_t RESERVED_0[2048];
4924 __O uint32_t LDR_CASR;
4925 __O uint32_t LDR_CAA;
4926 __O uint32_t LDR_CA[9];
4927 uint8_t RESERVED_1[20];
4928 __I uint32_t STR_CASR;
4929 __I uint32_t STR_CAA;
4930 __I uint32_t STR_CA[9];
4931 uint8_t RESERVED_2[20];
4932 __O uint32_t ADR_CASR;
4933 __O uint32_t ADR_CAA;
4934 __O uint32_t ADR_CA[9];
4935 uint8_t RESERVED_3[20];
4936 __O uint32_t RADR_CASR;
4937 __O uint32_t RADR_CAA;
4938 __O uint32_t RADR_CA[9];
4939 uint8_t RESERVED_4[84];
4940 __O uint32_t XOR_CASR;
4941 __O uint32_t XOR_CAA;
4942 __O uint32_t XOR_CA[9];
4943 uint8_t RESERVED_5[20];
4944 __O uint32_t ROTL_CASR;
4945 __O uint32_t ROTL_CAA;
4946 __O uint32_t ROTL_CA[9];
4947 uint8_t RESERVED_6[276];
4948 __O uint32_t AESC_CASR;
4949 __O uint32_t AESC_CAA;
4950 __O uint32_t AESC_CA[9];
4951 uint8_t RESERVED_7[20];
4952 __O uint32_t AESIC_CASR;
4953 __O uint32_t AESIC_CAA;
4954 __O uint32_t AESIC_CA[9];
4955} CAU_Type;
4956
4957/* ----------------------------------------------------------------------------
4958 -- CAU Register Masks
4959 ---------------------------------------------------------------------------- */
4960
4968#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
4969#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
4970#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
4971#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
4972#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
4973#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
4974#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
4975#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
4976#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
4977#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
4978#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
4979#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
4980#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
4981#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
4982#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
4983#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
4984#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
4985#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
4986#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
4987#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
4988#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
4989#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
4990#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
4991#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
4992#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
4993#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
4994#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
4995#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
4996#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
4997#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
4998#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
4999#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
5000#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
5001#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
5002#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
5003#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
5004#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
5005#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
5006#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
5007#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
5008#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
5009#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
5010#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
5011#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
5012#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
5013#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
5014#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
5015#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
5018/* The count of CAU_DIRECT */
5019#define CAU_DIRECT_COUNT (16U)
5020
5023#define CAU_LDR_CASR_IC_MASK (0x1U)
5024#define CAU_LDR_CASR_IC_SHIFT (0U)
5029#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
5030#define CAU_LDR_CASR_DPE_MASK (0x2U)
5031#define CAU_LDR_CASR_DPE_SHIFT (1U)
5036#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
5037#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
5038#define CAU_LDR_CASR_VER_SHIFT (28U)
5043#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
5048#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
5049#define CAU_LDR_CAA_ACC_SHIFT (0U)
5050#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
5055#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
5056#define CAU_LDR_CA_CA0_SHIFT (0U)
5057#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
5058#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
5059#define CAU_LDR_CA_CA1_SHIFT (0U)
5060#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
5061#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
5062#define CAU_LDR_CA_CA2_SHIFT (0U)
5063#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
5064#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
5065#define CAU_LDR_CA_CA3_SHIFT (0U)
5066#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
5067#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
5068#define CAU_LDR_CA_CA4_SHIFT (0U)
5069#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
5070#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
5071#define CAU_LDR_CA_CA5_SHIFT (0U)
5072#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
5073#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
5074#define CAU_LDR_CA_CA6_SHIFT (0U)
5075#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
5076#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
5077#define CAU_LDR_CA_CA7_SHIFT (0U)
5078#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
5079#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
5080#define CAU_LDR_CA_CA8_SHIFT (0U)
5081#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
5084/* The count of CAU_LDR_CA */
5085#define CAU_LDR_CA_COUNT (9U)
5086
5089#define CAU_STR_CASR_IC_MASK (0x1U)
5090#define CAU_STR_CASR_IC_SHIFT (0U)
5095#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
5096#define CAU_STR_CASR_DPE_MASK (0x2U)
5097#define CAU_STR_CASR_DPE_SHIFT (1U)
5102#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
5103#define CAU_STR_CASR_VER_MASK (0xF0000000U)
5104#define CAU_STR_CASR_VER_SHIFT (28U)
5109#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
5114#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
5115#define CAU_STR_CAA_ACC_SHIFT (0U)
5116#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
5121#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
5122#define CAU_STR_CA_CA0_SHIFT (0U)
5123#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
5124#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
5125#define CAU_STR_CA_CA1_SHIFT (0U)
5126#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
5127#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
5128#define CAU_STR_CA_CA2_SHIFT (0U)
5129#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
5130#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
5131#define CAU_STR_CA_CA3_SHIFT (0U)
5132#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
5133#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
5134#define CAU_STR_CA_CA4_SHIFT (0U)
5135#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
5136#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
5137#define CAU_STR_CA_CA5_SHIFT (0U)
5138#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
5139#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
5140#define CAU_STR_CA_CA6_SHIFT (0U)
5141#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
5142#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
5143#define CAU_STR_CA_CA7_SHIFT (0U)
5144#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
5145#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
5146#define CAU_STR_CA_CA8_SHIFT (0U)
5147#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
5150/* The count of CAU_STR_CA */
5151#define CAU_STR_CA_COUNT (9U)
5152
5155#define CAU_ADR_CASR_IC_MASK (0x1U)
5156#define CAU_ADR_CASR_IC_SHIFT (0U)
5161#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
5162#define CAU_ADR_CASR_DPE_MASK (0x2U)
5163#define CAU_ADR_CASR_DPE_SHIFT (1U)
5168#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
5169#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
5170#define CAU_ADR_CASR_VER_SHIFT (28U)
5175#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
5180#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
5181#define CAU_ADR_CAA_ACC_SHIFT (0U)
5182#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
5187#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
5188#define CAU_ADR_CA_CA0_SHIFT (0U)
5189#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
5190#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
5191#define CAU_ADR_CA_CA1_SHIFT (0U)
5192#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
5193#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
5194#define CAU_ADR_CA_CA2_SHIFT (0U)
5195#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
5196#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
5197#define CAU_ADR_CA_CA3_SHIFT (0U)
5198#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
5199#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
5200#define CAU_ADR_CA_CA4_SHIFT (0U)
5201#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
5202#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
5203#define CAU_ADR_CA_CA5_SHIFT (0U)
5204#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
5205#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
5206#define CAU_ADR_CA_CA6_SHIFT (0U)
5207#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
5208#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
5209#define CAU_ADR_CA_CA7_SHIFT (0U)
5210#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
5211#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
5212#define CAU_ADR_CA_CA8_SHIFT (0U)
5213#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
5216/* The count of CAU_ADR_CA */
5217#define CAU_ADR_CA_COUNT (9U)
5218
5221#define CAU_RADR_CASR_IC_MASK (0x1U)
5222#define CAU_RADR_CASR_IC_SHIFT (0U)
5227#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
5228#define CAU_RADR_CASR_DPE_MASK (0x2U)
5229#define CAU_RADR_CASR_DPE_SHIFT (1U)
5234#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
5235#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
5236#define CAU_RADR_CASR_VER_SHIFT (28U)
5241#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
5246#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
5247#define CAU_RADR_CAA_ACC_SHIFT (0U)
5248#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
5253#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
5254#define CAU_RADR_CA_CA0_SHIFT (0U)
5255#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
5256#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
5257#define CAU_RADR_CA_CA1_SHIFT (0U)
5258#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
5259#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
5260#define CAU_RADR_CA_CA2_SHIFT (0U)
5261#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
5262#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
5263#define CAU_RADR_CA_CA3_SHIFT (0U)
5264#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
5265#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
5266#define CAU_RADR_CA_CA4_SHIFT (0U)
5267#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
5268#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
5269#define CAU_RADR_CA_CA5_SHIFT (0U)
5270#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
5271#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
5272#define CAU_RADR_CA_CA6_SHIFT (0U)
5273#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
5274#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
5275#define CAU_RADR_CA_CA7_SHIFT (0U)
5276#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
5277#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
5278#define CAU_RADR_CA_CA8_SHIFT (0U)
5279#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
5282/* The count of CAU_RADR_CA */
5283#define CAU_RADR_CA_COUNT (9U)
5284
5287#define CAU_XOR_CASR_IC_MASK (0x1U)
5288#define CAU_XOR_CASR_IC_SHIFT (0U)
5293#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
5294#define CAU_XOR_CASR_DPE_MASK (0x2U)
5295#define CAU_XOR_CASR_DPE_SHIFT (1U)
5300#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
5301#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
5302#define CAU_XOR_CASR_VER_SHIFT (28U)
5307#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
5312#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
5313#define CAU_XOR_CAA_ACC_SHIFT (0U)
5314#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
5319#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
5320#define CAU_XOR_CA_CA0_SHIFT (0U)
5321#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
5322#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
5323#define CAU_XOR_CA_CA1_SHIFT (0U)
5324#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
5325#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
5326#define CAU_XOR_CA_CA2_SHIFT (0U)
5327#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
5328#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
5329#define CAU_XOR_CA_CA3_SHIFT (0U)
5330#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
5331#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
5332#define CAU_XOR_CA_CA4_SHIFT (0U)
5333#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
5334#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
5335#define CAU_XOR_CA_CA5_SHIFT (0U)
5336#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
5337#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
5338#define CAU_XOR_CA_CA6_SHIFT (0U)
5339#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
5340#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
5341#define CAU_XOR_CA_CA7_SHIFT (0U)
5342#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
5343#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
5344#define CAU_XOR_CA_CA8_SHIFT (0U)
5345#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
5348/* The count of CAU_XOR_CA */
5349#define CAU_XOR_CA_COUNT (9U)
5350
5353#define CAU_ROTL_CASR_IC_MASK (0x1U)
5354#define CAU_ROTL_CASR_IC_SHIFT (0U)
5359#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
5360#define CAU_ROTL_CASR_DPE_MASK (0x2U)
5361#define CAU_ROTL_CASR_DPE_SHIFT (1U)
5366#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
5367#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
5368#define CAU_ROTL_CASR_VER_SHIFT (28U)
5373#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
5378#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
5379#define CAU_ROTL_CAA_ACC_SHIFT (0U)
5380#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
5385#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
5386#define CAU_ROTL_CA_CA0_SHIFT (0U)
5387#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
5388#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
5389#define CAU_ROTL_CA_CA1_SHIFT (0U)
5390#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
5391#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
5392#define CAU_ROTL_CA_CA2_SHIFT (0U)
5393#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
5394#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
5395#define CAU_ROTL_CA_CA3_SHIFT (0U)
5396#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
5397#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
5398#define CAU_ROTL_CA_CA4_SHIFT (0U)
5399#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
5400#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
5401#define CAU_ROTL_CA_CA5_SHIFT (0U)
5402#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
5403#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
5404#define CAU_ROTL_CA_CA6_SHIFT (0U)
5405#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
5406#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
5407#define CAU_ROTL_CA_CA7_SHIFT (0U)
5408#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
5409#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
5410#define CAU_ROTL_CA_CA8_SHIFT (0U)
5411#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
5414/* The count of CAU_ROTL_CA */
5415#define CAU_ROTL_CA_COUNT (9U)
5416
5419#define CAU_AESC_CASR_IC_MASK (0x1U)
5420#define CAU_AESC_CASR_IC_SHIFT (0U)
5425#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
5426#define CAU_AESC_CASR_DPE_MASK (0x2U)
5427#define CAU_AESC_CASR_DPE_SHIFT (1U)
5432#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
5433#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
5434#define CAU_AESC_CASR_VER_SHIFT (28U)
5439#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
5444#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
5445#define CAU_AESC_CAA_ACC_SHIFT (0U)
5446#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
5451#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
5452#define CAU_AESC_CA_CA0_SHIFT (0U)
5453#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
5454#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
5455#define CAU_AESC_CA_CA1_SHIFT (0U)
5456#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
5457#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
5458#define CAU_AESC_CA_CA2_SHIFT (0U)
5459#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
5460#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
5461#define CAU_AESC_CA_CA3_SHIFT (0U)
5462#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
5463#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
5464#define CAU_AESC_CA_CA4_SHIFT (0U)
5465#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
5466#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
5467#define CAU_AESC_CA_CA5_SHIFT (0U)
5468#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
5469#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
5470#define CAU_AESC_CA_CA6_SHIFT (0U)
5471#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
5472#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
5473#define CAU_AESC_CA_CA7_SHIFT (0U)
5474#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
5475#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
5476#define CAU_AESC_CA_CA8_SHIFT (0U)
5477#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
5480/* The count of CAU_AESC_CA */
5481#define CAU_AESC_CA_COUNT (9U)
5482
5485#define CAU_AESIC_CASR_IC_MASK (0x1U)
5486#define CAU_AESIC_CASR_IC_SHIFT (0U)
5491#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
5492#define CAU_AESIC_CASR_DPE_MASK (0x2U)
5493#define CAU_AESIC_CASR_DPE_SHIFT (1U)
5498#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
5499#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
5500#define CAU_AESIC_CASR_VER_SHIFT (28U)
5505#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
5510#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
5511#define CAU_AESIC_CAA_ACC_SHIFT (0U)
5512#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
5517#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
5518#define CAU_AESIC_CA_CA0_SHIFT (0U)
5519#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
5520#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
5521#define CAU_AESIC_CA_CA1_SHIFT (0U)
5522#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
5523#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
5524#define CAU_AESIC_CA_CA2_SHIFT (0U)
5525#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
5526#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
5527#define CAU_AESIC_CA_CA3_SHIFT (0U)
5528#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
5529#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
5530#define CAU_AESIC_CA_CA4_SHIFT (0U)
5531#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
5532#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
5533#define CAU_AESIC_CA_CA5_SHIFT (0U)
5534#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
5535#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
5536#define CAU_AESIC_CA_CA6_SHIFT (0U)
5537#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
5538#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
5539#define CAU_AESIC_CA_CA7_SHIFT (0U)
5540#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
5541#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
5542#define CAU_AESIC_CA_CA8_SHIFT (0U)
5543#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
5546/* The count of CAU_AESIC_CA */
5547#define CAU_AESIC_CA_COUNT (9U)
5548
5549
5552 /* end of group CAU_Register_Masks */
5553
5554
5555/* CAU - Peripheral instance base addresses */
5557#define CAU_BASE (0xE0081000u)
5559#define CAU ((CAU_Type *)CAU_BASE)
5561#define CAU_BASE_ADDRS { CAU_BASE }
5563#define CAU_BASE_PTRS { CAU }
5564
5567 /* end of group CAU_Peripheral_Access_Layer */
5568
5569
5570/* ----------------------------------------------------------------------------
5571 -- CMP Peripheral Access Layer
5572 ---------------------------------------------------------------------------- */
5573
5580typedef struct {
5581 __IO uint8_t CR0;
5582 __IO uint8_t CR1;
5583 __IO uint8_t FPR;
5584 __IO uint8_t SCR;
5585 __IO uint8_t DACCR;
5586 __IO uint8_t MUXCR;
5587} CMP_Type;
5588
5589/* ----------------------------------------------------------------------------
5590 -- CMP Register Masks
5591 ---------------------------------------------------------------------------- */
5592
5600#define CMP_CR0_HYSTCTR_MASK (0x3U)
5601#define CMP_CR0_HYSTCTR_SHIFT (0U)
5608#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
5609#define CMP_CR0_FILTER_CNT_MASK (0x70U)
5610#define CMP_CR0_FILTER_CNT_SHIFT (4U)
5621#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
5626#define CMP_CR1_EN_MASK (0x1U)
5627#define CMP_CR1_EN_SHIFT (0U)
5632#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
5633#define CMP_CR1_OPE_MASK (0x2U)
5634#define CMP_CR1_OPE_SHIFT (1U)
5639#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
5640#define CMP_CR1_COS_MASK (0x4U)
5641#define CMP_CR1_COS_SHIFT (2U)
5646#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
5647#define CMP_CR1_INV_MASK (0x8U)
5648#define CMP_CR1_INV_SHIFT (3U)
5653#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
5654#define CMP_CR1_PMODE_MASK (0x10U)
5655#define CMP_CR1_PMODE_SHIFT (4U)
5660#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
5661#define CMP_CR1_TRIGM_MASK (0x20U)
5662#define CMP_CR1_TRIGM_SHIFT (5U)
5667#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
5668#define CMP_CR1_WE_MASK (0x40U)
5669#define CMP_CR1_WE_SHIFT (6U)
5674#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
5675#define CMP_CR1_SE_MASK (0x80U)
5676#define CMP_CR1_SE_SHIFT (7U)
5681#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
5686#define CMP_FPR_FILT_PER_MASK (0xFFU)
5687#define CMP_FPR_FILT_PER_SHIFT (0U)
5688#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
5693#define CMP_SCR_COUT_MASK (0x1U)
5694#define CMP_SCR_COUT_SHIFT (0U)
5695#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
5696#define CMP_SCR_CFF_MASK (0x2U)
5697#define CMP_SCR_CFF_SHIFT (1U)
5702#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
5703#define CMP_SCR_CFR_MASK (0x4U)
5704#define CMP_SCR_CFR_SHIFT (2U)
5709#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
5710#define CMP_SCR_IEF_MASK (0x8U)
5711#define CMP_SCR_IEF_SHIFT (3U)
5716#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
5717#define CMP_SCR_IER_MASK (0x10U)
5718#define CMP_SCR_IER_SHIFT (4U)
5723#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
5724#define CMP_SCR_DMAEN_MASK (0x40U)
5725#define CMP_SCR_DMAEN_SHIFT (6U)
5730#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
5735#define CMP_DACCR_VOSEL_MASK (0x3FU)
5736#define CMP_DACCR_VOSEL_SHIFT (0U)
5737#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
5738#define CMP_DACCR_VRSEL_MASK (0x40U)
5739#define CMP_DACCR_VRSEL_SHIFT (6U)
5744#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
5745#define CMP_DACCR_DACEN_MASK (0x80U)
5746#define CMP_DACCR_DACEN_SHIFT (7U)
5751#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
5756#define CMP_MUXCR_MSEL_MASK (0x7U)
5757#define CMP_MUXCR_MSEL_SHIFT (0U)
5768#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
5769#define CMP_MUXCR_PSEL_MASK (0x38U)
5770#define CMP_MUXCR_PSEL_SHIFT (3U)
5781#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
5782#define CMP_MUXCR_PSTM_MASK (0x80U)
5783#define CMP_MUXCR_PSTM_SHIFT (7U)
5788#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
5794 /* end of group CMP_Register_Masks */
5795
5796
5797/* CMP - Peripheral instance base addresses */
5799#define CMP0_BASE (0x40073000u)
5801#define CMP0 ((CMP_Type *)CMP0_BASE)
5803#define CMP1_BASE (0x40073008u)
5805#define CMP1 ((CMP_Type *)CMP1_BASE)
5807#define CMP2_BASE (0x40073010u)
5809#define CMP2 ((CMP_Type *)CMP2_BASE)
5811#define CMP3_BASE (0x40073018u)
5813#define CMP3 ((CMP_Type *)CMP3_BASE)
5815#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
5817#define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
5819#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
5820
5823 /* end of group CMP_Peripheral_Access_Layer */
5824
5825
5826/* ----------------------------------------------------------------------------
5827 -- CMT Peripheral Access Layer
5828 ---------------------------------------------------------------------------- */
5829
5836typedef struct {
5837 __IO uint8_t CGH1;
5838 __IO uint8_t CGL1;
5839 __IO uint8_t CGH2;
5840 __IO uint8_t CGL2;
5841 __IO uint8_t OC;
5842 __IO uint8_t MSC;
5843 __IO uint8_t CMD1;
5844 __IO uint8_t CMD2;
5845 __IO uint8_t CMD3;
5846 __IO uint8_t CMD4;
5847 __IO uint8_t PPS;
5848 __IO uint8_t DMA;
5849} CMT_Type;
5850
5851/* ----------------------------------------------------------------------------
5852 -- CMT Register Masks
5853 ---------------------------------------------------------------------------- */
5854
5862#define CMT_CGH1_PH_MASK (0xFFU)
5863#define CMT_CGH1_PH_SHIFT (0U)
5864#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
5869#define CMT_CGL1_PL_MASK (0xFFU)
5870#define CMT_CGL1_PL_SHIFT (0U)
5871#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
5876#define CMT_CGH2_SH_MASK (0xFFU)
5877#define CMT_CGH2_SH_SHIFT (0U)
5878#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
5883#define CMT_CGL2_SL_MASK (0xFFU)
5884#define CMT_CGL2_SL_SHIFT (0U)
5885#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
5890#define CMT_OC_IROPEN_MASK (0x20U)
5891#define CMT_OC_IROPEN_SHIFT (5U)
5896#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
5897#define CMT_OC_CMTPOL_MASK (0x40U)
5898#define CMT_OC_CMTPOL_SHIFT (6U)
5903#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
5904#define CMT_OC_IROL_MASK (0x80U)
5905#define CMT_OC_IROL_SHIFT (7U)
5906#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
5911#define CMT_MSC_MCGEN_MASK (0x1U)
5912#define CMT_MSC_MCGEN_SHIFT (0U)
5917#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
5918#define CMT_MSC_EOCIE_MASK (0x2U)
5919#define CMT_MSC_EOCIE_SHIFT (1U)
5924#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
5925#define CMT_MSC_FSK_MASK (0x4U)
5926#define CMT_MSC_FSK_SHIFT (2U)
5931#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
5932#define CMT_MSC_BASE_MASK (0x8U)
5933#define CMT_MSC_BASE_SHIFT (3U)
5938#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
5939#define CMT_MSC_EXSPC_MASK (0x10U)
5940#define CMT_MSC_EXSPC_SHIFT (4U)
5945#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
5946#define CMT_MSC_CMTDIV_MASK (0x60U)
5947#define CMT_MSC_CMTDIV_SHIFT (5U)
5954#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
5955#define CMT_MSC_EOCF_MASK (0x80U)
5956#define CMT_MSC_EOCF_SHIFT (7U)
5961#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
5966#define CMT_CMD1_MB_MASK (0xFFU)
5967#define CMT_CMD1_MB_SHIFT (0U)
5968#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
5973#define CMT_CMD2_MB_MASK (0xFFU)
5974#define CMT_CMD2_MB_SHIFT (0U)
5975#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
5980#define CMT_CMD3_SB_MASK (0xFFU)
5981#define CMT_CMD3_SB_SHIFT (0U)
5982#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
5987#define CMT_CMD4_SB_MASK (0xFFU)
5988#define CMT_CMD4_SB_SHIFT (0U)
5989#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
5994#define CMT_PPS_PPSDIV_MASK (0xFU)
5995#define CMT_PPS_PPSDIV_SHIFT (0U)
6014#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
6019#define CMT_DMA_DMA_MASK (0x1U)
6020#define CMT_DMA_DMA_SHIFT (0U)
6025#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
6031 /* end of group CMT_Register_Masks */
6032
6033
6034/* CMT - Peripheral instance base addresses */
6036#define CMT_BASE (0x40062000u)
6038#define CMT ((CMT_Type *)CMT_BASE)
6040#define CMT_BASE_ADDRS { CMT_BASE }
6042#define CMT_BASE_PTRS { CMT }
6044#define CMT_IRQS { CMT_IRQn }
6045
6048 /* end of group CMT_Peripheral_Access_Layer */
6049
6050
6051/* ----------------------------------------------------------------------------
6052 -- CRC Peripheral Access Layer
6053 ---------------------------------------------------------------------------- */
6054
6061typedef struct {
6062 union { /* offset: 0x0 */
6063 struct { /* offset: 0x0 */
6064 __IO uint16_t DATAL;
6065 __IO uint16_t DATAH;
6066 } ACCESS16BIT;
6067 __IO uint32_t DATA;
6068 struct { /* offset: 0x0 */
6069 __IO uint8_t DATALL;
6070 __IO uint8_t DATALU;
6071 __IO uint8_t DATAHL;
6072 __IO uint8_t DATAHU;
6073 } ACCESS8BIT;
6074 };
6075 union { /* offset: 0x4 */
6076 struct { /* offset: 0x4 */
6077 __IO uint16_t GPOLYL;
6078 __IO uint16_t GPOLYH;
6079 } GPOLY_ACCESS16BIT;
6080 __IO uint32_t GPOLY;
6081 struct { /* offset: 0x4 */
6082 __IO uint8_t GPOLYLL;
6083 __IO uint8_t GPOLYLU;
6084 __IO uint8_t GPOLYHL;
6085 __IO uint8_t GPOLYHU;
6086 } GPOLY_ACCESS8BIT;
6087 };
6088 union { /* offset: 0x8 */
6089 __IO uint32_t CTRL;
6090 struct { /* offset: 0x8 */
6091 uint8_t RESERVED_0[3];
6092 __IO uint8_t CTRLHU;
6093 } CTRL_ACCESS8BIT;
6094 };
6095} CRC_Type;
6096
6097/* ----------------------------------------------------------------------------
6098 -- CRC Register Masks
6099 ---------------------------------------------------------------------------- */
6100
6108#define CRC_DATAL_DATAL_MASK (0xFFFFU)
6109#define CRC_DATAL_DATAL_SHIFT (0U)
6110#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
6115#define CRC_DATAH_DATAH_MASK (0xFFFFU)
6116#define CRC_DATAH_DATAH_SHIFT (0U)
6117#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
6122#define CRC_DATA_LL_MASK (0xFFU)
6123#define CRC_DATA_LL_SHIFT (0U)
6124#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
6125#define CRC_DATA_LU_MASK (0xFF00U)
6126#define CRC_DATA_LU_SHIFT (8U)
6127#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
6128#define CRC_DATA_HL_MASK (0xFF0000U)
6129#define CRC_DATA_HL_SHIFT (16U)
6130#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
6131#define CRC_DATA_HU_MASK (0xFF000000U)
6132#define CRC_DATA_HU_SHIFT (24U)
6133#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
6138#define CRC_DATALL_DATALL_MASK (0xFFU)
6139#define CRC_DATALL_DATALL_SHIFT (0U)
6140#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
6145#define CRC_DATALU_DATALU_MASK (0xFFU)
6146#define CRC_DATALU_DATALU_SHIFT (0U)
6147#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
6152#define CRC_DATAHL_DATAHL_MASK (0xFFU)
6153#define CRC_DATAHL_DATAHL_SHIFT (0U)
6154#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
6159#define CRC_DATAHU_DATAHU_MASK (0xFFU)
6160#define CRC_DATAHU_DATAHU_SHIFT (0U)
6161#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
6166#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
6167#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
6168#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
6173#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
6174#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
6175#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
6180#define CRC_GPOLY_LOW_MASK (0xFFFFU)
6181#define CRC_GPOLY_LOW_SHIFT (0U)
6182#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
6183#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
6184#define CRC_GPOLY_HIGH_SHIFT (16U)
6185#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
6190#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
6191#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
6192#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
6197#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
6198#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
6199#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
6204#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
6205#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
6206#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
6211#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
6212#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
6213#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
6218#define CRC_CTRL_TCRC_MASK (0x1000000U)
6219#define CRC_CTRL_TCRC_SHIFT (24U)
6224#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
6225#define CRC_CTRL_WAS_MASK (0x2000000U)
6226#define CRC_CTRL_WAS_SHIFT (25U)
6231#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
6232#define CRC_CTRL_FXOR_MASK (0x4000000U)
6233#define CRC_CTRL_FXOR_SHIFT (26U)
6238#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
6239#define CRC_CTRL_TOTR_MASK (0x30000000U)
6240#define CRC_CTRL_TOTR_SHIFT (28U)
6247#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
6248#define CRC_CTRL_TOT_MASK (0xC0000000U)
6249#define CRC_CTRL_TOT_SHIFT (30U)
6256#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
6261#define CRC_CTRLHU_TCRC_MASK (0x1U)
6262#define CRC_CTRLHU_TCRC_SHIFT (0U)
6267#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
6268#define CRC_CTRLHU_WAS_MASK (0x2U)
6269#define CRC_CTRLHU_WAS_SHIFT (1U)
6274#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
6275#define CRC_CTRLHU_FXOR_MASK (0x4U)
6276#define CRC_CTRLHU_FXOR_SHIFT (2U)
6281#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
6282#define CRC_CTRLHU_TOTR_MASK (0x30U)
6283#define CRC_CTRLHU_TOTR_SHIFT (4U)
6290#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
6291#define CRC_CTRLHU_TOT_MASK (0xC0U)
6292#define CRC_CTRLHU_TOT_SHIFT (6U)
6299#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
6305 /* end of group CRC_Register_Masks */
6306
6307
6308/* CRC - Peripheral instance base addresses */
6310#define CRC_BASE (0x40032000u)
6312#define CRC0 ((CRC_Type *)CRC_BASE)
6314#define CRC_BASE_ADDRS { CRC_BASE }
6316#define CRC_BASE_PTRS { CRC0 }
6317
6320 /* end of group CRC_Peripheral_Access_Layer */
6321
6322
6323/* ----------------------------------------------------------------------------
6324 -- DAC Peripheral Access Layer
6325 ---------------------------------------------------------------------------- */
6326
6333typedef struct {
6334 struct { /* offset: 0x0, array step: 0x2 */
6335 __IO uint8_t DATL;
6336 __IO uint8_t DATH;
6337 } DAT[16];
6338 __IO uint8_t SR;
6339 __IO uint8_t C0;
6340 __IO uint8_t C1;
6341 __IO uint8_t C2;
6342} DAC_Type;
6343
6344/* ----------------------------------------------------------------------------
6345 -- DAC Register Masks
6346 ---------------------------------------------------------------------------- */
6347
6355#define DAC_DATL_DATA0_MASK (0xFFU)
6356#define DAC_DATL_DATA0_SHIFT (0U)
6357#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
6360/* The count of DAC_DATL */
6361#define DAC_DATL_COUNT (16U)
6362
6365#define DAC_DATH_DATA1_MASK (0xFU)
6366#define DAC_DATH_DATA1_SHIFT (0U)
6367#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
6370/* The count of DAC_DATH */
6371#define DAC_DATH_COUNT (16U)
6372
6375#define DAC_SR_DACBFRPBF_MASK (0x1U)
6376#define DAC_SR_DACBFRPBF_SHIFT (0U)
6381#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
6382#define DAC_SR_DACBFRPTF_MASK (0x2U)
6383#define DAC_SR_DACBFRPTF_SHIFT (1U)
6388#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
6389#define DAC_SR_DACBFWMF_MASK (0x4U)
6390#define DAC_SR_DACBFWMF_SHIFT (2U)
6395#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
6400#define DAC_C0_DACBBIEN_MASK (0x1U)
6401#define DAC_C0_DACBBIEN_SHIFT (0U)
6406#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
6407#define DAC_C0_DACBTIEN_MASK (0x2U)
6408#define DAC_C0_DACBTIEN_SHIFT (1U)
6413#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
6414#define DAC_C0_DACBWIEN_MASK (0x4U)
6415#define DAC_C0_DACBWIEN_SHIFT (2U)
6420#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
6421#define DAC_C0_LPEN_MASK (0x8U)
6422#define DAC_C0_LPEN_SHIFT (3U)
6427#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
6428#define DAC_C0_DACSWTRG_MASK (0x10U)
6429#define DAC_C0_DACSWTRG_SHIFT (4U)
6434#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
6435#define DAC_C0_DACTRGSEL_MASK (0x20U)
6436#define DAC_C0_DACTRGSEL_SHIFT (5U)
6441#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
6442#define DAC_C0_DACRFS_MASK (0x40U)
6443#define DAC_C0_DACRFS_SHIFT (6U)
6448#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
6449#define DAC_C0_DACEN_MASK (0x80U)
6450#define DAC_C0_DACEN_SHIFT (7U)
6455#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
6460#define DAC_C1_DACBFEN_MASK (0x1U)
6461#define DAC_C1_DACBFEN_SHIFT (0U)
6466#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
6467#define DAC_C1_DACBFMD_MASK (0x6U)
6468#define DAC_C1_DACBFMD_SHIFT (1U)
6475#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
6476#define DAC_C1_DACBFWM_MASK (0x18U)
6477#define DAC_C1_DACBFWM_SHIFT (3U)
6484#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
6485#define DAC_C1_DMAEN_MASK (0x80U)
6486#define DAC_C1_DMAEN_SHIFT (7U)
6491#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
6496#define DAC_C2_DACBFUP_MASK (0xFU)
6497#define DAC_C2_DACBFUP_SHIFT (0U)
6498#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
6499#define DAC_C2_DACBFRP_MASK (0xF0U)
6500#define DAC_C2_DACBFRP_SHIFT (4U)
6501#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
6507 /* end of group DAC_Register_Masks */
6508
6509
6510/* DAC - Peripheral instance base addresses */
6512#define DAC0_BASE (0x400CC000u)
6514#define DAC0 ((DAC_Type *)DAC0_BASE)
6516#define DAC1_BASE (0x400CD000u)
6518#define DAC1 ((DAC_Type *)DAC1_BASE)
6520#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
6522#define DAC_BASE_PTRS { DAC0, DAC1 }
6524#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
6525
6528 /* end of group DAC_Peripheral_Access_Layer */
6529
6530
6531/* ----------------------------------------------------------------------------
6532 -- DMA Peripheral Access Layer
6533 ---------------------------------------------------------------------------- */
6534
6541typedef struct {
6542 __IO uint32_t CR;
6543 __I uint32_t ES;
6544 uint8_t RESERVED_0[4];
6545 __IO uint32_t ERQ;
6546 uint8_t RESERVED_1[4];
6547 __IO uint32_t EEI;
6548 __O uint8_t CEEI;
6549 __O uint8_t SEEI;
6550 __O uint8_t CERQ;
6551 __O uint8_t SERQ;
6552 __O uint8_t CDNE;
6553 __O uint8_t SSRT;
6554 __O uint8_t CERR;
6555 __O uint8_t CINT;
6556 uint8_t RESERVED_2[4];
6557 __IO uint32_t INT;
6558 uint8_t RESERVED_3[4];
6559 __IO uint32_t ERR;
6560 uint8_t RESERVED_4[4];
6561 __I uint32_t HRS;
6562 uint8_t RESERVED_5[12];
6563 __IO uint32_t EARS;
6564 uint8_t RESERVED_6[184];
6565 __IO uint8_t DCHPRI3;
6566 __IO uint8_t DCHPRI2;
6567 __IO uint8_t DCHPRI1;
6568 __IO uint8_t DCHPRI0;
6569 __IO uint8_t DCHPRI7;
6570 __IO uint8_t DCHPRI6;
6571 __IO uint8_t DCHPRI5;
6572 __IO uint8_t DCHPRI4;
6573 __IO uint8_t DCHPRI11;
6574 __IO uint8_t DCHPRI10;
6575 __IO uint8_t DCHPRI9;
6576 __IO uint8_t DCHPRI8;
6577 __IO uint8_t DCHPRI15;
6578 __IO uint8_t DCHPRI14;
6579 __IO uint8_t DCHPRI13;
6580 __IO uint8_t DCHPRI12;
6581 __IO uint8_t DCHPRI19;
6582 __IO uint8_t DCHPRI18;
6583 __IO uint8_t DCHPRI17;
6584 __IO uint8_t DCHPRI16;
6585 __IO uint8_t DCHPRI23;
6586 __IO uint8_t DCHPRI22;
6587 __IO uint8_t DCHPRI21;
6588 __IO uint8_t DCHPRI20;
6589 __IO uint8_t DCHPRI27;
6590 __IO uint8_t DCHPRI26;
6591 __IO uint8_t DCHPRI25;
6592 __IO uint8_t DCHPRI24;
6593 __IO uint8_t DCHPRI31;
6594 __IO uint8_t DCHPRI30;
6595 __IO uint8_t DCHPRI29;
6596 __IO uint8_t DCHPRI28;
6597 uint8_t RESERVED_7[3808];
6598 struct { /* offset: 0x1000, array step: 0x20 */
6599 __IO uint32_t SADDR;
6600 __IO uint16_t SOFF;
6601 __IO uint16_t ATTR;
6602 union { /* offset: 0x1008, array step: 0x20 */
6603 __IO uint32_t NBYTES_MLNO;
6604 __IO uint32_t NBYTES_MLOFFNO;
6605 __IO uint32_t NBYTES_MLOFFYES;
6606 };
6607 __IO uint32_t SLAST;
6608 __IO uint32_t DADDR;
6609 __IO uint16_t DOFF;
6610 union { /* offset: 0x1016, array step: 0x20 */
6611 __IO uint16_t CITER_ELINKNO;
6612 __IO uint16_t CITER_ELINKYES;
6613 };
6614 __IO uint32_t DLAST_SGA;
6615 __IO uint16_t CSR;
6616 union { /* offset: 0x101E, array step: 0x20 */
6617 __IO uint16_t BITER_ELINKNO;
6618 __IO uint16_t BITER_ELINKYES;
6619 };
6620 } TCD[32];
6621} DMA_Type;
6622
6623/* ----------------------------------------------------------------------------
6624 -- DMA Register Masks
6625 ---------------------------------------------------------------------------- */
6626
6634#define DMA_CR_EDBG_MASK (0x2U)
6635#define DMA_CR_EDBG_SHIFT (1U)
6640#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
6641#define DMA_CR_ERCA_MASK (0x4U)
6642#define DMA_CR_ERCA_SHIFT (2U)
6647#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
6648#define DMA_CR_ERGA_MASK (0x8U)
6649#define DMA_CR_ERGA_SHIFT (3U)
6654#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
6655#define DMA_CR_HOE_MASK (0x10U)
6656#define DMA_CR_HOE_SHIFT (4U)
6661#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
6662#define DMA_CR_HALT_MASK (0x20U)
6663#define DMA_CR_HALT_SHIFT (5U)
6668#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
6669#define DMA_CR_CLM_MASK (0x40U)
6670#define DMA_CR_CLM_SHIFT (6U)
6675#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
6676#define DMA_CR_EMLM_MASK (0x80U)
6677#define DMA_CR_EMLM_SHIFT (7U)
6682#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
6683#define DMA_CR_GRP0PRI_MASK (0x100U)
6684#define DMA_CR_GRP0PRI_SHIFT (8U)
6685#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
6686#define DMA_CR_GRP1PRI_MASK (0x400U)
6687#define DMA_CR_GRP1PRI_SHIFT (10U)
6688#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
6689#define DMA_CR_ECX_MASK (0x10000U)
6690#define DMA_CR_ECX_SHIFT (16U)
6695#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
6696#define DMA_CR_CX_MASK (0x20000U)
6697#define DMA_CR_CX_SHIFT (17U)
6702#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
6707#define DMA_ES_DBE_MASK (0x1U)
6708#define DMA_ES_DBE_SHIFT (0U)
6713#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
6714#define DMA_ES_SBE_MASK (0x2U)
6715#define DMA_ES_SBE_SHIFT (1U)
6720#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
6721#define DMA_ES_SGE_MASK (0x4U)
6722#define DMA_ES_SGE_SHIFT (2U)
6727#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
6728#define DMA_ES_NCE_MASK (0x8U)
6729#define DMA_ES_NCE_SHIFT (3U)
6734#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
6735#define DMA_ES_DOE_MASK (0x10U)
6736#define DMA_ES_DOE_SHIFT (4U)
6741#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
6742#define DMA_ES_DAE_MASK (0x20U)
6743#define DMA_ES_DAE_SHIFT (5U)
6748#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
6749#define DMA_ES_SOE_MASK (0x40U)
6750#define DMA_ES_SOE_SHIFT (6U)
6755#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
6756#define DMA_ES_SAE_MASK (0x80U)
6757#define DMA_ES_SAE_SHIFT (7U)
6762#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
6763#define DMA_ES_ERRCHN_MASK (0x1F00U)
6764#define DMA_ES_ERRCHN_SHIFT (8U)
6765#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
6766#define DMA_ES_CPE_MASK (0x4000U)
6767#define DMA_ES_CPE_SHIFT (14U)
6772#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
6773#define DMA_ES_GPE_MASK (0x8000U)
6774#define DMA_ES_GPE_SHIFT (15U)
6779#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
6780#define DMA_ES_ECX_MASK (0x10000U)
6781#define DMA_ES_ECX_SHIFT (16U)
6786#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
6787#define DMA_ES_VLD_MASK (0x80000000U)
6788#define DMA_ES_VLD_SHIFT (31U)
6793#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
6798#define DMA_ERQ_ERQ0_MASK (0x1U)
6799#define DMA_ERQ_ERQ0_SHIFT (0U)
6804#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
6805#define DMA_ERQ_ERQ1_MASK (0x2U)
6806#define DMA_ERQ_ERQ1_SHIFT (1U)
6811#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
6812#define DMA_ERQ_ERQ2_MASK (0x4U)
6813#define DMA_ERQ_ERQ2_SHIFT (2U)
6818#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
6819#define DMA_ERQ_ERQ3_MASK (0x8U)
6820#define DMA_ERQ_ERQ3_SHIFT (3U)
6825#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
6826#define DMA_ERQ_ERQ4_MASK (0x10U)
6827#define DMA_ERQ_ERQ4_SHIFT (4U)
6832#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
6833#define DMA_ERQ_ERQ5_MASK (0x20U)
6834#define DMA_ERQ_ERQ5_SHIFT (5U)
6839#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
6840#define DMA_ERQ_ERQ6_MASK (0x40U)
6841#define DMA_ERQ_ERQ6_SHIFT (6U)
6846#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
6847#define DMA_ERQ_ERQ7_MASK (0x80U)
6848#define DMA_ERQ_ERQ7_SHIFT (7U)
6853#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
6854#define DMA_ERQ_ERQ8_MASK (0x100U)
6855#define DMA_ERQ_ERQ8_SHIFT (8U)
6860#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
6861#define DMA_ERQ_ERQ9_MASK (0x200U)
6862#define DMA_ERQ_ERQ9_SHIFT (9U)
6867#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
6868#define DMA_ERQ_ERQ10_MASK (0x400U)
6869#define DMA_ERQ_ERQ10_SHIFT (10U)
6874#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
6875#define DMA_ERQ_ERQ11_MASK (0x800U)
6876#define DMA_ERQ_ERQ11_SHIFT (11U)
6881#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
6882#define DMA_ERQ_ERQ12_MASK (0x1000U)
6883#define DMA_ERQ_ERQ12_SHIFT (12U)
6888#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
6889#define DMA_ERQ_ERQ13_MASK (0x2000U)
6890#define DMA_ERQ_ERQ13_SHIFT (13U)
6895#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
6896#define DMA_ERQ_ERQ14_MASK (0x4000U)
6897#define DMA_ERQ_ERQ14_SHIFT (14U)
6902#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
6903#define DMA_ERQ_ERQ15_MASK (0x8000U)
6904#define DMA_ERQ_ERQ15_SHIFT (15U)
6909#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
6910#define DMA_ERQ_ERQ16_MASK (0x10000U)
6911#define DMA_ERQ_ERQ16_SHIFT (16U)
6916#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
6917#define DMA_ERQ_ERQ17_MASK (0x20000U)
6918#define DMA_ERQ_ERQ17_SHIFT (17U)
6923#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
6924#define DMA_ERQ_ERQ18_MASK (0x40000U)
6925#define DMA_ERQ_ERQ18_SHIFT (18U)
6930#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
6931#define DMA_ERQ_ERQ19_MASK (0x80000U)
6932#define DMA_ERQ_ERQ19_SHIFT (19U)
6937#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
6938#define DMA_ERQ_ERQ20_MASK (0x100000U)
6939#define DMA_ERQ_ERQ20_SHIFT (20U)
6944#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
6945#define DMA_ERQ_ERQ21_MASK (0x200000U)
6946#define DMA_ERQ_ERQ21_SHIFT (21U)
6951#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
6952#define DMA_ERQ_ERQ22_MASK (0x400000U)
6953#define DMA_ERQ_ERQ22_SHIFT (22U)
6958#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
6959#define DMA_ERQ_ERQ23_MASK (0x800000U)
6960#define DMA_ERQ_ERQ23_SHIFT (23U)
6965#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
6966#define DMA_ERQ_ERQ24_MASK (0x1000000U)
6967#define DMA_ERQ_ERQ24_SHIFT (24U)
6972#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
6973#define DMA_ERQ_ERQ25_MASK (0x2000000U)
6974#define DMA_ERQ_ERQ25_SHIFT (25U)
6979#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
6980#define DMA_ERQ_ERQ26_MASK (0x4000000U)
6981#define DMA_ERQ_ERQ26_SHIFT (26U)
6986#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
6987#define DMA_ERQ_ERQ27_MASK (0x8000000U)
6988#define DMA_ERQ_ERQ27_SHIFT (27U)
6993#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
6994#define DMA_ERQ_ERQ28_MASK (0x10000000U)
6995#define DMA_ERQ_ERQ28_SHIFT (28U)
7000#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
7001#define DMA_ERQ_ERQ29_MASK (0x20000000U)
7002#define DMA_ERQ_ERQ29_SHIFT (29U)
7007#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
7008#define DMA_ERQ_ERQ30_MASK (0x40000000U)
7009#define DMA_ERQ_ERQ30_SHIFT (30U)
7014#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
7015#define DMA_ERQ_ERQ31_MASK (0x80000000U)
7016#define DMA_ERQ_ERQ31_SHIFT (31U)
7021#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
7026#define DMA_EEI_EEI0_MASK (0x1U)
7027#define DMA_EEI_EEI0_SHIFT (0U)
7032#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
7033#define DMA_EEI_EEI1_MASK (0x2U)
7034#define DMA_EEI_EEI1_SHIFT (1U)
7039#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
7040#define DMA_EEI_EEI2_MASK (0x4U)
7041#define DMA_EEI_EEI2_SHIFT (2U)
7046#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
7047#define DMA_EEI_EEI3_MASK (0x8U)
7048#define DMA_EEI_EEI3_SHIFT (3U)
7053#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
7054#define DMA_EEI_EEI4_MASK (0x10U)
7055#define DMA_EEI_EEI4_SHIFT (4U)
7060#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
7061#define DMA_EEI_EEI5_MASK (0x20U)
7062#define DMA_EEI_EEI5_SHIFT (5U)
7067#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
7068#define DMA_EEI_EEI6_MASK (0x40U)
7069#define DMA_EEI_EEI6_SHIFT (6U)
7074#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
7075#define DMA_EEI_EEI7_MASK (0x80U)
7076#define DMA_EEI_EEI7_SHIFT (7U)
7081#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
7082#define DMA_EEI_EEI8_MASK (0x100U)
7083#define DMA_EEI_EEI8_SHIFT (8U)
7088#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
7089#define DMA_EEI_EEI9_MASK (0x200U)
7090#define DMA_EEI_EEI9_SHIFT (9U)
7095#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
7096#define DMA_EEI_EEI10_MASK (0x400U)
7097#define DMA_EEI_EEI10_SHIFT (10U)
7102#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
7103#define DMA_EEI_EEI11_MASK (0x800U)
7104#define DMA_EEI_EEI11_SHIFT (11U)
7109#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
7110#define DMA_EEI_EEI12_MASK (0x1000U)
7111#define DMA_EEI_EEI12_SHIFT (12U)
7116#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
7117#define DMA_EEI_EEI13_MASK (0x2000U)
7118#define DMA_EEI_EEI13_SHIFT (13U)
7123#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
7124#define DMA_EEI_EEI14_MASK (0x4000U)
7125#define DMA_EEI_EEI14_SHIFT (14U)
7130#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
7131#define DMA_EEI_EEI15_MASK (0x8000U)
7132#define DMA_EEI_EEI15_SHIFT (15U)
7137#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
7138#define DMA_EEI_EEI16_MASK (0x10000U)
7139#define DMA_EEI_EEI16_SHIFT (16U)
7144#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
7145#define DMA_EEI_EEI17_MASK (0x20000U)
7146#define DMA_EEI_EEI17_SHIFT (17U)
7151#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
7152#define DMA_EEI_EEI18_MASK (0x40000U)
7153#define DMA_EEI_EEI18_SHIFT (18U)
7158#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
7159#define DMA_EEI_EEI19_MASK (0x80000U)
7160#define DMA_EEI_EEI19_SHIFT (19U)
7165#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
7166#define DMA_EEI_EEI20_MASK (0x100000U)
7167#define DMA_EEI_EEI20_SHIFT (20U)
7172#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
7173#define DMA_EEI_EEI21_MASK (0x200000U)
7174#define DMA_EEI_EEI21_SHIFT (21U)
7179#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
7180#define DMA_EEI_EEI22_MASK (0x400000U)
7181#define DMA_EEI_EEI22_SHIFT (22U)
7186#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
7187#define DMA_EEI_EEI23_MASK (0x800000U)
7188#define DMA_EEI_EEI23_SHIFT (23U)
7193#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
7194#define DMA_EEI_EEI24_MASK (0x1000000U)
7195#define DMA_EEI_EEI24_SHIFT (24U)
7200#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
7201#define DMA_EEI_EEI25_MASK (0x2000000U)
7202#define DMA_EEI_EEI25_SHIFT (25U)
7207#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
7208#define DMA_EEI_EEI26_MASK (0x4000000U)
7209#define DMA_EEI_EEI26_SHIFT (26U)
7214#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
7215#define DMA_EEI_EEI27_MASK (0x8000000U)
7216#define DMA_EEI_EEI27_SHIFT (27U)
7221#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
7222#define DMA_EEI_EEI28_MASK (0x10000000U)
7223#define DMA_EEI_EEI28_SHIFT (28U)
7228#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
7229#define DMA_EEI_EEI29_MASK (0x20000000U)
7230#define DMA_EEI_EEI29_SHIFT (29U)
7235#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
7236#define DMA_EEI_EEI30_MASK (0x40000000U)
7237#define DMA_EEI_EEI30_SHIFT (30U)
7242#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
7243#define DMA_EEI_EEI31_MASK (0x80000000U)
7244#define DMA_EEI_EEI31_SHIFT (31U)
7249#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
7254#define DMA_CEEI_CEEI_MASK (0x1FU)
7255#define DMA_CEEI_CEEI_SHIFT (0U)
7256#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
7257#define DMA_CEEI_CAEE_MASK (0x40U)
7258#define DMA_CEEI_CAEE_SHIFT (6U)
7263#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
7264#define DMA_CEEI_NOP_MASK (0x80U)
7265#define DMA_CEEI_NOP_SHIFT (7U)
7270#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
7275#define DMA_SEEI_SEEI_MASK (0x1FU)
7276#define DMA_SEEI_SEEI_SHIFT (0U)
7277#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
7278#define DMA_SEEI_SAEE_MASK (0x40U)
7279#define DMA_SEEI_SAEE_SHIFT (6U)
7284#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
7285#define DMA_SEEI_NOP_MASK (0x80U)
7286#define DMA_SEEI_NOP_SHIFT (7U)
7291#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
7296#define DMA_CERQ_CERQ_MASK (0x1FU)
7297#define DMA_CERQ_CERQ_SHIFT (0U)
7298#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
7299#define DMA_CERQ_CAER_MASK (0x40U)
7300#define DMA_CERQ_CAER_SHIFT (6U)
7305#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
7306#define DMA_CERQ_NOP_MASK (0x80U)
7307#define DMA_CERQ_NOP_SHIFT (7U)
7312#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
7317#define DMA_SERQ_SERQ_MASK (0x1FU)
7318#define DMA_SERQ_SERQ_SHIFT (0U)
7319#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
7320#define DMA_SERQ_SAER_MASK (0x40U)
7321#define DMA_SERQ_SAER_SHIFT (6U)
7326#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
7327#define DMA_SERQ_NOP_MASK (0x80U)
7328#define DMA_SERQ_NOP_SHIFT (7U)
7333#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
7338#define DMA_CDNE_CDNE_MASK (0x1FU)
7339#define DMA_CDNE_CDNE_SHIFT (0U)
7340#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
7341#define DMA_CDNE_CADN_MASK (0x40U)
7342#define DMA_CDNE_CADN_SHIFT (6U)
7347#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
7348#define DMA_CDNE_NOP_MASK (0x80U)
7349#define DMA_CDNE_NOP_SHIFT (7U)
7354#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
7359#define DMA_SSRT_SSRT_MASK (0x1FU)
7360#define DMA_SSRT_SSRT_SHIFT (0U)
7361#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
7362#define DMA_SSRT_SAST_MASK (0x40U)
7363#define DMA_SSRT_SAST_SHIFT (6U)
7368#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
7369#define DMA_SSRT_NOP_MASK (0x80U)
7370#define DMA_SSRT_NOP_SHIFT (7U)
7375#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
7380#define DMA_CERR_CERR_MASK (0x1FU)
7381#define DMA_CERR_CERR_SHIFT (0U)
7382#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
7383#define DMA_CERR_CAEI_MASK (0x40U)
7384#define DMA_CERR_CAEI_SHIFT (6U)
7389#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
7390#define DMA_CERR_NOP_MASK (0x80U)
7391#define DMA_CERR_NOP_SHIFT (7U)
7396#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
7401#define DMA_CINT_CINT_MASK (0x1FU)
7402#define DMA_CINT_CINT_SHIFT (0U)
7403#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
7404#define DMA_CINT_CAIR_MASK (0x40U)
7405#define DMA_CINT_CAIR_SHIFT (6U)
7410#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
7411#define DMA_CINT_NOP_MASK (0x80U)
7412#define DMA_CINT_NOP_SHIFT (7U)
7417#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
7422#define DMA_INT_INT0_MASK (0x1U)
7423#define DMA_INT_INT0_SHIFT (0U)
7428#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
7429#define DMA_INT_INT1_MASK (0x2U)
7430#define DMA_INT_INT1_SHIFT (1U)
7435#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
7436#define DMA_INT_INT2_MASK (0x4U)
7437#define DMA_INT_INT2_SHIFT (2U)
7442#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
7443#define DMA_INT_INT3_MASK (0x8U)
7444#define DMA_INT_INT3_SHIFT (3U)
7449#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
7450#define DMA_INT_INT4_MASK (0x10U)
7451#define DMA_INT_INT4_SHIFT (4U)
7456#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
7457#define DMA_INT_INT5_MASK (0x20U)
7458#define DMA_INT_INT5_SHIFT (5U)
7463#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
7464#define DMA_INT_INT6_MASK (0x40U)
7465#define DMA_INT_INT6_SHIFT (6U)
7470#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
7471#define DMA_INT_INT7_MASK (0x80U)
7472#define DMA_INT_INT7_SHIFT (7U)
7477#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
7478#define DMA_INT_INT8_MASK (0x100U)
7479#define DMA_INT_INT8_SHIFT (8U)
7484#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
7485#define DMA_INT_INT9_MASK (0x200U)
7486#define DMA_INT_INT9_SHIFT (9U)
7491#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
7492#define DMA_INT_INT10_MASK (0x400U)
7493#define DMA_INT_INT10_SHIFT (10U)
7498#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
7499#define DMA_INT_INT11_MASK (0x800U)
7500#define DMA_INT_INT11_SHIFT (11U)
7505#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
7506#define DMA_INT_INT12_MASK (0x1000U)
7507#define DMA_INT_INT12_SHIFT (12U)
7512#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
7513#define DMA_INT_INT13_MASK (0x2000U)
7514#define DMA_INT_INT13_SHIFT (13U)
7519#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
7520#define DMA_INT_INT14_MASK (0x4000U)
7521#define DMA_INT_INT14_SHIFT (14U)
7526#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
7527#define DMA_INT_INT15_MASK (0x8000U)
7528#define DMA_INT_INT15_SHIFT (15U)
7533#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
7534#define DMA_INT_INT16_MASK (0x10000U)
7535#define DMA_INT_INT16_SHIFT (16U)
7540#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
7541#define DMA_INT_INT17_MASK (0x20000U)
7542#define DMA_INT_INT17_SHIFT (17U)
7547#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
7548#define DMA_INT_INT18_MASK (0x40000U)
7549#define DMA_INT_INT18_SHIFT (18U)
7554#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
7555#define DMA_INT_INT19_MASK (0x80000U)
7556#define DMA_INT_INT19_SHIFT (19U)
7561#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
7562#define DMA_INT_INT20_MASK (0x100000U)
7563#define DMA_INT_INT20_SHIFT (20U)
7568#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
7569#define DMA_INT_INT21_MASK (0x200000U)
7570#define DMA_INT_INT21_SHIFT (21U)
7575#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
7576#define DMA_INT_INT22_MASK (0x400000U)
7577#define DMA_INT_INT22_SHIFT (22U)
7582#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
7583#define DMA_INT_INT23_MASK (0x800000U)
7584#define DMA_INT_INT23_SHIFT (23U)
7589#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
7590#define DMA_INT_INT24_MASK (0x1000000U)
7591#define DMA_INT_INT24_SHIFT (24U)
7596#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
7597#define DMA_INT_INT25_MASK (0x2000000U)
7598#define DMA_INT_INT25_SHIFT (25U)
7603#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
7604#define DMA_INT_INT26_MASK (0x4000000U)
7605#define DMA_INT_INT26_SHIFT (26U)
7610#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
7611#define DMA_INT_INT27_MASK (0x8000000U)
7612#define DMA_INT_INT27_SHIFT (27U)
7617#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
7618#define DMA_INT_INT28_MASK (0x10000000U)
7619#define DMA_INT_INT28_SHIFT (28U)
7624#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
7625#define DMA_INT_INT29_MASK (0x20000000U)
7626#define DMA_INT_INT29_SHIFT (29U)
7631#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
7632#define DMA_INT_INT30_MASK (0x40000000U)
7633#define DMA_INT_INT30_SHIFT (30U)
7638#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
7639#define DMA_INT_INT31_MASK (0x80000000U)
7640#define DMA_INT_INT31_SHIFT (31U)
7645#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
7650#define DMA_ERR_ERR0_MASK (0x1U)
7651#define DMA_ERR_ERR0_SHIFT (0U)
7656#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
7657#define DMA_ERR_ERR1_MASK (0x2U)
7658#define DMA_ERR_ERR1_SHIFT (1U)
7663#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
7664#define DMA_ERR_ERR2_MASK (0x4U)
7665#define DMA_ERR_ERR2_SHIFT (2U)
7670#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
7671#define DMA_ERR_ERR3_MASK (0x8U)
7672#define DMA_ERR_ERR3_SHIFT (3U)
7677#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
7678#define DMA_ERR_ERR4_MASK (0x10U)
7679#define DMA_ERR_ERR4_SHIFT (4U)
7684#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
7685#define DMA_ERR_ERR5_MASK (0x20U)
7686#define DMA_ERR_ERR5_SHIFT (5U)
7691#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
7692#define DMA_ERR_ERR6_MASK (0x40U)
7693#define DMA_ERR_ERR6_SHIFT (6U)
7698#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
7699#define DMA_ERR_ERR7_MASK (0x80U)
7700#define DMA_ERR_ERR7_SHIFT (7U)
7705#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
7706#define DMA_ERR_ERR8_MASK (0x100U)
7707#define DMA_ERR_ERR8_SHIFT (8U)
7712#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
7713#define DMA_ERR_ERR9_MASK (0x200U)
7714#define DMA_ERR_ERR9_SHIFT (9U)
7719#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
7720#define DMA_ERR_ERR10_MASK (0x400U)
7721#define DMA_ERR_ERR10_SHIFT (10U)
7726#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
7727#define DMA_ERR_ERR11_MASK (0x800U)
7728#define DMA_ERR_ERR11_SHIFT (11U)
7733#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
7734#define DMA_ERR_ERR12_MASK (0x1000U)
7735#define DMA_ERR_ERR12_SHIFT (12U)
7740#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
7741#define DMA_ERR_ERR13_MASK (0x2000U)
7742#define DMA_ERR_ERR13_SHIFT (13U)
7747#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
7748#define DMA_ERR_ERR14_MASK (0x4000U)
7749#define DMA_ERR_ERR14_SHIFT (14U)
7754#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
7755#define DMA_ERR_ERR15_MASK (0x8000U)
7756#define DMA_ERR_ERR15_SHIFT (15U)
7761#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
7762#define DMA_ERR_ERR16_MASK (0x10000U)
7763#define DMA_ERR_ERR16_SHIFT (16U)
7768#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
7769#define DMA_ERR_ERR17_MASK (0x20000U)
7770#define DMA_ERR_ERR17_SHIFT (17U)
7775#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
7776#define DMA_ERR_ERR18_MASK (0x40000U)
7777#define DMA_ERR_ERR18_SHIFT (18U)
7782#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
7783#define DMA_ERR_ERR19_MASK (0x80000U)
7784#define DMA_ERR_ERR19_SHIFT (19U)
7789#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
7790#define DMA_ERR_ERR20_MASK (0x100000U)
7791#define DMA_ERR_ERR20_SHIFT (20U)
7796#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
7797#define DMA_ERR_ERR21_MASK (0x200000U)
7798#define DMA_ERR_ERR21_SHIFT (21U)
7803#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
7804#define DMA_ERR_ERR22_MASK (0x400000U)
7805#define DMA_ERR_ERR22_SHIFT (22U)
7810#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
7811#define DMA_ERR_ERR23_MASK (0x800000U)
7812#define DMA_ERR_ERR23_SHIFT (23U)
7817#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
7818#define DMA_ERR_ERR24_MASK (0x1000000U)
7819#define DMA_ERR_ERR24_SHIFT (24U)
7824#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
7825#define DMA_ERR_ERR25_MASK (0x2000000U)
7826#define DMA_ERR_ERR25_SHIFT (25U)
7831#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
7832#define DMA_ERR_ERR26_MASK (0x4000000U)
7833#define DMA_ERR_ERR26_SHIFT (26U)
7838#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
7839#define DMA_ERR_ERR27_MASK (0x8000000U)
7840#define DMA_ERR_ERR27_SHIFT (27U)
7845#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
7846#define DMA_ERR_ERR28_MASK (0x10000000U)
7847#define DMA_ERR_ERR28_SHIFT (28U)
7852#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
7853#define DMA_ERR_ERR29_MASK (0x20000000U)
7854#define DMA_ERR_ERR29_SHIFT (29U)
7859#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
7860#define DMA_ERR_ERR30_MASK (0x40000000U)
7861#define DMA_ERR_ERR30_SHIFT (30U)
7866#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
7867#define DMA_ERR_ERR31_MASK (0x80000000U)
7868#define DMA_ERR_ERR31_SHIFT (31U)
7873#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
7878#define DMA_HRS_HRS0_MASK (0x1U)
7879#define DMA_HRS_HRS0_SHIFT (0U)
7884#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
7885#define DMA_HRS_HRS1_MASK (0x2U)
7886#define DMA_HRS_HRS1_SHIFT (1U)
7891#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
7892#define DMA_HRS_HRS2_MASK (0x4U)
7893#define DMA_HRS_HRS2_SHIFT (2U)
7898#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
7899#define DMA_HRS_HRS3_MASK (0x8U)
7900#define DMA_HRS_HRS3_SHIFT (3U)
7905#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
7906#define DMA_HRS_HRS4_MASK (0x10U)
7907#define DMA_HRS_HRS4_SHIFT (4U)
7912#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
7913#define DMA_HRS_HRS5_MASK (0x20U)
7914#define DMA_HRS_HRS5_SHIFT (5U)
7919#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
7920#define DMA_HRS_HRS6_MASK (0x40U)
7921#define DMA_HRS_HRS6_SHIFT (6U)
7926#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
7927#define DMA_HRS_HRS7_MASK (0x80U)
7928#define DMA_HRS_HRS7_SHIFT (7U)
7933#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
7934#define DMA_HRS_HRS8_MASK (0x100U)
7935#define DMA_HRS_HRS8_SHIFT (8U)
7940#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
7941#define DMA_HRS_HRS9_MASK (0x200U)
7942#define DMA_HRS_HRS9_SHIFT (9U)
7947#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
7948#define DMA_HRS_HRS10_MASK (0x400U)
7949#define DMA_HRS_HRS10_SHIFT (10U)
7954#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
7955#define DMA_HRS_HRS11_MASK (0x800U)
7956#define DMA_HRS_HRS11_SHIFT (11U)
7961#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
7962#define DMA_HRS_HRS12_MASK (0x1000U)
7963#define DMA_HRS_HRS12_SHIFT (12U)
7968#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
7969#define DMA_HRS_HRS13_MASK (0x2000U)
7970#define DMA_HRS_HRS13_SHIFT (13U)
7975#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
7976#define DMA_HRS_HRS14_MASK (0x4000U)
7977#define DMA_HRS_HRS14_SHIFT (14U)
7982#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
7983#define DMA_HRS_HRS15_MASK (0x8000U)
7984#define DMA_HRS_HRS15_SHIFT (15U)
7989#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
7990#define DMA_HRS_HRS16_MASK (0x10000U)
7991#define DMA_HRS_HRS16_SHIFT (16U)
7996#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
7997#define DMA_HRS_HRS17_MASK (0x20000U)
7998#define DMA_HRS_HRS17_SHIFT (17U)
8003#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
8004#define DMA_HRS_HRS18_MASK (0x40000U)
8005#define DMA_HRS_HRS18_SHIFT (18U)
8010#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
8011#define DMA_HRS_HRS19_MASK (0x80000U)
8012#define DMA_HRS_HRS19_SHIFT (19U)
8017#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
8018#define DMA_HRS_HRS20_MASK (0x100000U)
8019#define DMA_HRS_HRS20_SHIFT (20U)
8024#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
8025#define DMA_HRS_HRS21_MASK (0x200000U)
8026#define DMA_HRS_HRS21_SHIFT (21U)
8031#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
8032#define DMA_HRS_HRS22_MASK (0x400000U)
8033#define DMA_HRS_HRS22_SHIFT (22U)
8038#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
8039#define DMA_HRS_HRS23_MASK (0x800000U)
8040#define DMA_HRS_HRS23_SHIFT (23U)
8045#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
8046#define DMA_HRS_HRS24_MASK (0x1000000U)
8047#define DMA_HRS_HRS24_SHIFT (24U)
8052#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
8053#define DMA_HRS_HRS25_MASK (0x2000000U)
8054#define DMA_HRS_HRS25_SHIFT (25U)
8059#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
8060#define DMA_HRS_HRS26_MASK (0x4000000U)
8061#define DMA_HRS_HRS26_SHIFT (26U)
8066#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
8067#define DMA_HRS_HRS27_MASK (0x8000000U)
8068#define DMA_HRS_HRS27_SHIFT (27U)
8073#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
8074#define DMA_HRS_HRS28_MASK (0x10000000U)
8075#define DMA_HRS_HRS28_SHIFT (28U)
8080#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
8081#define DMA_HRS_HRS29_MASK (0x20000000U)
8082#define DMA_HRS_HRS29_SHIFT (29U)
8087#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
8088#define DMA_HRS_HRS30_MASK (0x40000000U)
8089#define DMA_HRS_HRS30_SHIFT (30U)
8094#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
8095#define DMA_HRS_HRS31_MASK (0x80000000U)
8096#define DMA_HRS_HRS31_SHIFT (31U)
8101#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
8106#define DMA_EARS_EDREQ_0_MASK (0x1U)
8107#define DMA_EARS_EDREQ_0_SHIFT (0U)
8112#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
8113#define DMA_EARS_EDREQ_1_MASK (0x2U)
8114#define DMA_EARS_EDREQ_1_SHIFT (1U)
8119#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
8120#define DMA_EARS_EDREQ_2_MASK (0x4U)
8121#define DMA_EARS_EDREQ_2_SHIFT (2U)
8126#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
8127#define DMA_EARS_EDREQ_3_MASK (0x8U)
8128#define DMA_EARS_EDREQ_3_SHIFT (3U)
8133#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
8134#define DMA_EARS_EDREQ_4_MASK (0x10U)
8135#define DMA_EARS_EDREQ_4_SHIFT (4U)
8140#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
8141#define DMA_EARS_EDREQ_5_MASK (0x20U)
8142#define DMA_EARS_EDREQ_5_SHIFT (5U)
8147#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
8148#define DMA_EARS_EDREQ_6_MASK (0x40U)
8149#define DMA_EARS_EDREQ_6_SHIFT (6U)
8154#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
8155#define DMA_EARS_EDREQ_7_MASK (0x80U)
8156#define DMA_EARS_EDREQ_7_SHIFT (7U)
8161#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
8162#define DMA_EARS_EDREQ_8_MASK (0x100U)
8163#define DMA_EARS_EDREQ_8_SHIFT (8U)
8168#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
8169#define DMA_EARS_EDREQ_9_MASK (0x200U)
8170#define DMA_EARS_EDREQ_9_SHIFT (9U)
8175#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
8176#define DMA_EARS_EDREQ_10_MASK (0x400U)
8177#define DMA_EARS_EDREQ_10_SHIFT (10U)
8182#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
8183#define DMA_EARS_EDREQ_11_MASK (0x800U)
8184#define DMA_EARS_EDREQ_11_SHIFT (11U)
8189#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
8190#define DMA_EARS_EDREQ_12_MASK (0x1000U)
8191#define DMA_EARS_EDREQ_12_SHIFT (12U)
8196#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
8197#define DMA_EARS_EDREQ_13_MASK (0x2000U)
8198#define DMA_EARS_EDREQ_13_SHIFT (13U)
8203#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
8204#define DMA_EARS_EDREQ_14_MASK (0x4000U)
8205#define DMA_EARS_EDREQ_14_SHIFT (14U)
8210#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
8211#define DMA_EARS_EDREQ_15_MASK (0x8000U)
8212#define DMA_EARS_EDREQ_15_SHIFT (15U)
8217#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
8218#define DMA_EARS_EDREQ_16_MASK (0x10000U)
8219#define DMA_EARS_EDREQ_16_SHIFT (16U)
8224#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
8225#define DMA_EARS_EDREQ_17_MASK (0x20000U)
8226#define DMA_EARS_EDREQ_17_SHIFT (17U)
8231#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
8232#define DMA_EARS_EDREQ_18_MASK (0x40000U)
8233#define DMA_EARS_EDREQ_18_SHIFT (18U)
8238#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
8239#define DMA_EARS_EDREQ_19_MASK (0x80000U)
8240#define DMA_EARS_EDREQ_19_SHIFT (19U)
8245#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
8246#define DMA_EARS_EDREQ_20_MASK (0x100000U)
8247#define DMA_EARS_EDREQ_20_SHIFT (20U)
8252#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
8253#define DMA_EARS_EDREQ_21_MASK (0x200000U)
8254#define DMA_EARS_EDREQ_21_SHIFT (21U)
8259#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
8260#define DMA_EARS_EDREQ_22_MASK (0x400000U)
8261#define DMA_EARS_EDREQ_22_SHIFT (22U)
8266#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
8267#define DMA_EARS_EDREQ_23_MASK (0x800000U)
8268#define DMA_EARS_EDREQ_23_SHIFT (23U)
8273#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
8274#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
8275#define DMA_EARS_EDREQ_24_SHIFT (24U)
8280#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
8281#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
8282#define DMA_EARS_EDREQ_25_SHIFT (25U)
8287#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
8288#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
8289#define DMA_EARS_EDREQ_26_SHIFT (26U)
8294#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
8295#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
8296#define DMA_EARS_EDREQ_27_SHIFT (27U)
8301#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
8302#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
8303#define DMA_EARS_EDREQ_28_SHIFT (28U)
8308#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
8309#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
8310#define DMA_EARS_EDREQ_29_SHIFT (29U)
8315#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
8316#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
8317#define DMA_EARS_EDREQ_30_SHIFT (30U)
8322#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
8323#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
8324#define DMA_EARS_EDREQ_31_SHIFT (31U)
8329#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
8334#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
8335#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
8336#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
8337#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
8338#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
8339#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
8340#define DMA_DCHPRI3_DPA_MASK (0x40U)
8341#define DMA_DCHPRI3_DPA_SHIFT (6U)
8346#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
8347#define DMA_DCHPRI3_ECP_MASK (0x80U)
8348#define DMA_DCHPRI3_ECP_SHIFT (7U)
8353#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
8358#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
8359#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
8360#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
8361#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
8362#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
8363#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
8364#define DMA_DCHPRI2_DPA_MASK (0x40U)
8365#define DMA_DCHPRI2_DPA_SHIFT (6U)
8370#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
8371#define DMA_DCHPRI2_ECP_MASK (0x80U)
8372#define DMA_DCHPRI2_ECP_SHIFT (7U)
8377#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
8382#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
8383#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
8384#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
8385#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
8386#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
8387#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
8388#define DMA_DCHPRI1_DPA_MASK (0x40U)
8389#define DMA_DCHPRI1_DPA_SHIFT (6U)
8394#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
8395#define DMA_DCHPRI1_ECP_MASK (0x80U)
8396#define DMA_DCHPRI1_ECP_SHIFT (7U)
8401#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
8406#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
8407#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
8408#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
8409#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
8410#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
8411#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
8412#define DMA_DCHPRI0_DPA_MASK (0x40U)
8413#define DMA_DCHPRI0_DPA_SHIFT (6U)
8418#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
8419#define DMA_DCHPRI0_ECP_MASK (0x80U)
8420#define DMA_DCHPRI0_ECP_SHIFT (7U)
8425#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
8430#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
8431#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
8432#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
8433#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
8434#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
8435#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
8436#define DMA_DCHPRI7_DPA_MASK (0x40U)
8437#define DMA_DCHPRI7_DPA_SHIFT (6U)
8442#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
8443#define DMA_DCHPRI7_ECP_MASK (0x80U)
8444#define DMA_DCHPRI7_ECP_SHIFT (7U)
8449#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
8454#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
8455#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
8456#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
8457#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
8458#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
8459#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
8460#define DMA_DCHPRI6_DPA_MASK (0x40U)
8461#define DMA_DCHPRI6_DPA_SHIFT (6U)
8466#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
8467#define DMA_DCHPRI6_ECP_MASK (0x80U)
8468#define DMA_DCHPRI6_ECP_SHIFT (7U)
8473#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
8478#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
8479#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
8480#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
8481#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
8482#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
8483#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
8484#define DMA_DCHPRI5_DPA_MASK (0x40U)
8485#define DMA_DCHPRI5_DPA_SHIFT (6U)
8490#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
8491#define DMA_DCHPRI5_ECP_MASK (0x80U)
8492#define DMA_DCHPRI5_ECP_SHIFT (7U)
8497#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
8502#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
8503#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
8504#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
8505#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
8506#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
8507#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
8508#define DMA_DCHPRI4_DPA_MASK (0x40U)
8509#define DMA_DCHPRI4_DPA_SHIFT (6U)
8514#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
8515#define DMA_DCHPRI4_ECP_MASK (0x80U)
8516#define DMA_DCHPRI4_ECP_SHIFT (7U)
8521#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
8526#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
8527#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
8528#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
8529#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
8530#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
8531#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
8532#define DMA_DCHPRI11_DPA_MASK (0x40U)
8533#define DMA_DCHPRI11_DPA_SHIFT (6U)
8538#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
8539#define DMA_DCHPRI11_ECP_MASK (0x80U)
8540#define DMA_DCHPRI11_ECP_SHIFT (7U)
8545#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
8550#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
8551#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
8552#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
8553#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
8554#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
8555#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
8556#define DMA_DCHPRI10_DPA_MASK (0x40U)
8557#define DMA_DCHPRI10_DPA_SHIFT (6U)
8562#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
8563#define DMA_DCHPRI10_ECP_MASK (0x80U)
8564#define DMA_DCHPRI10_ECP_SHIFT (7U)
8569#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
8574#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
8575#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
8576#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
8577#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
8578#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
8579#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
8580#define DMA_DCHPRI9_DPA_MASK (0x40U)
8581#define DMA_DCHPRI9_DPA_SHIFT (6U)
8586#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
8587#define DMA_DCHPRI9_ECP_MASK (0x80U)
8588#define DMA_DCHPRI9_ECP_SHIFT (7U)
8593#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
8598#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
8599#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
8600#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
8601#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
8602#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
8603#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
8604#define DMA_DCHPRI8_DPA_MASK (0x40U)
8605#define DMA_DCHPRI8_DPA_SHIFT (6U)
8610#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
8611#define DMA_DCHPRI8_ECP_MASK (0x80U)
8612#define DMA_DCHPRI8_ECP_SHIFT (7U)
8617#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
8622#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
8623#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
8624#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
8625#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
8626#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
8627#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
8628#define DMA_DCHPRI15_DPA_MASK (0x40U)
8629#define DMA_DCHPRI15_DPA_SHIFT (6U)
8634#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
8635#define DMA_DCHPRI15_ECP_MASK (0x80U)
8636#define DMA_DCHPRI15_ECP_SHIFT (7U)
8641#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
8646#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
8647#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
8648#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
8649#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
8650#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
8651#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
8652#define DMA_DCHPRI14_DPA_MASK (0x40U)
8653#define DMA_DCHPRI14_DPA_SHIFT (6U)
8658#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
8659#define DMA_DCHPRI14_ECP_MASK (0x80U)
8660#define DMA_DCHPRI14_ECP_SHIFT (7U)
8665#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
8670#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
8671#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
8672#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
8673#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
8674#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
8675#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
8676#define DMA_DCHPRI13_DPA_MASK (0x40U)
8677#define DMA_DCHPRI13_DPA_SHIFT (6U)
8682#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
8683#define DMA_DCHPRI13_ECP_MASK (0x80U)
8684#define DMA_DCHPRI13_ECP_SHIFT (7U)
8689#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
8694#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
8695#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
8696#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
8697#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
8698#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
8699#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
8700#define DMA_DCHPRI12_DPA_MASK (0x40U)
8701#define DMA_DCHPRI12_DPA_SHIFT (6U)
8706#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
8707#define DMA_DCHPRI12_ECP_MASK (0x80U)
8708#define DMA_DCHPRI12_ECP_SHIFT (7U)
8713#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
8718#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
8719#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
8720#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
8721#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
8722#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
8723#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
8724#define DMA_DCHPRI19_DPA_MASK (0x40U)
8725#define DMA_DCHPRI19_DPA_SHIFT (6U)
8730#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
8731#define DMA_DCHPRI19_ECP_MASK (0x80U)
8732#define DMA_DCHPRI19_ECP_SHIFT (7U)
8737#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
8742#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
8743#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
8744#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
8745#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
8746#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
8747#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
8748#define DMA_DCHPRI18_DPA_MASK (0x40U)
8749#define DMA_DCHPRI18_DPA_SHIFT (6U)
8754#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
8755#define DMA_DCHPRI18_ECP_MASK (0x80U)
8756#define DMA_DCHPRI18_ECP_SHIFT (7U)
8761#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
8766#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
8767#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
8768#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
8769#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
8770#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
8771#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
8772#define DMA_DCHPRI17_DPA_MASK (0x40U)
8773#define DMA_DCHPRI17_DPA_SHIFT (6U)
8778#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
8779#define DMA_DCHPRI17_ECP_MASK (0x80U)
8780#define DMA_DCHPRI17_ECP_SHIFT (7U)
8785#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
8790#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
8791#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
8792#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
8793#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
8794#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
8795#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
8796#define DMA_DCHPRI16_DPA_MASK (0x40U)
8797#define DMA_DCHPRI16_DPA_SHIFT (6U)
8802#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
8803#define DMA_DCHPRI16_ECP_MASK (0x80U)
8804#define DMA_DCHPRI16_ECP_SHIFT (7U)
8809#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
8814#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
8815#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
8816#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
8817#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
8818#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
8819#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
8820#define DMA_DCHPRI23_DPA_MASK (0x40U)
8821#define DMA_DCHPRI23_DPA_SHIFT (6U)
8826#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
8827#define DMA_DCHPRI23_ECP_MASK (0x80U)
8828#define DMA_DCHPRI23_ECP_SHIFT (7U)
8833#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
8838#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
8839#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
8840#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
8841#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
8842#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
8843#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
8844#define DMA_DCHPRI22_DPA_MASK (0x40U)
8845#define DMA_DCHPRI22_DPA_SHIFT (6U)
8850#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
8851#define DMA_DCHPRI22_ECP_MASK (0x80U)
8852#define DMA_DCHPRI22_ECP_SHIFT (7U)
8857#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
8862#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
8863#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
8864#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
8865#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
8866#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
8867#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
8868#define DMA_DCHPRI21_DPA_MASK (0x40U)
8869#define DMA_DCHPRI21_DPA_SHIFT (6U)
8874#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
8875#define DMA_DCHPRI21_ECP_MASK (0x80U)
8876#define DMA_DCHPRI21_ECP_SHIFT (7U)
8881#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
8886#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
8887#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
8888#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
8889#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
8890#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
8891#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
8892#define DMA_DCHPRI20_DPA_MASK (0x40U)
8893#define DMA_DCHPRI20_DPA_SHIFT (6U)
8898#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
8899#define DMA_DCHPRI20_ECP_MASK (0x80U)
8900#define DMA_DCHPRI20_ECP_SHIFT (7U)
8905#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
8910#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
8911#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
8912#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
8913#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
8914#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
8915#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
8916#define DMA_DCHPRI27_DPA_MASK (0x40U)
8917#define DMA_DCHPRI27_DPA_SHIFT (6U)
8922#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
8923#define DMA_DCHPRI27_ECP_MASK (0x80U)
8924#define DMA_DCHPRI27_ECP_SHIFT (7U)
8929#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
8934#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
8935#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
8936#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
8937#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
8938#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
8939#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
8940#define DMA_DCHPRI26_DPA_MASK (0x40U)
8941#define DMA_DCHPRI26_DPA_SHIFT (6U)
8946#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
8947#define DMA_DCHPRI26_ECP_MASK (0x80U)
8948#define DMA_DCHPRI26_ECP_SHIFT (7U)
8953#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
8958#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
8959#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
8960#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
8961#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
8962#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
8963#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
8964#define DMA_DCHPRI25_DPA_MASK (0x40U)
8965#define DMA_DCHPRI25_DPA_SHIFT (6U)
8970#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
8971#define DMA_DCHPRI25_ECP_MASK (0x80U)
8972#define DMA_DCHPRI25_ECP_SHIFT (7U)
8977#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
8982#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
8983#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
8984#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
8985#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
8986#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
8987#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
8988#define DMA_DCHPRI24_DPA_MASK (0x40U)
8989#define DMA_DCHPRI24_DPA_SHIFT (6U)
8994#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
8995#define DMA_DCHPRI24_ECP_MASK (0x80U)
8996#define DMA_DCHPRI24_ECP_SHIFT (7U)
9001#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
9006#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
9007#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
9008#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
9009#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
9010#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
9011#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
9012#define DMA_DCHPRI31_DPA_MASK (0x40U)
9013#define DMA_DCHPRI31_DPA_SHIFT (6U)
9018#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
9019#define DMA_DCHPRI31_ECP_MASK (0x80U)
9020#define DMA_DCHPRI31_ECP_SHIFT (7U)
9025#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
9030#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
9031#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
9032#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
9033#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
9034#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
9035#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
9036#define DMA_DCHPRI30_DPA_MASK (0x40U)
9037#define DMA_DCHPRI30_DPA_SHIFT (6U)
9042#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
9043#define DMA_DCHPRI30_ECP_MASK (0x80U)
9044#define DMA_DCHPRI30_ECP_SHIFT (7U)
9049#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
9054#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
9055#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
9056#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
9057#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
9058#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
9059#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
9060#define DMA_DCHPRI29_DPA_MASK (0x40U)
9061#define DMA_DCHPRI29_DPA_SHIFT (6U)
9066#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
9067#define DMA_DCHPRI29_ECP_MASK (0x80U)
9068#define DMA_DCHPRI29_ECP_SHIFT (7U)
9073#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
9078#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
9079#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
9080#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
9081#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
9082#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
9083#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
9084#define DMA_DCHPRI28_DPA_MASK (0x40U)
9085#define DMA_DCHPRI28_DPA_SHIFT (6U)
9090#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
9091#define DMA_DCHPRI28_ECP_MASK (0x80U)
9092#define DMA_DCHPRI28_ECP_SHIFT (7U)
9097#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
9102#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
9103#define DMA_SADDR_SADDR_SHIFT (0U)
9104#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
9107/* The count of DMA_SADDR */
9108#define DMA_SADDR_COUNT (32U)
9109
9112#define DMA_SOFF_SOFF_MASK (0xFFFFU)
9113#define DMA_SOFF_SOFF_SHIFT (0U)
9114#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
9117/* The count of DMA_SOFF */
9118#define DMA_SOFF_COUNT (32U)
9119
9122#define DMA_ATTR_DSIZE_MASK (0x7U)
9123#define DMA_ATTR_DSIZE_SHIFT (0U)
9124#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
9125#define DMA_ATTR_DMOD_MASK (0xF8U)
9126#define DMA_ATTR_DMOD_SHIFT (3U)
9127#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
9128#define DMA_ATTR_SSIZE_MASK (0x700U)
9129#define DMA_ATTR_SSIZE_SHIFT (8U)
9140#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
9141#define DMA_ATTR_SMOD_MASK (0xF800U)
9142#define DMA_ATTR_SMOD_SHIFT (11U)
9146#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
9149/* The count of DMA_ATTR */
9150#define DMA_ATTR_COUNT (32U)
9151
9154#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
9155#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
9156#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
9159/* The count of DMA_NBYTES_MLNO */
9160#define DMA_NBYTES_MLNO_COUNT (32U)
9161
9164#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
9165#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
9166#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
9167#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
9168#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
9173#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
9174#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
9175#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
9180#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
9183/* The count of DMA_NBYTES_MLOFFNO */
9184#define DMA_NBYTES_MLOFFNO_COUNT (32U)
9185
9188#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
9189#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
9190#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
9191#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
9192#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
9193#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
9194#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
9195#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
9200#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
9201#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
9202#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
9207#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
9210/* The count of DMA_NBYTES_MLOFFYES */
9211#define DMA_NBYTES_MLOFFYES_COUNT (32U)
9212
9215#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
9216#define DMA_SLAST_SLAST_SHIFT (0U)
9217#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
9220/* The count of DMA_SLAST */
9221#define DMA_SLAST_COUNT (32U)
9222
9225#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
9226#define DMA_DADDR_DADDR_SHIFT (0U)
9227#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
9230/* The count of DMA_DADDR */
9231#define DMA_DADDR_COUNT (32U)
9232
9235#define DMA_DOFF_DOFF_MASK (0xFFFFU)
9236#define DMA_DOFF_DOFF_SHIFT (0U)
9237#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
9240/* The count of DMA_DOFF */
9241#define DMA_DOFF_COUNT (32U)
9242
9245#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
9246#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
9247#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
9248#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
9249#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
9254#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
9257/* The count of DMA_CITER_ELINKNO */
9258#define DMA_CITER_ELINKNO_COUNT (32U)
9259
9262#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
9263#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
9264#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
9265#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
9266#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
9267#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
9268#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
9269#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
9274#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
9277/* The count of DMA_CITER_ELINKYES */
9278#define DMA_CITER_ELINKYES_COUNT (32U)
9279
9282#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
9283#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
9284#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
9287/* The count of DMA_DLAST_SGA */
9288#define DMA_DLAST_SGA_COUNT (32U)
9289
9292#define DMA_CSR_START_MASK (0x1U)
9293#define DMA_CSR_START_SHIFT (0U)
9298#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
9299#define DMA_CSR_INTMAJOR_MASK (0x2U)
9300#define DMA_CSR_INTMAJOR_SHIFT (1U)
9305#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
9306#define DMA_CSR_INTHALF_MASK (0x4U)
9307#define DMA_CSR_INTHALF_SHIFT (2U)
9312#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
9313#define DMA_CSR_DREQ_MASK (0x8U)
9314#define DMA_CSR_DREQ_SHIFT (3U)
9319#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
9320#define DMA_CSR_ESG_MASK (0x10U)
9321#define DMA_CSR_ESG_SHIFT (4U)
9326#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
9327#define DMA_CSR_MAJORELINK_MASK (0x20U)
9328#define DMA_CSR_MAJORELINK_SHIFT (5U)
9333#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
9334#define DMA_CSR_ACTIVE_MASK (0x40U)
9335#define DMA_CSR_ACTIVE_SHIFT (6U)
9336#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
9337#define DMA_CSR_DONE_MASK (0x80U)
9338#define DMA_CSR_DONE_SHIFT (7U)
9339#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
9340#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
9341#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
9342#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
9343#define DMA_CSR_BWC_MASK (0xC000U)
9344#define DMA_CSR_BWC_SHIFT (14U)
9351#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
9354/* The count of DMA_CSR */
9355#define DMA_CSR_COUNT (32U)
9356
9359#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
9360#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
9361#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
9362#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
9363#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
9368#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
9371/* The count of DMA_BITER_ELINKNO */
9372#define DMA_BITER_ELINKNO_COUNT (32U)
9373
9376#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
9377#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
9378#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
9379#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
9380#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
9381#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
9382#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
9383#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
9388#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
9391/* The count of DMA_BITER_ELINKYES */
9392#define DMA_BITER_ELINKYES_COUNT (32U)
9393
9394
9397 /* end of group DMA_Register_Masks */
9398
9399
9400/* DMA - Peripheral instance base addresses */
9402#define DMA_BASE (0x40008000u)
9404#define DMA0 ((DMA_Type *)DMA_BASE)
9406#define DMA_BASE_ADDRS { DMA_BASE }
9408#define DMA_BASE_PTRS { DMA0 }
9410#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
9411#define DMA_ERROR_IRQS { DMA_Error_IRQn }
9412
9415 /* end of group DMA_Peripheral_Access_Layer */
9416
9417
9418/* ----------------------------------------------------------------------------
9419 -- DMAMUX Peripheral Access Layer
9420 ---------------------------------------------------------------------------- */
9421
9428typedef struct {
9429 __IO uint8_t CHCFG[32];
9430} DMAMUX_Type;
9431
9432/* ----------------------------------------------------------------------------
9433 -- DMAMUX Register Masks
9434 ---------------------------------------------------------------------------- */
9435
9443#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
9444#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
9510#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
9511#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
9512#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
9517#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
9518#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
9519#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
9524#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
9527/* The count of DMAMUX_CHCFG */
9528#define DMAMUX_CHCFG_COUNT (32U)
9529
9530
9533 /* end of group DMAMUX_Register_Masks */
9534
9535
9536/* DMAMUX - Peripheral instance base addresses */
9538#define DMAMUX_BASE (0x40021000u)
9540#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
9542#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
9544#define DMAMUX_BASE_PTRS { DMAMUX }
9545
9548 /* end of group DMAMUX_Peripheral_Access_Layer */
9549
9550
9551/* ----------------------------------------------------------------------------
9552 -- ENET Peripheral Access Layer
9553 ---------------------------------------------------------------------------- */
9554
9561typedef struct {
9562 uint8_t RESERVED_0[4];
9563 __IO uint32_t EIR;
9564 __IO uint32_t EIMR;
9565 uint8_t RESERVED_1[4];
9566 __IO uint32_t RDAR;
9567 __IO uint32_t TDAR;
9568 uint8_t RESERVED_2[12];
9569 __IO uint32_t ECR;
9570 uint8_t RESERVED_3[24];
9571 __IO uint32_t MMFR;
9572 __IO uint32_t MSCR;
9573 uint8_t RESERVED_4[28];
9574 __IO uint32_t MIBC;
9575 uint8_t RESERVED_5[28];
9576 __IO uint32_t RCR;
9577 uint8_t RESERVED_6[60];
9578 __IO uint32_t TCR;
9579 uint8_t RESERVED_7[28];
9580 __IO uint32_t PALR;
9581 __IO uint32_t PAUR;
9582 __IO uint32_t OPD;
9583 uint8_t RESERVED_8[40];
9584 __IO uint32_t IAUR;
9585 __IO uint32_t IALR;
9586 __IO uint32_t GAUR;
9587 __IO uint32_t GALR;
9588 uint8_t RESERVED_9[28];
9589 __IO uint32_t TFWR;
9590 uint8_t RESERVED_10[56];
9591 __IO uint32_t RDSR;
9592 __IO uint32_t TDSR;
9593 __IO uint32_t MRBR;
9594 uint8_t RESERVED_11[4];
9595 __IO uint32_t RSFL;
9596 __IO uint32_t RSEM;
9597 __IO uint32_t RAEM;
9598 __IO uint32_t RAFL;
9599 __IO uint32_t TSEM;
9600 __IO uint32_t TAEM;
9601 __IO uint32_t TAFL;
9602 __IO uint32_t TIPG;
9603 __IO uint32_t FTRL;
9604 uint8_t RESERVED_12[12];
9605 __IO uint32_t TACC;
9606 __IO uint32_t RACC;
9607 uint8_t RESERVED_13[56];
9608 uint32_t RMON_T_DROP;
9609 __I uint32_t RMON_T_PACKETS;
9610 __I uint32_t RMON_T_BC_PKT;
9611 __I uint32_t RMON_T_MC_PKT;
9612 __I uint32_t RMON_T_CRC_ALIGN;
9613 __I uint32_t RMON_T_UNDERSIZE;
9614 __I uint32_t RMON_T_OVERSIZE;
9615 __I uint32_t RMON_T_FRAG;
9616 __I uint32_t RMON_T_JAB;
9617 __I uint32_t RMON_T_COL;
9618 __I uint32_t RMON_T_P64;
9619 __I uint32_t RMON_T_P65TO127;
9620 __I uint32_t RMON_T_P128TO255;
9621 __I uint32_t RMON_T_P256TO511;
9622 __I uint32_t RMON_T_P512TO1023;
9623 __I uint32_t RMON_T_P1024TO2047;
9624 __I uint32_t RMON_T_P_GTE2048;
9625 __I uint32_t RMON_T_OCTETS;
9626 uint32_t IEEE_T_DROP;
9627 __I uint32_t IEEE_T_FRAME_OK;
9628 __I uint32_t IEEE_T_1COL;
9629 __I uint32_t IEEE_T_MCOL;
9630 __I uint32_t IEEE_T_DEF;
9631 __I uint32_t IEEE_T_LCOL;
9632 __I uint32_t IEEE_T_EXCOL;
9633 __I uint32_t IEEE_T_MACERR;
9634 __I uint32_t IEEE_T_CSERR;
9635 __I uint32_t IEEE_T_SQE;
9636 __I uint32_t IEEE_T_FDXFC;
9637 __I uint32_t IEEE_T_OCTETS_OK;
9638 uint8_t RESERVED_14[12];
9639 __I uint32_t RMON_R_PACKETS;
9640 __I uint32_t RMON_R_BC_PKT;
9641 __I uint32_t RMON_R_MC_PKT;
9642 __I uint32_t RMON_R_CRC_ALIGN;
9643 __I uint32_t RMON_R_UNDERSIZE;
9644 __I uint32_t RMON_R_OVERSIZE;
9645 __I uint32_t RMON_R_FRAG;
9646 __I uint32_t RMON_R_JAB;
9647 uint32_t RMON_R_RESVD_0;
9648 __I uint32_t RMON_R_P64;
9649 __I uint32_t RMON_R_P65TO127;
9650 __I uint32_t RMON_R_P128TO255;
9651 __I uint32_t RMON_R_P256TO511;
9652 __I uint32_t RMON_R_P512TO1023;
9653 __I uint32_t RMON_R_P1024TO2047;
9654 __I uint32_t RMON_R_P_GTE2048;
9655 __I uint32_t RMON_R_OCTETS;
9656 __I uint32_t IEEE_R_DROP;
9657 __I uint32_t IEEE_R_FRAME_OK;
9658 __I uint32_t IEEE_R_CRC;
9659 __I uint32_t IEEE_R_ALIGN;
9660 __I uint32_t IEEE_R_MACERR;
9661 __I uint32_t IEEE_R_FDXFC;
9662 __I uint32_t IEEE_R_OCTETS_OK;
9663 uint8_t RESERVED_15[284];
9664 __IO uint32_t ATCR;
9665 __IO uint32_t ATVR;
9666 __IO uint32_t ATOFF;
9667 __IO uint32_t ATPER;
9668 __IO uint32_t ATCOR;
9669 __IO uint32_t ATINC;
9670 __I uint32_t ATSTMP;
9671 uint8_t RESERVED_16[488];
9672 __IO uint32_t TGSR;
9673 struct { /* offset: 0x608, array step: 0x8 */
9674 __IO uint32_t TCSR;
9675 __IO uint32_t TCCR;
9676 } CHANNEL[4];
9677} ENET_Type;
9678
9679/* ----------------------------------------------------------------------------
9680 -- ENET Register Masks
9681 ---------------------------------------------------------------------------- */
9682
9690#define ENET_EIR_TS_TIMER_MASK (0x8000U)
9691#define ENET_EIR_TS_TIMER_SHIFT (15U)
9692#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
9693#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
9694#define ENET_EIR_TS_AVAIL_SHIFT (16U)
9695#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
9696#define ENET_EIR_WAKEUP_MASK (0x20000U)
9697#define ENET_EIR_WAKEUP_SHIFT (17U)
9698#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
9699#define ENET_EIR_PLR_MASK (0x40000U)
9700#define ENET_EIR_PLR_SHIFT (18U)
9701#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
9702#define ENET_EIR_UN_MASK (0x80000U)
9703#define ENET_EIR_UN_SHIFT (19U)
9704#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
9705#define ENET_EIR_RL_MASK (0x100000U)
9706#define ENET_EIR_RL_SHIFT (20U)
9707#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
9708#define ENET_EIR_LC_MASK (0x200000U)
9709#define ENET_EIR_LC_SHIFT (21U)
9710#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
9711#define ENET_EIR_EBERR_MASK (0x400000U)
9712#define ENET_EIR_EBERR_SHIFT (22U)
9713#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
9714#define ENET_EIR_MII_MASK (0x800000U)
9715#define ENET_EIR_MII_SHIFT (23U)
9716#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
9717#define ENET_EIR_RXB_MASK (0x1000000U)
9718#define ENET_EIR_RXB_SHIFT (24U)
9719#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
9720#define ENET_EIR_RXF_MASK (0x2000000U)
9721#define ENET_EIR_RXF_SHIFT (25U)
9722#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
9723#define ENET_EIR_TXB_MASK (0x4000000U)
9724#define ENET_EIR_TXB_SHIFT (26U)
9725#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
9726#define ENET_EIR_TXF_MASK (0x8000000U)
9727#define ENET_EIR_TXF_SHIFT (27U)
9728#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
9729#define ENET_EIR_GRA_MASK (0x10000000U)
9730#define ENET_EIR_GRA_SHIFT (28U)
9731#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
9732#define ENET_EIR_BABT_MASK (0x20000000U)
9733#define ENET_EIR_BABT_SHIFT (29U)
9734#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
9735#define ENET_EIR_BABR_MASK (0x40000000U)
9736#define ENET_EIR_BABR_SHIFT (30U)
9737#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
9742#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
9743#define ENET_EIMR_TS_TIMER_SHIFT (15U)
9744#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
9745#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
9746#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
9747#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
9748#define ENET_EIMR_WAKEUP_MASK (0x20000U)
9749#define ENET_EIMR_WAKEUP_SHIFT (17U)
9750#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
9751#define ENET_EIMR_PLR_MASK (0x40000U)
9752#define ENET_EIMR_PLR_SHIFT (18U)
9753#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
9754#define ENET_EIMR_UN_MASK (0x80000U)
9755#define ENET_EIMR_UN_SHIFT (19U)
9756#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
9757#define ENET_EIMR_RL_MASK (0x100000U)
9758#define ENET_EIMR_RL_SHIFT (20U)
9759#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
9760#define ENET_EIMR_LC_MASK (0x200000U)
9761#define ENET_EIMR_LC_SHIFT (21U)
9762#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
9763#define ENET_EIMR_EBERR_MASK (0x400000U)
9764#define ENET_EIMR_EBERR_SHIFT (22U)
9765#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
9766#define ENET_EIMR_MII_MASK (0x800000U)
9767#define ENET_EIMR_MII_SHIFT (23U)
9768#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
9769#define ENET_EIMR_RXB_MASK (0x1000000U)
9770#define ENET_EIMR_RXB_SHIFT (24U)
9771#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
9772#define ENET_EIMR_RXF_MASK (0x2000000U)
9773#define ENET_EIMR_RXF_SHIFT (25U)
9774#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
9775#define ENET_EIMR_TXB_MASK (0x4000000U)
9776#define ENET_EIMR_TXB_SHIFT (26U)
9781#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
9782#define ENET_EIMR_TXF_MASK (0x8000000U)
9783#define ENET_EIMR_TXF_SHIFT (27U)
9788#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
9789#define ENET_EIMR_GRA_MASK (0x10000000U)
9790#define ENET_EIMR_GRA_SHIFT (28U)
9795#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
9796#define ENET_EIMR_BABT_MASK (0x20000000U)
9797#define ENET_EIMR_BABT_SHIFT (29U)
9802#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
9803#define ENET_EIMR_BABR_MASK (0x40000000U)
9804#define ENET_EIMR_BABR_SHIFT (30U)
9809#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
9814#define ENET_RDAR_RDAR_MASK (0x1000000U)
9815#define ENET_RDAR_RDAR_SHIFT (24U)
9816#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
9821#define ENET_TDAR_TDAR_MASK (0x1000000U)
9822#define ENET_TDAR_TDAR_SHIFT (24U)
9823#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
9828#define ENET_ECR_RESET_MASK (0x1U)
9829#define ENET_ECR_RESET_SHIFT (0U)
9830#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
9831#define ENET_ECR_ETHEREN_MASK (0x2U)
9832#define ENET_ECR_ETHEREN_SHIFT (1U)
9837#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
9838#define ENET_ECR_MAGICEN_MASK (0x4U)
9839#define ENET_ECR_MAGICEN_SHIFT (2U)
9844#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
9845#define ENET_ECR_SLEEP_MASK (0x8U)
9846#define ENET_ECR_SLEEP_SHIFT (3U)
9851#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
9852#define ENET_ECR_EN1588_MASK (0x10U)
9853#define ENET_ECR_EN1588_SHIFT (4U)
9858#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
9859#define ENET_ECR_DBGEN_MASK (0x40U)
9860#define ENET_ECR_DBGEN_SHIFT (6U)
9865#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
9866#define ENET_ECR_STOPEN_MASK (0x80U)
9867#define ENET_ECR_STOPEN_SHIFT (7U)
9868#define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
9869#define ENET_ECR_DBSWP_MASK (0x100U)
9870#define ENET_ECR_DBSWP_SHIFT (8U)
9875#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
9880#define ENET_MMFR_DATA_MASK (0xFFFFU)
9881#define ENET_MMFR_DATA_SHIFT (0U)
9882#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
9883#define ENET_MMFR_TA_MASK (0x30000U)
9884#define ENET_MMFR_TA_SHIFT (16U)
9885#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
9886#define ENET_MMFR_RA_MASK (0x7C0000U)
9887#define ENET_MMFR_RA_SHIFT (18U)
9888#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
9889#define ENET_MMFR_PA_MASK (0xF800000U)
9890#define ENET_MMFR_PA_SHIFT (23U)
9891#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
9892#define ENET_MMFR_OP_MASK (0x30000000U)
9893#define ENET_MMFR_OP_SHIFT (28U)
9894#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
9895#define ENET_MMFR_ST_MASK (0xC0000000U)
9896#define ENET_MMFR_ST_SHIFT (30U)
9897#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
9902#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
9903#define ENET_MSCR_MII_SPEED_SHIFT (1U)
9904#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
9905#define ENET_MSCR_DIS_PRE_MASK (0x80U)
9906#define ENET_MSCR_DIS_PRE_SHIFT (7U)
9911#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
9912#define ENET_MSCR_HOLDTIME_MASK (0x700U)
9913#define ENET_MSCR_HOLDTIME_SHIFT (8U)
9920#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
9925#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
9926#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
9931#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
9932#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
9933#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
9938#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
9939#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
9940#define ENET_MIBC_MIB_DIS_SHIFT (31U)
9945#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
9950#define ENET_RCR_LOOP_MASK (0x1U)
9951#define ENET_RCR_LOOP_SHIFT (0U)
9956#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
9957#define ENET_RCR_DRT_MASK (0x2U)
9958#define ENET_RCR_DRT_SHIFT (1U)
9963#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
9964#define ENET_RCR_MII_MODE_MASK (0x4U)
9965#define ENET_RCR_MII_MODE_SHIFT (2U)
9970#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
9971#define ENET_RCR_PROM_MASK (0x8U)
9972#define ENET_RCR_PROM_SHIFT (3U)
9977#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
9978#define ENET_RCR_BC_REJ_MASK (0x10U)
9979#define ENET_RCR_BC_REJ_SHIFT (4U)
9980#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
9981#define ENET_RCR_FCE_MASK (0x20U)
9982#define ENET_RCR_FCE_SHIFT (5U)
9983#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
9984#define ENET_RCR_RMII_MODE_MASK (0x100U)
9985#define ENET_RCR_RMII_MODE_SHIFT (8U)
9990#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
9991#define ENET_RCR_RMII_10T_MASK (0x200U)
9992#define ENET_RCR_RMII_10T_SHIFT (9U)
9997#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
9998#define ENET_RCR_PADEN_MASK (0x1000U)
9999#define ENET_RCR_PADEN_SHIFT (12U)
10004#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
10005#define ENET_RCR_PAUFWD_MASK (0x2000U)
10006#define ENET_RCR_PAUFWD_SHIFT (13U)
10011#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
10012#define ENET_RCR_CRCFWD_MASK (0x4000U)
10013#define ENET_RCR_CRCFWD_SHIFT (14U)
10018#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
10019#define ENET_RCR_CFEN_MASK (0x8000U)
10020#define ENET_RCR_CFEN_SHIFT (15U)
10025#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
10026#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
10027#define ENET_RCR_MAX_FL_SHIFT (16U)
10028#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
10029#define ENET_RCR_NLC_MASK (0x40000000U)
10030#define ENET_RCR_NLC_SHIFT (30U)
10035#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
10036#define ENET_RCR_GRS_MASK (0x80000000U)
10037#define ENET_RCR_GRS_SHIFT (31U)
10038#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
10043#define ENET_TCR_GTS_MASK (0x1U)
10044#define ENET_TCR_GTS_SHIFT (0U)
10045#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
10046#define ENET_TCR_FDEN_MASK (0x4U)
10047#define ENET_TCR_FDEN_SHIFT (2U)
10048#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
10049#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
10050#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
10055#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
10056#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
10057#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
10058#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
10059#define ENET_TCR_ADDSEL_MASK (0xE0U)
10060#define ENET_TCR_ADDSEL_SHIFT (5U)
10067#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
10068#define ENET_TCR_ADDINS_MASK (0x100U)
10069#define ENET_TCR_ADDINS_SHIFT (8U)
10074#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
10075#define ENET_TCR_CRCFWD_MASK (0x200U)
10076#define ENET_TCR_CRCFWD_SHIFT (9U)
10081#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
10086#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
10087#define ENET_PALR_PADDR1_SHIFT (0U)
10088#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
10093#define ENET_PAUR_TYPE_MASK (0xFFFFU)
10094#define ENET_PAUR_TYPE_SHIFT (0U)
10095#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
10096#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
10097#define ENET_PAUR_PADDR2_SHIFT (16U)
10098#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
10103#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
10104#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
10105#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
10106#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
10107#define ENET_OPD_OPCODE_SHIFT (16U)
10108#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
10113#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
10114#define ENET_IAUR_IADDR1_SHIFT (0U)
10115#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
10120#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
10121#define ENET_IALR_IADDR2_SHIFT (0U)
10122#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
10127#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
10128#define ENET_GAUR_GADDR1_SHIFT (0U)
10129#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
10134#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
10135#define ENET_GALR_GADDR2_SHIFT (0U)
10136#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
10141#define ENET_TFWR_TFWR_MASK (0x3FU)
10142#define ENET_TFWR_TFWR_SHIFT (0U)
10150#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
10151#define ENET_TFWR_STRFWD_MASK (0x100U)
10152#define ENET_TFWR_STRFWD_SHIFT (8U)
10157#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
10162#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
10163#define ENET_RDSR_R_DES_START_SHIFT (3U)
10164#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
10169#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
10170#define ENET_TDSR_X_DES_START_SHIFT (3U)
10171#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
10176#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
10177#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
10178#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
10183#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
10184#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
10185#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
10190#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
10191#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
10192#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
10193#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
10194#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
10195#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
10200#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
10201#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
10202#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
10207#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
10208#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
10209#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
10214#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
10215#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
10216#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
10221#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
10222#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
10223#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
10228#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
10229#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
10230#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
10235#define ENET_TIPG_IPG_MASK (0x1FU)
10236#define ENET_TIPG_IPG_SHIFT (0U)
10237#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
10242#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
10243#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
10244#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
10249#define ENET_TACC_SHIFT16_MASK (0x1U)
10250#define ENET_TACC_SHIFT16_SHIFT (0U)
10255#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
10256#define ENET_TACC_IPCHK_MASK (0x8U)
10257#define ENET_TACC_IPCHK_SHIFT (3U)
10262#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
10263#define ENET_TACC_PROCHK_MASK (0x10U)
10264#define ENET_TACC_PROCHK_SHIFT (4U)
10269#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
10274#define ENET_RACC_PADREM_MASK (0x1U)
10275#define ENET_RACC_PADREM_SHIFT (0U)
10280#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
10281#define ENET_RACC_IPDIS_MASK (0x2U)
10282#define ENET_RACC_IPDIS_SHIFT (1U)
10287#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
10288#define ENET_RACC_PRODIS_MASK (0x4U)
10289#define ENET_RACC_PRODIS_SHIFT (2U)
10294#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
10295#define ENET_RACC_LINEDIS_MASK (0x40U)
10296#define ENET_RACC_LINEDIS_SHIFT (6U)
10301#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
10302#define ENET_RACC_SHIFT16_MASK (0x80U)
10303#define ENET_RACC_SHIFT16_SHIFT (7U)
10308#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
10313#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
10314#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
10315#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
10320#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
10321#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
10322#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
10327#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
10328#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
10329#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
10334#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
10335#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
10336#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
10341#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
10342#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
10343#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
10348#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
10349#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
10350#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
10355#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
10356#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
10357#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
10362#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
10363#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
10364#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
10369#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
10370#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
10371#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
10376#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
10377#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
10378#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
10383#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
10384#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
10385#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
10390#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
10391#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
10392#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
10397#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
10398#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
10399#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
10404#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
10405#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
10406#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
10411#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
10412#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
10413#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
10418#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
10419#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
10420#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
10425#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
10426#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
10427#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
10432#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
10433#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
10434#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
10439#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
10440#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
10441#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
10446#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
10447#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
10448#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
10453#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
10454#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
10455#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
10460#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
10461#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
10462#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
10467#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
10468#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
10469#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
10474#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
10475#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
10476#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
10481#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
10482#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
10483#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
10488#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
10489#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
10490#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
10495#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
10496#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
10497#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
10502#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
10503#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
10504#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
10509#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
10510#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
10511#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
10516#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
10517#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
10518#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
10523#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
10524#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
10525#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
10530#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
10531#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
10532#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
10537#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
10538#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
10539#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
10544#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
10545#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
10546#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
10551#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
10552#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
10553#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
10558#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
10559#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
10560#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
10565#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
10566#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
10567#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
10572#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
10573#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
10574#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
10579#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
10580#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
10581#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
10586#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
10587#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
10588#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
10593#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
10594#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
10595#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
10600#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
10601#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
10602#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
10607#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
10608#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
10609#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
10614#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
10615#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
10616#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
10621#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
10622#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
10623#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
10628#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
10629#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
10630#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
10635#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
10636#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
10637#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
10642#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
10643#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
10644#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
10649#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
10650#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
10651#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
10656#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
10657#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
10658#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
10663#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
10664#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
10665#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
10670#define ENET_ATCR_EN_MASK (0x1U)
10671#define ENET_ATCR_EN_SHIFT (0U)
10676#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
10677#define ENET_ATCR_OFFEN_MASK (0x4U)
10678#define ENET_ATCR_OFFEN_SHIFT (2U)
10683#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
10684#define ENET_ATCR_OFFRST_MASK (0x8U)
10685#define ENET_ATCR_OFFRST_SHIFT (3U)
10690#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
10691#define ENET_ATCR_PEREN_MASK (0x10U)
10692#define ENET_ATCR_PEREN_SHIFT (4U)
10697#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
10698#define ENET_ATCR_PINPER_MASK (0x80U)
10699#define ENET_ATCR_PINPER_SHIFT (7U)
10704#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
10705#define ENET_ATCR_RESTART_MASK (0x200U)
10706#define ENET_ATCR_RESTART_SHIFT (9U)
10707#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
10708#define ENET_ATCR_CAPTURE_MASK (0x800U)
10709#define ENET_ATCR_CAPTURE_SHIFT (11U)
10714#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
10715#define ENET_ATCR_SLAVE_MASK (0x2000U)
10716#define ENET_ATCR_SLAVE_SHIFT (13U)
10721#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
10726#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
10727#define ENET_ATVR_ATIME_SHIFT (0U)
10728#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
10733#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
10734#define ENET_ATOFF_OFFSET_SHIFT (0U)
10735#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
10740#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
10741#define ENET_ATPER_PERIOD_SHIFT (0U)
10742#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
10747#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
10748#define ENET_ATCOR_COR_SHIFT (0U)
10749#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
10754#define ENET_ATINC_INC_MASK (0x7FU)
10755#define ENET_ATINC_INC_SHIFT (0U)
10756#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
10757#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
10758#define ENET_ATINC_INC_CORR_SHIFT (8U)
10759#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
10764#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
10765#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
10766#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
10771#define ENET_TGSR_TF0_MASK (0x1U)
10772#define ENET_TGSR_TF0_SHIFT (0U)
10777#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
10778#define ENET_TGSR_TF1_MASK (0x2U)
10779#define ENET_TGSR_TF1_SHIFT (1U)
10784#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
10785#define ENET_TGSR_TF2_MASK (0x4U)
10786#define ENET_TGSR_TF2_SHIFT (2U)
10791#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
10792#define ENET_TGSR_TF3_MASK (0x8U)
10793#define ENET_TGSR_TF3_SHIFT (3U)
10798#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
10803#define ENET_TCSR_TDRE_MASK (0x1U)
10804#define ENET_TCSR_TDRE_SHIFT (0U)
10809#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
10810#define ENET_TCSR_TMODE_MASK (0x3CU)
10811#define ENET_TCSR_TMODE_SHIFT (2U)
10828#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
10829#define ENET_TCSR_TIE_MASK (0x40U)
10830#define ENET_TCSR_TIE_SHIFT (6U)
10835#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
10836#define ENET_TCSR_TF_MASK (0x80U)
10837#define ENET_TCSR_TF_SHIFT (7U)
10842#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
10845/* The count of ENET_TCSR */
10846#define ENET_TCSR_COUNT (4U)
10847
10850#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
10851#define ENET_TCCR_TCC_SHIFT (0U)
10852#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
10855/* The count of ENET_TCCR */
10856#define ENET_TCCR_COUNT (4U)
10857
10858
10861 /* end of group ENET_Register_Masks */
10862
10863
10864/* ENET - Peripheral instance base addresses */
10866#define ENET_BASE (0x400C0000u)
10868#define ENET ((ENET_Type *)ENET_BASE)
10870#define ENET_BASE_ADDRS { ENET_BASE }
10872#define ENET_BASE_PTRS { ENET }
10874#define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
10875#define ENET_Receive_IRQS { ENET_Receive_IRQn }
10876#define ENET_Error_IRQS { ENET_Error_IRQn }
10877#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
10878/* ENET Buffer Descriptor and Buffer Address Alignment. */
10879#define ENET_BUFF_ALIGNMENT (16U)
10880
10881
10884 /* end of group ENET_Peripheral_Access_Layer */
10885
10886
10887/* ----------------------------------------------------------------------------
10888 -- EWM Peripheral Access Layer
10889 ---------------------------------------------------------------------------- */
10890
10897typedef struct {
10898 __IO uint8_t CTRL;
10899 __O uint8_t SERV;
10900 __IO uint8_t CMPL;
10901 __IO uint8_t CMPH;
10902} EWM_Type;
10903
10904/* ----------------------------------------------------------------------------
10905 -- EWM Register Masks
10906 ---------------------------------------------------------------------------- */
10907
10915#define EWM_CTRL_EWMEN_MASK (0x1U)
10916#define EWM_CTRL_EWMEN_SHIFT (0U)
10917#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
10918#define EWM_CTRL_ASSIN_MASK (0x2U)
10919#define EWM_CTRL_ASSIN_SHIFT (1U)
10920#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
10921#define EWM_CTRL_INEN_MASK (0x4U)
10922#define EWM_CTRL_INEN_SHIFT (2U)
10923#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
10924#define EWM_CTRL_INTEN_MASK (0x8U)
10925#define EWM_CTRL_INTEN_SHIFT (3U)
10926#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
10931#define EWM_SERV_SERVICE_MASK (0xFFU)
10932#define EWM_SERV_SERVICE_SHIFT (0U)
10933#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
10938#define EWM_CMPL_COMPAREL_MASK (0xFFU)
10939#define EWM_CMPL_COMPAREL_SHIFT (0U)
10940#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
10945#define EWM_CMPH_COMPAREH_MASK (0xFFU)
10946#define EWM_CMPH_COMPAREH_SHIFT (0U)
10947#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
10953 /* end of group EWM_Register_Masks */
10954
10955
10956/* EWM - Peripheral instance base addresses */
10958#define EWM_BASE (0x40061000u)
10960#define EWM ((EWM_Type *)EWM_BASE)
10962#define EWM_BASE_ADDRS { EWM_BASE }
10964#define EWM_BASE_PTRS { EWM }
10966#define EWM_IRQS { WDOG_EWM_IRQn }
10967
10970 /* end of group EWM_Peripheral_Access_Layer */
10971
10972
10973/* ----------------------------------------------------------------------------
10974 -- FB Peripheral Access Layer
10975 ---------------------------------------------------------------------------- */
10976
10983typedef struct {
10984 struct { /* offset: 0x0, array step: 0xC */
10985 __IO uint32_t CSAR;
10986 __IO uint32_t CSMR;
10987 __IO uint32_t CSCR;
10988 } CS[6];
10989 uint8_t RESERVED_0[24];
10990 __IO uint32_t CSPMCR;
10991} FB_Type;
10992
10993/* ----------------------------------------------------------------------------
10994 -- FB Register Masks
10995 ---------------------------------------------------------------------------- */
10996
11004#define FB_CSAR_BA_MASK (0xFFFF0000U)
11005#define FB_CSAR_BA_SHIFT (16U)
11006#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
11009/* The count of FB_CSAR */
11010#define FB_CSAR_COUNT (6U)
11011
11014#define FB_CSMR_V_MASK (0x1U)
11015#define FB_CSMR_V_SHIFT (0U)
11020#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
11021#define FB_CSMR_WP_MASK (0x100U)
11022#define FB_CSMR_WP_SHIFT (8U)
11027#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
11028#define FB_CSMR_BAM_MASK (0xFFFF0000U)
11029#define FB_CSMR_BAM_SHIFT (16U)
11034#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
11037/* The count of FB_CSMR */
11038#define FB_CSMR_COUNT (6U)
11039
11042#define FB_CSCR_BSTW_MASK (0x8U)
11043#define FB_CSCR_BSTW_SHIFT (3U)
11048#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
11049#define FB_CSCR_BSTR_MASK (0x10U)
11050#define FB_CSCR_BSTR_SHIFT (4U)
11055#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
11056#define FB_CSCR_BEM_MASK (0x20U)
11057#define FB_CSCR_BEM_SHIFT (5U)
11062#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
11063#define FB_CSCR_PS_MASK (0xC0U)
11064#define FB_CSCR_PS_SHIFT (6U)
11070#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
11071#define FB_CSCR_AA_MASK (0x100U)
11072#define FB_CSCR_AA_SHIFT (8U)
11077#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
11078#define FB_CSCR_BLS_MASK (0x200U)
11079#define FB_CSCR_BLS_SHIFT (9U)
11084#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
11085#define FB_CSCR_WS_MASK (0xFC00U)
11086#define FB_CSCR_WS_SHIFT (10U)
11087#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
11088#define FB_CSCR_WRAH_MASK (0x30000U)
11089#define FB_CSCR_WRAH_SHIFT (16U)
11096#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
11097#define FB_CSCR_RDAH_MASK (0xC0000U)
11098#define FB_CSCR_RDAH_SHIFT (18U)
11105#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
11106#define FB_CSCR_ASET_MASK (0x300000U)
11107#define FB_CSCR_ASET_SHIFT (20U)
11114#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
11115#define FB_CSCR_EXTS_MASK (0x400000U)
11116#define FB_CSCR_EXTS_SHIFT (22U)
11121#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
11122#define FB_CSCR_SWSEN_MASK (0x800000U)
11123#define FB_CSCR_SWSEN_SHIFT (23U)
11128#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
11129#define FB_CSCR_SWS_MASK (0xFC000000U)
11130#define FB_CSCR_SWS_SHIFT (26U)
11131#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
11134/* The count of FB_CSCR */
11135#define FB_CSCR_COUNT (6U)
11136
11139#define FB_CSPMCR_GROUP5_MASK (0xF000U)
11140#define FB_CSPMCR_GROUP5_SHIFT (12U)
11146#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
11147#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
11148#define FB_CSPMCR_GROUP4_SHIFT (16U)
11154#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
11155#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
11156#define FB_CSPMCR_GROUP3_SHIFT (20U)
11162#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
11163#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
11164#define FB_CSPMCR_GROUP2_SHIFT (24U)
11170#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
11171#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
11172#define FB_CSPMCR_GROUP1_SHIFT (28U)
11178#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
11184 /* end of group FB_Register_Masks */
11185
11186
11187/* FB - Peripheral instance base addresses */
11189#define FB_BASE (0x4000C000u)
11191#define FB ((FB_Type *)FB_BASE)
11193#define FB_BASE_ADDRS { FB_BASE }
11195#define FB_BASE_PTRS { FB }
11196
11199 /* end of group FB_Peripheral_Access_Layer */
11200
11201
11202/* ----------------------------------------------------------------------------
11203 -- FMC Peripheral Access Layer
11204 ---------------------------------------------------------------------------- */
11205
11212typedef struct {
11213 __IO uint32_t PFAPR;
11214 __IO uint32_t PFB01CR;
11215 __IO uint32_t PFB23CR;
11216 uint8_t RESERVED_0[244];
11217 __IO uint32_t TAGVDW0S[4];
11218 __IO uint32_t TAGVDW1S[4];
11219 __IO uint32_t TAGVDW2S[4];
11220 __IO uint32_t TAGVDW3S[4];
11221 uint8_t RESERVED_1[192];
11222 struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
11223 __IO uint32_t DATA_UM;
11224 __IO uint32_t DATA_MU;
11225 __IO uint32_t DATA_ML;
11226 __IO uint32_t DATA_LM;
11227 } SET[4][4];
11228} FMC_Type;
11229
11230/* ----------------------------------------------------------------------------
11231 -- FMC Register Masks
11232 ---------------------------------------------------------------------------- */
11233
11241#define FMC_PFAPR_M0AP_MASK (0x3U)
11242#define FMC_PFAPR_M0AP_SHIFT (0U)
11249#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
11250#define FMC_PFAPR_M1AP_MASK (0xCU)
11251#define FMC_PFAPR_M1AP_SHIFT (2U)
11258#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
11259#define FMC_PFAPR_M2AP_MASK (0x30U)
11260#define FMC_PFAPR_M2AP_SHIFT (4U)
11267#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
11268#define FMC_PFAPR_M3AP_MASK (0xC0U)
11269#define FMC_PFAPR_M3AP_SHIFT (6U)
11276#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
11277#define FMC_PFAPR_M4AP_MASK (0x300U)
11278#define FMC_PFAPR_M4AP_SHIFT (8U)
11285#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
11286#define FMC_PFAPR_M5AP_MASK (0xC00U)
11287#define FMC_PFAPR_M5AP_SHIFT (10U)
11294#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
11295#define FMC_PFAPR_M6AP_MASK (0x3000U)
11296#define FMC_PFAPR_M6AP_SHIFT (12U)
11303#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
11304#define FMC_PFAPR_M7AP_MASK (0xC000U)
11305#define FMC_PFAPR_M7AP_SHIFT (14U)
11312#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
11313#define FMC_PFAPR_M0PFD_MASK (0x10000U)
11314#define FMC_PFAPR_M0PFD_SHIFT (16U)
11319#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
11320#define FMC_PFAPR_M1PFD_MASK (0x20000U)
11321#define FMC_PFAPR_M1PFD_SHIFT (17U)
11326#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
11327#define FMC_PFAPR_M2PFD_MASK (0x40000U)
11328#define FMC_PFAPR_M2PFD_SHIFT (18U)
11333#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
11334#define FMC_PFAPR_M3PFD_MASK (0x80000U)
11335#define FMC_PFAPR_M3PFD_SHIFT (19U)
11340#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
11341#define FMC_PFAPR_M4PFD_MASK (0x100000U)
11342#define FMC_PFAPR_M4PFD_SHIFT (20U)
11347#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
11348#define FMC_PFAPR_M5PFD_MASK (0x200000U)
11349#define FMC_PFAPR_M5PFD_SHIFT (21U)
11354#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
11355#define FMC_PFAPR_M6PFD_MASK (0x400000U)
11356#define FMC_PFAPR_M6PFD_SHIFT (22U)
11361#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
11362#define FMC_PFAPR_M7PFD_MASK (0x800000U)
11363#define FMC_PFAPR_M7PFD_SHIFT (23U)
11368#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
11373#define FMC_PFB01CR_RFU_MASK (0x1U)
11374#define FMC_PFB01CR_RFU_SHIFT (0U)
11375#define FMC_PFB01CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
11376#define FMC_PFB01CR_B0IPE_MASK (0x2U)
11377#define FMC_PFB01CR_B0IPE_SHIFT (1U)
11382#define FMC_PFB01CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
11383#define FMC_PFB01CR_B0DPE_MASK (0x4U)
11384#define FMC_PFB01CR_B0DPE_SHIFT (2U)
11389#define FMC_PFB01CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
11390#define FMC_PFB01CR_B0ICE_MASK (0x8U)
11391#define FMC_PFB01CR_B0ICE_SHIFT (3U)
11396#define FMC_PFB01CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
11397#define FMC_PFB01CR_B0DCE_MASK (0x10U)
11398#define FMC_PFB01CR_B0DCE_SHIFT (4U)
11403#define FMC_PFB01CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
11404#define FMC_PFB01CR_CRC_MASK (0xE0U)
11405#define FMC_PFB01CR_CRC_SHIFT (5U)
11413#define FMC_PFB01CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
11414#define FMC_PFB01CR_B0MW_MASK (0x60000U)
11415#define FMC_PFB01CR_B0MW_SHIFT (17U)
11422#define FMC_PFB01CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
11423#define FMC_PFB01CR_S_B_INV_MASK (0x80000U)
11424#define FMC_PFB01CR_S_B_INV_SHIFT (19U)
11429#define FMC_PFB01CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
11430#define FMC_PFB01CR_CINV_WAY_MASK (0xF00000U)
11431#define FMC_PFB01CR_CINV_WAY_SHIFT (20U)
11436#define FMC_PFB01CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
11437#define FMC_PFB01CR_CLCK_WAY_MASK (0xF000000U)
11438#define FMC_PFB01CR_CLCK_WAY_SHIFT (24U)
11443#define FMC_PFB01CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
11444#define FMC_PFB01CR_B0RWSC_MASK (0xF0000000U)
11445#define FMC_PFB01CR_B0RWSC_SHIFT (28U)
11446#define FMC_PFB01CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
11451#define FMC_PFB23CR_RFU_MASK (0x1U)
11452#define FMC_PFB23CR_RFU_SHIFT (0U)
11453#define FMC_PFB23CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
11454#define FMC_PFB23CR_B1IPE_MASK (0x2U)
11455#define FMC_PFB23CR_B1IPE_SHIFT (1U)
11460#define FMC_PFB23CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
11461#define FMC_PFB23CR_B1DPE_MASK (0x4U)
11462#define FMC_PFB23CR_B1DPE_SHIFT (2U)
11467#define FMC_PFB23CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
11468#define FMC_PFB23CR_B1ICE_MASK (0x8U)
11469#define FMC_PFB23CR_B1ICE_SHIFT (3U)
11474#define FMC_PFB23CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
11475#define FMC_PFB23CR_B1DCE_MASK (0x10U)
11476#define FMC_PFB23CR_B1DCE_SHIFT (4U)
11481#define FMC_PFB23CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
11482#define FMC_PFB23CR_B1MW_MASK (0x60000U)
11483#define FMC_PFB23CR_B1MW_SHIFT (17U)
11490#define FMC_PFB23CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
11491#define FMC_PFB23CR_B1RWSC_MASK (0xF0000000U)
11492#define FMC_PFB23CR_B1RWSC_SHIFT (28U)
11493#define FMC_PFB23CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
11498#define FMC_TAGVDW0S_valid_MASK (0x1U)
11499#define FMC_TAGVDW0S_valid_SHIFT (0U)
11500#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
11501#define FMC_TAGVDW0S_tag_MASK (0x3FFFC0U)
11502#define FMC_TAGVDW0S_tag_SHIFT (6U)
11503#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
11506/* The count of FMC_TAGVDW0S */
11507#define FMC_TAGVDW0S_COUNT (4U)
11508
11511#define FMC_TAGVDW1S_valid_MASK (0x1U)
11512#define FMC_TAGVDW1S_valid_SHIFT (0U)
11513#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
11514#define FMC_TAGVDW1S_tag_MASK (0x3FFFC0U)
11515#define FMC_TAGVDW1S_tag_SHIFT (6U)
11516#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
11519/* The count of FMC_TAGVDW1S */
11520#define FMC_TAGVDW1S_COUNT (4U)
11521
11524#define FMC_TAGVDW2S_valid_MASK (0x1U)
11525#define FMC_TAGVDW2S_valid_SHIFT (0U)
11526#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
11527#define FMC_TAGVDW2S_tag_MASK (0x3FFFC0U)
11528#define FMC_TAGVDW2S_tag_SHIFT (6U)
11529#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
11532/* The count of FMC_TAGVDW2S */
11533#define FMC_TAGVDW2S_COUNT (4U)
11534
11537#define FMC_TAGVDW3S_valid_MASK (0x1U)
11538#define FMC_TAGVDW3S_valid_SHIFT (0U)
11539#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
11540#define FMC_TAGVDW3S_tag_MASK (0x3FFFC0U)
11541#define FMC_TAGVDW3S_tag_SHIFT (6U)
11542#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
11545/* The count of FMC_TAGVDW3S */
11546#define FMC_TAGVDW3S_COUNT (4U)
11547
11550#define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
11551#define FMC_DATA_UM_data_SHIFT (0U)
11552#define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
11555/* The count of FMC_DATA_UM */
11556#define FMC_DATA_UM_COUNT (4U)
11557
11558/* The count of FMC_DATA_UM */
11559#define FMC_DATA_UM_COUNT2 (4U)
11560
11563#define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
11564#define FMC_DATA_MU_data_SHIFT (0U)
11565#define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
11568/* The count of FMC_DATA_MU */
11569#define FMC_DATA_MU_COUNT (4U)
11570
11571/* The count of FMC_DATA_MU */
11572#define FMC_DATA_MU_COUNT2 (4U)
11573
11576#define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
11577#define FMC_DATA_ML_data_SHIFT (0U)
11578#define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
11581/* The count of FMC_DATA_ML */
11582#define FMC_DATA_ML_COUNT (4U)
11583
11584/* The count of FMC_DATA_ML */
11585#define FMC_DATA_ML_COUNT2 (4U)
11586
11589#define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
11590#define FMC_DATA_LM_data_SHIFT (0U)
11591#define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
11594/* The count of FMC_DATA_LM */
11595#define FMC_DATA_LM_COUNT (4U)
11596
11597/* The count of FMC_DATA_LM */
11598#define FMC_DATA_LM_COUNT2 (4U)
11599
11600
11603 /* end of group FMC_Register_Masks */
11604
11605
11606/* FMC - Peripheral instance base addresses */
11608#define FMC_BASE (0x4001F000u)
11610#define FMC ((FMC_Type *)FMC_BASE)
11612#define FMC_BASE_ADDRS { FMC_BASE }
11614#define FMC_BASE_PTRS { FMC }
11615
11618 /* end of group FMC_Peripheral_Access_Layer */
11619
11620
11621/* ----------------------------------------------------------------------------
11622 -- FTFE Peripheral Access Layer
11623 ---------------------------------------------------------------------------- */
11624
11631typedef struct {
11632 __IO uint8_t FSTAT;
11633 __IO uint8_t FCNFG;
11634 __I uint8_t FSEC;
11635 __I uint8_t FOPT;
11636 __IO uint8_t FCCOB3;
11637 __IO uint8_t FCCOB2;
11638 __IO uint8_t FCCOB1;
11639 __IO uint8_t FCCOB0;
11640 __IO uint8_t FCCOB7;
11641 __IO uint8_t FCCOB6;
11642 __IO uint8_t FCCOB5;
11643 __IO uint8_t FCCOB4;
11644 __IO uint8_t FCCOBB;
11645 __IO uint8_t FCCOBA;
11646 __IO uint8_t FCCOB9;
11647 __IO uint8_t FCCOB8;
11648 __IO uint8_t FPROT3;
11649 __IO uint8_t FPROT2;
11650 __IO uint8_t FPROT1;
11651 __IO uint8_t FPROT0;
11652 uint8_t RESERVED_0[2];
11653 __IO uint8_t FEPROT;
11654 __IO uint8_t FDPROT;
11655 __I uint8_t XACCH3;
11656 __I uint8_t XACCH2;
11657 __I uint8_t XACCH1;
11658 __I uint8_t XACCH0;
11659 __I uint8_t XACCL3;
11660 __I uint8_t XACCL2;
11661 __I uint8_t XACCL1;
11662 __I uint8_t XACCL0;
11663 __I uint8_t SACCH3;
11664 __I uint8_t SACCH2;
11665 __I uint8_t SACCH1;
11666 __I uint8_t SACCH0;
11667 __I uint8_t SACCL3;
11668 __I uint8_t SACCL2;
11669 __I uint8_t SACCL1;
11670 __I uint8_t SACCL0;
11671 __I uint8_t FACSS;
11672 uint8_t RESERVED_1[2];
11673 __I uint8_t FACSN;
11674} FTFE_Type;
11675
11676/* ----------------------------------------------------------------------------
11677 -- FTFE Register Masks
11678 ---------------------------------------------------------------------------- */
11679
11687#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
11688#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
11689#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
11690#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
11691#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
11696#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
11697#define FTFE_FSTAT_ACCERR_MASK (0x20U)
11698#define FTFE_FSTAT_ACCERR_SHIFT (5U)
11703#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
11704#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
11705#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
11710#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
11711#define FTFE_FSTAT_CCIF_MASK (0x80U)
11712#define FTFE_FSTAT_CCIF_SHIFT (7U)
11717#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
11722#define FTFE_FCNFG_EEERDY_MASK (0x1U)
11723#define FTFE_FCNFG_EEERDY_SHIFT (0U)
11728#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
11729#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
11730#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
11735#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
11736#define FTFE_FCNFG_PFLSH_MASK (0x4U)
11737#define FTFE_FCNFG_PFLSH_SHIFT (2U)
11742#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
11743#define FTFE_FCNFG_SWAP_MASK (0x8U)
11744#define FTFE_FCNFG_SWAP_SHIFT (3U)
11749#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
11750#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
11751#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
11756#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
11757#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
11758#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
11763#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
11764#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
11765#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
11770#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
11771#define FTFE_FCNFG_CCIE_MASK (0x80U)
11772#define FTFE_FCNFG_CCIE_SHIFT (7U)
11777#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
11782#define FTFE_FSEC_SEC_MASK (0x3U)
11783#define FTFE_FSEC_SEC_SHIFT (0U)
11790#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
11791#define FTFE_FSEC_FSLACC_MASK (0xCU)
11792#define FTFE_FSEC_FSLACC_SHIFT (2U)
11799#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
11800#define FTFE_FSEC_MEEN_MASK (0x30U)
11801#define FTFE_FSEC_MEEN_SHIFT (4U)
11808#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
11809#define FTFE_FSEC_KEYEN_MASK (0xC0U)
11810#define FTFE_FSEC_KEYEN_SHIFT (6U)
11817#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
11822#define FTFE_FOPT_OPT_MASK (0xFFU)
11823#define FTFE_FOPT_OPT_SHIFT (0U)
11824#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
11829#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
11830#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
11831#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
11836#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
11837#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
11838#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
11843#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
11844#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
11845#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
11850#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
11851#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
11852#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
11857#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
11858#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
11859#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
11864#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
11865#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
11866#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
11871#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
11872#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
11873#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
11878#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
11879#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
11880#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
11885#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
11886#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
11887#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
11892#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
11893#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
11894#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
11899#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
11900#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
11901#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
11906#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
11907#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
11908#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
11913#define FTFE_FPROT3_PROT_MASK (0xFFU)
11914#define FTFE_FPROT3_PROT_SHIFT (0U)
11919#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
11924#define FTFE_FPROT2_PROT_MASK (0xFFU)
11925#define FTFE_FPROT2_PROT_SHIFT (0U)
11930#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
11935#define FTFE_FPROT1_PROT_MASK (0xFFU)
11936#define FTFE_FPROT1_PROT_SHIFT (0U)
11941#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
11946#define FTFE_FPROT0_PROT_MASK (0xFFU)
11947#define FTFE_FPROT0_PROT_SHIFT (0U)
11952#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
11957#define FTFE_FEPROT_EPROT_MASK (0xFFU)
11958#define FTFE_FEPROT_EPROT_SHIFT (0U)
11963#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
11968#define FTFE_FDPROT_DPROT_MASK (0xFFU)
11969#define FTFE_FDPROT_DPROT_SHIFT (0U)
11974#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
11979#define FTFE_XACCH3_XA_MASK (0xFFU)
11980#define FTFE_XACCH3_XA_SHIFT (0U)
11985#define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
11990#define FTFE_XACCH2_XA_MASK (0xFFU)
11991#define FTFE_XACCH2_XA_SHIFT (0U)
11996#define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
12001#define FTFE_XACCH1_XA_MASK (0xFFU)
12002#define FTFE_XACCH1_XA_SHIFT (0U)
12007#define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
12012#define FTFE_XACCH0_XA_MASK (0xFFU)
12013#define FTFE_XACCH0_XA_SHIFT (0U)
12018#define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
12023#define FTFE_XACCL3_XA_MASK (0xFFU)
12024#define FTFE_XACCL3_XA_SHIFT (0U)
12029#define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
12034#define FTFE_XACCL2_XA_MASK (0xFFU)
12035#define FTFE_XACCL2_XA_SHIFT (0U)
12040#define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
12045#define FTFE_XACCL1_XA_MASK (0xFFU)
12046#define FTFE_XACCL1_XA_SHIFT (0U)
12051#define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
12056#define FTFE_XACCL0_XA_MASK (0xFFU)
12057#define FTFE_XACCL0_XA_SHIFT (0U)
12062#define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
12067#define FTFE_SACCH3_SA_MASK (0xFFU)
12068#define FTFE_SACCH3_SA_SHIFT (0U)
12073#define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
12078#define FTFE_SACCH2_SA_MASK (0xFFU)
12079#define FTFE_SACCH2_SA_SHIFT (0U)
12084#define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
12089#define FTFE_SACCH1_SA_MASK (0xFFU)
12090#define FTFE_SACCH1_SA_SHIFT (0U)
12095#define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
12100#define FTFE_SACCH0_SA_MASK (0xFFU)
12101#define FTFE_SACCH0_SA_SHIFT (0U)
12106#define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
12111#define FTFE_SACCL3_SA_MASK (0xFFU)
12112#define FTFE_SACCL3_SA_SHIFT (0U)
12117#define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
12122#define FTFE_SACCL2_SA_MASK (0xFFU)
12123#define FTFE_SACCL2_SA_SHIFT (0U)
12128#define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
12133#define FTFE_SACCL1_SA_MASK (0xFFU)
12134#define FTFE_SACCL1_SA_SHIFT (0U)
12139#define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
12144#define FTFE_SACCL0_SA_MASK (0xFFU)
12145#define FTFE_SACCL0_SA_SHIFT (0U)
12150#define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
12155#define FTFE_FACSS_SGSIZE_MASK (0xFFU)
12156#define FTFE_FACSS_SGSIZE_SHIFT (0U)
12157#define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
12162#define FTFE_FACSN_NUMSG_MASK (0xFFU)
12163#define FTFE_FACSN_NUMSG_SHIFT (0U)
12168#define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
12174 /* end of group FTFE_Register_Masks */
12175
12176
12177/* FTFE - Peripheral instance base addresses */
12179#define FTFE_BASE (0x40020000u)
12181#define FTFE ((FTFE_Type *)FTFE_BASE)
12183#define FTFE_BASE_ADDRS { FTFE_BASE }
12185#define FTFE_BASE_PTRS { FTFE }
12187#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
12188#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
12189
12192 /* end of group FTFE_Peripheral_Access_Layer */
12193
12194
12195/* ----------------------------------------------------------------------------
12196 -- FTM Peripheral Access Layer
12197 ---------------------------------------------------------------------------- */
12198
12205typedef struct {
12206 __IO uint32_t SC;
12207 __IO uint32_t CNT;
12208 __IO uint32_t MOD;
12209 struct { /* offset: 0xC, array step: 0x8 */
12210 __IO uint32_t CnSC;
12211 __IO uint32_t CnV;
12212 } CONTROLS[8];
12213 __IO uint32_t CNTIN;
12214 __IO uint32_t STATUS;
12215 __IO uint32_t MODE;
12216 __IO uint32_t SYNC;
12217 __IO uint32_t OUTINIT;
12218 __IO uint32_t OUTMASK;
12219 __IO uint32_t COMBINE;
12220 __IO uint32_t DEADTIME;
12221 __IO uint32_t EXTTRIG;
12222 __IO uint32_t POL;
12223 __IO uint32_t FMS;
12224 __IO uint32_t FILTER;
12225 __IO uint32_t FLTCTRL;
12226 __IO uint32_t QDCTRL;
12227 __IO uint32_t CONF;
12228 __IO uint32_t FLTPOL;
12229 __IO uint32_t SYNCONF;
12230 __IO uint32_t INVCTRL;
12231 __IO uint32_t SWOCTRL;
12232 __IO uint32_t PWMLOAD;
12233} FTM_Type;
12234
12235/* ----------------------------------------------------------------------------
12236 -- FTM Register Masks
12237 ---------------------------------------------------------------------------- */
12238
12246#define FTM_SC_PS_MASK (0x7U)
12247#define FTM_SC_PS_SHIFT (0U)
12258#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
12259#define FTM_SC_CLKS_MASK (0x18U)
12260#define FTM_SC_CLKS_SHIFT (3U)
12267#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
12268#define FTM_SC_CPWMS_MASK (0x20U)
12269#define FTM_SC_CPWMS_SHIFT (5U)
12274#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
12275#define FTM_SC_TOIE_MASK (0x40U)
12276#define FTM_SC_TOIE_SHIFT (6U)
12281#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
12282#define FTM_SC_TOF_MASK (0x80U)
12283#define FTM_SC_TOF_SHIFT (7U)
12288#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
12293#define FTM_CNT_COUNT_MASK (0xFFFFU)
12294#define FTM_CNT_COUNT_SHIFT (0U)
12295#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
12300#define FTM_MOD_MOD_MASK (0xFFFFU)
12301#define FTM_MOD_MOD_SHIFT (0U)
12302#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
12307#define FTM_CnSC_DMA_MASK (0x1U)
12308#define FTM_CnSC_DMA_SHIFT (0U)
12313#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
12314#define FTM_CnSC_ELSA_MASK (0x4U)
12315#define FTM_CnSC_ELSA_SHIFT (2U)
12316#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
12317#define FTM_CnSC_ELSB_MASK (0x8U)
12318#define FTM_CnSC_ELSB_SHIFT (3U)
12319#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
12320#define FTM_CnSC_MSA_MASK (0x10U)
12321#define FTM_CnSC_MSA_SHIFT (4U)
12322#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
12323#define FTM_CnSC_MSB_MASK (0x20U)
12324#define FTM_CnSC_MSB_SHIFT (5U)
12325#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
12326#define FTM_CnSC_CHIE_MASK (0x40U)
12327#define FTM_CnSC_CHIE_SHIFT (6U)
12332#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
12333#define FTM_CnSC_CHF_MASK (0x80U)
12334#define FTM_CnSC_CHF_SHIFT (7U)
12339#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
12342/* The count of FTM_CnSC */
12343#define FTM_CnSC_COUNT (8U)
12344
12347#define FTM_CnV_VAL_MASK (0xFFFFU)
12348#define FTM_CnV_VAL_SHIFT (0U)
12349#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
12352/* The count of FTM_CnV */
12353#define FTM_CnV_COUNT (8U)
12354
12357#define FTM_CNTIN_INIT_MASK (0xFFFFU)
12358#define FTM_CNTIN_INIT_SHIFT (0U)
12359#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
12364#define FTM_STATUS_CH0F_MASK (0x1U)
12365#define FTM_STATUS_CH0F_SHIFT (0U)
12370#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
12371#define FTM_STATUS_CH1F_MASK (0x2U)
12372#define FTM_STATUS_CH1F_SHIFT (1U)
12377#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
12378#define FTM_STATUS_CH2F_MASK (0x4U)
12379#define FTM_STATUS_CH2F_SHIFT (2U)
12384#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
12385#define FTM_STATUS_CH3F_MASK (0x8U)
12386#define FTM_STATUS_CH3F_SHIFT (3U)
12391#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
12392#define FTM_STATUS_CH4F_MASK (0x10U)
12393#define FTM_STATUS_CH4F_SHIFT (4U)
12398#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
12399#define FTM_STATUS_CH5F_MASK (0x20U)
12400#define FTM_STATUS_CH5F_SHIFT (5U)
12405#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
12406#define FTM_STATUS_CH6F_MASK (0x40U)
12407#define FTM_STATUS_CH6F_SHIFT (6U)
12412#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
12413#define FTM_STATUS_CH7F_MASK (0x80U)
12414#define FTM_STATUS_CH7F_SHIFT (7U)
12419#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
12424#define FTM_MODE_FTMEN_MASK (0x1U)
12425#define FTM_MODE_FTMEN_SHIFT (0U)
12430#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
12431#define FTM_MODE_INIT_MASK (0x2U)
12432#define FTM_MODE_INIT_SHIFT (1U)
12433#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
12434#define FTM_MODE_WPDIS_MASK (0x4U)
12435#define FTM_MODE_WPDIS_SHIFT (2U)
12440#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
12441#define FTM_MODE_PWMSYNC_MASK (0x8U)
12442#define FTM_MODE_PWMSYNC_SHIFT (3U)
12447#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
12448#define FTM_MODE_CAPTEST_MASK (0x10U)
12449#define FTM_MODE_CAPTEST_SHIFT (4U)
12454#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
12455#define FTM_MODE_FAULTM_MASK (0x60U)
12456#define FTM_MODE_FAULTM_SHIFT (5U)
12463#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
12464#define FTM_MODE_FAULTIE_MASK (0x80U)
12465#define FTM_MODE_FAULTIE_SHIFT (7U)
12470#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
12475#define FTM_SYNC_CNTMIN_MASK (0x1U)
12476#define FTM_SYNC_CNTMIN_SHIFT (0U)
12481#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
12482#define FTM_SYNC_CNTMAX_MASK (0x2U)
12483#define FTM_SYNC_CNTMAX_SHIFT (1U)
12488#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
12489#define FTM_SYNC_REINIT_MASK (0x4U)
12490#define FTM_SYNC_REINIT_SHIFT (2U)
12495#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
12496#define FTM_SYNC_SYNCHOM_MASK (0x8U)
12497#define FTM_SYNC_SYNCHOM_SHIFT (3U)
12502#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
12503#define FTM_SYNC_TRIG0_MASK (0x10U)
12504#define FTM_SYNC_TRIG0_SHIFT (4U)
12509#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
12510#define FTM_SYNC_TRIG1_MASK (0x20U)
12511#define FTM_SYNC_TRIG1_SHIFT (5U)
12516#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
12517#define FTM_SYNC_TRIG2_MASK (0x40U)
12518#define FTM_SYNC_TRIG2_SHIFT (6U)
12523#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
12524#define FTM_SYNC_SWSYNC_MASK (0x80U)
12525#define FTM_SYNC_SWSYNC_SHIFT (7U)
12530#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
12535#define FTM_OUTINIT_CH0OI_MASK (0x1U)
12536#define FTM_OUTINIT_CH0OI_SHIFT (0U)
12541#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
12542#define FTM_OUTINIT_CH1OI_MASK (0x2U)
12543#define FTM_OUTINIT_CH1OI_SHIFT (1U)
12548#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
12549#define FTM_OUTINIT_CH2OI_MASK (0x4U)
12550#define FTM_OUTINIT_CH2OI_SHIFT (2U)
12555#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
12556#define FTM_OUTINIT_CH3OI_MASK (0x8U)
12557#define FTM_OUTINIT_CH3OI_SHIFT (3U)
12562#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
12563#define FTM_OUTINIT_CH4OI_MASK (0x10U)
12564#define FTM_OUTINIT_CH4OI_SHIFT (4U)
12569#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
12570#define FTM_OUTINIT_CH5OI_MASK (0x20U)
12571#define FTM_OUTINIT_CH5OI_SHIFT (5U)
12576#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
12577#define FTM_OUTINIT_CH6OI_MASK (0x40U)
12578#define FTM_OUTINIT_CH6OI_SHIFT (6U)
12583#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
12584#define FTM_OUTINIT_CH7OI_MASK (0x80U)
12585#define FTM_OUTINIT_CH7OI_SHIFT (7U)
12590#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
12595#define FTM_OUTMASK_CH0OM_MASK (0x1U)
12596#define FTM_OUTMASK_CH0OM_SHIFT (0U)
12601#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
12602#define FTM_OUTMASK_CH1OM_MASK (0x2U)
12603#define FTM_OUTMASK_CH1OM_SHIFT (1U)
12608#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
12609#define FTM_OUTMASK_CH2OM_MASK (0x4U)
12610#define FTM_OUTMASK_CH2OM_SHIFT (2U)
12615#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
12616#define FTM_OUTMASK_CH3OM_MASK (0x8U)
12617#define FTM_OUTMASK_CH3OM_SHIFT (3U)
12622#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
12623#define FTM_OUTMASK_CH4OM_MASK (0x10U)
12624#define FTM_OUTMASK_CH4OM_SHIFT (4U)
12629#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
12630#define FTM_OUTMASK_CH5OM_MASK (0x20U)
12631#define FTM_OUTMASK_CH5OM_SHIFT (5U)
12636#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
12637#define FTM_OUTMASK_CH6OM_MASK (0x40U)
12638#define FTM_OUTMASK_CH6OM_SHIFT (6U)
12643#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
12644#define FTM_OUTMASK_CH7OM_MASK (0x80U)
12645#define FTM_OUTMASK_CH7OM_SHIFT (7U)
12650#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
12655#define FTM_COMBINE_COMBINE0_MASK (0x1U)
12656#define FTM_COMBINE_COMBINE0_SHIFT (0U)
12661#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
12662#define FTM_COMBINE_COMP0_MASK (0x2U)
12663#define FTM_COMBINE_COMP0_SHIFT (1U)
12668#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
12669#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
12670#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
12675#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
12676#define FTM_COMBINE_DECAP0_MASK (0x8U)
12677#define FTM_COMBINE_DECAP0_SHIFT (3U)
12682#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
12683#define FTM_COMBINE_DTEN0_MASK (0x10U)
12684#define FTM_COMBINE_DTEN0_SHIFT (4U)
12689#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
12690#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
12691#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
12696#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
12697#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
12698#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
12703#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
12704#define FTM_COMBINE_COMBINE1_MASK (0x100U)
12705#define FTM_COMBINE_COMBINE1_SHIFT (8U)
12710#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
12711#define FTM_COMBINE_COMP1_MASK (0x200U)
12712#define FTM_COMBINE_COMP1_SHIFT (9U)
12717#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
12718#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
12719#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
12724#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
12725#define FTM_COMBINE_DECAP1_MASK (0x800U)
12726#define FTM_COMBINE_DECAP1_SHIFT (11U)
12731#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
12732#define FTM_COMBINE_DTEN1_MASK (0x1000U)
12733#define FTM_COMBINE_DTEN1_SHIFT (12U)
12738#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
12739#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
12740#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
12745#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
12746#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
12747#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
12752#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
12753#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
12754#define FTM_COMBINE_COMBINE2_SHIFT (16U)
12759#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
12760#define FTM_COMBINE_COMP2_MASK (0x20000U)
12761#define FTM_COMBINE_COMP2_SHIFT (17U)
12766#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
12767#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
12768#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
12773#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
12774#define FTM_COMBINE_DECAP2_MASK (0x80000U)
12775#define FTM_COMBINE_DECAP2_SHIFT (19U)
12780#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
12781#define FTM_COMBINE_DTEN2_MASK (0x100000U)
12782#define FTM_COMBINE_DTEN2_SHIFT (20U)
12787#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
12788#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
12789#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
12794#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
12795#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
12796#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
12801#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
12802#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
12803#define FTM_COMBINE_COMBINE3_SHIFT (24U)
12808#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
12809#define FTM_COMBINE_COMP3_MASK (0x2000000U)
12810#define FTM_COMBINE_COMP3_SHIFT (25U)
12815#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
12816#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
12817#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
12822#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
12823#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
12824#define FTM_COMBINE_DECAP3_SHIFT (27U)
12829#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
12830#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
12831#define FTM_COMBINE_DTEN3_SHIFT (28U)
12836#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
12837#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
12838#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
12843#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
12844#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
12845#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
12850#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
12855#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
12856#define FTM_DEADTIME_DTVAL_SHIFT (0U)
12857#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
12858#define FTM_DEADTIME_DTPS_MASK (0xC0U)
12859#define FTM_DEADTIME_DTPS_SHIFT (6U)
12865#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
12870#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
12871#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
12876#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
12877#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
12878#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
12883#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
12884#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
12885#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
12890#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
12891#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
12892#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
12897#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
12898#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
12899#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
12904#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
12905#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
12906#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
12911#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
12912#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
12913#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
12918#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
12919#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
12920#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
12925#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
12930#define FTM_POL_POL0_MASK (0x1U)
12931#define FTM_POL_POL0_SHIFT (0U)
12936#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
12937#define FTM_POL_POL1_MASK (0x2U)
12938#define FTM_POL_POL1_SHIFT (1U)
12943#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
12944#define FTM_POL_POL2_MASK (0x4U)
12945#define FTM_POL_POL2_SHIFT (2U)
12950#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
12951#define FTM_POL_POL3_MASK (0x8U)
12952#define FTM_POL_POL3_SHIFT (3U)
12957#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
12958#define FTM_POL_POL4_MASK (0x10U)
12959#define FTM_POL_POL4_SHIFT (4U)
12964#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
12965#define FTM_POL_POL5_MASK (0x20U)
12966#define FTM_POL_POL5_SHIFT (5U)
12971#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
12972#define FTM_POL_POL6_MASK (0x40U)
12973#define FTM_POL_POL6_SHIFT (6U)
12978#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
12979#define FTM_POL_POL7_MASK (0x80U)
12980#define FTM_POL_POL7_SHIFT (7U)
12985#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
12990#define FTM_FMS_FAULTF0_MASK (0x1U)
12991#define FTM_FMS_FAULTF0_SHIFT (0U)
12996#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
12997#define FTM_FMS_FAULTF1_MASK (0x2U)
12998#define FTM_FMS_FAULTF1_SHIFT (1U)
13003#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
13004#define FTM_FMS_FAULTF2_MASK (0x4U)
13005#define FTM_FMS_FAULTF2_SHIFT (2U)
13010#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
13011#define FTM_FMS_FAULTF3_MASK (0x8U)
13012#define FTM_FMS_FAULTF3_SHIFT (3U)
13017#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
13018#define FTM_FMS_FAULTIN_MASK (0x20U)
13019#define FTM_FMS_FAULTIN_SHIFT (5U)
13024#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
13025#define FTM_FMS_WPEN_MASK (0x40U)
13026#define FTM_FMS_WPEN_SHIFT (6U)
13031#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
13032#define FTM_FMS_FAULTF_MASK (0x80U)
13033#define FTM_FMS_FAULTF_SHIFT (7U)
13038#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
13043#define FTM_FILTER_CH0FVAL_MASK (0xFU)
13044#define FTM_FILTER_CH0FVAL_SHIFT (0U)
13045#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
13046#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
13047#define FTM_FILTER_CH1FVAL_SHIFT (4U)
13048#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
13049#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
13050#define FTM_FILTER_CH2FVAL_SHIFT (8U)
13051#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
13052#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
13053#define FTM_FILTER_CH3FVAL_SHIFT (12U)
13054#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
13059#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
13060#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
13065#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
13066#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
13067#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
13072#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
13073#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
13074#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
13079#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
13080#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
13081#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
13086#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
13087#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
13088#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
13093#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
13094#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
13095#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
13100#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
13101#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
13102#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
13107#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
13108#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
13109#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
13114#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
13115#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
13116#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
13117#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
13122#define FTM_QDCTRL_QUADEN_MASK (0x1U)
13123#define FTM_QDCTRL_QUADEN_SHIFT (0U)
13128#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
13129#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
13130#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
13135#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
13136#define FTM_QDCTRL_QUADIR_MASK (0x4U)
13137#define FTM_QDCTRL_QUADIR_SHIFT (2U)
13142#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
13143#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
13144#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
13149#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
13150#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
13151#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
13156#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
13157#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
13158#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
13163#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
13164#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
13165#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
13170#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
13171#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
13172#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
13177#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
13182#define FTM_CONF_NUMTOF_MASK (0x1FU)
13183#define FTM_CONF_NUMTOF_SHIFT (0U)
13184#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
13185#define FTM_CONF_BDMMODE_MASK (0xC0U)
13186#define FTM_CONF_BDMMODE_SHIFT (6U)
13187#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
13188#define FTM_CONF_GTBEEN_MASK (0x200U)
13189#define FTM_CONF_GTBEEN_SHIFT (9U)
13194#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
13195#define FTM_CONF_GTBEOUT_MASK (0x400U)
13196#define FTM_CONF_GTBEOUT_SHIFT (10U)
13201#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
13206#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
13207#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
13212#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
13213#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
13214#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
13219#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
13220#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
13221#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
13226#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
13227#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
13228#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
13233#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
13238#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
13239#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
13244#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
13245#define FTM_SYNCONF_CNTINC_MASK (0x4U)
13246#define FTM_SYNCONF_CNTINC_SHIFT (2U)
13251#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
13252#define FTM_SYNCONF_INVC_MASK (0x10U)
13253#define FTM_SYNCONF_INVC_SHIFT (4U)
13258#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
13259#define FTM_SYNCONF_SWOC_MASK (0x20U)
13260#define FTM_SYNCONF_SWOC_SHIFT (5U)
13265#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
13266#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
13267#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
13272#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
13273#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
13274#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
13279#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
13280#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
13281#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
13286#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
13287#define FTM_SYNCONF_SWOM_MASK (0x400U)
13288#define FTM_SYNCONF_SWOM_SHIFT (10U)
13293#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
13294#define FTM_SYNCONF_SWINVC_MASK (0x800U)
13295#define FTM_SYNCONF_SWINVC_SHIFT (11U)
13300#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
13301#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
13302#define FTM_SYNCONF_SWSOC_SHIFT (12U)
13307#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
13308#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
13309#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
13314#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
13315#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
13316#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
13321#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
13322#define FTM_SYNCONF_HWOM_MASK (0x40000U)
13323#define FTM_SYNCONF_HWOM_SHIFT (18U)
13328#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
13329#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
13330#define FTM_SYNCONF_HWINVC_SHIFT (19U)
13335#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
13336#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
13337#define FTM_SYNCONF_HWSOC_SHIFT (20U)
13342#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
13347#define FTM_INVCTRL_INV0EN_MASK (0x1U)
13348#define FTM_INVCTRL_INV0EN_SHIFT (0U)
13353#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
13354#define FTM_INVCTRL_INV1EN_MASK (0x2U)
13355#define FTM_INVCTRL_INV1EN_SHIFT (1U)
13360#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
13361#define FTM_INVCTRL_INV2EN_MASK (0x4U)
13362#define FTM_INVCTRL_INV2EN_SHIFT (2U)
13367#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
13368#define FTM_INVCTRL_INV3EN_MASK (0x8U)
13369#define FTM_INVCTRL_INV3EN_SHIFT (3U)
13374#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
13379#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
13380#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
13385#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
13386#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
13387#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
13392#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
13393#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
13394#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
13399#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
13400#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
13401#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
13406#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
13407#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
13408#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
13413#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
13414#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
13415#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
13420#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
13421#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
13422#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
13427#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
13428#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
13429#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
13434#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
13435#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
13436#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
13441#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
13442#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
13443#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
13448#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
13449#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
13450#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
13455#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
13456#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
13457#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
13462#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
13463#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
13464#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
13469#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
13470#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
13471#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
13476#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
13477#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
13478#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
13483#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
13484#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
13485#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
13490#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
13495#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
13496#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
13501#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
13502#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
13503#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
13508#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
13509#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
13510#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
13515#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
13516#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
13517#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
13522#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
13523#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
13524#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
13529#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
13530#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
13531#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
13536#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
13537#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
13538#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
13543#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
13544#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
13545#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
13550#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
13551#define FTM_PWMLOAD_LDOK_MASK (0x200U)
13552#define FTM_PWMLOAD_LDOK_SHIFT (9U)
13557#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
13563 /* end of group FTM_Register_Masks */
13564
13565
13566/* FTM - Peripheral instance base addresses */
13568#define FTM0_BASE (0x40038000u)
13570#define FTM0 ((FTM_Type *)FTM0_BASE)
13572#define FTM1_BASE (0x40039000u)
13574#define FTM1 ((FTM_Type *)FTM1_BASE)
13576#define FTM2_BASE (0x4003A000u)
13578#define FTM2 ((FTM_Type *)FTM2_BASE)
13580#define FTM3_BASE (0x400B9000u)
13582#define FTM3 ((FTM_Type *)FTM3_BASE)
13584#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
13586#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
13588#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
13589
13592 /* end of group FTM_Peripheral_Access_Layer */
13593
13594
13595/* ----------------------------------------------------------------------------
13596 -- GPIO Peripheral Access Layer
13597 ---------------------------------------------------------------------------- */
13598
13605typedef struct {
13606 __IO uint32_t PDOR;
13607 __O uint32_t PSOR;
13608 __O uint32_t PCOR;
13609 __O uint32_t PTOR;
13610 __I uint32_t PDIR;
13611 __IO uint32_t PDDR;
13612} GPIO_Type;
13613
13614/* ----------------------------------------------------------------------------
13615 -- GPIO Register Masks
13616 ---------------------------------------------------------------------------- */
13617
13625#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
13626#define GPIO_PDOR_PDO_SHIFT (0U)
13631#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
13636#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
13637#define GPIO_PSOR_PTSO_SHIFT (0U)
13642#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
13647#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
13648#define GPIO_PCOR_PTCO_SHIFT (0U)
13653#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
13658#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
13659#define GPIO_PTOR_PTTO_SHIFT (0U)
13664#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
13669#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
13670#define GPIO_PDIR_PDI_SHIFT (0U)
13675#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
13680#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
13681#define GPIO_PDDR_PDD_SHIFT (0U)
13686#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
13692 /* end of group GPIO_Register_Masks */
13693
13694
13695/* GPIO - Peripheral instance base addresses */
13697#define GPIOA_BASE (0x400FF000u)
13699#define GPIOA ((GPIO_Type *)GPIOA_BASE)
13701#define GPIOB_BASE (0x400FF040u)
13703#define GPIOB ((GPIO_Type *)GPIOB_BASE)
13705#define GPIOC_BASE (0x400FF080u)
13707#define GPIOC ((GPIO_Type *)GPIOC_BASE)
13709#define GPIOD_BASE (0x400FF0C0u)
13711#define GPIOD ((GPIO_Type *)GPIOD_BASE)
13713#define GPIOE_BASE (0x400FF100u)
13715#define GPIOE ((GPIO_Type *)GPIOE_BASE)
13717#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
13719#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
13720
13723 /* end of group GPIO_Peripheral_Access_Layer */
13724
13725
13726/* ----------------------------------------------------------------------------
13727 -- I2C Peripheral Access Layer
13728 ---------------------------------------------------------------------------- */
13729
13736typedef struct {
13737 __IO uint8_t A1;
13738 __IO uint8_t F;
13739 __IO uint8_t C1;
13740 __IO uint8_t S;
13741 __IO uint8_t D;
13742 __IO uint8_t C2;
13743 __IO uint8_t FLT;
13744 __IO uint8_t RA;
13745 __IO uint8_t SMB;
13746 __IO uint8_t A2;
13747 __IO uint8_t SLTH;
13748 __IO uint8_t SLTL;
13749} I2C_Type;
13750
13751/* ----------------------------------------------------------------------------
13752 -- I2C Register Masks
13753 ---------------------------------------------------------------------------- */
13754
13762#define I2C_A1_AD_MASK (0xFEU)
13763#define I2C_A1_AD_SHIFT (1U)
13764#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
13769#define I2C_F_ICR_MASK (0x3FU)
13770#define I2C_F_ICR_SHIFT (0U)
13771#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
13772#define I2C_F_MULT_MASK (0xC0U)
13773#define I2C_F_MULT_SHIFT (6U)
13780#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
13785#define I2C_C1_DMAEN_MASK (0x1U)
13786#define I2C_C1_DMAEN_SHIFT (0U)
13791#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
13792#define I2C_C1_WUEN_MASK (0x2U)
13793#define I2C_C1_WUEN_SHIFT (1U)
13798#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
13799#define I2C_C1_RSTA_MASK (0x4U)
13800#define I2C_C1_RSTA_SHIFT (2U)
13801#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
13802#define I2C_C1_TXAK_MASK (0x8U)
13803#define I2C_C1_TXAK_SHIFT (3U)
13808#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
13809#define I2C_C1_TX_MASK (0x10U)
13810#define I2C_C1_TX_SHIFT (4U)
13815#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
13816#define I2C_C1_MST_MASK (0x20U)
13817#define I2C_C1_MST_SHIFT (5U)
13822#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
13823#define I2C_C1_IICIE_MASK (0x40U)
13824#define I2C_C1_IICIE_SHIFT (6U)
13829#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
13830#define I2C_C1_IICEN_MASK (0x80U)
13831#define I2C_C1_IICEN_SHIFT (7U)
13836#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
13841#define I2C_S_RXAK_MASK (0x1U)
13842#define I2C_S_RXAK_SHIFT (0U)
13847#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
13848#define I2C_S_IICIF_MASK (0x2U)
13849#define I2C_S_IICIF_SHIFT (1U)
13854#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
13855#define I2C_S_SRW_MASK (0x4U)
13856#define I2C_S_SRW_SHIFT (2U)
13861#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
13862#define I2C_S_RAM_MASK (0x8U)
13863#define I2C_S_RAM_SHIFT (3U)
13868#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
13869#define I2C_S_ARBL_MASK (0x10U)
13870#define I2C_S_ARBL_SHIFT (4U)
13875#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
13876#define I2C_S_BUSY_MASK (0x20U)
13877#define I2C_S_BUSY_SHIFT (5U)
13882#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
13883#define I2C_S_IAAS_MASK (0x40U)
13884#define I2C_S_IAAS_SHIFT (6U)
13889#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
13890#define I2C_S_TCF_MASK (0x80U)
13891#define I2C_S_TCF_SHIFT (7U)
13896#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
13901#define I2C_D_DATA_MASK (0xFFU)
13902#define I2C_D_DATA_SHIFT (0U)
13903#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
13908#define I2C_C2_AD_MASK (0x7U)
13909#define I2C_C2_AD_SHIFT (0U)
13910#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
13911#define I2C_C2_RMEN_MASK (0x8U)
13912#define I2C_C2_RMEN_SHIFT (3U)
13917#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
13918#define I2C_C2_SBRC_MASK (0x10U)
13919#define I2C_C2_SBRC_SHIFT (4U)
13924#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
13925#define I2C_C2_HDRS_MASK (0x20U)
13926#define I2C_C2_HDRS_SHIFT (5U)
13931#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
13932#define I2C_C2_ADEXT_MASK (0x40U)
13933#define I2C_C2_ADEXT_SHIFT (6U)
13938#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
13939#define I2C_C2_GCAEN_MASK (0x80U)
13940#define I2C_C2_GCAEN_SHIFT (7U)
13945#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
13950#define I2C_FLT_FLT_MASK (0xFU)
13951#define I2C_FLT_FLT_SHIFT (0U)
13955#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
13956#define I2C_FLT_STARTF_MASK (0x10U)
13957#define I2C_FLT_STARTF_SHIFT (4U)
13962#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
13963#define I2C_FLT_SSIE_MASK (0x20U)
13964#define I2C_FLT_SSIE_SHIFT (5U)
13969#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
13970#define I2C_FLT_STOPF_MASK (0x40U)
13971#define I2C_FLT_STOPF_SHIFT (6U)
13976#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
13977#define I2C_FLT_SHEN_MASK (0x80U)
13978#define I2C_FLT_SHEN_SHIFT (7U)
13983#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
13988#define I2C_RA_RAD_MASK (0xFEU)
13989#define I2C_RA_RAD_SHIFT (1U)
13990#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
13995#define I2C_SMB_SHTF2IE_MASK (0x1U)
13996#define I2C_SMB_SHTF2IE_SHIFT (0U)
14001#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
14002#define I2C_SMB_SHTF2_MASK (0x2U)
14003#define I2C_SMB_SHTF2_SHIFT (1U)
14008#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
14009#define I2C_SMB_SHTF1_MASK (0x4U)
14010#define I2C_SMB_SHTF1_SHIFT (2U)
14015#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
14016#define I2C_SMB_SLTF_MASK (0x8U)
14017#define I2C_SMB_SLTF_SHIFT (3U)
14022#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
14023#define I2C_SMB_TCKSEL_MASK (0x10U)
14024#define I2C_SMB_TCKSEL_SHIFT (4U)
14029#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
14030#define I2C_SMB_SIICAEN_MASK (0x20U)
14031#define I2C_SMB_SIICAEN_SHIFT (5U)
14036#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
14037#define I2C_SMB_ALERTEN_MASK (0x40U)
14038#define I2C_SMB_ALERTEN_SHIFT (6U)
14043#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
14044#define I2C_SMB_FACK_MASK (0x80U)
14045#define I2C_SMB_FACK_SHIFT (7U)
14050#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
14055#define I2C_A2_SAD_MASK (0xFEU)
14056#define I2C_A2_SAD_SHIFT (1U)
14057#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
14062#define I2C_SLTH_SSLT_MASK (0xFFU)
14063#define I2C_SLTH_SSLT_SHIFT (0U)
14064#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
14069#define I2C_SLTL_SSLT_MASK (0xFFU)
14070#define I2C_SLTL_SSLT_SHIFT (0U)
14071#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
14077 /* end of group I2C_Register_Masks */
14078
14079
14080/* I2C - Peripheral instance base addresses */
14082#define I2C0_BASE (0x40066000u)
14084#define I2C0 ((I2C_Type *)I2C0_BASE)
14086#define I2C1_BASE (0x40067000u)
14088#define I2C1 ((I2C_Type *)I2C1_BASE)
14090#define I2C2_BASE (0x400E6000u)
14092#define I2C2 ((I2C_Type *)I2C2_BASE)
14094#define I2C3_BASE (0x400E7000u)
14096#define I2C3 ((I2C_Type *)I2C3_BASE)
14098#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
14100#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
14102#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
14103
14106 /* end of group I2C_Peripheral_Access_Layer */
14107
14108
14109/* ----------------------------------------------------------------------------
14110 -- I2S Peripheral Access Layer
14111 ---------------------------------------------------------------------------- */
14112
14119typedef struct {
14120 __IO uint32_t TCSR;
14121 __IO uint32_t TCR1;
14122 __IO uint32_t TCR2;
14123 __IO uint32_t TCR3;
14124 __IO uint32_t TCR4;
14125 __IO uint32_t TCR5;
14126 uint8_t RESERVED_0[8];
14127 __O uint32_t TDR[2];
14128 uint8_t RESERVED_1[24];
14129 __I uint32_t TFR[2];
14130 uint8_t RESERVED_2[24];
14131 __IO uint32_t TMR;
14132 uint8_t RESERVED_3[28];
14133 __IO uint32_t RCSR;
14134 __IO uint32_t RCR1;
14135 __IO uint32_t RCR2;
14136 __IO uint32_t RCR3;
14137 __IO uint32_t RCR4;
14138 __IO uint32_t RCR5;
14139 uint8_t RESERVED_4[8];
14140 __I uint32_t RDR[2];
14141 uint8_t RESERVED_5[24];
14142 __I uint32_t RFR[2];
14143 uint8_t RESERVED_6[24];
14144 __IO uint32_t RMR;
14145 uint8_t RESERVED_7[28];
14146 __IO uint32_t MCR;
14147 __IO uint32_t MDR;
14148} I2S_Type;
14149
14150/* ----------------------------------------------------------------------------
14151 -- I2S Register Masks
14152 ---------------------------------------------------------------------------- */
14153
14161#define I2S_TCSR_FRDE_MASK (0x1U)
14162#define I2S_TCSR_FRDE_SHIFT (0U)
14167#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
14168#define I2S_TCSR_FWDE_MASK (0x2U)
14169#define I2S_TCSR_FWDE_SHIFT (1U)
14174#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
14175#define I2S_TCSR_FRIE_MASK (0x100U)
14176#define I2S_TCSR_FRIE_SHIFT (8U)
14181#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
14182#define I2S_TCSR_FWIE_MASK (0x200U)
14183#define I2S_TCSR_FWIE_SHIFT (9U)
14188#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
14189#define I2S_TCSR_FEIE_MASK (0x400U)
14190#define I2S_TCSR_FEIE_SHIFT (10U)
14195#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
14196#define I2S_TCSR_SEIE_MASK (0x800U)
14197#define I2S_TCSR_SEIE_SHIFT (11U)
14202#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
14203#define I2S_TCSR_WSIE_MASK (0x1000U)
14204#define I2S_TCSR_WSIE_SHIFT (12U)
14209#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
14210#define I2S_TCSR_FRF_MASK (0x10000U)
14211#define I2S_TCSR_FRF_SHIFT (16U)
14216#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
14217#define I2S_TCSR_FWF_MASK (0x20000U)
14218#define I2S_TCSR_FWF_SHIFT (17U)
14223#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
14224#define I2S_TCSR_FEF_MASK (0x40000U)
14225#define I2S_TCSR_FEF_SHIFT (18U)
14230#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
14231#define I2S_TCSR_SEF_MASK (0x80000U)
14232#define I2S_TCSR_SEF_SHIFT (19U)
14237#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
14238#define I2S_TCSR_WSF_MASK (0x100000U)
14239#define I2S_TCSR_WSF_SHIFT (20U)
14244#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
14245#define I2S_TCSR_SR_MASK (0x1000000U)
14246#define I2S_TCSR_SR_SHIFT (24U)
14251#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
14252#define I2S_TCSR_FR_MASK (0x2000000U)
14253#define I2S_TCSR_FR_SHIFT (25U)
14258#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
14259#define I2S_TCSR_BCE_MASK (0x10000000U)
14260#define I2S_TCSR_BCE_SHIFT (28U)
14265#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
14266#define I2S_TCSR_DBGE_MASK (0x20000000U)
14267#define I2S_TCSR_DBGE_SHIFT (29U)
14272#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
14273#define I2S_TCSR_STOPE_MASK (0x40000000U)
14274#define I2S_TCSR_STOPE_SHIFT (30U)
14279#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
14280#define I2S_TCSR_TE_MASK (0x80000000U)
14281#define I2S_TCSR_TE_SHIFT (31U)
14286#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
14291#define I2S_TCR1_TFW_MASK (0x7U)
14292#define I2S_TCR1_TFW_SHIFT (0U)
14293#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
14298#define I2S_TCR2_DIV_MASK (0xFFU)
14299#define I2S_TCR2_DIV_SHIFT (0U)
14300#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
14301#define I2S_TCR2_BCD_MASK (0x1000000U)
14302#define I2S_TCR2_BCD_SHIFT (24U)
14307#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
14308#define I2S_TCR2_BCP_MASK (0x2000000U)
14309#define I2S_TCR2_BCP_SHIFT (25U)
14314#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
14315#define I2S_TCR2_MSEL_MASK (0xC000000U)
14316#define I2S_TCR2_MSEL_SHIFT (26U)
14323#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
14324#define I2S_TCR2_BCI_MASK (0x10000000U)
14325#define I2S_TCR2_BCI_SHIFT (28U)
14330#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
14331#define I2S_TCR2_BCS_MASK (0x20000000U)
14332#define I2S_TCR2_BCS_SHIFT (29U)
14337#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
14338#define I2S_TCR2_SYNC_MASK (0xC0000000U)
14339#define I2S_TCR2_SYNC_SHIFT (30U)
14346#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
14351#define I2S_TCR3_WDFL_MASK (0x1FU)
14352#define I2S_TCR3_WDFL_SHIFT (0U)
14353#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
14354#define I2S_TCR3_TCE_MASK (0x30000U)
14355#define I2S_TCR3_TCE_SHIFT (16U)
14360#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
14361#define I2S_TCR3_CFR_MASK (0x3000000U)
14362#define I2S_TCR3_CFR_SHIFT (24U)
14367#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
14372#define I2S_TCR4_FSD_MASK (0x1U)
14373#define I2S_TCR4_FSD_SHIFT (0U)
14378#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
14379#define I2S_TCR4_FSP_MASK (0x2U)
14380#define I2S_TCR4_FSP_SHIFT (1U)
14385#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
14386#define I2S_TCR4_ONDEM_MASK (0x4U)
14387#define I2S_TCR4_ONDEM_SHIFT (2U)
14392#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
14393#define I2S_TCR4_FSE_MASK (0x8U)
14394#define I2S_TCR4_FSE_SHIFT (3U)
14399#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
14400#define I2S_TCR4_MF_MASK (0x10U)
14401#define I2S_TCR4_MF_SHIFT (4U)
14406#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
14407#define I2S_TCR4_SYWD_MASK (0x1F00U)
14408#define I2S_TCR4_SYWD_SHIFT (8U)
14409#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
14410#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
14411#define I2S_TCR4_FRSZ_SHIFT (16U)
14412#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
14413#define I2S_TCR4_FPACK_MASK (0x3000000U)
14414#define I2S_TCR4_FPACK_SHIFT (24U)
14421#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
14422#define I2S_TCR4_FCOMB_MASK (0xC000000U)
14423#define I2S_TCR4_FCOMB_SHIFT (26U)
14430#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
14431#define I2S_TCR4_FCONT_MASK (0x10000000U)
14432#define I2S_TCR4_FCONT_SHIFT (28U)
14437#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
14442#define I2S_TCR5_FBT_MASK (0x1F00U)
14443#define I2S_TCR5_FBT_SHIFT (8U)
14444#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
14445#define I2S_TCR5_W0W_MASK (0x1F0000U)
14446#define I2S_TCR5_W0W_SHIFT (16U)
14447#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
14448#define I2S_TCR5_WNW_MASK (0x1F000000U)
14449#define I2S_TCR5_WNW_SHIFT (24U)
14450#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
14455#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
14456#define I2S_TDR_TDR_SHIFT (0U)
14457#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
14460/* The count of I2S_TDR */
14461#define I2S_TDR_COUNT (2U)
14462
14465#define I2S_TFR_RFP_MASK (0xFU)
14466#define I2S_TFR_RFP_SHIFT (0U)
14467#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
14468#define I2S_TFR_WFP_MASK (0xF0000U)
14469#define I2S_TFR_WFP_SHIFT (16U)
14470#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
14471#define I2S_TFR_WCP_MASK (0x80000000U)
14472#define I2S_TFR_WCP_SHIFT (31U)
14477#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
14480/* The count of I2S_TFR */
14481#define I2S_TFR_COUNT (2U)
14482
14485#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
14486#define I2S_TMR_TWM_SHIFT (0U)
14491#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
14496#define I2S_RCSR_FRDE_MASK (0x1U)
14497#define I2S_RCSR_FRDE_SHIFT (0U)
14502#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
14503#define I2S_RCSR_FWDE_MASK (0x2U)
14504#define I2S_RCSR_FWDE_SHIFT (1U)
14509#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
14510#define I2S_RCSR_FRIE_MASK (0x100U)
14511#define I2S_RCSR_FRIE_SHIFT (8U)
14516#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
14517#define I2S_RCSR_FWIE_MASK (0x200U)
14518#define I2S_RCSR_FWIE_SHIFT (9U)
14523#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
14524#define I2S_RCSR_FEIE_MASK (0x400U)
14525#define I2S_RCSR_FEIE_SHIFT (10U)
14530#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
14531#define I2S_RCSR_SEIE_MASK (0x800U)
14532#define I2S_RCSR_SEIE_SHIFT (11U)
14537#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
14538#define I2S_RCSR_WSIE_MASK (0x1000U)
14539#define I2S_RCSR_WSIE_SHIFT (12U)
14544#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
14545#define I2S_RCSR_FRF_MASK (0x10000U)
14546#define I2S_RCSR_FRF_SHIFT (16U)
14551#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
14552#define I2S_RCSR_FWF_MASK (0x20000U)
14553#define I2S_RCSR_FWF_SHIFT (17U)
14558#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
14559#define I2S_RCSR_FEF_MASK (0x40000U)
14560#define I2S_RCSR_FEF_SHIFT (18U)
14565#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
14566#define I2S_RCSR_SEF_MASK (0x80000U)
14567#define I2S_RCSR_SEF_SHIFT (19U)
14572#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
14573#define I2S_RCSR_WSF_MASK (0x100000U)
14574#define I2S_RCSR_WSF_SHIFT (20U)
14579#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
14580#define I2S_RCSR_SR_MASK (0x1000000U)
14581#define I2S_RCSR_SR_SHIFT (24U)
14586#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
14587#define I2S_RCSR_FR_MASK (0x2000000U)
14588#define I2S_RCSR_FR_SHIFT (25U)
14593#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
14594#define I2S_RCSR_BCE_MASK (0x10000000U)
14595#define I2S_RCSR_BCE_SHIFT (28U)
14600#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
14601#define I2S_RCSR_DBGE_MASK (0x20000000U)
14602#define I2S_RCSR_DBGE_SHIFT (29U)
14607#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
14608#define I2S_RCSR_STOPE_MASK (0x40000000U)
14609#define I2S_RCSR_STOPE_SHIFT (30U)
14614#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
14615#define I2S_RCSR_RE_MASK (0x80000000U)
14616#define I2S_RCSR_RE_SHIFT (31U)
14621#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
14626#define I2S_RCR1_RFW_MASK (0x7U)
14627#define I2S_RCR1_RFW_SHIFT (0U)
14628#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
14633#define I2S_RCR2_DIV_MASK (0xFFU)
14634#define I2S_RCR2_DIV_SHIFT (0U)
14635#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
14636#define I2S_RCR2_BCD_MASK (0x1000000U)
14637#define I2S_RCR2_BCD_SHIFT (24U)
14642#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
14643#define I2S_RCR2_BCP_MASK (0x2000000U)
14644#define I2S_RCR2_BCP_SHIFT (25U)
14649#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
14650#define I2S_RCR2_MSEL_MASK (0xC000000U)
14651#define I2S_RCR2_MSEL_SHIFT (26U)
14658#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
14659#define I2S_RCR2_BCI_MASK (0x10000000U)
14660#define I2S_RCR2_BCI_SHIFT (28U)
14665#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
14666#define I2S_RCR2_BCS_MASK (0x20000000U)
14667#define I2S_RCR2_BCS_SHIFT (29U)
14672#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
14673#define I2S_RCR2_SYNC_MASK (0xC0000000U)
14674#define I2S_RCR2_SYNC_SHIFT (30U)
14681#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
14686#define I2S_RCR3_WDFL_MASK (0x1FU)
14687#define I2S_RCR3_WDFL_SHIFT (0U)
14688#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
14689#define I2S_RCR3_RCE_MASK (0x30000U)
14690#define I2S_RCR3_RCE_SHIFT (16U)
14695#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
14696#define I2S_RCR3_CFR_MASK (0x3000000U)
14697#define I2S_RCR3_CFR_SHIFT (24U)
14702#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
14707#define I2S_RCR4_FSD_MASK (0x1U)
14708#define I2S_RCR4_FSD_SHIFT (0U)
14713#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
14714#define I2S_RCR4_FSP_MASK (0x2U)
14715#define I2S_RCR4_FSP_SHIFT (1U)
14720#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
14721#define I2S_RCR4_ONDEM_MASK (0x4U)
14722#define I2S_RCR4_ONDEM_SHIFT (2U)
14727#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
14728#define I2S_RCR4_FSE_MASK (0x8U)
14729#define I2S_RCR4_FSE_SHIFT (3U)
14734#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
14735#define I2S_RCR4_MF_MASK (0x10U)
14736#define I2S_RCR4_MF_SHIFT (4U)
14741#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
14742#define I2S_RCR4_SYWD_MASK (0x1F00U)
14743#define I2S_RCR4_SYWD_SHIFT (8U)
14744#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
14745#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
14746#define I2S_RCR4_FRSZ_SHIFT (16U)
14747#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
14748#define I2S_RCR4_FPACK_MASK (0x3000000U)
14749#define I2S_RCR4_FPACK_SHIFT (24U)
14756#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
14757#define I2S_RCR4_FCOMB_MASK (0xC000000U)
14758#define I2S_RCR4_FCOMB_SHIFT (26U)
14765#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
14766#define I2S_RCR4_FCONT_MASK (0x10000000U)
14767#define I2S_RCR4_FCONT_SHIFT (28U)
14772#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
14777#define I2S_RCR5_FBT_MASK (0x1F00U)
14778#define I2S_RCR5_FBT_SHIFT (8U)
14779#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
14780#define I2S_RCR5_W0W_MASK (0x1F0000U)
14781#define I2S_RCR5_W0W_SHIFT (16U)
14782#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
14783#define I2S_RCR5_WNW_MASK (0x1F000000U)
14784#define I2S_RCR5_WNW_SHIFT (24U)
14785#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
14790#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
14791#define I2S_RDR_RDR_SHIFT (0U)
14792#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
14795/* The count of I2S_RDR */
14796#define I2S_RDR_COUNT (2U)
14797
14800#define I2S_RFR_RFP_MASK (0xFU)
14801#define I2S_RFR_RFP_SHIFT (0U)
14802#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
14803#define I2S_RFR_RCP_MASK (0x8000U)
14804#define I2S_RFR_RCP_SHIFT (15U)
14809#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
14810#define I2S_RFR_WFP_MASK (0xF0000U)
14811#define I2S_RFR_WFP_SHIFT (16U)
14812#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
14815/* The count of I2S_RFR */
14816#define I2S_RFR_COUNT (2U)
14817
14820#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
14821#define I2S_RMR_RWM_SHIFT (0U)
14826#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
14831#define I2S_MCR_MICS_MASK (0x3000000U)
14832#define I2S_MCR_MICS_SHIFT (24U)
14839#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
14840#define I2S_MCR_MOE_MASK (0x40000000U)
14841#define I2S_MCR_MOE_SHIFT (30U)
14846#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
14847#define I2S_MCR_DUF_MASK (0x80000000U)
14848#define I2S_MCR_DUF_SHIFT (31U)
14853#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
14858#define I2S_MDR_DIVIDE_MASK (0xFFFU)
14859#define I2S_MDR_DIVIDE_SHIFT (0U)
14860#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
14861#define I2S_MDR_FRACT_MASK (0xFF000U)
14862#define I2S_MDR_FRACT_SHIFT (12U)
14863#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
14869 /* end of group I2S_Register_Masks */
14870
14871
14872/* I2S - Peripheral instance base addresses */
14874#define I2S0_BASE (0x4002F000u)
14876#define I2S0 ((I2S_Type *)I2S0_BASE)
14878#define I2S_BASE_ADDRS { I2S0_BASE }
14880#define I2S_BASE_PTRS { I2S0 }
14882#define I2S_RX_IRQS { I2S0_Rx_IRQn }
14883#define I2S_TX_IRQS { I2S0_Tx_IRQn }
14884
14887 /* end of group I2S_Peripheral_Access_Layer */
14888
14889
14890/* ----------------------------------------------------------------------------
14891 -- LLWU Peripheral Access Layer
14892 ---------------------------------------------------------------------------- */
14893
14900typedef struct {
14901 __IO uint8_t PE1;
14902 __IO uint8_t PE2;
14903 __IO uint8_t PE3;
14904 __IO uint8_t PE4;
14905 __IO uint8_t PE5;
14906 __IO uint8_t PE6;
14907 __IO uint8_t PE7;
14908 __IO uint8_t PE8;
14909 __IO uint8_t ME;
14910 __IO uint8_t PF1;
14911 __IO uint8_t PF2;
14912 __IO uint8_t PF3;
14913 __IO uint8_t PF4;
14914 __I uint8_t MF5;
14915 __IO uint8_t FILT1;
14916 __IO uint8_t FILT2;
14917 __IO uint8_t FILT3;
14918 __IO uint8_t FILT4;
14919} LLWU_Type;
14920
14921/* ----------------------------------------------------------------------------
14922 -- LLWU Register Masks
14923 ---------------------------------------------------------------------------- */
14924
14932#define LLWU_PE1_WUPE0_MASK (0x3U)
14933#define LLWU_PE1_WUPE0_SHIFT (0U)
14940#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
14941#define LLWU_PE1_WUPE1_MASK (0xCU)
14942#define LLWU_PE1_WUPE1_SHIFT (2U)
14949#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
14950#define LLWU_PE1_WUPE2_MASK (0x30U)
14951#define LLWU_PE1_WUPE2_SHIFT (4U)
14958#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
14959#define LLWU_PE1_WUPE3_MASK (0xC0U)
14960#define LLWU_PE1_WUPE3_SHIFT (6U)
14967#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
14972#define LLWU_PE2_WUPE4_MASK (0x3U)
14973#define LLWU_PE2_WUPE4_SHIFT (0U)
14980#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
14981#define LLWU_PE2_WUPE5_MASK (0xCU)
14982#define LLWU_PE2_WUPE5_SHIFT (2U)
14989#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
14990#define LLWU_PE2_WUPE6_MASK (0x30U)
14991#define LLWU_PE2_WUPE6_SHIFT (4U)
14998#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
14999#define LLWU_PE2_WUPE7_MASK (0xC0U)
15000#define LLWU_PE2_WUPE7_SHIFT (6U)
15007#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
15012#define LLWU_PE3_WUPE8_MASK (0x3U)
15013#define LLWU_PE3_WUPE8_SHIFT (0U)
15020#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
15021#define LLWU_PE3_WUPE9_MASK (0xCU)
15022#define LLWU_PE3_WUPE9_SHIFT (2U)
15029#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
15030#define LLWU_PE3_WUPE10_MASK (0x30U)
15031#define LLWU_PE3_WUPE10_SHIFT (4U)
15038#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
15039#define LLWU_PE3_WUPE11_MASK (0xC0U)
15040#define LLWU_PE3_WUPE11_SHIFT (6U)
15047#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
15052#define LLWU_PE4_WUPE12_MASK (0x3U)
15053#define LLWU_PE4_WUPE12_SHIFT (0U)
15060#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
15061#define LLWU_PE4_WUPE13_MASK (0xCU)
15062#define LLWU_PE4_WUPE13_SHIFT (2U)
15069#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
15070#define LLWU_PE4_WUPE14_MASK (0x30U)
15071#define LLWU_PE4_WUPE14_SHIFT (4U)
15078#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
15079#define LLWU_PE4_WUPE15_MASK (0xC0U)
15080#define LLWU_PE4_WUPE15_SHIFT (6U)
15087#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
15092#define LLWU_PE5_WUPE16_MASK (0x3U)
15093#define LLWU_PE5_WUPE16_SHIFT (0U)
15100#define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
15101#define LLWU_PE5_WUPE17_MASK (0xCU)
15102#define LLWU_PE5_WUPE17_SHIFT (2U)
15109#define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
15110#define LLWU_PE5_WUPE18_MASK (0x30U)
15111#define LLWU_PE5_WUPE18_SHIFT (4U)
15118#define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
15119#define LLWU_PE5_WUPE19_MASK (0xC0U)
15120#define LLWU_PE5_WUPE19_SHIFT (6U)
15127#define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
15132#define LLWU_PE6_WUPE20_MASK (0x3U)
15133#define LLWU_PE6_WUPE20_SHIFT (0U)
15140#define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
15141#define LLWU_PE6_WUPE21_MASK (0xCU)
15142#define LLWU_PE6_WUPE21_SHIFT (2U)
15149#define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
15150#define LLWU_PE6_WUPE22_MASK (0x30U)
15151#define LLWU_PE6_WUPE22_SHIFT (4U)
15158#define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
15159#define LLWU_PE6_WUPE23_MASK (0xC0U)
15160#define LLWU_PE6_WUPE23_SHIFT (6U)
15167#define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
15172#define LLWU_PE7_WUPE24_MASK (0x3U)
15173#define LLWU_PE7_WUPE24_SHIFT (0U)
15180#define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
15181#define LLWU_PE7_WUPE25_MASK (0xCU)
15182#define LLWU_PE7_WUPE25_SHIFT (2U)
15189#define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
15190#define LLWU_PE7_WUPE26_MASK (0x30U)
15191#define LLWU_PE7_WUPE26_SHIFT (4U)
15198#define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
15199#define LLWU_PE7_WUPE27_MASK (0xC0U)
15200#define LLWU_PE7_WUPE27_SHIFT (6U)
15207#define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
15212#define LLWU_PE8_WUPE28_MASK (0x3U)
15213#define LLWU_PE8_WUPE28_SHIFT (0U)
15220#define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
15221#define LLWU_PE8_WUPE29_MASK (0xCU)
15222#define LLWU_PE8_WUPE29_SHIFT (2U)
15229#define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
15230#define LLWU_PE8_WUPE30_MASK (0x30U)
15231#define LLWU_PE8_WUPE30_SHIFT (4U)
15238#define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
15239#define LLWU_PE8_WUPE31_MASK (0xC0U)
15240#define LLWU_PE8_WUPE31_SHIFT (6U)
15247#define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
15252#define LLWU_ME_WUME0_MASK (0x1U)
15253#define LLWU_ME_WUME0_SHIFT (0U)
15258#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
15259#define LLWU_ME_WUME1_MASK (0x2U)
15260#define LLWU_ME_WUME1_SHIFT (1U)
15265#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
15266#define LLWU_ME_WUME2_MASK (0x4U)
15267#define LLWU_ME_WUME2_SHIFT (2U)
15272#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
15273#define LLWU_ME_WUME3_MASK (0x8U)
15274#define LLWU_ME_WUME3_SHIFT (3U)
15279#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
15280#define LLWU_ME_WUME4_MASK (0x10U)
15281#define LLWU_ME_WUME4_SHIFT (4U)
15286#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
15287#define LLWU_ME_WUME5_MASK (0x20U)
15288#define LLWU_ME_WUME5_SHIFT (5U)
15293#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
15294#define LLWU_ME_WUME6_MASK (0x40U)
15295#define LLWU_ME_WUME6_SHIFT (6U)
15300#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
15301#define LLWU_ME_WUME7_MASK (0x80U)
15302#define LLWU_ME_WUME7_SHIFT (7U)
15307#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
15312#define LLWU_PF1_WUF0_MASK (0x1U)
15313#define LLWU_PF1_WUF0_SHIFT (0U)
15318#define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
15319#define LLWU_PF1_WUF1_MASK (0x2U)
15320#define LLWU_PF1_WUF1_SHIFT (1U)
15325#define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
15326#define LLWU_PF1_WUF2_MASK (0x4U)
15327#define LLWU_PF1_WUF2_SHIFT (2U)
15332#define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
15333#define LLWU_PF1_WUF3_MASK (0x8U)
15334#define LLWU_PF1_WUF3_SHIFT (3U)
15339#define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
15340#define LLWU_PF1_WUF4_MASK (0x10U)
15341#define LLWU_PF1_WUF4_SHIFT (4U)
15346#define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
15347#define LLWU_PF1_WUF5_MASK (0x20U)
15348#define LLWU_PF1_WUF5_SHIFT (5U)
15353#define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
15354#define LLWU_PF1_WUF6_MASK (0x40U)
15355#define LLWU_PF1_WUF6_SHIFT (6U)
15360#define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
15361#define LLWU_PF1_WUF7_MASK (0x80U)
15362#define LLWU_PF1_WUF7_SHIFT (7U)
15367#define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
15372#define LLWU_PF2_WUF8_MASK (0x1U)
15373#define LLWU_PF2_WUF8_SHIFT (0U)
15378#define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
15379#define LLWU_PF2_WUF9_MASK (0x2U)
15380#define LLWU_PF2_WUF9_SHIFT (1U)
15385#define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
15386#define LLWU_PF2_WUF10_MASK (0x4U)
15387#define LLWU_PF2_WUF10_SHIFT (2U)
15392#define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
15393#define LLWU_PF2_WUF11_MASK (0x8U)
15394#define LLWU_PF2_WUF11_SHIFT (3U)
15399#define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
15400#define LLWU_PF2_WUF12_MASK (0x10U)
15401#define LLWU_PF2_WUF12_SHIFT (4U)
15406#define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
15407#define LLWU_PF2_WUF13_MASK (0x20U)
15408#define LLWU_PF2_WUF13_SHIFT (5U)
15413#define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
15414#define LLWU_PF2_WUF14_MASK (0x40U)
15415#define LLWU_PF2_WUF14_SHIFT (6U)
15420#define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
15421#define LLWU_PF2_WUF15_MASK (0x80U)
15422#define LLWU_PF2_WUF15_SHIFT (7U)
15427#define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
15432#define LLWU_PF3_WUF16_MASK (0x1U)
15433#define LLWU_PF3_WUF16_SHIFT (0U)
15438#define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
15439#define LLWU_PF3_WUF17_MASK (0x2U)
15440#define LLWU_PF3_WUF17_SHIFT (1U)
15445#define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
15446#define LLWU_PF3_WUF18_MASK (0x4U)
15447#define LLWU_PF3_WUF18_SHIFT (2U)
15452#define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
15453#define LLWU_PF3_WUF19_MASK (0x8U)
15454#define LLWU_PF3_WUF19_SHIFT (3U)
15459#define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
15460#define LLWU_PF3_WUF20_MASK (0x10U)
15461#define LLWU_PF3_WUF20_SHIFT (4U)
15466#define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
15467#define LLWU_PF3_WUF21_MASK (0x20U)
15468#define LLWU_PF3_WUF21_SHIFT (5U)
15473#define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
15474#define LLWU_PF3_WUF22_MASK (0x40U)
15475#define LLWU_PF3_WUF22_SHIFT (6U)
15480#define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
15481#define LLWU_PF3_WUF23_MASK (0x80U)
15482#define LLWU_PF3_WUF23_SHIFT (7U)
15487#define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
15492#define LLWU_PF4_WUF24_MASK (0x1U)
15493#define LLWU_PF4_WUF24_SHIFT (0U)
15498#define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
15499#define LLWU_PF4_WUF25_MASK (0x2U)
15500#define LLWU_PF4_WUF25_SHIFT (1U)
15505#define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
15506#define LLWU_PF4_WUF26_MASK (0x4U)
15507#define LLWU_PF4_WUF26_SHIFT (2U)
15512#define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
15513#define LLWU_PF4_WUF27_MASK (0x8U)
15514#define LLWU_PF4_WUF27_SHIFT (3U)
15519#define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
15520#define LLWU_PF4_WUF28_MASK (0x10U)
15521#define LLWU_PF4_WUF28_SHIFT (4U)
15526#define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
15527#define LLWU_PF4_WUF29_MASK (0x20U)
15528#define LLWU_PF4_WUF29_SHIFT (5U)
15533#define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
15534#define LLWU_PF4_WUF30_MASK (0x40U)
15535#define LLWU_PF4_WUF30_SHIFT (6U)
15540#define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
15541#define LLWU_PF4_WUF31_MASK (0x80U)
15542#define LLWU_PF4_WUF31_SHIFT (7U)
15547#define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
15552#define LLWU_MF5_MWUF0_MASK (0x1U)
15553#define LLWU_MF5_MWUF0_SHIFT (0U)
15558#define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
15559#define LLWU_MF5_MWUF1_MASK (0x2U)
15560#define LLWU_MF5_MWUF1_SHIFT (1U)
15565#define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
15566#define LLWU_MF5_MWUF2_MASK (0x4U)
15567#define LLWU_MF5_MWUF2_SHIFT (2U)
15572#define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
15573#define LLWU_MF5_MWUF3_MASK (0x8U)
15574#define LLWU_MF5_MWUF3_SHIFT (3U)
15579#define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
15580#define LLWU_MF5_MWUF4_MASK (0x10U)
15581#define LLWU_MF5_MWUF4_SHIFT (4U)
15586#define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
15587#define LLWU_MF5_MWUF5_MASK (0x20U)
15588#define LLWU_MF5_MWUF5_SHIFT (5U)
15593#define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
15594#define LLWU_MF5_MWUF6_MASK (0x40U)
15595#define LLWU_MF5_MWUF6_SHIFT (6U)
15600#define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
15601#define LLWU_MF5_MWUF7_MASK (0x80U)
15602#define LLWU_MF5_MWUF7_SHIFT (7U)
15607#define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
15612#define LLWU_FILT1_FILTSEL_MASK (0x1FU)
15613#define LLWU_FILT1_FILTSEL_SHIFT (0U)
15618#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
15619#define LLWU_FILT1_FILTE_MASK (0x60U)
15620#define LLWU_FILT1_FILTE_SHIFT (5U)
15627#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
15628#define LLWU_FILT1_FILTF_MASK (0x80U)
15629#define LLWU_FILT1_FILTF_SHIFT (7U)
15634#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
15639#define LLWU_FILT2_FILTSEL_MASK (0x1FU)
15640#define LLWU_FILT2_FILTSEL_SHIFT (0U)
15645#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
15646#define LLWU_FILT2_FILTE_MASK (0x60U)
15647#define LLWU_FILT2_FILTE_SHIFT (5U)
15654#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
15655#define LLWU_FILT2_FILTF_MASK (0x80U)
15656#define LLWU_FILT2_FILTF_SHIFT (7U)
15661#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
15666#define LLWU_FILT3_FILTSEL_MASK (0x1FU)
15667#define LLWU_FILT3_FILTSEL_SHIFT (0U)
15672#define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
15673#define LLWU_FILT3_FILTE_MASK (0x60U)
15674#define LLWU_FILT3_FILTE_SHIFT (5U)
15681#define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
15682#define LLWU_FILT3_FILTF_MASK (0x80U)
15683#define LLWU_FILT3_FILTF_SHIFT (7U)
15688#define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
15693#define LLWU_FILT4_FILTSEL_MASK (0x1FU)
15694#define LLWU_FILT4_FILTSEL_SHIFT (0U)
15699#define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
15700#define LLWU_FILT4_FILTE_MASK (0x60U)
15701#define LLWU_FILT4_FILTE_SHIFT (5U)
15708#define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
15709#define LLWU_FILT4_FILTF_MASK (0x80U)
15710#define LLWU_FILT4_FILTF_SHIFT (7U)
15715#define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
15721 /* end of group LLWU_Register_Masks */
15722
15723
15724/* LLWU - Peripheral instance base addresses */
15726#define LLWU_BASE (0x4007C000u)
15728#define LLWU ((LLWU_Type *)LLWU_BASE)
15730#define LLWU_BASE_ADDRS { LLWU_BASE }
15732#define LLWU_BASE_PTRS { LLWU }
15734#define LLWU_IRQS { LLWU_IRQn }
15735
15738 /* end of group LLWU_Peripheral_Access_Layer */
15739
15740
15741/* ----------------------------------------------------------------------------
15742 -- LMEM Peripheral Access Layer
15743 ---------------------------------------------------------------------------- */
15744
15751typedef struct {
15752 __IO uint32_t PCCCR;
15753 __IO uint32_t PCCLCR;
15754 __IO uint32_t PCCSAR;
15755 __IO uint32_t PCCCVR;
15756 uint8_t RESERVED_0[16];
15757 __IO uint32_t PCCRMR;
15758} LMEM_Type;
15759
15760/* ----------------------------------------------------------------------------
15761 -- LMEM Register Masks
15762 ---------------------------------------------------------------------------- */
15763
15771#define LMEM_PCCCR_ENCACHE_MASK (0x1U)
15772#define LMEM_PCCCR_ENCACHE_SHIFT (0U)
15777#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
15778#define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
15779#define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
15784#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
15785#define LMEM_PCCCR_PCCR2_MASK (0x4U)
15786#define LMEM_PCCCR_PCCR2_SHIFT (2U)
15787#define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
15788#define LMEM_PCCCR_PCCR3_MASK (0x8U)
15789#define LMEM_PCCCR_PCCR3_SHIFT (3U)
15790#define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
15791#define LMEM_PCCCR_INVW0_MASK (0x1000000U)
15792#define LMEM_PCCCR_INVW0_SHIFT (24U)
15797#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
15798#define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
15799#define LMEM_PCCCR_PUSHW0_SHIFT (25U)
15804#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
15805#define LMEM_PCCCR_INVW1_MASK (0x4000000U)
15806#define LMEM_PCCCR_INVW1_SHIFT (26U)
15811#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
15812#define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
15813#define LMEM_PCCCR_PUSHW1_SHIFT (27U)
15818#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
15819#define LMEM_PCCCR_GO_MASK (0x80000000U)
15820#define LMEM_PCCCR_GO_SHIFT (31U)
15825#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
15830#define LMEM_PCCLCR_LGO_MASK (0x1U)
15831#define LMEM_PCCLCR_LGO_SHIFT (0U)
15836#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
15837#define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
15838#define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
15839#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
15840#define LMEM_PCCLCR_WSEL_MASK (0x4000U)
15841#define LMEM_PCCLCR_WSEL_SHIFT (14U)
15846#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
15847#define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
15848#define LMEM_PCCLCR_TDSEL_SHIFT (16U)
15853#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
15854#define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
15855#define LMEM_PCCLCR_LCIVB_SHIFT (20U)
15856#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
15857#define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
15858#define LMEM_PCCLCR_LCIMB_SHIFT (21U)
15859#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
15860#define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
15861#define LMEM_PCCLCR_LCWAY_SHIFT (22U)
15862#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
15863#define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
15864#define LMEM_PCCLCR_LCMD_SHIFT (24U)
15871#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
15872#define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
15873#define LMEM_PCCLCR_LADSEL_SHIFT (26U)
15878#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
15879#define LMEM_PCCLCR_LACC_MASK (0x8000000U)
15880#define LMEM_PCCLCR_LACC_SHIFT (27U)
15885#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
15890#define LMEM_PCCSAR_LGO_MASK (0x1U)
15891#define LMEM_PCCSAR_LGO_SHIFT (0U)
15896#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
15897#define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
15898#define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
15899#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
15904#define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
15905#define LMEM_PCCCVR_DATA_SHIFT (0U)
15906#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
15911#define LMEM_PCCRMR_R15_MASK (0x3U)
15912#define LMEM_PCCRMR_R15_SHIFT (0U)
15919#define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
15920#define LMEM_PCCRMR_R14_MASK (0xCU)
15921#define LMEM_PCCRMR_R14_SHIFT (2U)
15928#define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
15929#define LMEM_PCCRMR_R13_MASK (0x30U)
15930#define LMEM_PCCRMR_R13_SHIFT (4U)
15937#define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
15938#define LMEM_PCCRMR_R12_MASK (0xC0U)
15939#define LMEM_PCCRMR_R12_SHIFT (6U)
15946#define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
15947#define LMEM_PCCRMR_R11_MASK (0x300U)
15948#define LMEM_PCCRMR_R11_SHIFT (8U)
15955#define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
15956#define LMEM_PCCRMR_R10_MASK (0xC00U)
15957#define LMEM_PCCRMR_R10_SHIFT (10U)
15964#define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
15965#define LMEM_PCCRMR_R9_MASK (0x3000U)
15966#define LMEM_PCCRMR_R9_SHIFT (12U)
15973#define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
15974#define LMEM_PCCRMR_R8_MASK (0xC000U)
15975#define LMEM_PCCRMR_R8_SHIFT (14U)
15982#define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
15983#define LMEM_PCCRMR_R7_MASK (0x30000U)
15984#define LMEM_PCCRMR_R7_SHIFT (16U)
15991#define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
15992#define LMEM_PCCRMR_R6_MASK (0xC0000U)
15993#define LMEM_PCCRMR_R6_SHIFT (18U)
16000#define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
16001#define LMEM_PCCRMR_R5_MASK (0x300000U)
16002#define LMEM_PCCRMR_R5_SHIFT (20U)
16009#define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
16010#define LMEM_PCCRMR_R4_MASK (0xC00000U)
16011#define LMEM_PCCRMR_R4_SHIFT (22U)
16018#define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
16019#define LMEM_PCCRMR_R3_MASK (0x3000000U)
16020#define LMEM_PCCRMR_R3_SHIFT (24U)
16027#define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
16028#define LMEM_PCCRMR_R2_MASK (0xC000000U)
16029#define LMEM_PCCRMR_R2_SHIFT (26U)
16036#define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
16037#define LMEM_PCCRMR_R1_MASK (0x30000000U)
16038#define LMEM_PCCRMR_R1_SHIFT (28U)
16045#define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
16046#define LMEM_PCCRMR_R0_MASK (0xC0000000U)
16047#define LMEM_PCCRMR_R0_SHIFT (30U)
16054#define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
16060 /* end of group LMEM_Register_Masks */
16061
16062
16063/* LMEM - Peripheral instance base addresses */
16065#define LMEM_BASE (0xE0082000u)
16067#define LMEM ((LMEM_Type *)LMEM_BASE)
16069#define LMEM_BASE_ADDRS { LMEM_BASE }
16071#define LMEM_BASE_PTRS { LMEM }
16072
16075 /* end of group LMEM_Peripheral_Access_Layer */
16076
16077
16078/* ----------------------------------------------------------------------------
16079 -- LPTMR Peripheral Access Layer
16080 ---------------------------------------------------------------------------- */
16081
16088typedef struct {
16089 __IO uint32_t CSR;
16090 __IO uint32_t PSR;
16091 __IO uint32_t CMR;
16092 __IO uint32_t CNR;
16093} LPTMR_Type;
16094
16095/* ----------------------------------------------------------------------------
16096 -- LPTMR Register Masks
16097 ---------------------------------------------------------------------------- */
16098
16106#define LPTMR_CSR_TEN_MASK (0x1U)
16107#define LPTMR_CSR_TEN_SHIFT (0U)
16112#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
16113#define LPTMR_CSR_TMS_MASK (0x2U)
16114#define LPTMR_CSR_TMS_SHIFT (1U)
16119#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
16120#define LPTMR_CSR_TFC_MASK (0x4U)
16121#define LPTMR_CSR_TFC_SHIFT (2U)
16126#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
16127#define LPTMR_CSR_TPP_MASK (0x8U)
16128#define LPTMR_CSR_TPP_SHIFT (3U)
16133#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
16134#define LPTMR_CSR_TPS_MASK (0x30U)
16135#define LPTMR_CSR_TPS_SHIFT (4U)
16142#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
16143#define LPTMR_CSR_TIE_MASK (0x40U)
16144#define LPTMR_CSR_TIE_SHIFT (6U)
16149#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
16150#define LPTMR_CSR_TCF_MASK (0x80U)
16151#define LPTMR_CSR_TCF_SHIFT (7U)
16156#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
16161#define LPTMR_PSR_PCS_MASK (0x3U)
16162#define LPTMR_PSR_PCS_SHIFT (0U)
16169#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
16170#define LPTMR_PSR_PBYP_MASK (0x4U)
16171#define LPTMR_PSR_PBYP_SHIFT (2U)
16176#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
16177#define LPTMR_PSR_PRESCALE_MASK (0x78U)
16178#define LPTMR_PSR_PRESCALE_SHIFT (3U)
16197#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
16202#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
16203#define LPTMR_CMR_COMPARE_SHIFT (0U)
16204#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
16209#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
16210#define LPTMR_CNR_COUNTER_SHIFT (0U)
16211#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
16217 /* end of group LPTMR_Register_Masks */
16218
16219
16220/* LPTMR - Peripheral instance base addresses */
16222#define LPTMR0_BASE (0x40040000u)
16224#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
16226#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
16228#define LPTMR_BASE_PTRS { LPTMR0 }
16230#define LPTMR_IRQS { LPTMR0_IRQn }
16231
16234 /* end of group LPTMR_Peripheral_Access_Layer */
16235
16236
16237/* ----------------------------------------------------------------------------
16238 -- LPUART Peripheral Access Layer
16239 ---------------------------------------------------------------------------- */
16240
16247typedef struct {
16248 __IO uint32_t BAUD;
16249 __IO uint32_t STAT;
16250 __IO uint32_t CTRL;
16251 __IO uint32_t DATA;
16252 __IO uint32_t MATCH;
16253 __IO uint32_t MODIR;
16254} LPUART_Type;
16255
16256/* ----------------------------------------------------------------------------
16257 -- LPUART Register Masks
16258 ---------------------------------------------------------------------------- */
16259
16267#define LPUART_BAUD_SBR_MASK (0x1FFFU)
16268#define LPUART_BAUD_SBR_SHIFT (0U)
16269#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
16270#define LPUART_BAUD_SBNS_MASK (0x2000U)
16271#define LPUART_BAUD_SBNS_SHIFT (13U)
16276#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
16277#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
16278#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
16283#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
16284#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
16285#define LPUART_BAUD_LBKDIE_SHIFT (15U)
16290#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
16291#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
16292#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
16297#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
16298#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
16299#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
16304#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
16305#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
16306#define LPUART_BAUD_MATCFG_SHIFT (18U)
16313#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
16314#define LPUART_BAUD_RDMAE_MASK (0x200000U)
16315#define LPUART_BAUD_RDMAE_SHIFT (21U)
16320#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
16321#define LPUART_BAUD_TDMAE_MASK (0x800000U)
16322#define LPUART_BAUD_TDMAE_SHIFT (23U)
16327#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
16328#define LPUART_BAUD_OSR_MASK (0x1F000000U)
16329#define LPUART_BAUD_OSR_SHIFT (24U)
16330#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
16331#define LPUART_BAUD_M10_MASK (0x20000000U)
16332#define LPUART_BAUD_M10_SHIFT (29U)
16337#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
16338#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
16339#define LPUART_BAUD_MAEN2_SHIFT (30U)
16344#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
16345#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
16346#define LPUART_BAUD_MAEN1_SHIFT (31U)
16351#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
16356#define LPUART_STAT_MA2F_MASK (0x4000U)
16357#define LPUART_STAT_MA2F_SHIFT (14U)
16362#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
16363#define LPUART_STAT_MA1F_MASK (0x8000U)
16364#define LPUART_STAT_MA1F_SHIFT (15U)
16369#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
16370#define LPUART_STAT_PF_MASK (0x10000U)
16371#define LPUART_STAT_PF_SHIFT (16U)
16376#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
16377#define LPUART_STAT_FE_MASK (0x20000U)
16378#define LPUART_STAT_FE_SHIFT (17U)
16383#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
16384#define LPUART_STAT_NF_MASK (0x40000U)
16385#define LPUART_STAT_NF_SHIFT (18U)
16390#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
16391#define LPUART_STAT_OR_MASK (0x80000U)
16392#define LPUART_STAT_OR_SHIFT (19U)
16397#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
16398#define LPUART_STAT_IDLE_MASK (0x100000U)
16399#define LPUART_STAT_IDLE_SHIFT (20U)
16404#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
16405#define LPUART_STAT_RDRF_MASK (0x200000U)
16406#define LPUART_STAT_RDRF_SHIFT (21U)
16411#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
16412#define LPUART_STAT_TC_MASK (0x400000U)
16413#define LPUART_STAT_TC_SHIFT (22U)
16418#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
16419#define LPUART_STAT_TDRE_MASK (0x800000U)
16420#define LPUART_STAT_TDRE_SHIFT (23U)
16425#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
16426#define LPUART_STAT_RAF_MASK (0x1000000U)
16427#define LPUART_STAT_RAF_SHIFT (24U)
16432#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
16433#define LPUART_STAT_LBKDE_MASK (0x2000000U)
16434#define LPUART_STAT_LBKDE_SHIFT (25U)
16439#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
16440#define LPUART_STAT_BRK13_MASK (0x4000000U)
16441#define LPUART_STAT_BRK13_SHIFT (26U)
16446#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
16447#define LPUART_STAT_RWUID_MASK (0x8000000U)
16448#define LPUART_STAT_RWUID_SHIFT (27U)
16453#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
16454#define LPUART_STAT_RXINV_MASK (0x10000000U)
16455#define LPUART_STAT_RXINV_SHIFT (28U)
16460#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
16461#define LPUART_STAT_MSBF_MASK (0x20000000U)
16462#define LPUART_STAT_MSBF_SHIFT (29U)
16467#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
16468#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
16469#define LPUART_STAT_RXEDGIF_SHIFT (30U)
16474#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
16475#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
16476#define LPUART_STAT_LBKDIF_SHIFT (31U)
16481#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
16486#define LPUART_CTRL_PT_MASK (0x1U)
16487#define LPUART_CTRL_PT_SHIFT (0U)
16492#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
16493#define LPUART_CTRL_PE_MASK (0x2U)
16494#define LPUART_CTRL_PE_SHIFT (1U)
16499#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
16500#define LPUART_CTRL_ILT_MASK (0x4U)
16501#define LPUART_CTRL_ILT_SHIFT (2U)
16506#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
16507#define LPUART_CTRL_WAKE_MASK (0x8U)
16508#define LPUART_CTRL_WAKE_SHIFT (3U)
16513#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
16514#define LPUART_CTRL_M_MASK (0x10U)
16515#define LPUART_CTRL_M_SHIFT (4U)
16520#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
16521#define LPUART_CTRL_RSRC_MASK (0x20U)
16522#define LPUART_CTRL_RSRC_SHIFT (5U)
16527#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
16528#define LPUART_CTRL_DOZEEN_MASK (0x40U)
16529#define LPUART_CTRL_DOZEEN_SHIFT (6U)
16534#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
16535#define LPUART_CTRL_LOOPS_MASK (0x80U)
16536#define LPUART_CTRL_LOOPS_SHIFT (7U)
16541#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
16542#define LPUART_CTRL_IDLECFG_MASK (0x700U)
16543#define LPUART_CTRL_IDLECFG_SHIFT (8U)
16554#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
16555#define LPUART_CTRL_MA2IE_MASK (0x4000U)
16556#define LPUART_CTRL_MA2IE_SHIFT (14U)
16561#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
16562#define LPUART_CTRL_MA1IE_MASK (0x8000U)
16563#define LPUART_CTRL_MA1IE_SHIFT (15U)
16568#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
16569#define LPUART_CTRL_SBK_MASK (0x10000U)
16570#define LPUART_CTRL_SBK_SHIFT (16U)
16575#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
16576#define LPUART_CTRL_RWU_MASK (0x20000U)
16577#define LPUART_CTRL_RWU_SHIFT (17U)
16582#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
16583#define LPUART_CTRL_RE_MASK (0x40000U)
16584#define LPUART_CTRL_RE_SHIFT (18U)
16589#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
16590#define LPUART_CTRL_TE_MASK (0x80000U)
16591#define LPUART_CTRL_TE_SHIFT (19U)
16596#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
16597#define LPUART_CTRL_ILIE_MASK (0x100000U)
16598#define LPUART_CTRL_ILIE_SHIFT (20U)
16603#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
16604#define LPUART_CTRL_RIE_MASK (0x200000U)
16605#define LPUART_CTRL_RIE_SHIFT (21U)
16610#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
16611#define LPUART_CTRL_TCIE_MASK (0x400000U)
16612#define LPUART_CTRL_TCIE_SHIFT (22U)
16617#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
16618#define LPUART_CTRL_TIE_MASK (0x800000U)
16619#define LPUART_CTRL_TIE_SHIFT (23U)
16624#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
16625#define LPUART_CTRL_PEIE_MASK (0x1000000U)
16626#define LPUART_CTRL_PEIE_SHIFT (24U)
16631#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
16632#define LPUART_CTRL_FEIE_MASK (0x2000000U)
16633#define LPUART_CTRL_FEIE_SHIFT (25U)
16638#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
16639#define LPUART_CTRL_NEIE_MASK (0x4000000U)
16640#define LPUART_CTRL_NEIE_SHIFT (26U)
16645#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
16646#define LPUART_CTRL_ORIE_MASK (0x8000000U)
16647#define LPUART_CTRL_ORIE_SHIFT (27U)
16652#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
16653#define LPUART_CTRL_TXINV_MASK (0x10000000U)
16654#define LPUART_CTRL_TXINV_SHIFT (28U)
16659#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
16660#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
16661#define LPUART_CTRL_TXDIR_SHIFT (29U)
16666#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
16667#define LPUART_CTRL_R9T8_MASK (0x40000000U)
16668#define LPUART_CTRL_R9T8_SHIFT (30U)
16669#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
16670#define LPUART_CTRL_R8T9_MASK (0x80000000U)
16671#define LPUART_CTRL_R8T9_SHIFT (31U)
16672#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
16677#define LPUART_DATA_R0T0_MASK (0x1U)
16678#define LPUART_DATA_R0T0_SHIFT (0U)
16679#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
16680#define LPUART_DATA_R1T1_MASK (0x2U)
16681#define LPUART_DATA_R1T1_SHIFT (1U)
16682#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
16683#define LPUART_DATA_R2T2_MASK (0x4U)
16684#define LPUART_DATA_R2T2_SHIFT (2U)
16685#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
16686#define LPUART_DATA_R3T3_MASK (0x8U)
16687#define LPUART_DATA_R3T3_SHIFT (3U)
16688#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
16689#define LPUART_DATA_R4T4_MASK (0x10U)
16690#define LPUART_DATA_R4T4_SHIFT (4U)
16691#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
16692#define LPUART_DATA_R5T5_MASK (0x20U)
16693#define LPUART_DATA_R5T5_SHIFT (5U)
16694#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
16695#define LPUART_DATA_R6T6_MASK (0x40U)
16696#define LPUART_DATA_R6T6_SHIFT (6U)
16697#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
16698#define LPUART_DATA_R7T7_MASK (0x80U)
16699#define LPUART_DATA_R7T7_SHIFT (7U)
16700#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
16701#define LPUART_DATA_R8T8_MASK (0x100U)
16702#define LPUART_DATA_R8T8_SHIFT (8U)
16703#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
16704#define LPUART_DATA_R9T9_MASK (0x200U)
16705#define LPUART_DATA_R9T9_SHIFT (9U)
16706#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
16707#define LPUART_DATA_IDLINE_MASK (0x800U)
16708#define LPUART_DATA_IDLINE_SHIFT (11U)
16713#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
16714#define LPUART_DATA_RXEMPT_MASK (0x1000U)
16715#define LPUART_DATA_RXEMPT_SHIFT (12U)
16720#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
16721#define LPUART_DATA_FRETSC_MASK (0x2000U)
16722#define LPUART_DATA_FRETSC_SHIFT (13U)
16727#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
16728#define LPUART_DATA_PARITYE_MASK (0x4000U)
16729#define LPUART_DATA_PARITYE_SHIFT (14U)
16734#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
16735#define LPUART_DATA_NOISY_MASK (0x8000U)
16736#define LPUART_DATA_NOISY_SHIFT (15U)
16741#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
16746#define LPUART_MATCH_MA1_MASK (0x3FFU)
16747#define LPUART_MATCH_MA1_SHIFT (0U)
16748#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
16749#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
16750#define LPUART_MATCH_MA2_SHIFT (16U)
16751#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
16756#define LPUART_MODIR_TXCTSE_MASK (0x1U)
16757#define LPUART_MODIR_TXCTSE_SHIFT (0U)
16762#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
16763#define LPUART_MODIR_TXRTSE_MASK (0x2U)
16764#define LPUART_MODIR_TXRTSE_SHIFT (1U)
16769#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
16770#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
16771#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
16776#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
16777#define LPUART_MODIR_RXRTSE_MASK (0x8U)
16778#define LPUART_MODIR_RXRTSE_SHIFT (3U)
16783#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
16784#define LPUART_MODIR_TXCTSC_MASK (0x10U)
16785#define LPUART_MODIR_TXCTSC_SHIFT (4U)
16790#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
16791#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
16792#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
16797#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
16798#define LPUART_MODIR_TNP_MASK (0x30000U)
16799#define LPUART_MODIR_TNP_SHIFT (16U)
16806#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
16807#define LPUART_MODIR_IREN_MASK (0x40000U)
16808#define LPUART_MODIR_IREN_SHIFT (18U)
16813#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
16819 /* end of group LPUART_Register_Masks */
16820
16821
16822/* LPUART - Peripheral instance base addresses */
16824#define LPUART0_BASE (0x400C4000u)
16826#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
16828#define LPUART_BASE_ADDRS { LPUART0_BASE }
16830#define LPUART_BASE_PTRS { LPUART0 }
16832#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
16833#define LPUART_ERR_IRQS { LPUART0_IRQn }
16834
16837 /* end of group LPUART_Peripheral_Access_Layer */
16838
16839
16840/* ----------------------------------------------------------------------------
16841 -- MCG Peripheral Access Layer
16842 ---------------------------------------------------------------------------- */
16843
16850typedef struct {
16851 __IO uint8_t C1;
16852 __IO uint8_t C2;
16853 __IO uint8_t C3;
16854 __IO uint8_t C4;
16855 __IO uint8_t C5;
16856 __IO uint8_t C6;
16857 __IO uint8_t S;
16858 uint8_t RESERVED_0[1];
16859 __IO uint8_t SC;
16860 uint8_t RESERVED_1[1];
16861 __IO uint8_t ATCVH;
16862 __IO uint8_t ATCVL;
16863 __IO uint8_t C7;
16864 __IO uint8_t C8;
16865 __IO uint8_t C9;
16866 uint8_t RESERVED_2[1];
16867 __IO uint8_t C11;
16868 uint8_t RESERVED_3[1];
16869 __I uint8_t S2;
16870} MCG_Type;
16871
16872/* ----------------------------------------------------------------------------
16873 -- MCG Register Masks
16874 ---------------------------------------------------------------------------- */
16875
16883#define MCG_C1_IREFSTEN_MASK (0x1U)
16884#define MCG_C1_IREFSTEN_SHIFT (0U)
16889#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
16890#define MCG_C1_IRCLKEN_MASK (0x2U)
16891#define MCG_C1_IRCLKEN_SHIFT (1U)
16896#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
16897#define MCG_C1_IREFS_MASK (0x4U)
16898#define MCG_C1_IREFS_SHIFT (2U)
16903#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
16904#define MCG_C1_FRDIV_MASK (0x38U)
16905#define MCG_C1_FRDIV_SHIFT (3U)
16916#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
16917#define MCG_C1_CLKS_MASK (0xC0U)
16918#define MCG_C1_CLKS_SHIFT (6U)
16925#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
16930#define MCG_C2_IRCS_MASK (0x1U)
16931#define MCG_C2_IRCS_SHIFT (0U)
16936#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
16937#define MCG_C2_LP_MASK (0x2U)
16938#define MCG_C2_LP_SHIFT (1U)
16943#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
16944#define MCG_C2_EREFS_MASK (0x4U)
16945#define MCG_C2_EREFS_SHIFT (2U)
16950#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
16951#define MCG_C2_HGO_MASK (0x8U)
16952#define MCG_C2_HGO_SHIFT (3U)
16957#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
16958#define MCG_C2_RANGE_MASK (0x30U)
16959#define MCG_C2_RANGE_SHIFT (4U)
16965#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
16966#define MCG_C2_FCFTRIM_MASK (0x40U)
16967#define MCG_C2_FCFTRIM_SHIFT (6U)
16968#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
16969#define MCG_C2_LOCRE0_MASK (0x80U)
16970#define MCG_C2_LOCRE0_SHIFT (7U)
16975#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
16980#define MCG_C3_SCTRIM_MASK (0xFFU)
16981#define MCG_C3_SCTRIM_SHIFT (0U)
16982#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
16987#define MCG_C4_SCFTRIM_MASK (0x1U)
16988#define MCG_C4_SCFTRIM_SHIFT (0U)
16989#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
16990#define MCG_C4_FCTRIM_MASK (0x1EU)
16991#define MCG_C4_FCTRIM_SHIFT (1U)
16992#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
16993#define MCG_C4_DRST_DRS_MASK (0x60U)
16994#define MCG_C4_DRST_DRS_SHIFT (5U)
17001#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
17002#define MCG_C4_DMX32_MASK (0x80U)
17003#define MCG_C4_DMX32_SHIFT (7U)
17008#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
17013#define MCG_C5_PRDIV_MASK (0x7U)
17014#define MCG_C5_PRDIV_SHIFT (0U)
17025#define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
17026#define MCG_C5_PLLSTEN_MASK (0x20U)
17027#define MCG_C5_PLLSTEN_SHIFT (5U)
17032#define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
17033#define MCG_C5_PLLCLKEN_MASK (0x40U)
17034#define MCG_C5_PLLCLKEN_SHIFT (6U)
17039#define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
17044#define MCG_C6_VDIV_MASK (0x1FU)
17045#define MCG_C6_VDIV_SHIFT (0U)
17080#define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
17081#define MCG_C6_CME0_MASK (0x20U)
17082#define MCG_C6_CME0_SHIFT (5U)
17087#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
17088#define MCG_C6_PLLS_MASK (0x40U)
17089#define MCG_C6_PLLS_SHIFT (6U)
17094#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
17095#define MCG_C6_LOLIE0_MASK (0x80U)
17096#define MCG_C6_LOLIE0_SHIFT (7U)
17101#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
17106#define MCG_S_IRCST_MASK (0x1U)
17107#define MCG_S_IRCST_SHIFT (0U)
17112#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
17113#define MCG_S_OSCINIT0_MASK (0x2U)
17114#define MCG_S_OSCINIT0_SHIFT (1U)
17115#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
17116#define MCG_S_CLKST_MASK (0xCU)
17117#define MCG_S_CLKST_SHIFT (2U)
17124#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
17125#define MCG_S_IREFST_MASK (0x10U)
17126#define MCG_S_IREFST_SHIFT (4U)
17131#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
17132#define MCG_S_PLLST_MASK (0x20U)
17133#define MCG_S_PLLST_SHIFT (5U)
17138#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
17139#define MCG_S_LOCK0_MASK (0x40U)
17140#define MCG_S_LOCK0_SHIFT (6U)
17145#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
17146#define MCG_S_LOLS0_MASK (0x80U)
17147#define MCG_S_LOLS0_SHIFT (7U)
17152#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
17157#define MCG_SC_LOCS0_MASK (0x1U)
17158#define MCG_SC_LOCS0_SHIFT (0U)
17163#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
17164#define MCG_SC_FCRDIV_MASK (0xEU)
17165#define MCG_SC_FCRDIV_SHIFT (1U)
17176#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
17177#define MCG_SC_FLTPRSRV_MASK (0x10U)
17178#define MCG_SC_FLTPRSRV_SHIFT (4U)
17183#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
17184#define MCG_SC_ATMF_MASK (0x20U)
17185#define MCG_SC_ATMF_SHIFT (5U)
17190#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
17191#define MCG_SC_ATMS_MASK (0x40U)
17192#define MCG_SC_ATMS_SHIFT (6U)
17197#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
17198#define MCG_SC_ATME_MASK (0x80U)
17199#define MCG_SC_ATME_SHIFT (7U)
17204#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
17209#define MCG_ATCVH_ATCVH_MASK (0xFFU)
17210#define MCG_ATCVH_ATCVH_SHIFT (0U)
17211#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
17216#define MCG_ATCVL_ATCVL_MASK (0xFFU)
17217#define MCG_ATCVL_ATCVL_SHIFT (0U)
17218#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
17223#define MCG_C7_OSCSEL_MASK (0x3U)
17224#define MCG_C7_OSCSEL_SHIFT (0U)
17231#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
17236#define MCG_C8_LOCS1_MASK (0x1U)
17237#define MCG_C8_LOCS1_SHIFT (0U)
17242#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
17243#define MCG_C8_CME1_MASK (0x20U)
17244#define MCG_C8_CME1_SHIFT (5U)
17249#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
17250#define MCG_C8_LOLRE_MASK (0x40U)
17251#define MCG_C8_LOLRE_SHIFT (6U)
17256#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
17257#define MCG_C8_LOCRE1_MASK (0x80U)
17258#define MCG_C8_LOCRE1_SHIFT (7U)
17263#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
17268#define MCG_C9_EXT_PLL_LOCS_MASK (0x1U)
17269#define MCG_C9_EXT_PLL_LOCS_SHIFT (0U)
17274#define MCG_C9_EXT_PLL_LOCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
17275#define MCG_C9_PLL_LOCRE_MASK (0x10U)
17276#define MCG_C9_PLL_LOCRE_SHIFT (4U)
17281#define MCG_C9_PLL_LOCRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
17282#define MCG_C9_PLL_CME_MASK (0x20U)
17283#define MCG_C9_PLL_CME_SHIFT (5U)
17288#define MCG_C9_PLL_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
17293#define MCG_C11_PLLCS_MASK (0x10U)
17294#define MCG_C11_PLLCS_SHIFT (4U)
17299#define MCG_C11_PLLCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
17304#define MCG_S2_PLLCST_MASK (0x10U)
17305#define MCG_S2_PLLCST_SHIFT (4U)
17310#define MCG_S2_PLLCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
17316 /* end of group MCG_Register_Masks */
17317
17318
17319/* MCG - Peripheral instance base addresses */
17321#define MCG_BASE (0x40064000u)
17323#define MCG ((MCG_Type *)MCG_BASE)
17325#define MCG_BASE_ADDRS { MCG_BASE }
17327#define MCG_BASE_PTRS { MCG }
17328/* MCG C5[PLLCLKEN0] backward compatibility */
17329#define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
17330#define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
17331#define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
17332#define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
17333
17334/* MCG C5[PLLSTEN0] backward compatibility */
17335#define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
17336#define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
17337#define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
17338#define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
17339
17340/* MCG C5[PRDIV0] backward compatibility */
17341#define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
17342#define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
17343#define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
17344#define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
17345
17346/* MCG C6[VDIV0] backward compatibility */
17347#define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
17348#define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
17349#define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
17350#define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
17351
17352
17355 /* end of group MCG_Peripheral_Access_Layer */
17356
17357
17358/* ----------------------------------------------------------------------------
17359 -- MCM Peripheral Access Layer
17360 ---------------------------------------------------------------------------- */
17361
17368typedef struct {
17369 uint8_t RESERVED_0[8];
17370 __I uint16_t PLASC;
17371 __I uint16_t PLAMC;
17372 __IO uint32_t CR;
17373 __IO uint32_t ISCR;
17374 __IO uint32_t ETBCC;
17375 __IO uint32_t ETBRL;
17376 __I uint32_t ETBCNT;
17377 __I uint32_t FADR;
17378 __I uint32_t FATR;
17379 __I uint32_t FDR;
17380 uint8_t RESERVED_1[4];
17381 __IO uint32_t PID;
17382 uint8_t RESERVED_2[12];
17383 __IO uint32_t CPO;
17384} MCM_Type;
17385
17386/* ----------------------------------------------------------------------------
17387 -- MCM Register Masks
17388 ---------------------------------------------------------------------------- */
17389
17397#define MCM_PLASC_ASC_MASK (0xFFU)
17398#define MCM_PLASC_ASC_SHIFT (0U)
17403#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
17408#define MCM_PLAMC_AMC_MASK (0xFFU)
17409#define MCM_PLAMC_AMC_SHIFT (0U)
17414#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
17419#define MCM_CR_SRAMUAP_MASK (0x3000000U)
17420#define MCM_CR_SRAMUAP_SHIFT (24U)
17427#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
17428#define MCM_CR_SRAMUWP_MASK (0x4000000U)
17429#define MCM_CR_SRAMUWP_SHIFT (26U)
17430#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
17431#define MCM_CR_SRAMLAP_MASK (0x30000000U)
17432#define MCM_CR_SRAMLAP_SHIFT (28U)
17439#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
17440#define MCM_CR_SRAMLWP_MASK (0x40000000U)
17441#define MCM_CR_SRAMLWP_SHIFT (30U)
17442#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
17447#define MCM_ISCR_IRQ_MASK (0x2U)
17448#define MCM_ISCR_IRQ_SHIFT (1U)
17453#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
17454#define MCM_ISCR_NMI_MASK (0x4U)
17455#define MCM_ISCR_NMI_SHIFT (2U)
17460#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
17461#define MCM_ISCR_DHREQ_MASK (0x8U)
17462#define MCM_ISCR_DHREQ_SHIFT (3U)
17467#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
17468#define MCM_ISCR_FIOC_MASK (0x100U)
17469#define MCM_ISCR_FIOC_SHIFT (8U)
17474#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
17475#define MCM_ISCR_FDZC_MASK (0x200U)
17476#define MCM_ISCR_FDZC_SHIFT (9U)
17481#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
17482#define MCM_ISCR_FOFC_MASK (0x400U)
17483#define MCM_ISCR_FOFC_SHIFT (10U)
17488#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
17489#define MCM_ISCR_FUFC_MASK (0x800U)
17490#define MCM_ISCR_FUFC_SHIFT (11U)
17495#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
17496#define MCM_ISCR_FIXC_MASK (0x1000U)
17497#define MCM_ISCR_FIXC_SHIFT (12U)
17502#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
17503#define MCM_ISCR_FIDC_MASK (0x8000U)
17504#define MCM_ISCR_FIDC_SHIFT (15U)
17509#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
17510#define MCM_ISCR_FIOCE_MASK (0x1000000U)
17511#define MCM_ISCR_FIOCE_SHIFT (24U)
17516#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
17517#define MCM_ISCR_FDZCE_MASK (0x2000000U)
17518#define MCM_ISCR_FDZCE_SHIFT (25U)
17523#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
17524#define MCM_ISCR_FOFCE_MASK (0x4000000U)
17525#define MCM_ISCR_FOFCE_SHIFT (26U)
17530#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
17531#define MCM_ISCR_FUFCE_MASK (0x8000000U)
17532#define MCM_ISCR_FUFCE_SHIFT (27U)
17537#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
17538#define MCM_ISCR_FIXCE_MASK (0x10000000U)
17539#define MCM_ISCR_FIXCE_SHIFT (28U)
17544#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
17545#define MCM_ISCR_FIDCE_MASK (0x80000000U)
17546#define MCM_ISCR_FIDCE_SHIFT (31U)
17551#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
17556#define MCM_ETBCC_CNTEN_MASK (0x1U)
17557#define MCM_ETBCC_CNTEN_SHIFT (0U)
17562#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
17563#define MCM_ETBCC_RSPT_MASK (0x6U)
17564#define MCM_ETBCC_RSPT_SHIFT (1U)
17571#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
17572#define MCM_ETBCC_RLRQ_MASK (0x8U)
17573#define MCM_ETBCC_RLRQ_SHIFT (3U)
17578#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
17579#define MCM_ETBCC_ETDIS_MASK (0x10U)
17580#define MCM_ETBCC_ETDIS_SHIFT (4U)
17585#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
17586#define MCM_ETBCC_ITDIS_MASK (0x20U)
17587#define MCM_ETBCC_ITDIS_SHIFT (5U)
17592#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
17597#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
17598#define MCM_ETBRL_RELOAD_SHIFT (0U)
17599#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
17604#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
17605#define MCM_ETBCNT_COUNTER_SHIFT (0U)
17606#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
17611#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
17612#define MCM_FADR_ADDRESS_SHIFT (0U)
17613#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
17618#define MCM_FATR_BEDA_MASK (0x1U)
17619#define MCM_FATR_BEDA_SHIFT (0U)
17624#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
17625#define MCM_FATR_BEMD_MASK (0x2U)
17626#define MCM_FATR_BEMD_SHIFT (1U)
17631#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
17632#define MCM_FATR_BESZ_MASK (0x30U)
17633#define MCM_FATR_BESZ_SHIFT (4U)
17640#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
17641#define MCM_FATR_BEWT_MASK (0x80U)
17642#define MCM_FATR_BEWT_SHIFT (7U)
17647#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
17648#define MCM_FATR_BEMN_MASK (0xF00U)
17649#define MCM_FATR_BEMN_SHIFT (8U)
17650#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
17651#define MCM_FATR_BEOVR_MASK (0x80000000U)
17652#define MCM_FATR_BEOVR_SHIFT (31U)
17657#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
17662#define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
17663#define MCM_FDR_DATA_SHIFT (0U)
17664#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
17669#define MCM_PID_PID_MASK (0xFFU)
17670#define MCM_PID_PID_SHIFT (0U)
17671#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
17676#define MCM_CPO_CPOREQ_MASK (0x1U)
17677#define MCM_CPO_CPOREQ_SHIFT (0U)
17682#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
17683#define MCM_CPO_CPOACK_MASK (0x2U)
17684#define MCM_CPO_CPOACK_SHIFT (1U)
17689#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
17690#define MCM_CPO_CPOWOI_MASK (0x4U)
17691#define MCM_CPO_CPOWOI_SHIFT (2U)
17696#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
17702 /* end of group MCM_Register_Masks */
17703
17704
17705/* MCM - Peripheral instance base addresses */
17707#define MCM_BASE (0xE0080000u)
17709#define MCM ((MCM_Type *)MCM_BASE)
17711#define MCM_BASE_ADDRS { MCM_BASE }
17713#define MCM_BASE_PTRS { MCM }
17715#define MCM_IRQS { MCM_IRQn }
17716
17719 /* end of group MCM_Peripheral_Access_Layer */
17720
17721
17722/* ----------------------------------------------------------------------------
17723 -- NV Peripheral Access Layer
17724 ---------------------------------------------------------------------------- */
17725
17732typedef struct {
17733 __I uint8_t BACKKEY3;
17734 __I uint8_t BACKKEY2;
17735 __I uint8_t BACKKEY1;
17736 __I uint8_t BACKKEY0;
17737 __I uint8_t BACKKEY7;
17738 __I uint8_t BACKKEY6;
17739 __I uint8_t BACKKEY5;
17740 __I uint8_t BACKKEY4;
17741 __I uint8_t FPROT3;
17742 __I uint8_t FPROT2;
17743 __I uint8_t FPROT1;
17744 __I uint8_t FPROT0;
17745 __I uint8_t FSEC;
17746 __I uint8_t FOPT;
17747 __I uint8_t FEPROT;
17748 __I uint8_t FDPROT;
17749} NV_Type;
17750
17751/* ----------------------------------------------------------------------------
17752 -- NV Register Masks
17753 ---------------------------------------------------------------------------- */
17754
17762#define NV_BACKKEY3_KEY_MASK (0xFFU)
17763#define NV_BACKKEY3_KEY_SHIFT (0U)
17764#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
17769#define NV_BACKKEY2_KEY_MASK (0xFFU)
17770#define NV_BACKKEY2_KEY_SHIFT (0U)
17771#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
17776#define NV_BACKKEY1_KEY_MASK (0xFFU)
17777#define NV_BACKKEY1_KEY_SHIFT (0U)
17778#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
17783#define NV_BACKKEY0_KEY_MASK (0xFFU)
17784#define NV_BACKKEY0_KEY_SHIFT (0U)
17785#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
17790#define NV_BACKKEY7_KEY_MASK (0xFFU)
17791#define NV_BACKKEY7_KEY_SHIFT (0U)
17792#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
17797#define NV_BACKKEY6_KEY_MASK (0xFFU)
17798#define NV_BACKKEY6_KEY_SHIFT (0U)
17799#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
17804#define NV_BACKKEY5_KEY_MASK (0xFFU)
17805#define NV_BACKKEY5_KEY_SHIFT (0U)
17806#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
17811#define NV_BACKKEY4_KEY_MASK (0xFFU)
17812#define NV_BACKKEY4_KEY_SHIFT (0U)
17813#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
17818#define NV_FPROT3_PROT_MASK (0xFFU)
17819#define NV_FPROT3_PROT_SHIFT (0U)
17820#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
17825#define NV_FPROT2_PROT_MASK (0xFFU)
17826#define NV_FPROT2_PROT_SHIFT (0U)
17827#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
17832#define NV_FPROT1_PROT_MASK (0xFFU)
17833#define NV_FPROT1_PROT_SHIFT (0U)
17834#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
17839#define NV_FPROT0_PROT_MASK (0xFFU)
17840#define NV_FPROT0_PROT_SHIFT (0U)
17841#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
17846#define NV_FSEC_SEC_MASK (0x3U)
17847#define NV_FSEC_SEC_SHIFT (0U)
17852#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
17853#define NV_FSEC_FSLACC_MASK (0xCU)
17854#define NV_FSEC_FSLACC_SHIFT (2U)
17859#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
17860#define NV_FSEC_MEEN_MASK (0x30U)
17861#define NV_FSEC_MEEN_SHIFT (4U)
17866#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
17867#define NV_FSEC_KEYEN_MASK (0xC0U)
17868#define NV_FSEC_KEYEN_SHIFT (6U)
17873#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
17878#define NV_FOPT_LPBOOT_MASK (0x1U)
17879#define NV_FOPT_LPBOOT_SHIFT (0U)
17884#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
17885#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
17886#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
17891#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
17892#define NV_FOPT_NMI_DIS_MASK (0x4U)
17893#define NV_FOPT_NMI_DIS_SHIFT (2U)
17898#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
17903#define NV_FEPROT_EPROT_MASK (0xFFU)
17904#define NV_FEPROT_EPROT_SHIFT (0U)
17905#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
17910#define NV_FDPROT_DPROT_MASK (0xFFU)
17911#define NV_FDPROT_DPROT_SHIFT (0U)
17912#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
17918 /* end of group NV_Register_Masks */
17919
17920
17921/* NV - Peripheral instance base addresses */
17923#define FTFE_FlashConfig_BASE (0x400u)
17925#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
17927#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
17929#define NV_BASE_PTRS { FTFE_FlashConfig }
17930
17933 /* end of group NV_Peripheral_Access_Layer */
17934
17935
17936/* ----------------------------------------------------------------------------
17937 -- OSC Peripheral Access Layer
17938 ---------------------------------------------------------------------------- */
17939
17946typedef struct {
17947 __IO uint8_t CR;
17948 uint8_t RESERVED_0[1];
17949 __IO uint8_t DIV;
17950} OSC_Type;
17951
17952/* ----------------------------------------------------------------------------
17953 -- OSC Register Masks
17954 ---------------------------------------------------------------------------- */
17955
17963#define OSC_CR_SC16P_MASK (0x1U)
17964#define OSC_CR_SC16P_SHIFT (0U)
17969#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
17970#define OSC_CR_SC8P_MASK (0x2U)
17971#define OSC_CR_SC8P_SHIFT (1U)
17976#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
17977#define OSC_CR_SC4P_MASK (0x4U)
17978#define OSC_CR_SC4P_SHIFT (2U)
17983#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
17984#define OSC_CR_SC2P_MASK (0x8U)
17985#define OSC_CR_SC2P_SHIFT (3U)
17990#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
17991#define OSC_CR_EREFSTEN_MASK (0x20U)
17992#define OSC_CR_EREFSTEN_SHIFT (5U)
17997#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
17998#define OSC_CR_ERCLKEN_MASK (0x80U)
17999#define OSC_CR_ERCLKEN_SHIFT (7U)
18004#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
18009#define OSC_DIV_ERPS_MASK (0xC0U)
18010#define OSC_DIV_ERPS_SHIFT (6U)
18017#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
18023 /* end of group OSC_Register_Masks */
18024
18025
18026/* OSC - Peripheral instance base addresses */
18028#define OSC_BASE (0x40065000u)
18030#define OSC ((OSC_Type *)OSC_BASE)
18032#define OSC_BASE_ADDRS { OSC_BASE }
18034#define OSC_BASE_PTRS { OSC }
18035
18038 /* end of group OSC_Peripheral_Access_Layer */
18039
18040
18041/* ----------------------------------------------------------------------------
18042 -- PDB Peripheral Access Layer
18043 ---------------------------------------------------------------------------- */
18044
18051typedef struct {
18052 __IO uint32_t SC;
18053 __IO uint32_t MOD;
18054 __I uint32_t CNT;
18055 __IO uint32_t IDLY;
18056 struct { /* offset: 0x10, array step: 0x28 */
18057 __IO uint32_t C1;
18058 __IO uint32_t S;
18059 __IO uint32_t DLY[2];
18060 uint8_t RESERVED_0[24];
18061 } CH[2];
18062 uint8_t RESERVED_0[240];
18063 struct { /* offset: 0x150, array step: 0x8 */
18064 __IO uint32_t INTC;
18065 __IO uint32_t INT;
18066 } DAC[2];
18067 uint8_t RESERVED_1[48];
18068 __IO uint32_t POEN;
18069 __IO uint32_t PODLY[4];
18070} PDB_Type;
18071
18072/* ----------------------------------------------------------------------------
18073 -- PDB Register Masks
18074 ---------------------------------------------------------------------------- */
18075
18083#define PDB_SC_LDOK_MASK (0x1U)
18084#define PDB_SC_LDOK_SHIFT (0U)
18085#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
18086#define PDB_SC_CONT_MASK (0x2U)
18087#define PDB_SC_CONT_SHIFT (1U)
18092#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
18093#define PDB_SC_MULT_MASK (0xCU)
18094#define PDB_SC_MULT_SHIFT (2U)
18101#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
18102#define PDB_SC_PDBIE_MASK (0x20U)
18103#define PDB_SC_PDBIE_SHIFT (5U)
18108#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
18109#define PDB_SC_PDBIF_MASK (0x40U)
18110#define PDB_SC_PDBIF_SHIFT (6U)
18111#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
18112#define PDB_SC_PDBEN_MASK (0x80U)
18113#define PDB_SC_PDBEN_SHIFT (7U)
18118#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
18119#define PDB_SC_TRGSEL_MASK (0xF00U)
18120#define PDB_SC_TRGSEL_SHIFT (8U)
18139#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
18140#define PDB_SC_PRESCALER_MASK (0x7000U)
18141#define PDB_SC_PRESCALER_SHIFT (12U)
18152#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
18153#define PDB_SC_DMAEN_MASK (0x8000U)
18154#define PDB_SC_DMAEN_SHIFT (15U)
18159#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
18160#define PDB_SC_SWTRIG_MASK (0x10000U)
18161#define PDB_SC_SWTRIG_SHIFT (16U)
18162#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
18163#define PDB_SC_PDBEIE_MASK (0x20000U)
18164#define PDB_SC_PDBEIE_SHIFT (17U)
18169#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
18170#define PDB_SC_LDMOD_MASK (0xC0000U)
18171#define PDB_SC_LDMOD_SHIFT (18U)
18178#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
18183#define PDB_MOD_MOD_MASK (0xFFFFU)
18184#define PDB_MOD_MOD_SHIFT (0U)
18185#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
18190#define PDB_CNT_CNT_MASK (0xFFFFU)
18191#define PDB_CNT_CNT_SHIFT (0U)
18192#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
18197#define PDB_IDLY_IDLY_MASK (0xFFFFU)
18198#define PDB_IDLY_IDLY_SHIFT (0U)
18199#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
18204#define PDB_C1_EN_MASK (0xFFU)
18205#define PDB_C1_EN_SHIFT (0U)
18210#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
18211#define PDB_C1_TOS_MASK (0xFF00U)
18212#define PDB_C1_TOS_SHIFT (8U)
18217#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
18218#define PDB_C1_BB_MASK (0xFF0000U)
18219#define PDB_C1_BB_SHIFT (16U)
18224#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
18227/* The count of PDB_C1 */
18228#define PDB_C1_COUNT (2U)
18229
18232#define PDB_S_ERR_MASK (0xFFU)
18233#define PDB_S_ERR_SHIFT (0U)
18238#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
18239#define PDB_S_CF_MASK (0xFF0000U)
18240#define PDB_S_CF_SHIFT (16U)
18241#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
18244/* The count of PDB_S */
18245#define PDB_S_COUNT (2U)
18246
18249#define PDB_DLY_DLY_MASK (0xFFFFU)
18250#define PDB_DLY_DLY_SHIFT (0U)
18251#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
18254/* The count of PDB_DLY */
18255#define PDB_DLY_COUNT (2U)
18256
18257/* The count of PDB_DLY */
18258#define PDB_DLY_COUNT2 (2U)
18259
18262#define PDB_INTC_TOE_MASK (0x1U)
18263#define PDB_INTC_TOE_SHIFT (0U)
18268#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
18269#define PDB_INTC_EXT_MASK (0x2U)
18270#define PDB_INTC_EXT_SHIFT (1U)
18275#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
18278/* The count of PDB_INTC */
18279#define PDB_INTC_COUNT (2U)
18280
18283#define PDB_INT_INT_MASK (0xFFFFU)
18284#define PDB_INT_INT_SHIFT (0U)
18285#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
18288/* The count of PDB_INT */
18289#define PDB_INT_COUNT (2U)
18290
18293#define PDB_POEN_POEN_MASK (0xFFU)
18294#define PDB_POEN_POEN_SHIFT (0U)
18299#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
18304#define PDB_PODLY_DLY2_MASK (0xFFFFU)
18305#define PDB_PODLY_DLY2_SHIFT (0U)
18306#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
18307#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
18308#define PDB_PODLY_DLY1_SHIFT (16U)
18309#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
18312/* The count of PDB_PODLY */
18313#define PDB_PODLY_COUNT (4U)
18314
18315
18318 /* end of group PDB_Register_Masks */
18319
18320
18321/* PDB - Peripheral instance base addresses */
18323#define PDB0_BASE (0x40036000u)
18325#define PDB0 ((PDB_Type *)PDB0_BASE)
18327#define PDB_BASE_ADDRS { PDB0_BASE }
18329#define PDB_BASE_PTRS { PDB0 }
18331#define PDB_IRQS { PDB0_IRQn }
18332
18335 /* end of group PDB_Peripheral_Access_Layer */
18336
18337
18338/* ----------------------------------------------------------------------------
18339 -- PIT Peripheral Access Layer
18340 ---------------------------------------------------------------------------- */
18341
18348typedef struct {
18349 __IO uint32_t MCR;
18350 uint8_t RESERVED_0[220];
18351 __I uint32_t LTMR64H;
18352 __I uint32_t LTMR64L;
18353 uint8_t RESERVED_1[24];
18354 struct { /* offset: 0x100, array step: 0x10 */
18355 __IO uint32_t LDVAL;
18356 __I uint32_t CVAL;
18357 __IO uint32_t TCTRL;
18358 __IO uint32_t TFLG;
18359 } CHANNEL[4];
18360} PIT_Type;
18361
18362/* ----------------------------------------------------------------------------
18363 -- PIT Register Masks
18364 ---------------------------------------------------------------------------- */
18365
18373#define PIT_MCR_FRZ_MASK (0x1U)
18374#define PIT_MCR_FRZ_SHIFT (0U)
18379#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
18380#define PIT_MCR_MDIS_MASK (0x2U)
18381#define PIT_MCR_MDIS_SHIFT (1U)
18386#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
18391#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
18392#define PIT_LTMR64H_LTH_SHIFT (0U)
18393#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
18398#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
18399#define PIT_LTMR64L_LTL_SHIFT (0U)
18400#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
18405#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
18406#define PIT_LDVAL_TSV_SHIFT (0U)
18407#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
18410/* The count of PIT_LDVAL */
18411#define PIT_LDVAL_COUNT (4U)
18412
18415#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
18416#define PIT_CVAL_TVL_SHIFT (0U)
18417#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
18420/* The count of PIT_CVAL */
18421#define PIT_CVAL_COUNT (4U)
18422
18425#define PIT_TCTRL_TEN_MASK (0x1U)
18426#define PIT_TCTRL_TEN_SHIFT (0U)
18431#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
18432#define PIT_TCTRL_TIE_MASK (0x2U)
18433#define PIT_TCTRL_TIE_SHIFT (1U)
18438#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
18439#define PIT_TCTRL_CHN_MASK (0x4U)
18440#define PIT_TCTRL_CHN_SHIFT (2U)
18445#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
18448/* The count of PIT_TCTRL */
18449#define PIT_TCTRL_COUNT (4U)
18450
18453#define PIT_TFLG_TIF_MASK (0x1U)
18454#define PIT_TFLG_TIF_SHIFT (0U)
18459#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
18462/* The count of PIT_TFLG */
18463#define PIT_TFLG_COUNT (4U)
18464
18465
18468 /* end of group PIT_Register_Masks */
18469
18470
18471/* PIT - Peripheral instance base addresses */
18473#define PIT_BASE (0x40037000u)
18475#define PIT ((PIT_Type *)PIT_BASE)
18477#define PIT_BASE_ADDRS { PIT_BASE }
18479#define PIT_BASE_PTRS { PIT }
18481#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
18482
18485 /* end of group PIT_Peripheral_Access_Layer */
18486
18487
18488/* ----------------------------------------------------------------------------
18489 -- PMC Peripheral Access Layer
18490 ---------------------------------------------------------------------------- */
18491
18498typedef struct {
18499 __IO uint8_t LVDSC1;
18500 __IO uint8_t LVDSC2;
18501 __IO uint8_t REGSC;
18502} PMC_Type;
18503
18504/* ----------------------------------------------------------------------------
18505 -- PMC Register Masks
18506 ---------------------------------------------------------------------------- */
18507
18515#define PMC_LVDSC1_LVDV_MASK (0x3U)
18516#define PMC_LVDSC1_LVDV_SHIFT (0U)
18523#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
18524#define PMC_LVDSC1_LVDRE_MASK (0x10U)
18525#define PMC_LVDSC1_LVDRE_SHIFT (4U)
18530#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
18531#define PMC_LVDSC1_LVDIE_MASK (0x20U)
18532#define PMC_LVDSC1_LVDIE_SHIFT (5U)
18537#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
18538#define PMC_LVDSC1_LVDACK_MASK (0x40U)
18539#define PMC_LVDSC1_LVDACK_SHIFT (6U)
18540#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
18541#define PMC_LVDSC1_LVDF_MASK (0x80U)
18542#define PMC_LVDSC1_LVDF_SHIFT (7U)
18547#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
18552#define PMC_LVDSC2_LVWV_MASK (0x3U)
18553#define PMC_LVDSC2_LVWV_SHIFT (0U)
18560#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
18561#define PMC_LVDSC2_LVWIE_MASK (0x20U)
18562#define PMC_LVDSC2_LVWIE_SHIFT (5U)
18567#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
18568#define PMC_LVDSC2_LVWACK_MASK (0x40U)
18569#define PMC_LVDSC2_LVWACK_SHIFT (6U)
18570#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
18571#define PMC_LVDSC2_LVWF_MASK (0x80U)
18572#define PMC_LVDSC2_LVWF_SHIFT (7U)
18577#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
18582#define PMC_REGSC_BGBE_MASK (0x1U)
18583#define PMC_REGSC_BGBE_SHIFT (0U)
18588#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
18589#define PMC_REGSC_REGONS_MASK (0x4U)
18590#define PMC_REGSC_REGONS_SHIFT (2U)
18595#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
18596#define PMC_REGSC_ACKISO_MASK (0x8U)
18597#define PMC_REGSC_ACKISO_SHIFT (3U)
18602#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
18603#define PMC_REGSC_BGEN_MASK (0x10U)
18604#define PMC_REGSC_BGEN_SHIFT (4U)
18609#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
18615 /* end of group PMC_Register_Masks */
18616
18617
18618/* PMC - Peripheral instance base addresses */
18620#define PMC_BASE (0x4007D000u)
18622#define PMC ((PMC_Type *)PMC_BASE)
18624#define PMC_BASE_ADDRS { PMC_BASE }
18626#define PMC_BASE_PTRS { PMC }
18628#define PMC_IRQS { LVD_LVW_IRQn }
18629
18632 /* end of group PMC_Peripheral_Access_Layer */
18633
18634
18635/* ----------------------------------------------------------------------------
18636 -- PORT Peripheral Access Layer
18637 ---------------------------------------------------------------------------- */
18638
18645typedef struct {
18646 __IO uint32_t PCR[32];
18647 __O uint32_t GPCLR;
18648 __O uint32_t GPCHR;
18649 uint8_t RESERVED_0[24];
18650 __IO uint32_t ISFR;
18651 uint8_t RESERVED_1[28];
18652 __IO uint32_t DFER;
18653 __IO uint32_t DFCR;
18654 __IO uint32_t DFWR;
18655} PORT_Type;
18656
18657/* ----------------------------------------------------------------------------
18658 -- PORT Register Masks
18659 ---------------------------------------------------------------------------- */
18660
18668#define PORT_PCR_PS_MASK (0x1U)
18669#define PORT_PCR_PS_SHIFT (0U)
18674#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
18675#define PORT_PCR_PE_MASK (0x2U)
18676#define PORT_PCR_PE_SHIFT (1U)
18681#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
18682#define PORT_PCR_SRE_MASK (0x4U)
18683#define PORT_PCR_SRE_SHIFT (2U)
18688#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
18689#define PORT_PCR_PFE_MASK (0x10U)
18690#define PORT_PCR_PFE_SHIFT (4U)
18695#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
18696#define PORT_PCR_ODE_MASK (0x20U)
18697#define PORT_PCR_ODE_SHIFT (5U)
18702#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
18703#define PORT_PCR_DSE_MASK (0x40U)
18704#define PORT_PCR_DSE_SHIFT (6U)
18709#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
18710#define PORT_PCR_MUX_MASK (0x700U)
18711#define PORT_PCR_MUX_SHIFT (8U)
18722#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
18723#define PORT_PCR_LK_MASK (0x8000U)
18724#define PORT_PCR_LK_SHIFT (15U)
18729#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
18730#define PORT_PCR_IRQC_MASK (0xF0000U)
18731#define PORT_PCR_IRQC_SHIFT (16U)
18750#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
18751#define PORT_PCR_ISF_MASK (0x1000000U)
18752#define PORT_PCR_ISF_SHIFT (24U)
18757#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
18760/* The count of PORT_PCR */
18761#define PORT_PCR_COUNT (32U)
18762
18765#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
18766#define PORT_GPCLR_GPWD_SHIFT (0U)
18767#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
18768#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
18769#define PORT_GPCLR_GPWE_SHIFT (16U)
18774#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
18779#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
18780#define PORT_GPCHR_GPWD_SHIFT (0U)
18781#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
18782#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
18783#define PORT_GPCHR_GPWE_SHIFT (16U)
18788#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
18793#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
18794#define PORT_ISFR_ISF_SHIFT (0U)
18799#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
18804#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
18805#define PORT_DFER_DFE_SHIFT (0U)
18810#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
18815#define PORT_DFCR_CS_MASK (0x1U)
18816#define PORT_DFCR_CS_SHIFT (0U)
18821#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
18826#define PORT_DFWR_FILT_MASK (0x1FU)
18827#define PORT_DFWR_FILT_SHIFT (0U)
18828#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
18834 /* end of group PORT_Register_Masks */
18835
18836
18837/* PORT - Peripheral instance base addresses */
18839#define PORTA_BASE (0x40049000u)
18841#define PORTA ((PORT_Type *)PORTA_BASE)
18843#define PORTB_BASE (0x4004A000u)
18845#define PORTB ((PORT_Type *)PORTB_BASE)
18847#define PORTC_BASE (0x4004B000u)
18849#define PORTC ((PORT_Type *)PORTC_BASE)
18851#define PORTD_BASE (0x4004C000u)
18853#define PORTD ((PORT_Type *)PORTD_BASE)
18855#define PORTE_BASE (0x4004D000u)
18857#define PORTE ((PORT_Type *)PORTE_BASE)
18859#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
18861#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
18863#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
18864
18867 /* end of group PORT_Peripheral_Access_Layer */
18868
18869
18870/* ----------------------------------------------------------------------------
18871 -- RCM Peripheral Access Layer
18872 ---------------------------------------------------------------------------- */
18873
18880typedef struct {
18881 __I uint8_t SRS0;
18882 __I uint8_t SRS1;
18883 uint8_t RESERVED_0[2];
18884 __IO uint8_t RPFC;
18885 __IO uint8_t RPFW;
18886 uint8_t RESERVED_1[1];
18887 __I uint8_t MR;
18888 __IO uint8_t SSRS0;
18889 __IO uint8_t SSRS1;
18890} RCM_Type;
18891
18892/* ----------------------------------------------------------------------------
18893 -- RCM Register Masks
18894 ---------------------------------------------------------------------------- */
18895
18903#define RCM_SRS0_WAKEUP_MASK (0x1U)
18904#define RCM_SRS0_WAKEUP_SHIFT (0U)
18909#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
18910#define RCM_SRS0_LVD_MASK (0x2U)
18911#define RCM_SRS0_LVD_SHIFT (1U)
18916#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
18917#define RCM_SRS0_LOC_MASK (0x4U)
18918#define RCM_SRS0_LOC_SHIFT (2U)
18923#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
18924#define RCM_SRS0_LOL_MASK (0x8U)
18925#define RCM_SRS0_LOL_SHIFT (3U)
18930#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
18931#define RCM_SRS0_WDOG_MASK (0x20U)
18932#define RCM_SRS0_WDOG_SHIFT (5U)
18937#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
18938#define RCM_SRS0_PIN_MASK (0x40U)
18939#define RCM_SRS0_PIN_SHIFT (6U)
18944#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
18945#define RCM_SRS0_POR_MASK (0x80U)
18946#define RCM_SRS0_POR_SHIFT (7U)
18951#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
18956#define RCM_SRS1_JTAG_MASK (0x1U)
18957#define RCM_SRS1_JTAG_SHIFT (0U)
18962#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
18963#define RCM_SRS1_LOCKUP_MASK (0x2U)
18964#define RCM_SRS1_LOCKUP_SHIFT (1U)
18969#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
18970#define RCM_SRS1_SW_MASK (0x4U)
18971#define RCM_SRS1_SW_SHIFT (2U)
18976#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
18977#define RCM_SRS1_MDM_AP_MASK (0x8U)
18978#define RCM_SRS1_MDM_AP_SHIFT (3U)
18983#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
18984#define RCM_SRS1_EZPT_MASK (0x10U)
18985#define RCM_SRS1_EZPT_SHIFT (4U)
18990#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
18991#define RCM_SRS1_SACKERR_MASK (0x20U)
18992#define RCM_SRS1_SACKERR_SHIFT (5U)
18997#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
19002#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
19003#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
19010#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
19011#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
19012#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
19017#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
19022#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
19023#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
19058#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
19063#define RCM_MR_EZP_MS_MASK (0x2U)
19064#define RCM_MR_EZP_MS_SHIFT (1U)
19069#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
19074#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
19075#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
19080#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
19081#define RCM_SSRS0_SLVD_MASK (0x2U)
19082#define RCM_SSRS0_SLVD_SHIFT (1U)
19087#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
19088#define RCM_SSRS0_SLOC_MASK (0x4U)
19089#define RCM_SSRS0_SLOC_SHIFT (2U)
19094#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
19095#define RCM_SSRS0_SLOL_MASK (0x8U)
19096#define RCM_SSRS0_SLOL_SHIFT (3U)
19101#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
19102#define RCM_SSRS0_SWDOG_MASK (0x20U)
19103#define RCM_SSRS0_SWDOG_SHIFT (5U)
19108#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
19109#define RCM_SSRS0_SPIN_MASK (0x40U)
19110#define RCM_SSRS0_SPIN_SHIFT (6U)
19115#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
19116#define RCM_SSRS0_SPOR_MASK (0x80U)
19117#define RCM_SSRS0_SPOR_SHIFT (7U)
19122#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
19127#define RCM_SSRS1_SJTAG_MASK (0x1U)
19128#define RCM_SSRS1_SJTAG_SHIFT (0U)
19133#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
19134#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
19135#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
19140#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
19141#define RCM_SSRS1_SSW_MASK (0x4U)
19142#define RCM_SSRS1_SSW_SHIFT (2U)
19147#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
19148#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
19149#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
19154#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
19155#define RCM_SSRS1_SEZPT_MASK (0x10U)
19156#define RCM_SSRS1_SEZPT_SHIFT (4U)
19161#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
19162#define RCM_SSRS1_SSACKERR_MASK (0x20U)
19163#define RCM_SSRS1_SSACKERR_SHIFT (5U)
19168#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
19174 /* end of group RCM_Register_Masks */
19175
19176
19177/* RCM - Peripheral instance base addresses */
19179#define RCM_BASE (0x4007F000u)
19181#define RCM ((RCM_Type *)RCM_BASE)
19183#define RCM_BASE_ADDRS { RCM_BASE }
19185#define RCM_BASE_PTRS { RCM }
19186
19189 /* end of group RCM_Peripheral_Access_Layer */
19190
19191
19192/* ----------------------------------------------------------------------------
19193 -- RFSYS Peripheral Access Layer
19194 ---------------------------------------------------------------------------- */
19195
19202typedef struct {
19203 __IO uint32_t REG[8];
19204} RFSYS_Type;
19205
19206/* ----------------------------------------------------------------------------
19207 -- RFSYS Register Masks
19208 ---------------------------------------------------------------------------- */
19209
19217#define RFSYS_REG_LL_MASK (0xFFU)
19218#define RFSYS_REG_LL_SHIFT (0U)
19219#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
19220#define RFSYS_REG_LH_MASK (0xFF00U)
19221#define RFSYS_REG_LH_SHIFT (8U)
19222#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
19223#define RFSYS_REG_HL_MASK (0xFF0000U)
19224#define RFSYS_REG_HL_SHIFT (16U)
19225#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
19226#define RFSYS_REG_HH_MASK (0xFF000000U)
19227#define RFSYS_REG_HH_SHIFT (24U)
19228#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
19231/* The count of RFSYS_REG */
19232#define RFSYS_REG_COUNT (8U)
19233
19234
19237 /* end of group RFSYS_Register_Masks */
19238
19239
19240/* RFSYS - Peripheral instance base addresses */
19242#define RFSYS_BASE (0x40041000u)
19244#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
19246#define RFSYS_BASE_ADDRS { RFSYS_BASE }
19248#define RFSYS_BASE_PTRS { RFSYS }
19249
19252 /* end of group RFSYS_Peripheral_Access_Layer */
19253
19254
19255/* ----------------------------------------------------------------------------
19256 -- RFVBAT Peripheral Access Layer
19257 ---------------------------------------------------------------------------- */
19258
19265typedef struct {
19266 __IO uint32_t REG[8];
19267} RFVBAT_Type;
19268
19269/* ----------------------------------------------------------------------------
19270 -- RFVBAT Register Masks
19271 ---------------------------------------------------------------------------- */
19272
19280#define RFVBAT_REG_LL_MASK (0xFFU)
19281#define RFVBAT_REG_LL_SHIFT (0U)
19282#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
19283#define RFVBAT_REG_LH_MASK (0xFF00U)
19284#define RFVBAT_REG_LH_SHIFT (8U)
19285#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
19286#define RFVBAT_REG_HL_MASK (0xFF0000U)
19287#define RFVBAT_REG_HL_SHIFT (16U)
19288#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
19289#define RFVBAT_REG_HH_MASK (0xFF000000U)
19290#define RFVBAT_REG_HH_SHIFT (24U)
19291#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
19294/* The count of RFVBAT_REG */
19295#define RFVBAT_REG_COUNT (8U)
19296
19297
19300 /* end of group RFVBAT_Register_Masks */
19301
19302
19303/* RFVBAT - Peripheral instance base addresses */
19305#define RFVBAT_BASE (0x4003E000u)
19307#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
19309#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
19311#define RFVBAT_BASE_PTRS { RFVBAT }
19312
19315 /* end of group RFVBAT_Peripheral_Access_Layer */
19316
19317
19318/* ----------------------------------------------------------------------------
19319 -- RNG Peripheral Access Layer
19320 ---------------------------------------------------------------------------- */
19321
19328typedef struct {
19329 __IO uint32_t CR;
19330 __I uint32_t SR;
19331 __O uint32_t ER;
19332 __I uint32_t OR;
19333} RNG_Type;
19334
19335/* ----------------------------------------------------------------------------
19336 -- RNG Register Masks
19337 ---------------------------------------------------------------------------- */
19338
19346#define RNG_CR_GO_MASK (0x1U)
19347#define RNG_CR_GO_SHIFT (0U)
19352#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
19353#define RNG_CR_HA_MASK (0x2U)
19354#define RNG_CR_HA_SHIFT (1U)
19359#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
19360#define RNG_CR_INTM_MASK (0x4U)
19361#define RNG_CR_INTM_SHIFT (2U)
19366#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
19367#define RNG_CR_CLRI_MASK (0x8U)
19368#define RNG_CR_CLRI_SHIFT (3U)
19373#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
19374#define RNG_CR_SLP_MASK (0x10U)
19375#define RNG_CR_SLP_SHIFT (4U)
19380#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
19385#define RNG_SR_SECV_MASK (0x1U)
19386#define RNG_SR_SECV_SHIFT (0U)
19391#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
19392#define RNG_SR_LRS_MASK (0x2U)
19393#define RNG_SR_LRS_SHIFT (1U)
19398#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
19399#define RNG_SR_ORU_MASK (0x4U)
19400#define RNG_SR_ORU_SHIFT (2U)
19405#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
19406#define RNG_SR_ERRI_MASK (0x8U)
19407#define RNG_SR_ERRI_SHIFT (3U)
19412#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
19413#define RNG_SR_SLP_MASK (0x10U)
19414#define RNG_SR_SLP_SHIFT (4U)
19419#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
19420#define RNG_SR_OREG_LVL_MASK (0xFF00U)
19421#define RNG_SR_OREG_LVL_SHIFT (8U)
19426#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
19427#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
19428#define RNG_SR_OREG_SIZE_SHIFT (16U)
19432#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
19437#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
19438#define RNG_ER_EXT_ENT_SHIFT (0U)
19439#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
19444#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
19445#define RNG_OR_RANDOUT_SHIFT (0U)
19449#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
19455 /* end of group RNG_Register_Masks */
19456
19457
19458/* RNG - Peripheral instance base addresses */
19460#define RNG_BASE (0x400A0000u)
19462#define RNG ((RNG_Type *)RNG_BASE)
19464#define RNG_BASE_ADDRS { RNG_BASE }
19466#define RNG_BASE_PTRS { RNG }
19468#define RNG_IRQS { RNG_IRQn }
19469
19472 /* end of group RNG_Peripheral_Access_Layer */
19473
19474
19475/* ----------------------------------------------------------------------------
19476 -- RTC Peripheral Access Layer
19477 ---------------------------------------------------------------------------- */
19478
19485typedef struct {
19486 __IO uint32_t TSR;
19487 __IO uint32_t TPR;
19488 __IO uint32_t TAR;
19489 __IO uint32_t TCR;
19490 __IO uint32_t CR;
19491 __IO uint32_t SR;
19492 __IO uint32_t LR;
19493 __IO uint32_t IER;
19494 __I uint32_t TTSR;
19495 __IO uint32_t MER;
19496 __IO uint32_t MCLR;
19497 __IO uint32_t MCHR;
19498 uint8_t RESERVED_0[2000];
19499 __IO uint32_t WAR;
19500 __IO uint32_t RAR;
19501} RTC_Type;
19502
19503/* ----------------------------------------------------------------------------
19504 -- RTC Register Masks
19505 ---------------------------------------------------------------------------- */
19506
19514#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
19515#define RTC_TSR_TSR_SHIFT (0U)
19516#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
19521#define RTC_TPR_TPR_MASK (0xFFFFU)
19522#define RTC_TPR_TPR_SHIFT (0U)
19523#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
19528#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
19529#define RTC_TAR_TAR_SHIFT (0U)
19530#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
19535#define RTC_TCR_TCR_MASK (0xFFU)
19536#define RTC_TCR_TCR_SHIFT (0U)
19544#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
19545#define RTC_TCR_CIR_MASK (0xFF00U)
19546#define RTC_TCR_CIR_SHIFT (8U)
19547#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
19548#define RTC_TCR_TCV_MASK (0xFF0000U)
19549#define RTC_TCR_TCV_SHIFT (16U)
19550#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
19551#define RTC_TCR_CIC_MASK (0xFF000000U)
19552#define RTC_TCR_CIC_SHIFT (24U)
19553#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
19558#define RTC_CR_SWR_MASK (0x1U)
19559#define RTC_CR_SWR_SHIFT (0U)
19564#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
19565#define RTC_CR_WPE_MASK (0x2U)
19566#define RTC_CR_WPE_SHIFT (1U)
19571#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
19572#define RTC_CR_SUP_MASK (0x4U)
19573#define RTC_CR_SUP_SHIFT (2U)
19578#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
19579#define RTC_CR_UM_MASK (0x8U)
19580#define RTC_CR_UM_SHIFT (3U)
19585#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
19586#define RTC_CR_WPS_MASK (0x10U)
19587#define RTC_CR_WPS_SHIFT (4U)
19592#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
19593#define RTC_CR_OSCE_MASK (0x100U)
19594#define RTC_CR_OSCE_SHIFT (8U)
19599#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
19600#define RTC_CR_CLKO_MASK (0x200U)
19601#define RTC_CR_CLKO_SHIFT (9U)
19606#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
19607#define RTC_CR_SC16P_MASK (0x400U)
19608#define RTC_CR_SC16P_SHIFT (10U)
19613#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
19614#define RTC_CR_SC8P_MASK (0x800U)
19615#define RTC_CR_SC8P_SHIFT (11U)
19620#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
19621#define RTC_CR_SC4P_MASK (0x1000U)
19622#define RTC_CR_SC4P_SHIFT (12U)
19627#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
19628#define RTC_CR_SC2P_MASK (0x2000U)
19629#define RTC_CR_SC2P_SHIFT (13U)
19634#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
19639#define RTC_SR_TIF_MASK (0x1U)
19640#define RTC_SR_TIF_SHIFT (0U)
19645#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
19646#define RTC_SR_TOF_MASK (0x2U)
19647#define RTC_SR_TOF_SHIFT (1U)
19652#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
19653#define RTC_SR_TAF_MASK (0x4U)
19654#define RTC_SR_TAF_SHIFT (2U)
19659#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
19660#define RTC_SR_MOF_MASK (0x8U)
19661#define RTC_SR_MOF_SHIFT (3U)
19666#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
19667#define RTC_SR_TCE_MASK (0x10U)
19668#define RTC_SR_TCE_SHIFT (4U)
19673#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
19678#define RTC_LR_TCL_MASK (0x8U)
19679#define RTC_LR_TCL_SHIFT (3U)
19684#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
19685#define RTC_LR_CRL_MASK (0x10U)
19686#define RTC_LR_CRL_SHIFT (4U)
19691#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
19692#define RTC_LR_SRL_MASK (0x20U)
19693#define RTC_LR_SRL_SHIFT (5U)
19698#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
19699#define RTC_LR_LRL_MASK (0x40U)
19700#define RTC_LR_LRL_SHIFT (6U)
19705#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
19706#define RTC_LR_TTSL_MASK (0x100U)
19707#define RTC_LR_TTSL_SHIFT (8U)
19712#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
19713#define RTC_LR_MEL_MASK (0x200U)
19714#define RTC_LR_MEL_SHIFT (9U)
19719#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
19720#define RTC_LR_MCLL_MASK (0x400U)
19721#define RTC_LR_MCLL_SHIFT (10U)
19726#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
19727#define RTC_LR_MCHL_MASK (0x800U)
19728#define RTC_LR_MCHL_SHIFT (11U)
19733#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
19738#define RTC_IER_TIIE_MASK (0x1U)
19739#define RTC_IER_TIIE_SHIFT (0U)
19744#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
19745#define RTC_IER_TOIE_MASK (0x2U)
19746#define RTC_IER_TOIE_SHIFT (1U)
19751#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
19752#define RTC_IER_TAIE_MASK (0x4U)
19753#define RTC_IER_TAIE_SHIFT (2U)
19758#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
19759#define RTC_IER_MOIE_MASK (0x8U)
19760#define RTC_IER_MOIE_SHIFT (3U)
19765#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
19766#define RTC_IER_TSIE_MASK (0x10U)
19767#define RTC_IER_TSIE_SHIFT (4U)
19772#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
19773#define RTC_IER_WPON_MASK (0x80U)
19774#define RTC_IER_WPON_SHIFT (7U)
19779#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
19784#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
19785#define RTC_TTSR_TTS_SHIFT (0U)
19786#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
19791#define RTC_MER_MCE_MASK (0x10U)
19792#define RTC_MER_MCE_SHIFT (4U)
19797#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
19802#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
19803#define RTC_MCLR_MCL_SHIFT (0U)
19804#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
19809#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
19810#define RTC_MCHR_MCH_SHIFT (0U)
19811#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
19816#define RTC_WAR_TSRW_MASK (0x1U)
19817#define RTC_WAR_TSRW_SHIFT (0U)
19822#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
19823#define RTC_WAR_TPRW_MASK (0x2U)
19824#define RTC_WAR_TPRW_SHIFT (1U)
19829#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
19830#define RTC_WAR_TARW_MASK (0x4U)
19831#define RTC_WAR_TARW_SHIFT (2U)
19836#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
19837#define RTC_WAR_TCRW_MASK (0x8U)
19838#define RTC_WAR_TCRW_SHIFT (3U)
19843#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
19844#define RTC_WAR_CRW_MASK (0x10U)
19845#define RTC_WAR_CRW_SHIFT (4U)
19850#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
19851#define RTC_WAR_SRW_MASK (0x20U)
19852#define RTC_WAR_SRW_SHIFT (5U)
19857#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
19858#define RTC_WAR_LRW_MASK (0x40U)
19859#define RTC_WAR_LRW_SHIFT (6U)
19864#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
19865#define RTC_WAR_IERW_MASK (0x80U)
19866#define RTC_WAR_IERW_SHIFT (7U)
19871#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
19872#define RTC_WAR_TTSW_MASK (0x100U)
19873#define RTC_WAR_TTSW_SHIFT (8U)
19878#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
19879#define RTC_WAR_MERW_MASK (0x200U)
19880#define RTC_WAR_MERW_SHIFT (9U)
19885#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
19886#define RTC_WAR_MCLW_MASK (0x400U)
19887#define RTC_WAR_MCLW_SHIFT (10U)
19892#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
19893#define RTC_WAR_MCHW_MASK (0x800U)
19894#define RTC_WAR_MCHW_SHIFT (11U)
19899#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
19904#define RTC_RAR_TSRR_MASK (0x1U)
19905#define RTC_RAR_TSRR_SHIFT (0U)
19910#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
19911#define RTC_RAR_TPRR_MASK (0x2U)
19912#define RTC_RAR_TPRR_SHIFT (1U)
19917#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
19918#define RTC_RAR_TARR_MASK (0x4U)
19919#define RTC_RAR_TARR_SHIFT (2U)
19924#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
19925#define RTC_RAR_TCRR_MASK (0x8U)
19926#define RTC_RAR_TCRR_SHIFT (3U)
19931#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
19932#define RTC_RAR_CRR_MASK (0x10U)
19933#define RTC_RAR_CRR_SHIFT (4U)
19938#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
19939#define RTC_RAR_SRR_MASK (0x20U)
19940#define RTC_RAR_SRR_SHIFT (5U)
19945#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
19946#define RTC_RAR_LRR_MASK (0x40U)
19947#define RTC_RAR_LRR_SHIFT (6U)
19952#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
19953#define RTC_RAR_IERR_MASK (0x80U)
19954#define RTC_RAR_IERR_SHIFT (7U)
19959#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
19960#define RTC_RAR_TTSR_MASK (0x100U)
19961#define RTC_RAR_TTSR_SHIFT (8U)
19966#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
19967#define RTC_RAR_MERR_MASK (0x200U)
19968#define RTC_RAR_MERR_SHIFT (9U)
19973#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
19974#define RTC_RAR_MCLR_MASK (0x400U)
19975#define RTC_RAR_MCLR_SHIFT (10U)
19980#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
19981#define RTC_RAR_MCHR_MASK (0x800U)
19982#define RTC_RAR_MCHR_SHIFT (11U)
19987#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
19993 /* end of group RTC_Register_Masks */
19994
19995
19996/* RTC - Peripheral instance base addresses */
19998#define RTC_BASE (0x4003D000u)
20000#define RTC ((RTC_Type *)RTC_BASE)
20002#define RTC_BASE_ADDRS { RTC_BASE }
20004#define RTC_BASE_PTRS { RTC }
20006#define RTC_IRQS { RTC_IRQn }
20007#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
20008
20011 /* end of group RTC_Peripheral_Access_Layer */
20012
20013
20014/* ----------------------------------------------------------------------------
20015 -- SDHC Peripheral Access Layer
20016 ---------------------------------------------------------------------------- */
20017
20024typedef struct {
20025 __IO uint32_t DSADDR;
20026 __IO uint32_t BLKATTR;
20027 __IO uint32_t CMDARG;
20028 __IO uint32_t XFERTYP;
20029 __I uint32_t CMDRSP[4];
20030 __IO uint32_t DATPORT;
20031 __I uint32_t PRSSTAT;
20032 __IO uint32_t PROCTL;
20033 __IO uint32_t SYSCTL;
20034 __IO uint32_t IRQSTAT;
20035 __IO uint32_t IRQSTATEN;
20036 __IO uint32_t IRQSIGEN;
20037 __I uint32_t AC12ERR;
20038 __I uint32_t HTCAPBLT;
20039 __IO uint32_t WML;
20040 uint8_t RESERVED_0[8];
20041 __O uint32_t FEVT;
20042 __I uint32_t ADMAES;
20043 __IO uint32_t ADSADDR;
20044 uint8_t RESERVED_1[100];
20045 __IO uint32_t VENDOR;
20046 __IO uint32_t MMCBOOT;
20047 uint8_t RESERVED_2[52];
20048 __I uint32_t HOSTVER;
20049} SDHC_Type;
20050
20051/* ----------------------------------------------------------------------------
20052 -- SDHC Register Masks
20053 ---------------------------------------------------------------------------- */
20054
20062#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
20063#define SDHC_DSADDR_DSADDR_SHIFT (2U)
20064#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
20069#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
20070#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
20082#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
20083#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
20084#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
20091#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
20096#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
20097#define SDHC_CMDARG_CMDARG_SHIFT (0U)
20098#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
20103#define SDHC_XFERTYP_DMAEN_MASK (0x1U)
20104#define SDHC_XFERTYP_DMAEN_SHIFT (0U)
20109#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
20110#define SDHC_XFERTYP_BCEN_MASK (0x2U)
20111#define SDHC_XFERTYP_BCEN_SHIFT (1U)
20116#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
20117#define SDHC_XFERTYP_AC12EN_MASK (0x4U)
20118#define SDHC_XFERTYP_AC12EN_SHIFT (2U)
20123#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
20124#define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
20125#define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
20130#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
20131#define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
20132#define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
20137#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
20138#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
20139#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
20146#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
20147#define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
20148#define SDHC_XFERTYP_CCCEN_SHIFT (19U)
20153#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
20154#define SDHC_XFERTYP_CICEN_MASK (0x100000U)
20155#define SDHC_XFERTYP_CICEN_SHIFT (20U)
20160#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
20161#define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
20162#define SDHC_XFERTYP_DPSEL_SHIFT (21U)
20167#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
20168#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
20169#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
20176#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
20177#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
20178#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
20179#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
20184#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
20185#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
20186#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
20187#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
20188#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
20189#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
20190#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
20191#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
20192#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
20193#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
20194#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
20195#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
20198/* The count of SDHC_CMDRSP */
20199#define SDHC_CMDRSP_COUNT (4U)
20200
20203#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
20204#define SDHC_DATPORT_DATCONT_SHIFT (0U)
20205#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
20210#define SDHC_PRSSTAT_CIHB_MASK (0x1U)
20211#define SDHC_PRSSTAT_CIHB_SHIFT (0U)
20216#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
20217#define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
20218#define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
20223#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
20224#define SDHC_PRSSTAT_DLA_MASK (0x4U)
20225#define SDHC_PRSSTAT_DLA_SHIFT (2U)
20230#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
20231#define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
20232#define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
20237#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
20238#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
20239#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
20244#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
20245#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
20246#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
20251#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
20252#define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
20253#define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
20258#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
20259#define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
20260#define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
20265#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
20266#define SDHC_PRSSTAT_WTA_MASK (0x100U)
20267#define SDHC_PRSSTAT_WTA_SHIFT (8U)
20272#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
20273#define SDHC_PRSSTAT_RTA_MASK (0x200U)
20274#define SDHC_PRSSTAT_RTA_SHIFT (9U)
20279#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
20280#define SDHC_PRSSTAT_BWEN_MASK (0x400U)
20281#define SDHC_PRSSTAT_BWEN_SHIFT (10U)
20286#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
20287#define SDHC_PRSSTAT_BREN_MASK (0x800U)
20288#define SDHC_PRSSTAT_BREN_SHIFT (11U)
20293#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
20294#define SDHC_PRSSTAT_CINS_MASK (0x10000U)
20295#define SDHC_PRSSTAT_CINS_SHIFT (16U)
20300#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
20301#define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
20302#define SDHC_PRSSTAT_CLSL_SHIFT (23U)
20303#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
20304#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
20305#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
20306#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
20311#define SDHC_PROCTL_LCTL_MASK (0x1U)
20312#define SDHC_PROCTL_LCTL_SHIFT (0U)
20317#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
20318#define SDHC_PROCTL_DTW_MASK (0x6U)
20319#define SDHC_PROCTL_DTW_SHIFT (1U)
20326#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
20327#define SDHC_PROCTL_D3CD_MASK (0x8U)
20328#define SDHC_PROCTL_D3CD_SHIFT (3U)
20333#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
20334#define SDHC_PROCTL_EMODE_MASK (0x30U)
20335#define SDHC_PROCTL_EMODE_SHIFT (4U)
20342#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
20343#define SDHC_PROCTL_CDTL_MASK (0x40U)
20344#define SDHC_PROCTL_CDTL_SHIFT (6U)
20349#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
20350#define SDHC_PROCTL_CDSS_MASK (0x80U)
20351#define SDHC_PROCTL_CDSS_SHIFT (7U)
20356#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
20357#define SDHC_PROCTL_DMAS_MASK (0x300U)
20358#define SDHC_PROCTL_DMAS_SHIFT (8U)
20365#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
20366#define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
20367#define SDHC_PROCTL_SABGREQ_SHIFT (16U)
20372#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
20373#define SDHC_PROCTL_CREQ_MASK (0x20000U)
20374#define SDHC_PROCTL_CREQ_SHIFT (17U)
20379#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
20380#define SDHC_PROCTL_RWCTL_MASK (0x40000U)
20381#define SDHC_PROCTL_RWCTL_SHIFT (18U)
20386#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
20387#define SDHC_PROCTL_IABG_MASK (0x80000U)
20388#define SDHC_PROCTL_IABG_SHIFT (19U)
20393#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
20394#define SDHC_PROCTL_WECINT_MASK (0x1000000U)
20395#define SDHC_PROCTL_WECINT_SHIFT (24U)
20400#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
20401#define SDHC_PROCTL_WECINS_MASK (0x2000000U)
20402#define SDHC_PROCTL_WECINS_SHIFT (25U)
20407#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
20408#define SDHC_PROCTL_WECRM_MASK (0x4000000U)
20409#define SDHC_PROCTL_WECRM_SHIFT (26U)
20414#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
20419#define SDHC_SYSCTL_IPGEN_MASK (0x1U)
20420#define SDHC_SYSCTL_IPGEN_SHIFT (0U)
20425#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
20426#define SDHC_SYSCTL_HCKEN_MASK (0x2U)
20427#define SDHC_SYSCTL_HCKEN_SHIFT (1U)
20432#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
20433#define SDHC_SYSCTL_PEREN_MASK (0x4U)
20434#define SDHC_SYSCTL_PEREN_SHIFT (2U)
20439#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
20440#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
20441#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
20442#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
20443#define SDHC_SYSCTL_DVS_MASK (0xF0U)
20444#define SDHC_SYSCTL_DVS_SHIFT (4U)
20451#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
20452#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
20453#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
20464#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
20465#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
20466#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
20473#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
20474#define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
20475#define SDHC_SYSCTL_RSTA_SHIFT (24U)
20480#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
20481#define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
20482#define SDHC_SYSCTL_RSTC_SHIFT (25U)
20487#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
20488#define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
20489#define SDHC_SYSCTL_RSTD_SHIFT (26U)
20494#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
20495#define SDHC_SYSCTL_INITA_MASK (0x8000000U)
20496#define SDHC_SYSCTL_INITA_SHIFT (27U)
20497#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
20502#define SDHC_IRQSTAT_CC_MASK (0x1U)
20503#define SDHC_IRQSTAT_CC_SHIFT (0U)
20508#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
20509#define SDHC_IRQSTAT_TC_MASK (0x2U)
20510#define SDHC_IRQSTAT_TC_SHIFT (1U)
20515#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
20516#define SDHC_IRQSTAT_BGE_MASK (0x4U)
20517#define SDHC_IRQSTAT_BGE_SHIFT (2U)
20522#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
20523#define SDHC_IRQSTAT_DINT_MASK (0x8U)
20524#define SDHC_IRQSTAT_DINT_SHIFT (3U)
20529#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
20530#define SDHC_IRQSTAT_BWR_MASK (0x10U)
20531#define SDHC_IRQSTAT_BWR_SHIFT (4U)
20536#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
20537#define SDHC_IRQSTAT_BRR_MASK (0x20U)
20538#define SDHC_IRQSTAT_BRR_SHIFT (5U)
20543#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
20544#define SDHC_IRQSTAT_CINS_MASK (0x40U)
20545#define SDHC_IRQSTAT_CINS_SHIFT (6U)
20550#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
20551#define SDHC_IRQSTAT_CRM_MASK (0x80U)
20552#define SDHC_IRQSTAT_CRM_SHIFT (7U)
20557#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
20558#define SDHC_IRQSTAT_CINT_MASK (0x100U)
20559#define SDHC_IRQSTAT_CINT_SHIFT (8U)
20564#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
20565#define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
20566#define SDHC_IRQSTAT_CTOE_SHIFT (16U)
20571#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
20572#define SDHC_IRQSTAT_CCE_MASK (0x20000U)
20573#define SDHC_IRQSTAT_CCE_SHIFT (17U)
20578#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
20579#define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
20580#define SDHC_IRQSTAT_CEBE_SHIFT (18U)
20585#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
20586#define SDHC_IRQSTAT_CIE_MASK (0x80000U)
20587#define SDHC_IRQSTAT_CIE_SHIFT (19U)
20592#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
20593#define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
20594#define SDHC_IRQSTAT_DTOE_SHIFT (20U)
20599#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
20600#define SDHC_IRQSTAT_DCE_MASK (0x200000U)
20601#define SDHC_IRQSTAT_DCE_SHIFT (21U)
20606#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
20607#define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
20608#define SDHC_IRQSTAT_DEBE_SHIFT (22U)
20613#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
20614#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
20615#define SDHC_IRQSTAT_AC12E_SHIFT (24U)
20620#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
20621#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
20622#define SDHC_IRQSTAT_DMAE_SHIFT (28U)
20627#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
20632#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
20633#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
20638#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
20639#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
20640#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
20645#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
20646#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
20647#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
20652#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
20653#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
20654#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
20659#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
20660#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
20661#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
20666#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
20667#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
20668#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
20673#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
20674#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
20675#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
20680#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
20681#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
20682#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
20687#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
20688#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
20689#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
20694#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
20695#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
20696#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
20701#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
20702#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
20703#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
20708#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
20709#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
20710#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
20715#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
20716#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
20717#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
20722#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
20723#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
20724#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
20729#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
20730#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
20731#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
20736#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
20737#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
20738#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
20743#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
20744#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
20745#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
20750#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
20751#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
20752#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
20757#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
20762#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
20763#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
20768#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
20769#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
20770#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
20775#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
20776#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
20777#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
20782#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
20783#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
20784#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
20789#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
20790#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
20791#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
20796#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
20797#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
20798#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
20803#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
20804#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
20805#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
20810#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
20811#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
20812#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
20817#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
20818#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
20819#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
20824#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
20825#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
20826#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
20831#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
20832#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
20833#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
20838#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
20839#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
20840#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
20845#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
20846#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
20847#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
20852#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
20853#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
20854#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
20859#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
20860#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
20861#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
20866#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
20867#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
20868#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
20873#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
20874#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
20875#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
20880#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
20881#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
20882#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
20887#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
20892#define SDHC_AC12ERR_AC12NE_MASK (0x1U)
20893#define SDHC_AC12ERR_AC12NE_SHIFT (0U)
20898#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
20899#define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
20900#define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
20905#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
20906#define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
20907#define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
20912#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
20913#define SDHC_AC12ERR_AC12CE_MASK (0x8U)
20914#define SDHC_AC12ERR_AC12CE_SHIFT (3U)
20919#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
20920#define SDHC_AC12ERR_AC12IE_MASK (0x10U)
20921#define SDHC_AC12ERR_AC12IE_SHIFT (4U)
20926#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
20927#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
20928#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
20933#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
20938#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
20939#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
20946#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
20947#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
20948#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
20953#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
20954#define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
20955#define SDHC_HTCAPBLT_HSS_SHIFT (21U)
20960#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
20961#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
20962#define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
20967#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
20968#define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
20969#define SDHC_HTCAPBLT_SRS_SHIFT (23U)
20974#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
20975#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
20976#define SDHC_HTCAPBLT_VS33_SHIFT (24U)
20981#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
20986#define SDHC_WML_RDWML_MASK (0xFFU)
20987#define SDHC_WML_RDWML_SHIFT (0U)
20988#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
20989#define SDHC_WML_WRWML_MASK (0xFF0000U)
20990#define SDHC_WML_WRWML_SHIFT (16U)
20991#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
20996#define SDHC_FEVT_AC12NE_MASK (0x1U)
20997#define SDHC_FEVT_AC12NE_SHIFT (0U)
20998#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
20999#define SDHC_FEVT_AC12TOE_MASK (0x2U)
21000#define SDHC_FEVT_AC12TOE_SHIFT (1U)
21001#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
21002#define SDHC_FEVT_AC12CE_MASK (0x4U)
21003#define SDHC_FEVT_AC12CE_SHIFT (2U)
21004#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
21005#define SDHC_FEVT_AC12EBE_MASK (0x8U)
21006#define SDHC_FEVT_AC12EBE_SHIFT (3U)
21007#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
21008#define SDHC_FEVT_AC12IE_MASK (0x10U)
21009#define SDHC_FEVT_AC12IE_SHIFT (4U)
21010#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
21011#define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
21012#define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
21013#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
21014#define SDHC_FEVT_CTOE_MASK (0x10000U)
21015#define SDHC_FEVT_CTOE_SHIFT (16U)
21016#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
21017#define SDHC_FEVT_CCE_MASK (0x20000U)
21018#define SDHC_FEVT_CCE_SHIFT (17U)
21019#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
21020#define SDHC_FEVT_CEBE_MASK (0x40000U)
21021#define SDHC_FEVT_CEBE_SHIFT (18U)
21022#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
21023#define SDHC_FEVT_CIE_MASK (0x80000U)
21024#define SDHC_FEVT_CIE_SHIFT (19U)
21025#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
21026#define SDHC_FEVT_DTOE_MASK (0x100000U)
21027#define SDHC_FEVT_DTOE_SHIFT (20U)
21028#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
21029#define SDHC_FEVT_DCE_MASK (0x200000U)
21030#define SDHC_FEVT_DCE_SHIFT (21U)
21031#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
21032#define SDHC_FEVT_DEBE_MASK (0x400000U)
21033#define SDHC_FEVT_DEBE_SHIFT (22U)
21034#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
21035#define SDHC_FEVT_AC12E_MASK (0x1000000U)
21036#define SDHC_FEVT_AC12E_SHIFT (24U)
21037#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
21038#define SDHC_FEVT_DMAE_MASK (0x10000000U)
21039#define SDHC_FEVT_DMAE_SHIFT (28U)
21040#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
21041#define SDHC_FEVT_CINT_MASK (0x80000000U)
21042#define SDHC_FEVT_CINT_SHIFT (31U)
21043#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
21048#define SDHC_ADMAES_ADMAES_MASK (0x3U)
21049#define SDHC_ADMAES_ADMAES_SHIFT (0U)
21050#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
21051#define SDHC_ADMAES_ADMALME_MASK (0x4U)
21052#define SDHC_ADMAES_ADMALME_SHIFT (2U)
21057#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
21058#define SDHC_ADMAES_ADMADCE_MASK (0x8U)
21059#define SDHC_ADMAES_ADMADCE_SHIFT (3U)
21064#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
21069#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
21070#define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
21071#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
21076#define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
21077#define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
21082#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
21083#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
21084#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
21085#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
21090#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
21091#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
21104#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
21105#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
21106#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
21111#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
21112#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
21113#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
21118#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
21119#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
21120#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
21125#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
21126#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
21127#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
21128#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
21129#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
21130#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
21131#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
21136#define SDHC_HOSTVER_SVN_MASK (0xFFU)
21137#define SDHC_HOSTVER_SVN_SHIFT (0U)
21141#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
21142#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
21143#define SDHC_HOSTVER_VVN_SHIFT (8U)
21150#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
21156 /* end of group SDHC_Register_Masks */
21157
21158
21159/* SDHC - Peripheral instance base addresses */
21161#define SDHC_BASE (0x400B1000u)
21163#define SDHC ((SDHC_Type *)SDHC_BASE)
21165#define SDHC_BASE_ADDRS { SDHC_BASE }
21167#define SDHC_BASE_PTRS { SDHC }
21169#define SDHC_IRQS { SDHC_IRQn }
21170
21173 /* end of group SDHC_Peripheral_Access_Layer */
21174
21175
21176/* ----------------------------------------------------------------------------
21177 -- SDRAM Peripheral Access Layer
21178 ---------------------------------------------------------------------------- */
21179
21186typedef struct {
21187 uint8_t RESERVED_0[66];
21188 __IO uint16_t CTRL;
21189 uint8_t RESERVED_1[4];
21190 struct { /* offset: 0x48, array step: 0x8 */
21191 __IO uint32_t AC;
21192 __IO uint32_t CM;
21193 } BLOCK[2];
21194} SDRAM_Type;
21195
21196/* ----------------------------------------------------------------------------
21197 -- SDRAM Register Masks
21198 ---------------------------------------------------------------------------- */
21199
21207#define SDRAM_CTRL_RC_MASK (0x1FFU)
21208#define SDRAM_CTRL_RC_SHIFT (0U)
21209#define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
21210#define SDRAM_CTRL_RTIM_MASK (0x600U)
21211#define SDRAM_CTRL_RTIM_SHIFT (9U)
21218#define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
21219#define SDRAM_CTRL_IS_MASK (0x800U)
21220#define SDRAM_CTRL_IS_SHIFT (11U)
21225#define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
21230#define SDRAM_AC_IP_MASK (0x8U)
21231#define SDRAM_AC_IP_SHIFT (3U)
21236#define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
21237#define SDRAM_AC_PS_MASK (0x30U)
21238#define SDRAM_AC_PS_SHIFT (4U)
21245#define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
21246#define SDRAM_AC_IMRS_MASK (0x40U)
21247#define SDRAM_AC_IMRS_SHIFT (6U)
21252#define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
21253#define SDRAM_AC_CBM_MASK (0x700U)
21254#define SDRAM_AC_CBM_SHIFT (8U)
21255#define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
21256#define SDRAM_AC_CASL_MASK (0x3000U)
21257#define SDRAM_AC_CASL_SHIFT (12U)
21258#define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
21259#define SDRAM_AC_RE_MASK (0x8000U)
21260#define SDRAM_AC_RE_SHIFT (15U)
21265#define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
21266#define SDRAM_AC_BA_MASK (0xFFFC0000U)
21267#define SDRAM_AC_BA_SHIFT (18U)
21268#define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
21271/* The count of SDRAM_AC */
21272#define SDRAM_AC_COUNT (2U)
21273
21276#define SDRAM_CM_V_MASK (0x1U)
21277#define SDRAM_CM_V_SHIFT (0U)
21282#define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
21283#define SDRAM_CM_WP_MASK (0x100U)
21284#define SDRAM_CM_WP_SHIFT (8U)
21289#define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
21290#define SDRAM_CM_BAM_MASK (0xFFFC0000U)
21291#define SDRAM_CM_BAM_SHIFT (18U)
21296#define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
21299/* The count of SDRAM_CM */
21300#define SDRAM_CM_COUNT (2U)
21301
21302
21305 /* end of group SDRAM_Register_Masks */
21306
21307
21308/* SDRAM - Peripheral instance base addresses */
21310#define SDRAM_BASE (0x4000F000u)
21312#define SDRAM ((SDRAM_Type *)SDRAM_BASE)
21314#define SDRAM_BASE_ADDRS { SDRAM_BASE }
21316#define SDRAM_BASE_PTRS { SDRAM }
21317
21320 /* end of group SDRAM_Peripheral_Access_Layer */
21321
21322
21323/* ----------------------------------------------------------------------------
21324 -- SIM Peripheral Access Layer
21325 ---------------------------------------------------------------------------- */
21326
21333typedef struct {
21334 __IO uint32_t SOPT1;
21335 __IO uint32_t SOPT1CFG;
21336 __IO uint32_t USBPHYCTL;
21337 uint8_t RESERVED_0[4088];
21338 __IO uint32_t SOPT2;
21339 uint8_t RESERVED_1[4];
21340 __IO uint32_t SOPT4;
21341 __IO uint32_t SOPT5;
21342 uint8_t RESERVED_2[4];
21343 __IO uint32_t SOPT7;
21344 __IO uint32_t SOPT8;
21345 __IO uint32_t SOPT9;
21346 __I uint32_t SDID;
21347 __IO uint32_t SCGC1;
21348 __IO uint32_t SCGC2;
21349 __IO uint32_t SCGC3;
21350 __IO uint32_t SCGC4;
21351 __IO uint32_t SCGC5;
21352 __IO uint32_t SCGC6;
21353 __IO uint32_t SCGC7;
21354 __IO uint32_t CLKDIV1;
21355 __IO uint32_t CLKDIV2;
21356 __IO uint32_t FCFG1;
21357 __I uint32_t FCFG2;
21358 __I uint32_t UIDH;
21359 __I uint32_t UIDMH;
21360 __I uint32_t UIDML;
21361 __I uint32_t UIDL;
21362 __IO uint32_t CLKDIV3;
21363 __IO uint32_t CLKDIV4;
21364} SIM_Type;
21365
21366/* ----------------------------------------------------------------------------
21367 -- SIM Register Masks
21368 ---------------------------------------------------------------------------- */
21369
21377#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
21378#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
21390#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
21391#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
21392#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
21399#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
21400#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
21401#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
21406#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
21407#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
21408#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
21413#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
21414#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
21415#define SIM_SOPT1_USBREGEN_SHIFT (31U)
21420#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
21425#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
21426#define SIM_SOPT1CFG_URWE_SHIFT (24U)
21431#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
21432#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
21433#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
21438#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
21439#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
21440#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
21445#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
21450#define SIM_USBPHYCTL_USBVREGSEL_MASK (0x100U)
21451#define SIM_USBPHYCTL_USBVREGSEL_SHIFT (8U)
21456#define SIM_USBPHYCTL_USBVREGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
21457#define SIM_USBPHYCTL_USBVREGPD_MASK (0x200U)
21458#define SIM_USBPHYCTL_USBVREGPD_SHIFT (9U)
21463#define SIM_USBPHYCTL_USBVREGPD(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
21464#define SIM_USBPHYCTL_USB3VOUTTRG_MASK (0x700000U)
21465#define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20U)
21476#define SIM_USBPHYCTL_USB3VOUTTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
21477#define SIM_USBPHYCTL_USBDISILIM_MASK (0x800000U)
21478#define SIM_USBPHYCTL_USBDISILIM_SHIFT (23U)
21483#define SIM_USBPHYCTL_USBDISILIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
21488#define SIM_SOPT2_USBSLSRC_MASK (0x1U)
21489#define SIM_SOPT2_USBSLSRC_SHIFT (0U)
21494#define SIM_SOPT2_USBSLSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
21495#define SIM_SOPT2_USBREGEN_MASK (0x2U)
21496#define SIM_SOPT2_USBREGEN_SHIFT (1U)
21501#define SIM_SOPT2_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
21502#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
21503#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
21508#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
21509#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
21510#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
21521#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
21522#define SIM_SOPT2_FBSL_MASK (0x300U)
21523#define SIM_SOPT2_FBSL_SHIFT (8U)
21530#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
21531#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
21532#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
21537#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
21538#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
21539#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
21546#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
21547#define SIM_SOPT2_USBSRC_MASK (0x40000U)
21548#define SIM_SOPT2_USBSRC_SHIFT (18U)
21553#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
21554#define SIM_SOPT2_RMIISRC_MASK (0x80000U)
21555#define SIM_SOPT2_RMIISRC_SHIFT (19U)
21560#define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
21561#define SIM_SOPT2_TIMESRC_MASK (0x300000U)
21562#define SIM_SOPT2_TIMESRC_SHIFT (20U)
21569#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
21570#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
21571#define SIM_SOPT2_TPMSRC_SHIFT (24U)
21578#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
21579#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
21580#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
21587#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
21588#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
21589#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
21596#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
21601#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
21602#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
21607#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
21608#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
21609#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
21614#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
21615#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
21616#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
21621#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
21622#define SIM_SOPT4_FTM0FLT3_MASK (0x8U)
21623#define SIM_SOPT4_FTM0FLT3_SHIFT (3U)
21628#define SIM_SOPT4_FTM0FLT3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
21629#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
21630#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
21635#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
21636#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
21637#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
21642#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
21643#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
21644#define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
21649#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
21650#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
21651#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
21658#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
21659#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
21660#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
21667#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
21668#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
21669#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
21674#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
21675#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
21676#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
21681#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
21682#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
21683#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
21688#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
21689#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
21690#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
21695#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
21696#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
21697#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
21702#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
21703#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
21704#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
21709#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
21710#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
21711#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
21716#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
21717#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
21718#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
21723#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
21724#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
21725#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
21730#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
21735#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
21736#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
21743#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
21744#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
21745#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
21752#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
21753#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
21754#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
21761#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
21762#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
21763#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
21770#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
21771#define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
21772#define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
21779#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
21780#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
21781#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
21788#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
21793#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
21794#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
21813#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
21814#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
21815#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
21820#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
21821#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
21822#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
21827#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
21828#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
21829#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
21848#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
21849#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
21850#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
21855#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
21856#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
21857#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
21862#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
21867#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
21868#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
21873#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
21874#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
21875#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
21880#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
21881#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
21882#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
21887#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
21888#define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
21889#define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
21894#define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
21895#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
21896#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
21901#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
21902#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
21903#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
21908#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
21909#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
21910#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
21915#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
21916#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
21917#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
21922#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
21923#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
21924#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
21929#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
21930#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
21931#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
21936#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
21937#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
21938#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
21943#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
21944#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
21945#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
21950#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
21951#define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
21952#define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
21957#define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
21958#define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
21959#define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
21964#define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
21965#define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
21966#define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
21971#define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
21972#define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
21973#define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
21978#define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
21979#define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
21980#define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
21985#define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
21986#define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
21987#define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
21992#define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
21993#define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
21994#define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
21999#define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
22000#define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
22001#define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
22006#define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
22011#define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
22012#define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
22019#define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
22020#define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
22021#define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
22028#define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
22029#define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
22030#define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
22035#define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
22036#define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
22037#define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
22042#define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
22047#define SIM_SDID_PINID_MASK (0xFU)
22048#define SIM_SDID_PINID_SHIFT (0U)
22067#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
22068#define SIM_SDID_FAMID_MASK (0x70U)
22069#define SIM_SDID_FAMID_SHIFT (4U)
22080#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
22081#define SIM_SDID_DIEID_MASK (0xF80U)
22082#define SIM_SDID_DIEID_SHIFT (7U)
22083#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
22084#define SIM_SDID_REVID_MASK (0xF000U)
22085#define SIM_SDID_REVID_SHIFT (12U)
22086#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
22087#define SIM_SDID_SERIESID_MASK (0xF00000U)
22088#define SIM_SDID_SERIESID_SHIFT (20U)
22095#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
22096#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
22097#define SIM_SDID_SUBFAMID_SHIFT (24U)
22107#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
22108#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
22109#define SIM_SDID_FAMILYID_SHIFT (28U)
22120#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
22125#define SIM_SCGC1_I2C2_MASK (0x40U)
22126#define SIM_SCGC1_I2C2_SHIFT (6U)
22131#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
22132#define SIM_SCGC1_I2C3_MASK (0x80U)
22133#define SIM_SCGC1_I2C3_SHIFT (7U)
22138#define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
22139#define SIM_SCGC1_UART4_MASK (0x400U)
22140#define SIM_SCGC1_UART4_SHIFT (10U)
22145#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
22150#define SIM_SCGC2_ENET_MASK (0x1U)
22151#define SIM_SCGC2_ENET_SHIFT (0U)
22156#define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
22157#define SIM_SCGC2_LPUART0_MASK (0x10U)
22158#define SIM_SCGC2_LPUART0_SHIFT (4U)
22163#define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
22164#define SIM_SCGC2_TPM1_MASK (0x200U)
22165#define SIM_SCGC2_TPM1_SHIFT (9U)
22170#define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
22171#define SIM_SCGC2_TPM2_MASK (0x400U)
22172#define SIM_SCGC2_TPM2_SHIFT (10U)
22177#define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
22178#define SIM_SCGC2_DAC0_MASK (0x1000U)
22179#define SIM_SCGC2_DAC0_SHIFT (12U)
22184#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
22185#define SIM_SCGC2_DAC1_MASK (0x2000U)
22186#define SIM_SCGC2_DAC1_SHIFT (13U)
22191#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
22196#define SIM_SCGC3_RNGA_MASK (0x1U)
22197#define SIM_SCGC3_RNGA_SHIFT (0U)
22202#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
22203#define SIM_SCGC3_USBHS_MASK (0x2U)
22204#define SIM_SCGC3_USBHS_SHIFT (1U)
22209#define SIM_SCGC3_USBHS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
22210#define SIM_SCGC3_USBHSPHY_MASK (0x4U)
22211#define SIM_SCGC3_USBHSPHY_SHIFT (2U)
22216#define SIM_SCGC3_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
22217#define SIM_SCGC3_USBHSDCD_MASK (0x8U)
22218#define SIM_SCGC3_USBHSDCD_SHIFT (3U)
22223#define SIM_SCGC3_USBHSDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
22224#define SIM_SCGC3_FLEXCAN1_MASK (0x10U)
22225#define SIM_SCGC3_FLEXCAN1_SHIFT (4U)
22230#define SIM_SCGC3_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
22231#define SIM_SCGC3_SPI2_MASK (0x1000U)
22232#define SIM_SCGC3_SPI2_SHIFT (12U)
22237#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
22238#define SIM_SCGC3_SDHC_MASK (0x20000U)
22239#define SIM_SCGC3_SDHC_SHIFT (17U)
22244#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
22245#define SIM_SCGC3_FTM2_MASK (0x1000000U)
22246#define SIM_SCGC3_FTM2_SHIFT (24U)
22251#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
22252#define SIM_SCGC3_FTM3_MASK (0x2000000U)
22253#define SIM_SCGC3_FTM3_SHIFT (25U)
22258#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
22259#define SIM_SCGC3_ADC1_MASK (0x8000000U)
22260#define SIM_SCGC3_ADC1_SHIFT (27U)
22265#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
22270#define SIM_SCGC4_EWM_MASK (0x2U)
22271#define SIM_SCGC4_EWM_SHIFT (1U)
22276#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
22277#define SIM_SCGC4_CMT_MASK (0x4U)
22278#define SIM_SCGC4_CMT_SHIFT (2U)
22283#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
22284#define SIM_SCGC4_I2C0_MASK (0x40U)
22285#define SIM_SCGC4_I2C0_SHIFT (6U)
22290#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
22291#define SIM_SCGC4_I2C1_MASK (0x80U)
22292#define SIM_SCGC4_I2C1_SHIFT (7U)
22297#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
22298#define SIM_SCGC4_UART0_MASK (0x400U)
22299#define SIM_SCGC4_UART0_SHIFT (10U)
22304#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
22305#define SIM_SCGC4_UART1_MASK (0x800U)
22306#define SIM_SCGC4_UART1_SHIFT (11U)
22311#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
22312#define SIM_SCGC4_UART2_MASK (0x1000U)
22313#define SIM_SCGC4_UART2_SHIFT (12U)
22318#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
22319#define SIM_SCGC4_UART3_MASK (0x2000U)
22320#define SIM_SCGC4_UART3_SHIFT (13U)
22325#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
22326#define SIM_SCGC4_USBOTG_MASK (0x40000U)
22327#define SIM_SCGC4_USBOTG_SHIFT (18U)
22332#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
22333#define SIM_SCGC4_CMP_MASK (0x80000U)
22334#define SIM_SCGC4_CMP_SHIFT (19U)
22339#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
22340#define SIM_SCGC4_VREF_MASK (0x100000U)
22341#define SIM_SCGC4_VREF_SHIFT (20U)
22346#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
22351#define SIM_SCGC5_LPTMR_MASK (0x1U)
22352#define SIM_SCGC5_LPTMR_SHIFT (0U)
22357#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
22358#define SIM_SCGC5_TSI_MASK (0x20U)
22359#define SIM_SCGC5_TSI_SHIFT (5U)
22364#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
22365#define SIM_SCGC5_PORTA_MASK (0x200U)
22366#define SIM_SCGC5_PORTA_SHIFT (9U)
22371#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
22372#define SIM_SCGC5_PORTB_MASK (0x400U)
22373#define SIM_SCGC5_PORTB_SHIFT (10U)
22378#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
22379#define SIM_SCGC5_PORTC_MASK (0x800U)
22380#define SIM_SCGC5_PORTC_SHIFT (11U)
22385#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
22386#define SIM_SCGC5_PORTD_MASK (0x1000U)
22387#define SIM_SCGC5_PORTD_SHIFT (12U)
22392#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
22393#define SIM_SCGC5_PORTE_MASK (0x2000U)
22394#define SIM_SCGC5_PORTE_SHIFT (13U)
22399#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
22404#define SIM_SCGC6_FTF_MASK (0x1U)
22405#define SIM_SCGC6_FTF_SHIFT (0U)
22410#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
22411#define SIM_SCGC6_DMAMUX_MASK (0x2U)
22412#define SIM_SCGC6_DMAMUX_SHIFT (1U)
22417#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
22418#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
22419#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
22424#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
22425#define SIM_SCGC6_RNGA_MASK (0x200U)
22426#define SIM_SCGC6_RNGA_SHIFT (9U)
22427#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
22428#define SIM_SCGC6_SPI0_MASK (0x1000U)
22429#define SIM_SCGC6_SPI0_SHIFT (12U)
22434#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
22435#define SIM_SCGC6_SPI1_MASK (0x2000U)
22436#define SIM_SCGC6_SPI1_SHIFT (13U)
22441#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
22442#define SIM_SCGC6_I2S_MASK (0x8000U)
22443#define SIM_SCGC6_I2S_SHIFT (15U)
22448#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
22449#define SIM_SCGC6_CRC_MASK (0x40000U)
22450#define SIM_SCGC6_CRC_SHIFT (18U)
22455#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
22456#define SIM_SCGC6_USBDCD_MASK (0x200000U)
22457#define SIM_SCGC6_USBDCD_SHIFT (21U)
22462#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
22463#define SIM_SCGC6_PDB_MASK (0x400000U)
22464#define SIM_SCGC6_PDB_SHIFT (22U)
22469#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
22470#define SIM_SCGC6_PIT_MASK (0x800000U)
22471#define SIM_SCGC6_PIT_SHIFT (23U)
22476#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
22477#define SIM_SCGC6_FTM0_MASK (0x1000000U)
22478#define SIM_SCGC6_FTM0_SHIFT (24U)
22483#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
22484#define SIM_SCGC6_FTM1_MASK (0x2000000U)
22485#define SIM_SCGC6_FTM1_SHIFT (25U)
22490#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
22491#define SIM_SCGC6_FTM2_MASK (0x4000000U)
22492#define SIM_SCGC6_FTM2_SHIFT (26U)
22497#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
22498#define SIM_SCGC6_ADC0_MASK (0x8000000U)
22499#define SIM_SCGC6_ADC0_SHIFT (27U)
22504#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
22505#define SIM_SCGC6_RTC_MASK (0x20000000U)
22506#define SIM_SCGC6_RTC_SHIFT (29U)
22511#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
22512#define SIM_SCGC6_DAC0_MASK (0x80000000U)
22513#define SIM_SCGC6_DAC0_SHIFT (31U)
22518#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
22523#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
22524#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
22529#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
22530#define SIM_SCGC7_DMA_MASK (0x2U)
22531#define SIM_SCGC7_DMA_SHIFT (1U)
22536#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
22537#define SIM_SCGC7_MPU_MASK (0x4U)
22538#define SIM_SCGC7_MPU_SHIFT (2U)
22543#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
22544#define SIM_SCGC7_SDRAMC_MASK (0x8U)
22545#define SIM_SCGC7_SDRAMC_SHIFT (3U)
22550#define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
22555#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
22556#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
22575#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
22576#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
22577#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
22596#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
22597#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
22598#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
22617#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
22618#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
22619#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
22638#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
22643#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
22644#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
22645#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
22646#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
22647#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
22648#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
22653#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
22654#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
22659#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
22660#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
22661#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
22666#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
22667#define SIM_FCFG1_DEPART_MASK (0xF00U)
22668#define SIM_FCFG1_DEPART_SHIFT (8U)
22669#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
22670#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
22671#define SIM_FCFG1_EESIZE_SHIFT (16U)
22685#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
22686#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
22687#define SIM_FCFG1_PFSIZE_SHIFT (24U)
22697#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
22698#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
22699#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
22709#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
22714#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
22715#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
22716#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
22717#define SIM_FCFG2_PFLSH_MASK (0x800000U)
22718#define SIM_FCFG2_PFLSH_SHIFT (23U)
22723#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
22724#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
22725#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
22726#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
22727#define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
22728#define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
22733#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
22738#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
22739#define SIM_UIDH_UID_SHIFT (0U)
22740#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
22745#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
22746#define SIM_UIDMH_UID_SHIFT (0U)
22747#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
22752#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
22753#define SIM_UIDML_UID_SHIFT (0U)
22754#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
22759#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
22760#define SIM_UIDL_UID_SHIFT (0U)
22761#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
22766#define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
22767#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
22768#define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
22769#define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
22770#define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
22771#define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
22776#define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
22777#define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
22778#define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
22779#define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
22780#define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
22781#define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
22787 /* end of group SIM_Register_Masks */
22788
22789
22790/* SIM - Peripheral instance base addresses */
22792#define SIM_BASE (0x40047000u)
22794#define SIM ((SIM_Type *)SIM_BASE)
22796#define SIM_BASE_ADDRS { SIM_BASE }
22798#define SIM_BASE_PTRS { SIM }
22799
22802 /* end of group SIM_Peripheral_Access_Layer */
22803
22804
22805/* ----------------------------------------------------------------------------
22806 -- SMC Peripheral Access Layer
22807 ---------------------------------------------------------------------------- */
22808
22815typedef struct {
22816 __IO uint8_t PMPROT;
22817 __IO uint8_t PMCTRL;
22818 __IO uint8_t STOPCTRL;
22819 __I uint8_t PMSTAT;
22820} SMC_Type;
22821
22822/* ----------------------------------------------------------------------------
22823 -- SMC Register Masks
22824 ---------------------------------------------------------------------------- */
22825
22833#define SMC_PMPROT_AVLLS_MASK (0x2U)
22834#define SMC_PMPROT_AVLLS_SHIFT (1U)
22839#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
22840#define SMC_PMPROT_ALLS_MASK (0x8U)
22841#define SMC_PMPROT_ALLS_SHIFT (3U)
22846#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
22847#define SMC_PMPROT_AVLP_MASK (0x20U)
22848#define SMC_PMPROT_AVLP_SHIFT (5U)
22853#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
22854#define SMC_PMPROT_AHSRUN_MASK (0x80U)
22855#define SMC_PMPROT_AHSRUN_SHIFT (7U)
22860#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
22865#define SMC_PMCTRL_STOPM_MASK (0x7U)
22866#define SMC_PMCTRL_STOPM_SHIFT (0U)
22877#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
22878#define SMC_PMCTRL_STOPA_MASK (0x8U)
22879#define SMC_PMCTRL_STOPA_SHIFT (3U)
22884#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
22885#define SMC_PMCTRL_RUNM_MASK (0x60U)
22886#define SMC_PMCTRL_RUNM_SHIFT (5U)
22893#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
22898#define SMC_STOPCTRL_LLSM_MASK (0x7U)
22899#define SMC_STOPCTRL_LLSM_SHIFT (0U)
22910#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
22911#define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
22912#define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
22917#define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
22918#define SMC_STOPCTRL_PORPO_MASK (0x20U)
22919#define SMC_STOPCTRL_PORPO_SHIFT (5U)
22924#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
22925#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
22926#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
22933#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
22938#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
22939#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
22940#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
22946 /* end of group SMC_Register_Masks */
22947
22948
22949/* SMC - Peripheral instance base addresses */
22951#define SMC_BASE (0x4007E000u)
22953#define SMC ((SMC_Type *)SMC_BASE)
22955#define SMC_BASE_ADDRS { SMC_BASE }
22957#define SMC_BASE_PTRS { SMC }
22958
22961 /* end of group SMC_Peripheral_Access_Layer */
22962
22963
22964/* ----------------------------------------------------------------------------
22965 -- SPI Peripheral Access Layer
22966 ---------------------------------------------------------------------------- */
22967
22974typedef struct {
22975 __IO uint32_t MCR;
22976 uint8_t RESERVED_0[4];
22977 __IO uint32_t TCR;
22978 union { /* offset: 0xC */
22979 __IO uint32_t CTAR[2];
22980 __IO uint32_t CTAR_SLAVE[1];
22981 };
22982 uint8_t RESERVED_1[24];
22983 __IO uint32_t SR;
22984 __IO uint32_t RSER;
22985 union { /* offset: 0x34 */
22986 __IO uint32_t PUSHR;
22987 __IO uint32_t PUSHR_SLAVE;
22988 };
22989 __I uint32_t POPR;
22990 __I uint32_t TXFR0;
22991 __I uint32_t TXFR1;
22992 __I uint32_t TXFR2;
22993 __I uint32_t TXFR3;
22994 uint8_t RESERVED_2[48];
22995 __I uint32_t RXFR0;
22996 __I uint32_t RXFR1;
22997 __I uint32_t RXFR2;
22998 __I uint32_t RXFR3;
22999} SPI_Type;
23000
23001/* ----------------------------------------------------------------------------
23002 -- SPI Register Masks
23003 ---------------------------------------------------------------------------- */
23004
23012#define SPI_MCR_HALT_MASK (0x1U)
23013#define SPI_MCR_HALT_SHIFT (0U)
23018#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
23019#define SPI_MCR_SMPL_PT_MASK (0x300U)
23020#define SPI_MCR_SMPL_PT_SHIFT (8U)
23027#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
23028#define SPI_MCR_CLR_RXF_MASK (0x400U)
23029#define SPI_MCR_CLR_RXF_SHIFT (10U)
23034#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
23035#define SPI_MCR_CLR_TXF_MASK (0x800U)
23036#define SPI_MCR_CLR_TXF_SHIFT (11U)
23041#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
23042#define SPI_MCR_DIS_RXF_MASK (0x1000U)
23043#define SPI_MCR_DIS_RXF_SHIFT (12U)
23048#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
23049#define SPI_MCR_DIS_TXF_MASK (0x2000U)
23050#define SPI_MCR_DIS_TXF_SHIFT (13U)
23055#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
23056#define SPI_MCR_MDIS_MASK (0x4000U)
23057#define SPI_MCR_MDIS_SHIFT (14U)
23062#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
23063#define SPI_MCR_DOZE_MASK (0x8000U)
23064#define SPI_MCR_DOZE_SHIFT (15U)
23069#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
23070#define SPI_MCR_PCSIS_MASK (0x3F0000U)
23071#define SPI_MCR_PCSIS_SHIFT (16U)
23076#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
23077#define SPI_MCR_ROOE_MASK (0x1000000U)
23078#define SPI_MCR_ROOE_SHIFT (24U)
23083#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
23084#define SPI_MCR_PCSSE_MASK (0x2000000U)
23085#define SPI_MCR_PCSSE_SHIFT (25U)
23090#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
23091#define SPI_MCR_MTFE_MASK (0x4000000U)
23092#define SPI_MCR_MTFE_SHIFT (26U)
23097#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
23098#define SPI_MCR_FRZ_MASK (0x8000000U)
23099#define SPI_MCR_FRZ_SHIFT (27U)
23104#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
23105#define SPI_MCR_DCONF_MASK (0x30000000U)
23106#define SPI_MCR_DCONF_SHIFT (28U)
23113#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
23114#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
23115#define SPI_MCR_CONT_SCKE_SHIFT (30U)
23120#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
23121#define SPI_MCR_MSTR_MASK (0x80000000U)
23122#define SPI_MCR_MSTR_SHIFT (31U)
23127#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
23132#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
23133#define SPI_TCR_SPI_TCNT_SHIFT (16U)
23134#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
23139#define SPI_CTAR_BR_MASK (0xFU)
23140#define SPI_CTAR_BR_SHIFT (0U)
23141#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
23142#define SPI_CTAR_DT_MASK (0xF0U)
23143#define SPI_CTAR_DT_SHIFT (4U)
23144#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
23145#define SPI_CTAR_ASC_MASK (0xF00U)
23146#define SPI_CTAR_ASC_SHIFT (8U)
23147#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
23148#define SPI_CTAR_CSSCK_MASK (0xF000U)
23149#define SPI_CTAR_CSSCK_SHIFT (12U)
23150#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
23151#define SPI_CTAR_PBR_MASK (0x30000U)
23152#define SPI_CTAR_PBR_SHIFT (16U)
23159#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
23160#define SPI_CTAR_PDT_MASK (0xC0000U)
23161#define SPI_CTAR_PDT_SHIFT (18U)
23168#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
23169#define SPI_CTAR_PASC_MASK (0x300000U)
23170#define SPI_CTAR_PASC_SHIFT (20U)
23177#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
23178#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
23179#define SPI_CTAR_PCSSCK_SHIFT (22U)
23186#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
23187#define SPI_CTAR_LSBFE_MASK (0x1000000U)
23188#define SPI_CTAR_LSBFE_SHIFT (24U)
23193#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
23194#define SPI_CTAR_CPHA_MASK (0x2000000U)
23195#define SPI_CTAR_CPHA_SHIFT (25U)
23200#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
23201#define SPI_CTAR_CPOL_MASK (0x4000000U)
23202#define SPI_CTAR_CPOL_SHIFT (26U)
23207#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
23208#define SPI_CTAR_FMSZ_MASK (0x78000000U)
23209#define SPI_CTAR_FMSZ_SHIFT (27U)
23210#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
23211#define SPI_CTAR_DBR_MASK (0x80000000U)
23212#define SPI_CTAR_DBR_SHIFT (31U)
23217#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
23220/* The count of SPI_CTAR */
23221#define SPI_CTAR_COUNT (2U)
23222
23225#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
23226#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
23231#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
23232#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
23233#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
23238#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
23239#define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
23240#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
23241#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
23244/* The count of SPI_CTAR_SLAVE */
23245#define SPI_CTAR_SLAVE_COUNT (1U)
23246
23249#define SPI_SR_POPNXTPTR_MASK (0xFU)
23250#define SPI_SR_POPNXTPTR_SHIFT (0U)
23251#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
23252#define SPI_SR_RXCTR_MASK (0xF0U)
23253#define SPI_SR_RXCTR_SHIFT (4U)
23254#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
23255#define SPI_SR_TXNXTPTR_MASK (0xF00U)
23256#define SPI_SR_TXNXTPTR_SHIFT (8U)
23257#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
23258#define SPI_SR_TXCTR_MASK (0xF000U)
23259#define SPI_SR_TXCTR_SHIFT (12U)
23260#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
23261#define SPI_SR_RFDF_MASK (0x20000U)
23262#define SPI_SR_RFDF_SHIFT (17U)
23267#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
23268#define SPI_SR_RFOF_MASK (0x80000U)
23269#define SPI_SR_RFOF_SHIFT (19U)
23274#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
23275#define SPI_SR_TFFF_MASK (0x2000000U)
23276#define SPI_SR_TFFF_SHIFT (25U)
23281#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
23282#define SPI_SR_TFUF_MASK (0x8000000U)
23283#define SPI_SR_TFUF_SHIFT (27U)
23288#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
23289#define SPI_SR_EOQF_MASK (0x10000000U)
23290#define SPI_SR_EOQF_SHIFT (28U)
23295#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
23296#define SPI_SR_TXRXS_MASK (0x40000000U)
23297#define SPI_SR_TXRXS_SHIFT (30U)
23302#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
23303#define SPI_SR_TCF_MASK (0x80000000U)
23304#define SPI_SR_TCF_SHIFT (31U)
23309#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
23314#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
23315#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
23320#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
23321#define SPI_RSER_RFDF_RE_MASK (0x20000U)
23322#define SPI_RSER_RFDF_RE_SHIFT (17U)
23327#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
23328#define SPI_RSER_RFOF_RE_MASK (0x80000U)
23329#define SPI_RSER_RFOF_RE_SHIFT (19U)
23334#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
23335#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
23336#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
23341#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
23342#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
23343#define SPI_RSER_TFFF_RE_SHIFT (25U)
23348#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
23349#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
23350#define SPI_RSER_TFUF_RE_SHIFT (27U)
23355#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
23356#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
23357#define SPI_RSER_EOQF_RE_SHIFT (28U)
23362#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
23363#define SPI_RSER_TCF_RE_MASK (0x80000000U)
23364#define SPI_RSER_TCF_RE_SHIFT (31U)
23369#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
23374#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
23375#define SPI_PUSHR_TXDATA_SHIFT (0U)
23376#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
23377#define SPI_PUSHR_PCS_MASK (0x3F0000U)
23378#define SPI_PUSHR_PCS_SHIFT (16U)
23383#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
23384#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
23385#define SPI_PUSHR_CTCNT_SHIFT (26U)
23390#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
23391#define SPI_PUSHR_EOQ_MASK (0x8000000U)
23392#define SPI_PUSHR_EOQ_SHIFT (27U)
23397#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
23398#define SPI_PUSHR_CTAS_MASK (0x70000000U)
23399#define SPI_PUSHR_CTAS_SHIFT (28U)
23410#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
23411#define SPI_PUSHR_CONT_MASK (0x80000000U)
23412#define SPI_PUSHR_CONT_SHIFT (31U)
23417#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
23422#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
23423#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
23424#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
23429#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
23430#define SPI_POPR_RXDATA_SHIFT (0U)
23431#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
23436#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
23437#define SPI_TXFR0_TXDATA_SHIFT (0U)
23438#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
23439#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
23440#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
23441#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
23446#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
23447#define SPI_TXFR1_TXDATA_SHIFT (0U)
23448#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
23449#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
23450#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
23451#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
23456#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
23457#define SPI_TXFR2_TXDATA_SHIFT (0U)
23458#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
23459#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
23460#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
23461#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
23466#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
23467#define SPI_TXFR3_TXDATA_SHIFT (0U)
23468#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
23469#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
23470#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
23471#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
23476#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
23477#define SPI_RXFR0_RXDATA_SHIFT (0U)
23478#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
23483#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
23484#define SPI_RXFR1_RXDATA_SHIFT (0U)
23485#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
23490#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
23491#define SPI_RXFR2_RXDATA_SHIFT (0U)
23492#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
23497#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
23498#define SPI_RXFR3_RXDATA_SHIFT (0U)
23499#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
23505 /* end of group SPI_Register_Masks */
23506
23507
23508/* SPI - Peripheral instance base addresses */
23510#define SPI0_BASE (0x4002C000u)
23512#define SPI0 ((SPI_Type *)SPI0_BASE)
23514#define SPI1_BASE (0x4002D000u)
23516#define SPI1 ((SPI_Type *)SPI1_BASE)
23518#define SPI2_BASE (0x400AC000u)
23520#define SPI2 ((SPI_Type *)SPI2_BASE)
23522#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
23524#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
23526#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
23527
23530 /* end of group SPI_Peripheral_Access_Layer */
23531
23532
23533/* ----------------------------------------------------------------------------
23534 -- SYSMPU Peripheral Access Layer
23535 ---------------------------------------------------------------------------- */
23536
23543typedef struct {
23544 __IO uint32_t CESR;
23545 uint8_t RESERVED_0[12];
23546 struct { /* offset: 0x10, array step: 0x8 */
23547 __I uint32_t EAR;
23548 __I uint32_t EDR;
23549 } SP[5];
23550 uint8_t RESERVED_1[968];
23551 __IO uint32_t WORD[12][4];
23552 uint8_t RESERVED_2[832];
23553 __IO uint32_t RGDAAC[12];
23554} SYSMPU_Type;
23555
23556/* ----------------------------------------------------------------------------
23557 -- SYSMPU Register Masks
23558 ---------------------------------------------------------------------------- */
23559
23567#define SYSMPU_CESR_VLD_MASK (0x1U)
23568#define SYSMPU_CESR_VLD_SHIFT (0U)
23573#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
23574#define SYSMPU_CESR_NRGD_MASK (0xF00U)
23575#define SYSMPU_CESR_NRGD_SHIFT (8U)
23581#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
23582#define SYSMPU_CESR_NSP_MASK (0xF000U)
23583#define SYSMPU_CESR_NSP_SHIFT (12U)
23584#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
23585#define SYSMPU_CESR_HRL_MASK (0xF0000U)
23586#define SYSMPU_CESR_HRL_SHIFT (16U)
23587#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
23588#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
23589#define SYSMPU_CESR_SPERR_SHIFT (27U)
23594#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
23599#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
23600#define SYSMPU_EAR_EADDR_SHIFT (0U)
23601#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
23604/* The count of SYSMPU_EAR */
23605#define SYSMPU_EAR_COUNT (5U)
23606
23609#define SYSMPU_EDR_ERW_MASK (0x1U)
23610#define SYSMPU_EDR_ERW_SHIFT (0U)
23615#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
23616#define SYSMPU_EDR_EATTR_MASK (0xEU)
23617#define SYSMPU_EDR_EATTR_SHIFT (1U)
23624#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
23625#define SYSMPU_EDR_EMN_MASK (0xF0U)
23626#define SYSMPU_EDR_EMN_SHIFT (4U)
23627#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
23628#define SYSMPU_EDR_EPID_MASK (0xFF00U)
23629#define SYSMPU_EDR_EPID_SHIFT (8U)
23630#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
23631#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
23632#define SYSMPU_EDR_EACD_SHIFT (16U)
23633#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
23636/* The count of SYSMPU_EDR */
23637#define SYSMPU_EDR_COUNT (5U)
23638
23641#define SYSMPU_WORD_M0UM_MASK (0x7U)
23642#define SYSMPU_WORD_M0UM_SHIFT (0U)
23643#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
23644#define SYSMPU_WORD_VLD_MASK (0x1U)
23645#define SYSMPU_WORD_VLD_SHIFT (0U)
23650#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
23651#define SYSMPU_WORD_M0SM_MASK (0x18U)
23652#define SYSMPU_WORD_M0SM_SHIFT (3U)
23653#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
23654#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
23655#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
23656#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
23657#define SYSMPU_WORD_M0PE_MASK (0x20U)
23658#define SYSMPU_WORD_M0PE_SHIFT (5U)
23659#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
23660#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
23661#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
23662#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
23663#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
23664#define SYSMPU_WORD_M1UM_SHIFT (6U)
23665#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
23666#define SYSMPU_WORD_M1SM_MASK (0x600U)
23667#define SYSMPU_WORD_M1SM_SHIFT (9U)
23668#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
23669#define SYSMPU_WORD_M1PE_MASK (0x800U)
23670#define SYSMPU_WORD_M1PE_SHIFT (11U)
23671#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
23672#define SYSMPU_WORD_M2UM_MASK (0x7000U)
23673#define SYSMPU_WORD_M2UM_SHIFT (12U)
23674#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
23675#define SYSMPU_WORD_M2SM_MASK (0x18000U)
23676#define SYSMPU_WORD_M2SM_SHIFT (15U)
23677#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
23678#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
23679#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
23680#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
23681#define SYSMPU_WORD_M2PE_MASK (0x20000U)
23682#define SYSMPU_WORD_M2PE_SHIFT (17U)
23683#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
23684#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
23685#define SYSMPU_WORD_M3UM_SHIFT (18U)
23690#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
23691#define SYSMPU_WORD_M3SM_MASK (0x600000U)
23692#define SYSMPU_WORD_M3SM_SHIFT (21U)
23699#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
23700#define SYSMPU_WORD_M3PE_MASK (0x800000U)
23701#define SYSMPU_WORD_M3PE_SHIFT (23U)
23706#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
23707#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
23708#define SYSMPU_WORD_M4WE_SHIFT (24U)
23713#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
23714#define SYSMPU_WORD_PID_MASK (0xFF000000U)
23715#define SYSMPU_WORD_PID_SHIFT (24U)
23716#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
23717#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
23718#define SYSMPU_WORD_M4RE_SHIFT (25U)
23723#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
23724#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
23725#define SYSMPU_WORD_M5WE_SHIFT (26U)
23730#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
23731#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
23732#define SYSMPU_WORD_M5RE_SHIFT (27U)
23737#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
23738#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
23739#define SYSMPU_WORD_M6WE_SHIFT (28U)
23744#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
23745#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
23746#define SYSMPU_WORD_M6RE_SHIFT (29U)
23751#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
23752#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
23753#define SYSMPU_WORD_M7WE_SHIFT (30U)
23758#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
23759#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
23760#define SYSMPU_WORD_M7RE_SHIFT (31U)
23765#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
23768/* The count of SYSMPU_WORD */
23769#define SYSMPU_WORD_COUNT (12U)
23770
23771/* The count of SYSMPU_WORD */
23772#define SYSMPU_WORD_COUNT2 (4U)
23773
23776#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
23777#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
23778#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
23779#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
23780#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
23781#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
23782#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
23783#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
23784#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
23785#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
23786#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
23787#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
23788#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
23789#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
23790#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
23791#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
23792#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
23793#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
23794#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
23795#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
23796#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
23797#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
23798#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
23799#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
23800#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
23801#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
23802#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
23803#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
23804#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
23809#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
23810#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
23811#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
23818#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
23819#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
23820#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
23825#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
23826#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
23827#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
23832#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
23833#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
23834#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
23839#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
23840#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
23841#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
23846#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
23847#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
23848#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
23853#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
23854#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
23855#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
23860#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
23861#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
23862#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
23867#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
23868#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
23869#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
23874#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
23875#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
23876#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
23881#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
23884/* The count of SYSMPU_RGDAAC */
23885#define SYSMPU_RGDAAC_COUNT (12U)
23886
23887
23890 /* end of group SYSMPU_Register_Masks */
23891
23892
23893/* SYSMPU - Peripheral instance base addresses */
23895#define SYSMPU_BASE (0x4000D000u)
23897#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
23899#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
23901#define SYSMPU_BASE_PTRS { SYSMPU }
23902
23905 /* end of group SYSMPU_Peripheral_Access_Layer */
23906
23907
23908/* ----------------------------------------------------------------------------
23909 -- TPM Peripheral Access Layer
23910 ---------------------------------------------------------------------------- */
23911
23918typedef struct {
23919 __IO uint32_t SC;
23920 __IO uint32_t CNT;
23921 __IO uint32_t MOD;
23922 struct { /* offset: 0xC, array step: 0x8 */
23923 __IO uint32_t CnSC;
23924 __IO uint32_t CnV;
23925 } CONTROLS[2];
23926 uint8_t RESERVED_0[52];
23927 __IO uint32_t STATUS;
23928 uint8_t RESERVED_1[16];
23929 __IO uint32_t COMBINE;
23930 uint8_t RESERVED_2[8];
23931 __IO uint32_t POL;
23932 uint8_t RESERVED_3[4];
23933 __IO uint32_t FILTER;
23934 uint8_t RESERVED_4[4];
23935 __IO uint32_t QDCTRL;
23936 __IO uint32_t CONF;
23937} TPM_Type;
23938
23939/* ----------------------------------------------------------------------------
23940 -- TPM Register Masks
23941 ---------------------------------------------------------------------------- */
23942
23950#define TPM_SC_PS_MASK (0x7U)
23951#define TPM_SC_PS_SHIFT (0U)
23962#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
23963#define TPM_SC_CMOD_MASK (0x18U)
23964#define TPM_SC_CMOD_SHIFT (3U)
23971#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
23972#define TPM_SC_CPWMS_MASK (0x20U)
23973#define TPM_SC_CPWMS_SHIFT (5U)
23978#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
23979#define TPM_SC_TOIE_MASK (0x40U)
23980#define TPM_SC_TOIE_SHIFT (6U)
23985#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
23986#define TPM_SC_TOF_MASK (0x80U)
23987#define TPM_SC_TOF_SHIFT (7U)
23992#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
23993#define TPM_SC_DMA_MASK (0x100U)
23994#define TPM_SC_DMA_SHIFT (8U)
23999#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
24004#define TPM_CNT_COUNT_MASK (0xFFFFU)
24005#define TPM_CNT_COUNT_SHIFT (0U)
24006#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
24011#define TPM_MOD_MOD_MASK (0xFFFFU)
24012#define TPM_MOD_MOD_SHIFT (0U)
24013#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
24018#define TPM_CnSC_DMA_MASK (0x1U)
24019#define TPM_CnSC_DMA_SHIFT (0U)
24024#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
24025#define TPM_CnSC_ELSA_MASK (0x4U)
24026#define TPM_CnSC_ELSA_SHIFT (2U)
24027#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
24028#define TPM_CnSC_ELSB_MASK (0x8U)
24029#define TPM_CnSC_ELSB_SHIFT (3U)
24030#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
24031#define TPM_CnSC_MSA_MASK (0x10U)
24032#define TPM_CnSC_MSA_SHIFT (4U)
24033#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
24034#define TPM_CnSC_MSB_MASK (0x20U)
24035#define TPM_CnSC_MSB_SHIFT (5U)
24036#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
24037#define TPM_CnSC_CHIE_MASK (0x40U)
24038#define TPM_CnSC_CHIE_SHIFT (6U)
24043#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
24044#define TPM_CnSC_CHF_MASK (0x80U)
24045#define TPM_CnSC_CHF_SHIFT (7U)
24050#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
24053/* The count of TPM_CnSC */
24054#define TPM_CnSC_COUNT (2U)
24055
24058#define TPM_CnV_VAL_MASK (0xFFFFU)
24059#define TPM_CnV_VAL_SHIFT (0U)
24060#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
24063/* The count of TPM_CnV */
24064#define TPM_CnV_COUNT (2U)
24065
24068#define TPM_STATUS_CH0F_MASK (0x1U)
24069#define TPM_STATUS_CH0F_SHIFT (0U)
24074#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
24075#define TPM_STATUS_CH1F_MASK (0x2U)
24076#define TPM_STATUS_CH1F_SHIFT (1U)
24081#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
24082#define TPM_STATUS_TOF_MASK (0x100U)
24083#define TPM_STATUS_TOF_SHIFT (8U)
24088#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
24093#define TPM_COMBINE_COMBINE0_MASK (0x1U)
24094#define TPM_COMBINE_COMBINE0_SHIFT (0U)
24099#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
24100#define TPM_COMBINE_COMSWAP0_MASK (0x2U)
24101#define TPM_COMBINE_COMSWAP0_SHIFT (1U)
24106#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
24111#define TPM_POL_POL0_MASK (0x1U)
24112#define TPM_POL_POL0_SHIFT (0U)
24117#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
24118#define TPM_POL_POL1_MASK (0x2U)
24119#define TPM_POL_POL1_SHIFT (1U)
24124#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
24129#define TPM_FILTER_CH0FVAL_MASK (0xFU)
24130#define TPM_FILTER_CH0FVAL_SHIFT (0U)
24131#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
24132#define TPM_FILTER_CH1FVAL_MASK (0xF0U)
24133#define TPM_FILTER_CH1FVAL_SHIFT (4U)
24134#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
24139#define TPM_QDCTRL_QUADEN_MASK (0x1U)
24140#define TPM_QDCTRL_QUADEN_SHIFT (0U)
24145#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
24146#define TPM_QDCTRL_TOFDIR_MASK (0x2U)
24147#define TPM_QDCTRL_TOFDIR_SHIFT (1U)
24152#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
24153#define TPM_QDCTRL_QUADIR_MASK (0x4U)
24154#define TPM_QDCTRL_QUADIR_SHIFT (2U)
24159#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
24160#define TPM_QDCTRL_QUADMODE_MASK (0x8U)
24161#define TPM_QDCTRL_QUADMODE_SHIFT (3U)
24166#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
24171#define TPM_CONF_DOZEEN_MASK (0x20U)
24172#define TPM_CONF_DOZEEN_SHIFT (5U)
24177#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
24178#define TPM_CONF_DBGMODE_MASK (0xC0U)
24179#define TPM_CONF_DBGMODE_SHIFT (6U)
24184#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
24185#define TPM_CONF_GTBSYNC_MASK (0x100U)
24186#define TPM_CONF_GTBSYNC_SHIFT (8U)
24191#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
24192#define TPM_CONF_GTBEEN_MASK (0x200U)
24193#define TPM_CONF_GTBEEN_SHIFT (9U)
24198#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
24199#define TPM_CONF_CSOT_MASK (0x10000U)
24200#define TPM_CONF_CSOT_SHIFT (16U)
24205#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
24206#define TPM_CONF_CSOO_MASK (0x20000U)
24207#define TPM_CONF_CSOO_SHIFT (17U)
24212#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
24213#define TPM_CONF_CROT_MASK (0x40000U)
24214#define TPM_CONF_CROT_SHIFT (18U)
24219#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
24220#define TPM_CONF_CPOT_MASK (0x80000U)
24221#define TPM_CONF_CPOT_SHIFT (19U)
24222#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
24223#define TPM_CONF_TRGPOL_MASK (0x400000U)
24224#define TPM_CONF_TRGPOL_SHIFT (22U)
24229#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
24230#define TPM_CONF_TRGSRC_MASK (0x800000U)
24231#define TPM_CONF_TRGSRC_SHIFT (23U)
24236#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
24237#define TPM_CONF_TRGSEL_MASK (0xF000000U)
24238#define TPM_CONF_TRGSEL_SHIFT (24U)
24244#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
24250 /* end of group TPM_Register_Masks */
24251
24252
24253/* TPM - Peripheral instance base addresses */
24255#define TPM1_BASE (0x400C9000u)
24257#define TPM1 ((TPM_Type *)TPM1_BASE)
24259#define TPM2_BASE (0x400CA000u)
24261#define TPM2 ((TPM_Type *)TPM2_BASE)
24263#define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
24265#define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
24267#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
24268
24271 /* end of group TPM_Peripheral_Access_Layer */
24272
24273
24274/* ----------------------------------------------------------------------------
24275 -- TSI Peripheral Access Layer
24276 ---------------------------------------------------------------------------- */
24277
24284typedef struct {
24285 __IO uint32_t GENCS;
24286 __IO uint32_t DATA;
24287 __IO uint32_t TSHD;
24288} TSI_Type;
24289
24290/* ----------------------------------------------------------------------------
24291 -- TSI Register Masks
24292 ---------------------------------------------------------------------------- */
24293
24301#define TSI_GENCS_EOSDMEO_MASK (0x1U)
24302#define TSI_GENCS_EOSDMEO_SHIFT (0U)
24307#define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
24308#define TSI_GENCS_CURSW_MASK (0x2U)
24309#define TSI_GENCS_CURSW_SHIFT (1U)
24314#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
24315#define TSI_GENCS_EOSF_MASK (0x4U)
24316#define TSI_GENCS_EOSF_SHIFT (2U)
24321#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
24322#define TSI_GENCS_SCNIP_MASK (0x8U)
24323#define TSI_GENCS_SCNIP_SHIFT (3U)
24328#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
24329#define TSI_GENCS_STM_MASK (0x10U)
24330#define TSI_GENCS_STM_SHIFT (4U)
24335#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
24336#define TSI_GENCS_STPE_MASK (0x20U)
24337#define TSI_GENCS_STPE_SHIFT (5U)
24342#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
24343#define TSI_GENCS_TSIIEN_MASK (0x40U)
24344#define TSI_GENCS_TSIIEN_SHIFT (6U)
24349#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
24350#define TSI_GENCS_TSIEN_MASK (0x80U)
24351#define TSI_GENCS_TSIEN_SHIFT (7U)
24356#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
24357#define TSI_GENCS_NSCN_MASK (0x1F00U)
24358#define TSI_GENCS_NSCN_SHIFT (8U)
24393#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
24394#define TSI_GENCS_PS_MASK (0xE000U)
24395#define TSI_GENCS_PS_SHIFT (13U)
24406#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
24407#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
24408#define TSI_GENCS_EXTCHRG_SHIFT (16U)
24419#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
24420#define TSI_GENCS_DVOLT_MASK (0x180000U)
24421#define TSI_GENCS_DVOLT_SHIFT (19U)
24428#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
24429#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
24430#define TSI_GENCS_REFCHRG_SHIFT (21U)
24441#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
24442#define TSI_GENCS_MODE_MASK (0xF000000U)
24443#define TSI_GENCS_MODE_SHIFT (24U)
24450#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
24451#define TSI_GENCS_ESOR_MASK (0x10000000U)
24452#define TSI_GENCS_ESOR_SHIFT (28U)
24457#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
24458#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
24459#define TSI_GENCS_OUTRGF_SHIFT (31U)
24460#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
24465#define TSI_DATA_TSICNT_MASK (0xFFFFU)
24466#define TSI_DATA_TSICNT_SHIFT (0U)
24467#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
24468#define TSI_DATA_SWTS_MASK (0x400000U)
24469#define TSI_DATA_SWTS_SHIFT (22U)
24474#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
24475#define TSI_DATA_DMAEN_MASK (0x800000U)
24476#define TSI_DATA_DMAEN_SHIFT (23U)
24481#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
24482#define TSI_DATA_TSICH_MASK (0xF0000000U)
24483#define TSI_DATA_TSICH_SHIFT (28U)
24502#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
24507#define TSI_TSHD_THRESL_MASK (0xFFFFU)
24508#define TSI_TSHD_THRESL_SHIFT (0U)
24509#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
24510#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
24511#define TSI_TSHD_THRESH_SHIFT (16U)
24512#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
24518 /* end of group TSI_Register_Masks */
24519
24520
24521/* TSI - Peripheral instance base addresses */
24523#define TSI0_BASE (0x40045000u)
24525#define TSI0 ((TSI_Type *)TSI0_BASE)
24527#define TSI_BASE_ADDRS { TSI0_BASE }
24529#define TSI_BASE_PTRS { TSI0 }
24531#define TSI_IRQS { TSI0_IRQn }
24532
24535 /* end of group TSI_Peripheral_Access_Layer */
24536
24537
24538/* ----------------------------------------------------------------------------
24539 -- UART Peripheral Access Layer
24540 ---------------------------------------------------------------------------- */
24541
24548typedef struct {
24549 __IO uint8_t BDH;
24550 __IO uint8_t BDL;
24551 __IO uint8_t C1;
24552 __IO uint8_t C2;
24553 __I uint8_t S1;
24554 __IO uint8_t S2;
24555 __IO uint8_t C3;
24556 __IO uint8_t D;
24557 __IO uint8_t MA1;
24558 __IO uint8_t MA2;
24559 __IO uint8_t C4;
24560 __IO uint8_t C5;
24561 __I uint8_t ED;
24562 __IO uint8_t MODEM;
24563 __IO uint8_t IR;
24564 uint8_t RESERVED_0[1];
24565 __IO uint8_t PFIFO;
24566 __IO uint8_t CFIFO;
24567 __IO uint8_t SFIFO;
24568 __IO uint8_t TWFIFO;
24569 __I uint8_t TCFIFO;
24570 __IO uint8_t RWFIFO;
24571 __I uint8_t RCFIFO;
24572 uint8_t RESERVED_1[1];
24573 __IO uint8_t C7816;
24574 __IO uint8_t IE7816;
24575 __IO uint8_t IS7816;
24576 __IO uint8_t WP7816;
24577 __IO uint8_t WN7816;
24578 __IO uint8_t WF7816;
24579 __IO uint8_t ET7816;
24580 __IO uint8_t TL7816;
24581 uint8_t RESERVED_2[26];
24582 __IO uint8_t AP7816A_T0;
24583 __IO uint8_t AP7816B_T0;
24584 union { /* offset: 0x3C */
24585 struct { /* offset: 0x3C */
24586 __IO uint8_t WP7816A_T0;
24587 __IO uint8_t WP7816B_T0;
24588 } TYPE0;
24589 struct { /* offset: 0x3C */
24590 __IO uint8_t WP7816A_T1;
24591 __IO uint8_t WP7816B_T1;
24592 } TYPE1;
24593 };
24594 __IO uint8_t WGP7816_T1;
24595 __IO uint8_t WP7816C_T1;
24596} UART_Type;
24597
24598/* ----------------------------------------------------------------------------
24599 -- UART Register Masks
24600 ---------------------------------------------------------------------------- */
24601
24609#define UART_BDH_SBR_MASK (0x1FU)
24610#define UART_BDH_SBR_SHIFT (0U)
24611#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
24612#define UART_BDH_SBNS_MASK (0x20U)
24613#define UART_BDH_SBNS_SHIFT (5U)
24618#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
24619#define UART_BDH_RXEDGIE_MASK (0x40U)
24620#define UART_BDH_RXEDGIE_SHIFT (6U)
24625#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
24626#define UART_BDH_LBKDIE_MASK (0x80U)
24627#define UART_BDH_LBKDIE_SHIFT (7U)
24632#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
24637#define UART_BDL_SBR_MASK (0xFFU)
24638#define UART_BDL_SBR_SHIFT (0U)
24639#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
24644#define UART_C1_PT_MASK (0x1U)
24645#define UART_C1_PT_SHIFT (0U)
24650#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
24651#define UART_C1_PE_MASK (0x2U)
24652#define UART_C1_PE_SHIFT (1U)
24657#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
24658#define UART_C1_ILT_MASK (0x4U)
24659#define UART_C1_ILT_SHIFT (2U)
24664#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
24665#define UART_C1_WAKE_MASK (0x8U)
24666#define UART_C1_WAKE_SHIFT (3U)
24671#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
24672#define UART_C1_M_MASK (0x10U)
24673#define UART_C1_M_SHIFT (4U)
24678#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
24679#define UART_C1_RSRC_MASK (0x20U)
24680#define UART_C1_RSRC_SHIFT (5U)
24685#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
24686#define UART_C1_UARTSWAI_MASK (0x40U)
24687#define UART_C1_UARTSWAI_SHIFT (6U)
24692#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
24693#define UART_C1_LOOPS_MASK (0x80U)
24694#define UART_C1_LOOPS_SHIFT (7U)
24699#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
24704#define UART_C2_SBK_MASK (0x1U)
24705#define UART_C2_SBK_SHIFT (0U)
24710#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
24711#define UART_C2_RWU_MASK (0x2U)
24712#define UART_C2_RWU_SHIFT (1U)
24717#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
24718#define UART_C2_RE_MASK (0x4U)
24719#define UART_C2_RE_SHIFT (2U)
24724#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
24725#define UART_C2_TE_MASK (0x8U)
24726#define UART_C2_TE_SHIFT (3U)
24731#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
24732#define UART_C2_ILIE_MASK (0x10U)
24733#define UART_C2_ILIE_SHIFT (4U)
24738#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
24739#define UART_C2_RIE_MASK (0x20U)
24740#define UART_C2_RIE_SHIFT (5U)
24745#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
24746#define UART_C2_TCIE_MASK (0x40U)
24747#define UART_C2_TCIE_SHIFT (6U)
24752#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
24753#define UART_C2_TIE_MASK (0x80U)
24754#define UART_C2_TIE_SHIFT (7U)
24759#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
24764#define UART_S1_PF_MASK (0x1U)
24765#define UART_S1_PF_SHIFT (0U)
24770#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
24771#define UART_S1_FE_MASK (0x2U)
24772#define UART_S1_FE_SHIFT (1U)
24777#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
24778#define UART_S1_NF_MASK (0x4U)
24779#define UART_S1_NF_SHIFT (2U)
24784#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
24785#define UART_S1_OR_MASK (0x8U)
24786#define UART_S1_OR_SHIFT (3U)
24791#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
24792#define UART_S1_IDLE_MASK (0x10U)
24793#define UART_S1_IDLE_SHIFT (4U)
24798#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
24799#define UART_S1_RDRF_MASK (0x20U)
24800#define UART_S1_RDRF_SHIFT (5U)
24805#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
24806#define UART_S1_TC_MASK (0x40U)
24807#define UART_S1_TC_SHIFT (6U)
24812#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
24813#define UART_S1_TDRE_MASK (0x80U)
24814#define UART_S1_TDRE_SHIFT (7U)
24819#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
24824#define UART_S2_RAF_MASK (0x1U)
24825#define UART_S2_RAF_SHIFT (0U)
24830#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
24831#define UART_S2_LBKDE_MASK (0x2U)
24832#define UART_S2_LBKDE_SHIFT (1U)
24837#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
24838#define UART_S2_BRK13_MASK (0x4U)
24839#define UART_S2_BRK13_SHIFT (2U)
24844#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
24845#define UART_S2_RWUID_MASK (0x8U)
24846#define UART_S2_RWUID_SHIFT (3U)
24851#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
24852#define UART_S2_RXINV_MASK (0x10U)
24853#define UART_S2_RXINV_SHIFT (4U)
24858#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
24859#define UART_S2_MSBF_MASK (0x20U)
24860#define UART_S2_MSBF_SHIFT (5U)
24865#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
24866#define UART_S2_RXEDGIF_MASK (0x40U)
24867#define UART_S2_RXEDGIF_SHIFT (6U)
24872#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
24873#define UART_S2_LBKDIF_MASK (0x80U)
24874#define UART_S2_LBKDIF_SHIFT (7U)
24879#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
24884#define UART_C3_PEIE_MASK (0x1U)
24885#define UART_C3_PEIE_SHIFT (0U)
24890#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
24891#define UART_C3_FEIE_MASK (0x2U)
24892#define UART_C3_FEIE_SHIFT (1U)
24897#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
24898#define UART_C3_NEIE_MASK (0x4U)
24899#define UART_C3_NEIE_SHIFT (2U)
24904#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
24905#define UART_C3_ORIE_MASK (0x8U)
24906#define UART_C3_ORIE_SHIFT (3U)
24911#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
24912#define UART_C3_TXINV_MASK (0x10U)
24913#define UART_C3_TXINV_SHIFT (4U)
24918#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
24919#define UART_C3_TXDIR_MASK (0x20U)
24920#define UART_C3_TXDIR_SHIFT (5U)
24925#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
24926#define UART_C3_T8_MASK (0x40U)
24927#define UART_C3_T8_SHIFT (6U)
24928#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
24929#define UART_C3_R8_MASK (0x80U)
24930#define UART_C3_R8_SHIFT (7U)
24931#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
24936#define UART_D_RT_MASK (0xFFU)
24937#define UART_D_RT_SHIFT (0U)
24938#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
24943#define UART_MA1_MA_MASK (0xFFU)
24944#define UART_MA1_MA_SHIFT (0U)
24945#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
24950#define UART_MA2_MA_MASK (0xFFU)
24951#define UART_MA2_MA_SHIFT (0U)
24952#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
24957#define UART_C4_BRFA_MASK (0x1FU)
24958#define UART_C4_BRFA_SHIFT (0U)
24959#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
24960#define UART_C4_M10_MASK (0x20U)
24961#define UART_C4_M10_SHIFT (5U)
24966#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
24967#define UART_C4_MAEN2_MASK (0x40U)
24968#define UART_C4_MAEN2_SHIFT (6U)
24973#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
24974#define UART_C4_MAEN1_MASK (0x80U)
24975#define UART_C4_MAEN1_SHIFT (7U)
24980#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
24985#define UART_C5_RDMAS_MASK (0x20U)
24986#define UART_C5_RDMAS_SHIFT (5U)
24991#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
24992#define UART_C5_TDMAS_MASK (0x80U)
24993#define UART_C5_TDMAS_SHIFT (7U)
24998#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
25003#define UART_ED_PARITYE_MASK (0x40U)
25004#define UART_ED_PARITYE_SHIFT (6U)
25009#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
25010#define UART_ED_NOISY_MASK (0x80U)
25011#define UART_ED_NOISY_SHIFT (7U)
25016#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
25021#define UART_MODEM_TXCTSE_MASK (0x1U)
25022#define UART_MODEM_TXCTSE_SHIFT (0U)
25027#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
25028#define UART_MODEM_TXRTSE_MASK (0x2U)
25029#define UART_MODEM_TXRTSE_SHIFT (1U)
25034#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
25035#define UART_MODEM_TXRTSPOL_MASK (0x4U)
25036#define UART_MODEM_TXRTSPOL_SHIFT (2U)
25041#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
25042#define UART_MODEM_RXRTSE_MASK (0x8U)
25043#define UART_MODEM_RXRTSE_SHIFT (3U)
25048#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
25053#define UART_IR_TNP_MASK (0x3U)
25054#define UART_IR_TNP_SHIFT (0U)
25061#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
25062#define UART_IR_IREN_MASK (0x4U)
25063#define UART_IR_IREN_SHIFT (2U)
25068#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
25073#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
25074#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
25085#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
25086#define UART_PFIFO_RXFE_MASK (0x8U)
25087#define UART_PFIFO_RXFE_SHIFT (3U)
25092#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
25093#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
25094#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
25105#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
25106#define UART_PFIFO_TXFE_MASK (0x80U)
25107#define UART_PFIFO_TXFE_SHIFT (7U)
25112#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
25117#define UART_CFIFO_RXUFE_MASK (0x1U)
25118#define UART_CFIFO_RXUFE_SHIFT (0U)
25123#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
25124#define UART_CFIFO_TXOFE_MASK (0x2U)
25125#define UART_CFIFO_TXOFE_SHIFT (1U)
25130#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
25131#define UART_CFIFO_RXOFE_MASK (0x4U)
25132#define UART_CFIFO_RXOFE_SHIFT (2U)
25137#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
25138#define UART_CFIFO_RXFLUSH_MASK (0x40U)
25139#define UART_CFIFO_RXFLUSH_SHIFT (6U)
25144#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
25145#define UART_CFIFO_TXFLUSH_MASK (0x80U)
25146#define UART_CFIFO_TXFLUSH_SHIFT (7U)
25151#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
25156#define UART_SFIFO_RXUF_MASK (0x1U)
25157#define UART_SFIFO_RXUF_SHIFT (0U)
25162#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
25163#define UART_SFIFO_TXOF_MASK (0x2U)
25164#define UART_SFIFO_TXOF_SHIFT (1U)
25169#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
25170#define UART_SFIFO_RXOF_MASK (0x4U)
25171#define UART_SFIFO_RXOF_SHIFT (2U)
25176#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
25177#define UART_SFIFO_RXEMPT_MASK (0x40U)
25178#define UART_SFIFO_RXEMPT_SHIFT (6U)
25183#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
25184#define UART_SFIFO_TXEMPT_MASK (0x80U)
25185#define UART_SFIFO_TXEMPT_SHIFT (7U)
25190#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
25195#define UART_TWFIFO_TXWATER_MASK (0xFFU)
25196#define UART_TWFIFO_TXWATER_SHIFT (0U)
25197#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
25202#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
25203#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
25204#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
25209#define UART_RWFIFO_RXWATER_MASK (0xFFU)
25210#define UART_RWFIFO_RXWATER_SHIFT (0U)
25211#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
25216#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
25217#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
25218#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
25223#define UART_C7816_ISO_7816E_MASK (0x1U)
25224#define UART_C7816_ISO_7816E_SHIFT (0U)
25229#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
25230#define UART_C7816_TTYPE_MASK (0x2U)
25231#define UART_C7816_TTYPE_SHIFT (1U)
25236#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
25237#define UART_C7816_INIT_MASK (0x4U)
25238#define UART_C7816_INIT_SHIFT (2U)
25243#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
25244#define UART_C7816_ANACK_MASK (0x8U)
25245#define UART_C7816_ANACK_SHIFT (3U)
25250#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
25251#define UART_C7816_ONACK_MASK (0x10U)
25252#define UART_C7816_ONACK_SHIFT (4U)
25257#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
25262#define UART_IE7816_RXTE_MASK (0x1U)
25263#define UART_IE7816_RXTE_SHIFT (0U)
25268#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
25269#define UART_IE7816_TXTE_MASK (0x2U)
25270#define UART_IE7816_TXTE_SHIFT (1U)
25275#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
25276#define UART_IE7816_GTVE_MASK (0x4U)
25277#define UART_IE7816_GTVE_SHIFT (2U)
25282#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
25283#define UART_IE7816_ADTE_MASK (0x8U)
25284#define UART_IE7816_ADTE_SHIFT (3U)
25289#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
25290#define UART_IE7816_INITDE_MASK (0x10U)
25291#define UART_IE7816_INITDE_SHIFT (4U)
25296#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
25297#define UART_IE7816_BWTE_MASK (0x20U)
25298#define UART_IE7816_BWTE_SHIFT (5U)
25303#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
25304#define UART_IE7816_CWTE_MASK (0x40U)
25305#define UART_IE7816_CWTE_SHIFT (6U)
25310#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
25311#define UART_IE7816_WTE_MASK (0x80U)
25312#define UART_IE7816_WTE_SHIFT (7U)
25317#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
25322#define UART_IS7816_RXT_MASK (0x1U)
25323#define UART_IS7816_RXT_SHIFT (0U)
25328#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
25329#define UART_IS7816_TXT_MASK (0x2U)
25330#define UART_IS7816_TXT_SHIFT (1U)
25335#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
25336#define UART_IS7816_GTV_MASK (0x4U)
25337#define UART_IS7816_GTV_SHIFT (2U)
25342#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
25343#define UART_IS7816_ADT_MASK (0x8U)
25344#define UART_IS7816_ADT_SHIFT (3U)
25349#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
25350#define UART_IS7816_INITD_MASK (0x10U)
25351#define UART_IS7816_INITD_SHIFT (4U)
25356#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
25357#define UART_IS7816_BWT_MASK (0x20U)
25358#define UART_IS7816_BWT_SHIFT (5U)
25363#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
25364#define UART_IS7816_CWT_MASK (0x40U)
25365#define UART_IS7816_CWT_SHIFT (6U)
25370#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
25371#define UART_IS7816_WT_MASK (0x80U)
25372#define UART_IS7816_WT_SHIFT (7U)
25377#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
25382#define UART_WP7816_WTX_MASK (0xFFU)
25383#define UART_WP7816_WTX_SHIFT (0U)
25384#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
25389#define UART_WN7816_GTN_MASK (0xFFU)
25390#define UART_WN7816_GTN_SHIFT (0U)
25391#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
25396#define UART_WF7816_GTFD_MASK (0xFFU)
25397#define UART_WF7816_GTFD_SHIFT (0U)
25398#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
25403#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
25404#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
25405#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
25406#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
25407#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
25412#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
25417#define UART_TL7816_TLEN_MASK (0xFFU)
25418#define UART_TL7816_TLEN_SHIFT (0U)
25419#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
25424#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
25425#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
25426#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
25431#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
25432#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
25433#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
25438#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
25439#define UART_WP7816A_T0_WI_H_SHIFT (0U)
25440#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
25445#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
25446#define UART_WP7816B_T0_WI_L_SHIFT (0U)
25447#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
25452#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
25453#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
25454#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
25459#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
25460#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
25461#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
25466#define UART_WGP7816_T1_BGI_MASK (0xFU)
25467#define UART_WGP7816_T1_BGI_SHIFT (0U)
25468#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
25469#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
25470#define UART_WGP7816_T1_CWI1_SHIFT (4U)
25471#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
25476#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
25477#define UART_WP7816C_T1_CWI2_SHIFT (0U)
25478#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
25484 /* end of group UART_Register_Masks */
25485
25486
25487/* UART - Peripheral instance base addresses */
25489#define UART0_BASE (0x4006A000u)
25491#define UART0 ((UART_Type *)UART0_BASE)
25493#define UART1_BASE (0x4006B000u)
25495#define UART1 ((UART_Type *)UART1_BASE)
25497#define UART2_BASE (0x4006C000u)
25499#define UART2 ((UART_Type *)UART2_BASE)
25501#define UART3_BASE (0x4006D000u)
25503#define UART3 ((UART_Type *)UART3_BASE)
25505#define UART4_BASE (0x400EA000u)
25507#define UART4 ((UART_Type *)UART4_BASE)
25509#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
25511#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4 }
25513#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
25514#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
25515
25518 /* end of group UART_Peripheral_Access_Layer */
25519
25520
25521/* ----------------------------------------------------------------------------
25522 -- USB Peripheral Access Layer
25523 ---------------------------------------------------------------------------- */
25524
25531typedef struct {
25532 __I uint8_t PERID;
25533 uint8_t RESERVED_0[3];
25534 __I uint8_t IDCOMP;
25535 uint8_t RESERVED_1[3];
25536 __I uint8_t REV;
25537 uint8_t RESERVED_2[3];
25538 __I uint8_t ADDINFO;
25539 uint8_t RESERVED_3[3];
25540 __IO uint8_t OTGISTAT;
25541 uint8_t RESERVED_4[3];
25542 __IO uint8_t OTGICR;
25543 uint8_t RESERVED_5[3];
25544 __IO uint8_t OTGSTAT;
25545 uint8_t RESERVED_6[3];
25546 __IO uint8_t OTGCTL;
25547 uint8_t RESERVED_7[99];
25548 __IO uint8_t ISTAT;
25549 uint8_t RESERVED_8[3];
25550 __IO uint8_t INTEN;
25551 uint8_t RESERVED_9[3];
25552 __IO uint8_t ERRSTAT;
25553 uint8_t RESERVED_10[3];
25554 __IO uint8_t ERREN;
25555 uint8_t RESERVED_11[3];
25556 __I uint8_t STAT;
25557 uint8_t RESERVED_12[3];
25558 __IO uint8_t CTL;
25559 uint8_t RESERVED_13[3];
25560 __IO uint8_t ADDR;
25561 uint8_t RESERVED_14[3];
25562 __IO uint8_t BDTPAGE1;
25563 uint8_t RESERVED_15[3];
25564 __IO uint8_t FRMNUML;
25565 uint8_t RESERVED_16[3];
25566 __IO uint8_t FRMNUMH;
25567 uint8_t RESERVED_17[3];
25568 __IO uint8_t TOKEN;
25569 uint8_t RESERVED_18[3];
25570 __IO uint8_t SOFTHLD;
25571 uint8_t RESERVED_19[3];
25572 __IO uint8_t BDTPAGE2;
25573 uint8_t RESERVED_20[3];
25574 __IO uint8_t BDTPAGE3;
25575 uint8_t RESERVED_21[11];
25576 struct { /* offset: 0xC0, array step: 0x4 */
25577 __IO uint8_t ENDPT;
25578 uint8_t RESERVED_0[3];
25579 } ENDPOINT[16];
25580 __IO uint8_t USBCTRL;
25581 uint8_t RESERVED_22[3];
25582 __I uint8_t OBSERVE;
25583 uint8_t RESERVED_23[3];
25584 __IO uint8_t CONTROL;
25585 uint8_t RESERVED_24[3];
25586 __IO uint8_t USBTRC0;
25587 uint8_t RESERVED_25[7];
25588 __IO uint8_t USBFRMADJUST;
25589 uint8_t RESERVED_26[43];
25590 __IO uint8_t CLK_RECOVER_CTRL;
25591 uint8_t RESERVED_27[3];
25592 __IO uint8_t CLK_RECOVER_IRC_EN;
25593 uint8_t RESERVED_28[15];
25594 __IO uint8_t CLK_RECOVER_INT_EN;
25595 uint8_t RESERVED_29[7];
25596 __IO uint8_t CLK_RECOVER_INT_STATUS;
25597} USB_Type;
25598
25599/* ----------------------------------------------------------------------------
25600 -- USB Register Masks
25601 ---------------------------------------------------------------------------- */
25602
25610#define USB_PERID_ID_MASK (0x3FU)
25611#define USB_PERID_ID_SHIFT (0U)
25612#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
25617#define USB_IDCOMP_NID_MASK (0x3FU)
25618#define USB_IDCOMP_NID_SHIFT (0U)
25619#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
25624#define USB_REV_REV_MASK (0xFFU)
25625#define USB_REV_REV_SHIFT (0U)
25626#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
25631#define USB_ADDINFO_IEHOST_MASK (0x1U)
25632#define USB_ADDINFO_IEHOST_SHIFT (0U)
25633#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
25638#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
25639#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
25640#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
25641#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
25642#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
25643#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
25644#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
25645#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
25646#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
25647#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
25648#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
25649#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
25650#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
25651#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
25652#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
25653#define USB_OTGISTAT_IDCHG_MASK (0x80U)
25654#define USB_OTGISTAT_IDCHG_SHIFT (7U)
25655#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
25660#define USB_OTGICR_AVBUSEN_MASK (0x1U)
25661#define USB_OTGICR_AVBUSEN_SHIFT (0U)
25666#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
25667#define USB_OTGICR_BSESSEN_MASK (0x4U)
25668#define USB_OTGICR_BSESSEN_SHIFT (2U)
25673#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
25674#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
25675#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
25680#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
25681#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
25682#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
25687#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
25688#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
25689#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
25694#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
25695#define USB_OTGICR_IDEN_MASK (0x80U)
25696#define USB_OTGICR_IDEN_SHIFT (7U)
25701#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
25706#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
25707#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
25712#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
25713#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
25714#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
25719#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
25720#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
25721#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
25726#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
25727#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
25728#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
25733#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
25734#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
25735#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
25736#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
25737#define USB_OTGSTAT_ID_MASK (0x80U)
25738#define USB_OTGSTAT_ID_SHIFT (7U)
25743#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
25748#define USB_OTGCTL_OTGEN_MASK (0x4U)
25749#define USB_OTGCTL_OTGEN_SHIFT (2U)
25754#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
25755#define USB_OTGCTL_DMLOW_MASK (0x10U)
25756#define USB_OTGCTL_DMLOW_SHIFT (4U)
25761#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
25762#define USB_OTGCTL_DPLOW_MASK (0x20U)
25763#define USB_OTGCTL_DPLOW_SHIFT (5U)
25768#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
25769#define USB_OTGCTL_DPHIGH_MASK (0x80U)
25770#define USB_OTGCTL_DPHIGH_SHIFT (7U)
25775#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
25780#define USB_ISTAT_USBRST_MASK (0x1U)
25781#define USB_ISTAT_USBRST_SHIFT (0U)
25782#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
25783#define USB_ISTAT_ERROR_MASK (0x2U)
25784#define USB_ISTAT_ERROR_SHIFT (1U)
25785#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
25786#define USB_ISTAT_SOFTOK_MASK (0x4U)
25787#define USB_ISTAT_SOFTOK_SHIFT (2U)
25788#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
25789#define USB_ISTAT_TOKDNE_MASK (0x8U)
25790#define USB_ISTAT_TOKDNE_SHIFT (3U)
25791#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
25792#define USB_ISTAT_SLEEP_MASK (0x10U)
25793#define USB_ISTAT_SLEEP_SHIFT (4U)
25794#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
25795#define USB_ISTAT_RESUME_MASK (0x20U)
25796#define USB_ISTAT_RESUME_SHIFT (5U)
25797#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
25798#define USB_ISTAT_ATTACH_MASK (0x40U)
25799#define USB_ISTAT_ATTACH_SHIFT (6U)
25804#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
25805#define USB_ISTAT_STALL_MASK (0x80U)
25806#define USB_ISTAT_STALL_SHIFT (7U)
25807#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
25812#define USB_INTEN_USBRSTEN_MASK (0x1U)
25813#define USB_INTEN_USBRSTEN_SHIFT (0U)
25818#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
25819#define USB_INTEN_ERROREN_MASK (0x2U)
25820#define USB_INTEN_ERROREN_SHIFT (1U)
25825#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
25826#define USB_INTEN_SOFTOKEN_MASK (0x4U)
25827#define USB_INTEN_SOFTOKEN_SHIFT (2U)
25832#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
25833#define USB_INTEN_TOKDNEEN_MASK (0x8U)
25834#define USB_INTEN_TOKDNEEN_SHIFT (3U)
25839#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
25840#define USB_INTEN_SLEEPEN_MASK (0x10U)
25841#define USB_INTEN_SLEEPEN_SHIFT (4U)
25846#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
25847#define USB_INTEN_RESUMEEN_MASK (0x20U)
25848#define USB_INTEN_RESUMEEN_SHIFT (5U)
25853#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
25854#define USB_INTEN_ATTACHEN_MASK (0x40U)
25855#define USB_INTEN_ATTACHEN_SHIFT (6U)
25860#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
25861#define USB_INTEN_STALLEN_MASK (0x80U)
25862#define USB_INTEN_STALLEN_SHIFT (7U)
25867#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
25872#define USB_ERRSTAT_PIDERR_MASK (0x1U)
25873#define USB_ERRSTAT_PIDERR_SHIFT (0U)
25874#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
25875#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
25876#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
25877#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
25878#define USB_ERRSTAT_CRC16_MASK (0x4U)
25879#define USB_ERRSTAT_CRC16_SHIFT (2U)
25880#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
25881#define USB_ERRSTAT_DFN8_MASK (0x8U)
25882#define USB_ERRSTAT_DFN8_SHIFT (3U)
25883#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
25884#define USB_ERRSTAT_BTOERR_MASK (0x10U)
25885#define USB_ERRSTAT_BTOERR_SHIFT (4U)
25886#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
25887#define USB_ERRSTAT_DMAERR_MASK (0x20U)
25888#define USB_ERRSTAT_DMAERR_SHIFT (5U)
25889#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
25890#define USB_ERRSTAT_BTSERR_MASK (0x80U)
25891#define USB_ERRSTAT_BTSERR_SHIFT (7U)
25892#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
25897#define USB_ERREN_PIDERREN_MASK (0x1U)
25898#define USB_ERREN_PIDERREN_SHIFT (0U)
25903#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
25904#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
25905#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
25910#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
25911#define USB_ERREN_CRC16EN_MASK (0x4U)
25912#define USB_ERREN_CRC16EN_SHIFT (2U)
25917#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
25918#define USB_ERREN_DFN8EN_MASK (0x8U)
25919#define USB_ERREN_DFN8EN_SHIFT (3U)
25924#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
25925#define USB_ERREN_BTOERREN_MASK (0x10U)
25926#define USB_ERREN_BTOERREN_SHIFT (4U)
25931#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
25932#define USB_ERREN_DMAERREN_MASK (0x20U)
25933#define USB_ERREN_DMAERREN_SHIFT (5U)
25938#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
25939#define USB_ERREN_BTSERREN_MASK (0x80U)
25940#define USB_ERREN_BTSERREN_SHIFT (7U)
25945#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
25950#define USB_STAT_ODD_MASK (0x4U)
25951#define USB_STAT_ODD_SHIFT (2U)
25952#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
25953#define USB_STAT_TX_MASK (0x8U)
25954#define USB_STAT_TX_SHIFT (3U)
25959#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
25960#define USB_STAT_ENDP_MASK (0xF0U)
25961#define USB_STAT_ENDP_SHIFT (4U)
25962#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
25967#define USB_CTL_USBENSOFEN_MASK (0x1U)
25968#define USB_CTL_USBENSOFEN_SHIFT (0U)
25973#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
25974#define USB_CTL_ODDRST_MASK (0x2U)
25975#define USB_CTL_ODDRST_SHIFT (1U)
25976#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
25977#define USB_CTL_RESUME_MASK (0x4U)
25978#define USB_CTL_RESUME_SHIFT (2U)
25979#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
25980#define USB_CTL_HOSTMODEEN_MASK (0x8U)
25981#define USB_CTL_HOSTMODEEN_SHIFT (3U)
25982#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
25983#define USB_CTL_RESET_MASK (0x10U)
25984#define USB_CTL_RESET_SHIFT (4U)
25985#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
25986#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
25987#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
25988#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
25989#define USB_CTL_SE0_MASK (0x40U)
25990#define USB_CTL_SE0_SHIFT (6U)
25991#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
25992#define USB_CTL_JSTATE_MASK (0x80U)
25993#define USB_CTL_JSTATE_SHIFT (7U)
25994#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
25999#define USB_ADDR_ADDR_MASK (0x7FU)
26000#define USB_ADDR_ADDR_SHIFT (0U)
26001#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
26002#define USB_ADDR_LSEN_MASK (0x80U)
26003#define USB_ADDR_LSEN_SHIFT (7U)
26004#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
26009#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
26010#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
26011#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
26016#define USB_FRMNUML_FRM_MASK (0xFFU)
26017#define USB_FRMNUML_FRM_SHIFT (0U)
26018#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
26023#define USB_FRMNUMH_FRM_MASK (0x7U)
26024#define USB_FRMNUMH_FRM_SHIFT (0U)
26025#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
26030#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
26031#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
26032#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
26033#define USB_TOKEN_TOKENPID_MASK (0xF0U)
26034#define USB_TOKEN_TOKENPID_SHIFT (4U)
26040#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
26045#define USB_SOFTHLD_CNT_MASK (0xFFU)
26046#define USB_SOFTHLD_CNT_SHIFT (0U)
26047#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
26052#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
26053#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
26054#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
26059#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
26060#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
26061#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
26066#define USB_ENDPT_EPHSHK_MASK (0x1U)
26067#define USB_ENDPT_EPHSHK_SHIFT (0U)
26068#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
26069#define USB_ENDPT_EPSTALL_MASK (0x2U)
26070#define USB_ENDPT_EPSTALL_SHIFT (1U)
26071#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
26072#define USB_ENDPT_EPTXEN_MASK (0x4U)
26073#define USB_ENDPT_EPTXEN_SHIFT (2U)
26074#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
26075#define USB_ENDPT_EPRXEN_MASK (0x8U)
26076#define USB_ENDPT_EPRXEN_SHIFT (3U)
26077#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
26078#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
26079#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
26080#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
26081#define USB_ENDPT_RETRYDIS_MASK (0x40U)
26082#define USB_ENDPT_RETRYDIS_SHIFT (6U)
26083#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
26084#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
26085#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
26090#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
26093/* The count of USB_ENDPT */
26094#define USB_ENDPT_COUNT (16U)
26095
26098#define USB_USBCTRL_PDE_MASK (0x40U)
26099#define USB_USBCTRL_PDE_SHIFT (6U)
26104#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
26105#define USB_USBCTRL_SUSP_MASK (0x80U)
26106#define USB_USBCTRL_SUSP_SHIFT (7U)
26111#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
26116#define USB_OBSERVE_DMPD_MASK (0x10U)
26117#define USB_OBSERVE_DMPD_SHIFT (4U)
26122#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
26123#define USB_OBSERVE_DPPD_MASK (0x40U)
26124#define USB_OBSERVE_DPPD_SHIFT (6U)
26129#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
26130#define USB_OBSERVE_DPPU_MASK (0x80U)
26131#define USB_OBSERVE_DPPU_SHIFT (7U)
26136#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
26141#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
26142#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
26147#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
26152#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
26153#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
26158#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
26159#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
26160#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
26165#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
26166#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
26167#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
26168#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
26169#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
26170#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
26175#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
26176#define USB_USBTRC0_USBRESET_MASK (0x80U)
26177#define USB_USBTRC0_USBRESET_SHIFT (7U)
26182#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
26187#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
26188#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
26189#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
26194#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
26195#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
26200#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
26201#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
26202#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
26207#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
26208#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
26209#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
26214#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
26219#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
26220#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
26225#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
26226#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
26227#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
26232#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
26237#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
26238#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
26243#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
26248#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
26249#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
26254#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
26260 /* end of group USB_Register_Masks */
26261
26262
26263/* USB - Peripheral instance base addresses */
26265#define USB0_BASE (0x40072000u)
26267#define USB0 ((USB_Type *)USB0_BASE)
26269#define USB_BASE_ADDRS { USB0_BASE }
26271#define USB_BASE_PTRS { USB0 }
26273#define USB_IRQS { USB0_IRQn }
26274
26277 /* end of group USB_Peripheral_Access_Layer */
26278
26279
26280/* ----------------------------------------------------------------------------
26281 -- USBDCD Peripheral Access Layer
26282 ---------------------------------------------------------------------------- */
26283
26290typedef struct {
26291 __IO uint32_t CONTROL;
26292 __IO uint32_t CLOCK;
26293 __I uint32_t STATUS;
26294 __IO uint32_t SIGNAL_OVERRIDE;
26295 __IO uint32_t TIMER0;
26296 __IO uint32_t TIMER1;
26297 union { /* offset: 0x18 */
26298 __IO uint32_t TIMER2_BC11;
26299 __IO uint32_t TIMER2_BC12;
26300 };
26301} USBDCD_Type;
26302
26303/* ----------------------------------------------------------------------------
26304 -- USBDCD Register Masks
26305 ---------------------------------------------------------------------------- */
26306
26314#define USBDCD_CONTROL_IACK_MASK (0x1U)
26315#define USBDCD_CONTROL_IACK_SHIFT (0U)
26320#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
26321#define USBDCD_CONTROL_IF_MASK (0x100U)
26322#define USBDCD_CONTROL_IF_SHIFT (8U)
26327#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
26328#define USBDCD_CONTROL_IE_MASK (0x10000U)
26329#define USBDCD_CONTROL_IE_SHIFT (16U)
26334#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
26335#define USBDCD_CONTROL_BC12_MASK (0x20000U)
26336#define USBDCD_CONTROL_BC12_SHIFT (17U)
26341#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
26342#define USBDCD_CONTROL_START_MASK (0x1000000U)
26343#define USBDCD_CONTROL_START_SHIFT (24U)
26348#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
26349#define USBDCD_CONTROL_SR_MASK (0x2000000U)
26350#define USBDCD_CONTROL_SR_SHIFT (25U)
26355#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
26360#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
26361#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
26366#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
26367#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
26368#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
26369#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
26374#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
26375#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
26382#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
26383#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
26384#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
26391#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
26392#define USBDCD_STATUS_ERR_MASK (0x100000U)
26393#define USBDCD_STATUS_ERR_SHIFT (20U)
26398#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
26399#define USBDCD_STATUS_TO_MASK (0x200000U)
26400#define USBDCD_STATUS_TO_SHIFT (21U)
26405#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
26406#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
26407#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
26412#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
26417#define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
26418#define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
26425#define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
26430#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
26431#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
26432#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
26433#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
26434#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
26435#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
26440#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
26441#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
26442#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
26443#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
26444#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
26445#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
26450#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
26451#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
26452#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
26453#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
26454#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
26455#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
26460#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
26461#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
26462#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
26463#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
26464#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
26465#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
26471 /* end of group USBDCD_Register_Masks */
26472
26473
26474/* USBDCD - Peripheral instance base addresses */
26476#define USBDCD_BASE (0x40035000u)
26478#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
26480#define USBDCD_BASE_ADDRS { USBDCD_BASE }
26482#define USBDCD_BASE_PTRS { USBDCD }
26484#define USBDCD_IRQS { USBDCD_IRQn }
26485
26488 /* end of group USBDCD_Peripheral_Access_Layer */
26489
26490
26491/* ----------------------------------------------------------------------------
26492 -- USBHS Peripheral Access Layer
26493 ---------------------------------------------------------------------------- */
26494
26501typedef struct {
26502 __I uint32_t ID;
26503 __I uint32_t HWGENERAL;
26504 __I uint32_t HWHOST;
26505 __I uint32_t HWDEVICE;
26506 __I uint32_t HWTXBUF;
26507 __I uint32_t HWRXBUF;
26508 uint8_t RESERVED_0[104];
26509 __IO uint32_t GPTIMER0LD;
26510 __IO uint32_t GPTIMER0CTL;
26511 __IO uint32_t GPTIMER1LD;
26512 __IO uint32_t GPTIMER1CTL;
26513 __IO uint32_t USB_SBUSCFG;
26514 uint8_t RESERVED_1[108];
26515 __I uint32_t HCIVERSION;
26516 __I uint32_t HCSPARAMS;
26517 __I uint32_t HCCPARAMS;
26518 uint8_t RESERVED_2[22];
26519 __I uint16_t DCIVERSION;
26520 __I uint32_t DCCPARAMS;
26521 uint8_t RESERVED_3[24];
26522 __IO uint32_t USBCMD;
26523 __IO uint32_t USBSTS;
26524 __IO uint32_t USBINTR;
26525 __IO uint32_t FRINDEX;
26526 uint8_t RESERVED_4[4];
26527 union { /* offset: 0x154 */
26528 __IO uint32_t DEVICEADDR;
26529 __IO uint32_t PERIODICLISTBASE;
26530 };
26531 union { /* offset: 0x158 */
26532 __IO uint32_t ASYNCLISTADDR;
26533 __IO uint32_t EPLISTADDR;
26534 };
26535 __I uint32_t TTCTRL;
26536 __IO uint32_t BURSTSIZE;
26537 __IO uint32_t TXFILLTUNING;
26538 uint8_t RESERVED_5[16];
26539 __IO uint32_t ENDPTNAK;
26540 __IO uint32_t ENDPTNAKEN;
26541 uint32_t CONFIGFLAG;
26542 __IO uint32_t PORTSC1;
26543 uint8_t RESERVED_6[28];
26544 __IO uint32_t OTGSC;
26545 __IO uint32_t USBMODE;
26546 __IO uint32_t EPSETUPSR;
26547 __IO uint32_t EPPRIME;
26548 __IO uint32_t EPFLUSH;
26549 __I uint32_t EPSR;
26550 __IO uint32_t EPCOMPLETE;
26551 __IO uint32_t EPCR0;
26552 __IO uint32_t EPCR[7];
26553 uint8_t RESERVED_7[32];
26554 __IO uint32_t USBGENCTRL;
26555} USBHS_Type;
26556
26557/* ----------------------------------------------------------------------------
26558 -- USBHS Register Masks
26559 ---------------------------------------------------------------------------- */
26560
26568#define USBHS_ID_ID_MASK (0x3FU)
26569#define USBHS_ID_ID_SHIFT (0U)
26570#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
26571#define USBHS_ID_NID_MASK (0x3F00U)
26572#define USBHS_ID_NID_SHIFT (8U)
26573#define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
26574#define USBHS_ID_TAG_MASK (0x1F0000U)
26575#define USBHS_ID_TAG_SHIFT (16U)
26576#define USBHS_ID_TAG(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
26577#define USBHS_ID_REVISION_MASK (0x1E00000U)
26578#define USBHS_ID_REVISION_SHIFT (21U)
26579#define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
26580#define USBHS_ID_VERSION_MASK (0x1E000000U)
26581#define USBHS_ID_VERSION_SHIFT (25U)
26582#define USBHS_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
26583#define USBHS_ID_VERSIONID_MASK (0xE0000000U)
26584#define USBHS_ID_VERSIONID_SHIFT (29U)
26585#define USBHS_ID_VERSIONID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
26590#define USBHS_HWGENERAL_PHYW_MASK (0x30U)
26591#define USBHS_HWGENERAL_PHYW_SHIFT (4U)
26595#define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
26596#define USBHS_HWGENERAL_PHYM_MASK (0x1C0U)
26597#define USBHS_HWGENERAL_PHYM_SHIFT (6U)
26601#define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
26602#define USBHS_HWGENERAL_SM_MASK (0x600U)
26603#define USBHS_HWGENERAL_SM_SHIFT (9U)
26607#define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
26612#define USBHS_HWHOST_HC_MASK (0x1U)
26613#define USBHS_HWHOST_HC_SHIFT (0U)
26614#define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
26615#define USBHS_HWHOST_NPORT_MASK (0xEU)
26616#define USBHS_HWHOST_NPORT_SHIFT (1U)
26617#define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
26618#define USBHS_HWHOST_TTASY_MASK (0xFF0000U)
26619#define USBHS_HWHOST_TTASY_SHIFT (16U)
26620#define USBHS_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
26621#define USBHS_HWHOST_TTPER_MASK (0xFF000000U)
26622#define USBHS_HWHOST_TTPER_SHIFT (24U)
26623#define USBHS_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
26628#define USBHS_HWDEVICE_DC_MASK (0x1U)
26629#define USBHS_HWDEVICE_DC_SHIFT (0U)
26630#define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
26631#define USBHS_HWDEVICE_DEVEP_MASK (0x3EU)
26632#define USBHS_HWDEVICE_DEVEP_SHIFT (1U)
26633#define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
26638#define USBHS_HWTXBUF_TXBURST_MASK (0xFFU)
26639#define USBHS_HWTXBUF_TXBURST_SHIFT (0U)
26640#define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
26641#define USBHS_HWTXBUF_TXADD_MASK (0xFF00U)
26642#define USBHS_HWTXBUF_TXADD_SHIFT (8U)
26643#define USBHS_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
26644#define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
26645#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U)
26646#define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
26647#define USBHS_HWTXBUF_TXLC_MASK (0x80000000U)
26648#define USBHS_HWTXBUF_TXLC_SHIFT (31U)
26653#define USBHS_HWTXBUF_TXLC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
26658#define USBHS_HWRXBUF_RXBURST_MASK (0xFFU)
26659#define USBHS_HWRXBUF_RXBURST_SHIFT (0U)
26660#define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
26661#define USBHS_HWRXBUF_RXADD_MASK (0xFF00U)
26662#define USBHS_HWRXBUF_RXADD_SHIFT (8U)
26663#define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
26668#define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
26669#define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U)
26670#define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
26675#define USBHS_GPTIMER0CTL_GPTCNT_MASK (0xFFFFFFU)
26676#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT (0U)
26677#define USBHS_GPTIMER0CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
26678#define USBHS_GPTIMER0CTL_MODE_MASK (0x1000000U)
26679#define USBHS_GPTIMER0CTL_MODE_SHIFT (24U)
26684#define USBHS_GPTIMER0CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
26685#define USBHS_GPTIMER0CTL_RST_MASK (0x40000000U)
26686#define USBHS_GPTIMER0CTL_RST_SHIFT (30U)
26691#define USBHS_GPTIMER0CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
26692#define USBHS_GPTIMER0CTL_RUN_MASK (0x80000000U)
26693#define USBHS_GPTIMER0CTL_RUN_SHIFT (31U)
26698#define USBHS_GPTIMER0CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
26703#define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
26704#define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U)
26705#define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
26710#define USBHS_GPTIMER1CTL_GPTCNT_MASK (0xFFFFFFU)
26711#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT (0U)
26712#define USBHS_GPTIMER1CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
26713#define USBHS_GPTIMER1CTL_MODE_MASK (0x1000000U)
26714#define USBHS_GPTIMER1CTL_MODE_SHIFT (24U)
26719#define USBHS_GPTIMER1CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
26720#define USBHS_GPTIMER1CTL_RST_MASK (0x40000000U)
26721#define USBHS_GPTIMER1CTL_RST_SHIFT (30U)
26726#define USBHS_GPTIMER1CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
26727#define USBHS_GPTIMER1CTL_RUN_MASK (0x80000000U)
26728#define USBHS_GPTIMER1CTL_RUN_SHIFT (31U)
26733#define USBHS_GPTIMER1CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
26738#define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7U)
26739#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0U)
26750#define USBHS_USB_SBUSCFG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)
26755#define USBHS_HCIVERSION_CAPLENGTH_MASK (0xFFU)
26756#define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0U)
26757#define USBHS_HCIVERSION_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
26758#define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFF0000U)
26759#define USBHS_HCIVERSION_HCIVERSION_SHIFT (16U)
26760#define USBHS_HCIVERSION_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
26765#define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU)
26766#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U)
26767#define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
26768#define USBHS_HCSPARAMS_PPC_MASK (0x10U)
26769#define USBHS_HCSPARAMS_PPC_SHIFT (4U)
26773#define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
26774#define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U)
26775#define USBHS_HCSPARAMS_N_PCC_SHIFT (8U)
26776#define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
26777#define USBHS_HCSPARAMS_N_CC_MASK (0xF000U)
26778#define USBHS_HCSPARAMS_N_CC_SHIFT (12U)
26779#define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
26780#define USBHS_HCSPARAMS_PI_MASK (0x10000U)
26781#define USBHS_HCSPARAMS_PI_SHIFT (16U)
26786#define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
26787#define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U)
26788#define USBHS_HCSPARAMS_N_PTT_SHIFT (20U)
26789#define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
26790#define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U)
26791#define USBHS_HCSPARAMS_N_TT_SHIFT (24U)
26792#define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
26797#define USBHS_HCCPARAMS_ADC_MASK (0x1U)
26798#define USBHS_HCCPARAMS_ADC_SHIFT (0U)
26799#define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
26800#define USBHS_HCCPARAMS_PFL_MASK (0x2U)
26801#define USBHS_HCCPARAMS_PFL_SHIFT (1U)
26802#define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
26803#define USBHS_HCCPARAMS_ASP_MASK (0x4U)
26804#define USBHS_HCCPARAMS_ASP_SHIFT (2U)
26809#define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
26810#define USBHS_HCCPARAMS_IST_MASK (0xF0U)
26811#define USBHS_HCCPARAMS_IST_SHIFT (4U)
26815#define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
26816#define USBHS_HCCPARAMS_EECP_MASK (0xFF00U)
26817#define USBHS_HCCPARAMS_EECP_SHIFT (8U)
26821#define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
26826#define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
26827#define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U)
26828#define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
26833#define USBHS_DCCPARAMS_DEN_MASK (0x1FU)
26834#define USBHS_DCCPARAMS_DEN_SHIFT (0U)
26835#define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
26836#define USBHS_DCCPARAMS_DC_MASK (0x80U)
26837#define USBHS_DCCPARAMS_DC_SHIFT (7U)
26838#define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
26839#define USBHS_DCCPARAMS_HC_MASK (0x100U)
26840#define USBHS_DCCPARAMS_HC_SHIFT (8U)
26841#define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
26846#define USBHS_USBCMD_RS_MASK (0x1U)
26847#define USBHS_USBCMD_RS_SHIFT (0U)
26848#define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
26849#define USBHS_USBCMD_RST_MASK (0x2U)
26850#define USBHS_USBCMD_RST_SHIFT (1U)
26851#define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
26852#define USBHS_USBCMD_FS_MASK (0xCU)
26853#define USBHS_USBCMD_FS_SHIFT (2U)
26860#define USBHS_USBCMD_FS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
26861#define USBHS_USBCMD_PSE_MASK (0x10U)
26862#define USBHS_USBCMD_PSE_SHIFT (4U)
26867#define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
26868#define USBHS_USBCMD_ASE_MASK (0x20U)
26869#define USBHS_USBCMD_ASE_SHIFT (5U)
26874#define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
26875#define USBHS_USBCMD_IAA_MASK (0x40U)
26876#define USBHS_USBCMD_IAA_SHIFT (6U)
26877#define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
26878#define USBHS_USBCMD_ASP_MASK (0x300U)
26879#define USBHS_USBCMD_ASP_SHIFT (8U)
26880#define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
26881#define USBHS_USBCMD_ASPE_MASK (0x800U)
26882#define USBHS_USBCMD_ASPE_SHIFT (11U)
26887#define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
26888#define USBHS_USBCMD_SUTW_MASK (0x2000U)
26889#define USBHS_USBCMD_SUTW_SHIFT (13U)
26890#define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
26891#define USBHS_USBCMD_ATDTW_MASK (0x4000U)
26892#define USBHS_USBCMD_ATDTW_SHIFT (14U)
26893#define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
26894#define USBHS_USBCMD_FS2_MASK (0x8000U)
26895#define USBHS_USBCMD_FS2_SHIFT (15U)
26896#define USBHS_USBCMD_FS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
26897#define USBHS_USBCMD_ITC_MASK (0xFF0000U)
26898#define USBHS_USBCMD_ITC_SHIFT (16U)
26909#define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
26914#define USBHS_USBSTS_UI_MASK (0x1U)
26915#define USBHS_USBSTS_UI_SHIFT (0U)
26916#define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
26917#define USBHS_USBSTS_UEI_MASK (0x2U)
26918#define USBHS_USBSTS_UEI_SHIFT (1U)
26923#define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
26924#define USBHS_USBSTS_PCI_MASK (0x4U)
26925#define USBHS_USBSTS_PCI_SHIFT (2U)
26926#define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
26927#define USBHS_USBSTS_FRI_MASK (0x8U)
26928#define USBHS_USBSTS_FRI_SHIFT (3U)
26929#define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
26930#define USBHS_USBSTS_SEI_MASK (0x10U)
26931#define USBHS_USBSTS_SEI_SHIFT (4U)
26936#define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
26937#define USBHS_USBSTS_AAI_MASK (0x20U)
26938#define USBHS_USBSTS_AAI_SHIFT (5U)
26943#define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
26944#define USBHS_USBSTS_URI_MASK (0x40U)
26945#define USBHS_USBSTS_URI_SHIFT (6U)
26950#define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
26951#define USBHS_USBSTS_SRI_MASK (0x80U)
26952#define USBHS_USBSTS_SRI_SHIFT (7U)
26953#define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
26954#define USBHS_USBSTS_SLI_MASK (0x100U)
26955#define USBHS_USBSTS_SLI_SHIFT (8U)
26960#define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
26961#define USBHS_USBSTS_HCH_MASK (0x1000U)
26962#define USBHS_USBSTS_HCH_SHIFT (12U)
26967#define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
26968#define USBHS_USBSTS_RCL_MASK (0x2000U)
26969#define USBHS_USBSTS_RCL_SHIFT (13U)
26974#define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
26975#define USBHS_USBSTS_PS_MASK (0x4000U)
26976#define USBHS_USBSTS_PS_SHIFT (14U)
26981#define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
26982#define USBHS_USBSTS_AS_MASK (0x8000U)
26983#define USBHS_USBSTS_AS_SHIFT (15U)
26988#define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
26989#define USBHS_USBSTS_NAKI_MASK (0x10000U)
26990#define USBHS_USBSTS_NAKI_SHIFT (16U)
26991#define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
26992#define USBHS_USBSTS_UAI_MASK (0x40000U)
26993#define USBHS_USBSTS_UAI_SHIFT (18U)
26994#define USBHS_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
26995#define USBHS_USBSTS_UPI_MASK (0x80000U)
26996#define USBHS_USBSTS_UPI_SHIFT (19U)
26997#define USBHS_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
26998#define USBHS_USBSTS_TI0_MASK (0x1000000U)
26999#define USBHS_USBSTS_TI0_SHIFT (24U)
27004#define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
27005#define USBHS_USBSTS_TI1_MASK (0x2000000U)
27006#define USBHS_USBSTS_TI1_SHIFT (25U)
27011#define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
27016#define USBHS_USBINTR_UE_MASK (0x1U)
27017#define USBHS_USBINTR_UE_SHIFT (0U)
27022#define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
27023#define USBHS_USBINTR_UEE_MASK (0x2U)
27024#define USBHS_USBINTR_UEE_SHIFT (1U)
27029#define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
27030#define USBHS_USBINTR_PCE_MASK (0x4U)
27031#define USBHS_USBINTR_PCE_SHIFT (2U)
27036#define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
27037#define USBHS_USBINTR_FRE_MASK (0x8U)
27038#define USBHS_USBINTR_FRE_SHIFT (3U)
27043#define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
27044#define USBHS_USBINTR_SEE_MASK (0x10U)
27045#define USBHS_USBINTR_SEE_SHIFT (4U)
27050#define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
27051#define USBHS_USBINTR_AAE_MASK (0x20U)
27052#define USBHS_USBINTR_AAE_SHIFT (5U)
27057#define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
27058#define USBHS_USBINTR_URE_MASK (0x40U)
27059#define USBHS_USBINTR_URE_SHIFT (6U)
27064#define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
27065#define USBHS_USBINTR_SRE_MASK (0x80U)
27066#define USBHS_USBINTR_SRE_SHIFT (7U)
27071#define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
27072#define USBHS_USBINTR_SLE_MASK (0x100U)
27073#define USBHS_USBINTR_SLE_SHIFT (8U)
27078#define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
27079#define USBHS_USBINTR_NAKE_MASK (0x10000U)
27080#define USBHS_USBINTR_NAKE_SHIFT (16U)
27085#define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
27086#define USBHS_USBINTR_UAIE_MASK (0x40000U)
27087#define USBHS_USBINTR_UAIE_SHIFT (18U)
27088#define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
27089#define USBHS_USBINTR_UPIE_MASK (0x80000U)
27090#define USBHS_USBINTR_UPIE_SHIFT (19U)
27091#define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
27092#define USBHS_USBINTR_TIE0_MASK (0x1000000U)
27093#define USBHS_USBINTR_TIE0_SHIFT (24U)
27098#define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
27099#define USBHS_USBINTR_TIE1_MASK (0x2000000U)
27100#define USBHS_USBINTR_TIE1_SHIFT (25U)
27105#define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
27110#define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU)
27111#define USBHS_FRINDEX_FRINDEX_SHIFT (0U)
27112#define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
27113#define USBHS_FRINDEX_Reerved_MASK (0xFFFFC000U)
27114#define USBHS_FRINDEX_Reerved_SHIFT (14U)
27115#define USBHS_FRINDEX_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
27120#define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U)
27121#define USBHS_DEVICEADDR_USBADRA_SHIFT (24U)
27126#define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
27127#define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U)
27128#define USBHS_DEVICEADDR_USBADR_SHIFT (25U)
27129#define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
27134#define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xFFFFF000U)
27135#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12U)
27136#define USBHS_PERIODICLISTBASE_PERBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
27141#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
27142#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
27143#define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
27148#define USBHS_EPLISTADDR_EPBASE_MASK (0xFFFFF800U)
27149#define USBHS_EPLISTADDR_EPBASE_SHIFT (11U)
27150#define USBHS_EPLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
27155#define USBHS_TTCTRL_TTHA_MASK (0x7F000000U)
27156#define USBHS_TTCTRL_TTHA_SHIFT (24U)
27157#define USBHS_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
27158#define USBHS_TTCTRL_Reerved_MASK (0x80000000U)
27159#define USBHS_TTCTRL_Reerved_SHIFT (31U)
27160#define USBHS_TTCTRL_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
27165#define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU)
27166#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U)
27167#define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
27168#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U)
27169#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U)
27170#define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
27175#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU)
27176#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U)
27177#define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
27178#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
27179#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
27180#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
27181#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
27182#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
27183#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
27188#define USBHS_ENDPTNAK_EPRN_MASK (0xFU)
27189#define USBHS_ENDPTNAK_EPRN_SHIFT (0U)
27190#define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
27191#define USBHS_ENDPTNAK_EPTN_MASK (0xF0000U)
27192#define USBHS_ENDPTNAK_EPTN_SHIFT (16U)
27193#define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
27198#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFU)
27199#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U)
27200#define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
27201#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xF0000U)
27202#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U)
27203#define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
27208#define USBHS_PORTSC1_CCS_MASK (0x1U)
27209#define USBHS_PORTSC1_CCS_SHIFT (0U)
27214#define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
27215#define USBHS_PORTSC1_CSC_MASK (0x2U)
27216#define USBHS_PORTSC1_CSC_SHIFT (1U)
27221#define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
27222#define USBHS_PORTSC1_PE_MASK (0x4U)
27223#define USBHS_PORTSC1_PE_SHIFT (2U)
27224#define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
27225#define USBHS_PORTSC1_PEC_MASK (0x8U)
27226#define USBHS_PORTSC1_PEC_SHIFT (3U)
27231#define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
27232#define USBHS_PORTSC1_OCA_MASK (0x10U)
27233#define USBHS_PORTSC1_OCA_SHIFT (4U)
27238#define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
27239#define USBHS_PORTSC1_OCC_MASK (0x20U)
27240#define USBHS_PORTSC1_OCC_SHIFT (5U)
27245#define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
27246#define USBHS_PORTSC1_FPR_MASK (0x40U)
27247#define USBHS_PORTSC1_FPR_SHIFT (6U)
27252#define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
27253#define USBHS_PORTSC1_SUSP_MASK (0x80U)
27254#define USBHS_PORTSC1_SUSP_SHIFT (7U)
27259#define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
27260#define USBHS_PORTSC1_PR_MASK (0x100U)
27261#define USBHS_PORTSC1_PR_SHIFT (8U)
27266#define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
27267#define USBHS_PORTSC1_HSP_MASK (0x200U)
27268#define USBHS_PORTSC1_HSP_SHIFT (9U)
27273#define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
27274#define USBHS_PORTSC1_LS_MASK (0xC00U)
27275#define USBHS_PORTSC1_LS_SHIFT (10U)
27282#define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
27283#define USBHS_PORTSC1_PP_MASK (0x1000U)
27284#define USBHS_PORTSC1_PP_SHIFT (12U)
27285#define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
27286#define USBHS_PORTSC1_PO_MASK (0x2000U)
27287#define USBHS_PORTSC1_PO_SHIFT (13U)
27288#define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
27289#define USBHS_PORTSC1_PIC_MASK (0xC000U)
27290#define USBHS_PORTSC1_PIC_SHIFT (14U)
27291#define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
27292#define USBHS_PORTSC1_PTC_MASK (0xF0000U)
27293#define USBHS_PORTSC1_PTC_SHIFT (16U)
27304#define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
27305#define USBHS_PORTSC1_WKCN_MASK (0x100000U)
27306#define USBHS_PORTSC1_WKCN_SHIFT (20U)
27307#define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
27308#define USBHS_PORTSC1_WKDS_MASK (0x200000U)
27309#define USBHS_PORTSC1_WKDS_SHIFT (21U)
27310#define USBHS_PORTSC1_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
27311#define USBHS_PORTSC1_WKOC_MASK (0x400000U)
27312#define USBHS_PORTSC1_WKOC_SHIFT (22U)
27313#define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
27314#define USBHS_PORTSC1_PHCD_MASK (0x800000U)
27315#define USBHS_PORTSC1_PHCD_SHIFT (23U)
27316#define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
27317#define USBHS_PORTSC1_PFSC_MASK (0x1000000U)
27318#define USBHS_PORTSC1_PFSC_SHIFT (24U)
27323#define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
27324#define USBHS_PORTSC1_PTS2_MASK (0x2000000U)
27325#define USBHS_PORTSC1_PTS2_SHIFT (25U)
27326#define USBHS_PORTSC1_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
27327#define USBHS_PORTSC1_PSPD_MASK (0xC000000U)
27328#define USBHS_PORTSC1_PSPD_SHIFT (26U)
27335#define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
27336#define USBHS_PORTSC1_PTS_MASK (0xC0000000U)
27337#define USBHS_PORTSC1_PTS_SHIFT (30U)
27341#define USBHS_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
27346#define USBHS_OTGSC_VD_MASK (0x1U)
27347#define USBHS_OTGSC_VD_SHIFT (0U)
27348#define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
27349#define USBHS_OTGSC_VC_MASK (0x2U)
27350#define USBHS_OTGSC_VC_SHIFT (1U)
27351#define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
27352#define USBHS_OTGSC_HAAR_MASK (0x4U)
27353#define USBHS_OTGSC_HAAR_SHIFT (2U)
27358#define USBHS_OTGSC_HAAR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
27359#define USBHS_OTGSC_OT_MASK (0x8U)
27360#define USBHS_OTGSC_OT_SHIFT (3U)
27365#define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
27366#define USBHS_OTGSC_DP_MASK (0x10U)
27367#define USBHS_OTGSC_DP_SHIFT (4U)
27372#define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
27373#define USBHS_OTGSC_IDPU_MASK (0x20U)
27374#define USBHS_OTGSC_IDPU_SHIFT (5U)
27379#define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
27380#define USBHS_OTGSC_HABA_MASK (0x80U)
27381#define USBHS_OTGSC_HABA_SHIFT (7U)
27386#define USBHS_OTGSC_HABA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
27387#define USBHS_OTGSC_ID_MASK (0x100U)
27388#define USBHS_OTGSC_ID_SHIFT (8U)
27393#define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
27394#define USBHS_OTGSC_AVV_MASK (0x200U)
27395#define USBHS_OTGSC_AVV_SHIFT (9U)
27400#define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
27401#define USBHS_OTGSC_ASV_MASK (0x400U)
27402#define USBHS_OTGSC_ASV_SHIFT (10U)
27407#define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
27408#define USBHS_OTGSC_BSV_MASK (0x800U)
27409#define USBHS_OTGSC_BSV_SHIFT (11U)
27414#define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
27415#define USBHS_OTGSC_BSE_MASK (0x1000U)
27416#define USBHS_OTGSC_BSE_SHIFT (12U)
27421#define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
27422#define USBHS_OTGSC_MST_MASK (0x2000U)
27423#define USBHS_OTGSC_MST_SHIFT (13U)
27424#define USBHS_OTGSC_MST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
27425#define USBHS_OTGSC_DPS_MASK (0x4000U)
27426#define USBHS_OTGSC_DPS_SHIFT (14U)
27431#define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
27432#define USBHS_OTGSC_IDIS_MASK (0x10000U)
27433#define USBHS_OTGSC_IDIS_SHIFT (16U)
27434#define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
27435#define USBHS_OTGSC_AVVIS_MASK (0x20000U)
27436#define USBHS_OTGSC_AVVIS_SHIFT (17U)
27437#define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
27438#define USBHS_OTGSC_ASVIS_MASK (0x40000U)
27439#define USBHS_OTGSC_ASVIS_SHIFT (18U)
27440#define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
27441#define USBHS_OTGSC_BSVIS_MASK (0x80000U)
27442#define USBHS_OTGSC_BSVIS_SHIFT (19U)
27443#define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
27444#define USBHS_OTGSC_BSEIS_MASK (0x100000U)
27445#define USBHS_OTGSC_BSEIS_SHIFT (20U)
27446#define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
27447#define USBHS_OTGSC_MSS_MASK (0x200000U)
27448#define USBHS_OTGSC_MSS_SHIFT (21U)
27449#define USBHS_OTGSC_MSS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
27450#define USBHS_OTGSC_DPIS_MASK (0x400000U)
27451#define USBHS_OTGSC_DPIS_SHIFT (22U)
27452#define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
27453#define USBHS_OTGSC_IDIE_MASK (0x1000000U)
27454#define USBHS_OTGSC_IDIE_SHIFT (24U)
27459#define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
27460#define USBHS_OTGSC_AVVIE_MASK (0x2000000U)
27461#define USBHS_OTGSC_AVVIE_SHIFT (25U)
27466#define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
27467#define USBHS_OTGSC_ASVIE_MASK (0x4000000U)
27468#define USBHS_OTGSC_ASVIE_SHIFT (26U)
27473#define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
27474#define USBHS_OTGSC_BSVIE_MASK (0x8000000U)
27475#define USBHS_OTGSC_BSVIE_SHIFT (27U)
27480#define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
27481#define USBHS_OTGSC_BSEIE_MASK (0x10000000U)
27482#define USBHS_OTGSC_BSEIE_SHIFT (28U)
27487#define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
27488#define USBHS_OTGSC_MSE_MASK (0x20000000U)
27489#define USBHS_OTGSC_MSE_SHIFT (29U)
27494#define USBHS_OTGSC_MSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
27495#define USBHS_OTGSC_DPIE_MASK (0x40000000U)
27496#define USBHS_OTGSC_DPIE_SHIFT (30U)
27501#define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
27506#define USBHS_USBMODE_CM_MASK (0x3U)
27507#define USBHS_USBMODE_CM_SHIFT (0U)
27514#define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
27515#define USBHS_USBMODE_ES_MASK (0x4U)
27516#define USBHS_USBMODE_ES_SHIFT (2U)
27521#define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
27522#define USBHS_USBMODE_SLOM_MASK (0x8U)
27523#define USBHS_USBMODE_SLOM_SHIFT (3U)
27524#define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
27525#define USBHS_USBMODE_SDIS_MASK (0x10U)
27526#define USBHS_USBMODE_SDIS_SHIFT (4U)
27531#define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
27532#define USBHS_USBMODE_TXHSD_MASK (0x7000U)
27533#define USBHS_USBMODE_TXHSD_SHIFT (12U)
27544#define USBHS_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
27549#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xFU)
27550#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0U)
27551#define USBHS_EPSETUPSR_EPSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
27556#define USBHS_EPPRIME_PERB_MASK (0xFU)
27557#define USBHS_EPPRIME_PERB_SHIFT (0U)
27558#define USBHS_EPPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
27559#define USBHS_EPPRIME_PETB_MASK (0xF0000U)
27560#define USBHS_EPPRIME_PETB_SHIFT (16U)
27561#define USBHS_EPPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
27566#define USBHS_EPFLUSH_FERB_MASK (0xFU)
27567#define USBHS_EPFLUSH_FERB_SHIFT (0U)
27568#define USBHS_EPFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
27569#define USBHS_EPFLUSH_FETB_MASK (0xF0000U)
27570#define USBHS_EPFLUSH_FETB_SHIFT (16U)
27571#define USBHS_EPFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
27576#define USBHS_EPSR_ERBR_MASK (0xFU)
27577#define USBHS_EPSR_ERBR_SHIFT (0U)
27578#define USBHS_EPSR_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
27579#define USBHS_EPSR_ETBR_MASK (0xF0000U)
27580#define USBHS_EPSR_ETBR_SHIFT (16U)
27581#define USBHS_EPSR_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
27586#define USBHS_EPCOMPLETE_ERCE_MASK (0xFU)
27587#define USBHS_EPCOMPLETE_ERCE_SHIFT (0U)
27588#define USBHS_EPCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
27589#define USBHS_EPCOMPLETE_ETCE_MASK (0xF0000U)
27590#define USBHS_EPCOMPLETE_ETCE_SHIFT (16U)
27591#define USBHS_EPCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
27596#define USBHS_EPCR0_RXS_MASK (0x1U)
27597#define USBHS_EPCR0_RXS_SHIFT (0U)
27602#define USBHS_EPCR0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
27603#define USBHS_EPCR0_RXT_MASK (0xCU)
27604#define USBHS_EPCR0_RXT_SHIFT (2U)
27608#define USBHS_EPCR0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
27609#define USBHS_EPCR0_RXE_MASK (0x80U)
27610#define USBHS_EPCR0_RXE_SHIFT (7U)
27614#define USBHS_EPCR0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
27615#define USBHS_EPCR0_TXS_MASK (0x10000U)
27616#define USBHS_EPCR0_TXS_SHIFT (16U)
27621#define USBHS_EPCR0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
27622#define USBHS_EPCR0_TXT_MASK (0xC0000U)
27623#define USBHS_EPCR0_TXT_SHIFT (18U)
27627#define USBHS_EPCR0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
27628#define USBHS_EPCR0_TXE_MASK (0x800000U)
27629#define USBHS_EPCR0_TXE_SHIFT (23U)
27633#define USBHS_EPCR0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
27638#define USBHS_EPCR_RXS_MASK (0x1U)
27639#define USBHS_EPCR_RXS_SHIFT (0U)
27644#define USBHS_EPCR_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
27645#define USBHS_EPCR_RXD_MASK (0x2U)
27646#define USBHS_EPCR_RXD_SHIFT (1U)
27647#define USBHS_EPCR_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
27648#define USBHS_EPCR_RXT_MASK (0xCU)
27649#define USBHS_EPCR_RXT_SHIFT (2U)
27656#define USBHS_EPCR_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
27657#define USBHS_EPCR_RXI_MASK (0x20U)
27658#define USBHS_EPCR_RXI_SHIFT (5U)
27663#define USBHS_EPCR_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
27664#define USBHS_EPCR_RXR_MASK (0x40U)
27665#define USBHS_EPCR_RXR_SHIFT (6U)
27666#define USBHS_EPCR_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
27667#define USBHS_EPCR_RXE_MASK (0x80U)
27668#define USBHS_EPCR_RXE_SHIFT (7U)
27673#define USBHS_EPCR_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
27674#define USBHS_EPCR_TXS_MASK (0x10000U)
27675#define USBHS_EPCR_TXS_SHIFT (16U)
27680#define USBHS_EPCR_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
27681#define USBHS_EPCR_TXD_MASK (0x20000U)
27682#define USBHS_EPCR_TXD_SHIFT (17U)
27683#define USBHS_EPCR_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
27684#define USBHS_EPCR_TXT_MASK (0xC0000U)
27685#define USBHS_EPCR_TXT_SHIFT (18U)
27692#define USBHS_EPCR_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
27693#define USBHS_EPCR_TXI_MASK (0x200000U)
27694#define USBHS_EPCR_TXI_SHIFT (21U)
27699#define USBHS_EPCR_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
27700#define USBHS_EPCR_TXR_MASK (0x400000U)
27701#define USBHS_EPCR_TXR_SHIFT (22U)
27702#define USBHS_EPCR_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
27703#define USBHS_EPCR_TXE_MASK (0x800000U)
27704#define USBHS_EPCR_TXE_SHIFT (23U)
27709#define USBHS_EPCR_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
27712/* The count of USBHS_EPCR */
27713#define USBHS_EPCR_COUNT (7U)
27714
27717#define USBHS_USBGENCTRL_WU_IE_MASK (0x1U)
27718#define USBHS_USBGENCTRL_WU_IE_SHIFT (0U)
27723#define USBHS_USBGENCTRL_WU_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
27724#define USBHS_USBGENCTRL_WU_INT_CLR_MASK (0x20U)
27725#define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT (5U)
27730#define USBHS_USBGENCTRL_WU_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
27736 /* end of group USBHS_Register_Masks */
27737
27738
27739/* USBHS - Peripheral instance base addresses */
27741#define USBHS_BASE (0x400A1000u)
27743#define USBHS ((USBHS_Type *)USBHS_BASE)
27745#define USBHS_BASE_ADDRS { USBHS_BASE }
27747#define USBHS_BASE_PTRS { USBHS }
27749#define USBHS_IRQS { USBHS_IRQn }
27750
27753 /* end of group USBHS_Peripheral_Access_Layer */
27754
27755
27756/* ----------------------------------------------------------------------------
27757 -- USBHSDCD Peripheral Access Layer
27758 ---------------------------------------------------------------------------- */
27759
27766typedef struct {
27767 __IO uint32_t CONTROL;
27768 __IO uint32_t CLOCK;
27769 __I uint32_t STATUS;
27770 __IO uint32_t SIGNAL_OVERRIDE;
27771 __IO uint32_t TIMER0;
27772 __IO uint32_t TIMER1;
27773 union { /* offset: 0x18 */
27774 __IO uint32_t TIMER2_BC11;
27775 __IO uint32_t TIMER2_BC12;
27776 };
27777} USBHSDCD_Type;
27778
27779/* ----------------------------------------------------------------------------
27780 -- USBHSDCD Register Masks
27781 ---------------------------------------------------------------------------- */
27782
27790#define USBHSDCD_CONTROL_IACK_MASK (0x1U)
27791#define USBHSDCD_CONTROL_IACK_SHIFT (0U)
27796#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
27797#define USBHSDCD_CONTROL_IF_MASK (0x100U)
27798#define USBHSDCD_CONTROL_IF_SHIFT (8U)
27803#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
27804#define USBHSDCD_CONTROL_IE_MASK (0x10000U)
27805#define USBHSDCD_CONTROL_IE_SHIFT (16U)
27810#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
27811#define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
27812#define USBHSDCD_CONTROL_BC12_SHIFT (17U)
27817#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
27818#define USBHSDCD_CONTROL_START_MASK (0x1000000U)
27819#define USBHSDCD_CONTROL_START_SHIFT (24U)
27824#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
27825#define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
27826#define USBHSDCD_CONTROL_SR_SHIFT (25U)
27831#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
27836#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
27837#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
27842#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
27843#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
27844#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
27845#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
27850#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
27851#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
27858#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
27859#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
27860#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
27867#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
27868#define USBHSDCD_STATUS_ERR_MASK (0x100000U)
27869#define USBHSDCD_STATUS_ERR_SHIFT (20U)
27874#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
27875#define USBHSDCD_STATUS_TO_MASK (0x200000U)
27876#define USBHSDCD_STATUS_TO_SHIFT (21U)
27881#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
27882#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
27883#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
27888#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
27893#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
27894#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
27901#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
27906#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
27907#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
27908#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
27909#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
27910#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
27911#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
27916#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
27917#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
27918#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
27919#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
27920#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
27921#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
27926#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
27927#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
27928#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
27929#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
27930#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
27931#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
27936#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
27937#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
27938#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
27939#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
27940#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
27941#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
27947 /* end of group USBHSDCD_Register_Masks */
27948
27949
27950/* USBHSDCD - Peripheral instance base addresses */
27952#define USBHSDCD_BASE (0x400A3000u)
27954#define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
27956#define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
27958#define USBHSDCD_BASE_PTRS { USBHSDCD }
27960#define USBHSDCD_IRQS { USBHSDCD_IRQn }
27961
27964 /* end of group USBHSDCD_Peripheral_Access_Layer */
27965
27966
27967/* ----------------------------------------------------------------------------
27968 -- USBPHY Peripheral Access Layer
27969 ---------------------------------------------------------------------------- */
27970
27977typedef struct {
27978 __IO uint32_t PWD;
27979 __IO uint32_t PWD_SET;
27980 __IO uint32_t PWD_CLR;
27981 __IO uint32_t PWD_TOG;
27982 __IO uint32_t TX;
27983 __IO uint32_t TX_SET;
27984 __IO uint32_t TX_CLR;
27985 __IO uint32_t TX_TOG;
27986 __IO uint32_t RX;
27987 __IO uint32_t RX_SET;
27988 __IO uint32_t RX_CLR;
27989 __IO uint32_t RX_TOG;
27990 __IO uint32_t CTRL;
27991 __IO uint32_t CTRL_SET;
27992 __IO uint32_t CTRL_CLR;
27993 __IO uint32_t CTRL_TOG;
27994 __IO uint32_t STATUS;
27995 uint8_t RESERVED_0[12];
27996 __IO uint32_t DEBUGr;
27997 __IO uint32_t DEBUG_SET;
27998 __IO uint32_t DEBUG_CLR;
27999 __IO uint32_t DEBUG_TOG;
28000 __I uint32_t DEBUG0_STATUS;
28001 uint8_t RESERVED_1[12];
28002 __IO uint32_t DEBUG1;
28003 __IO uint32_t DEBUG1_SET;
28004 __IO uint32_t DEBUG1_CLR;
28005 __IO uint32_t DEBUG1_TOG;
28006 __I uint32_t VERSION;
28007 uint8_t RESERVED_2[28];
28008 __IO uint32_t PLL_SIC;
28009 __IO uint32_t PLL_SIC_SET;
28010 __IO uint32_t PLL_SIC_CLR;
28011 __IO uint32_t PLL_SIC_TOG;
28012 uint8_t RESERVED_3[16];
28013 __IO uint32_t USB1_VBUS_DETECT;
28014 __IO uint32_t USB1_VBUS_DETECT_SET;
28015 __IO uint32_t USB1_VBUS_DETECT_CLR;
28016 __IO uint32_t USB1_VBUS_DETECT_TOG;
28017 __I uint32_t USB1_VBUS_DET_STAT;
28018 uint8_t RESERVED_4[28];
28019 __I uint32_t USB1_CHRG_DET_STAT;
28020 uint8_t RESERVED_5[12];
28021 __IO uint32_t ANACTRL;
28022 __IO uint32_t ANACTRL_SET;
28023 __IO uint32_t ANACTRL_CLR;
28024 __IO uint32_t ANACTRL_TOG;
28025 __IO uint32_t USB1_LOOPBACK;
28026 __IO uint32_t USB1_LOOPBACK_SET;
28027 __IO uint32_t USB1_LOOPBACK_CLR;
28028 __IO uint32_t USB1_LOOPBACK_TOG;
28029 __IO uint32_t USB1_LOOPBACK_HSFSCNT;
28030 __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;
28031 __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;
28032 __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;
28033 __IO uint32_t TRIM_OVERRIDE_EN;
28034 __IO uint32_t TRIM_OVERRIDE_EN_SET;
28035 __IO uint32_t TRIM_OVERRIDE_EN_CLR;
28036 __IO uint32_t TRIM_OVERRIDE_EN_TOG;
28037} USBPHY_Type;
28038
28039/* ----------------------------------------------------------------------------
28040 -- USBPHY Register Masks
28041 ---------------------------------------------------------------------------- */
28042
28050#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
28051#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
28056#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
28057#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
28058#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
28063#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
28064#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
28065#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
28070#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
28071#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
28072#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
28077#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
28078#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
28079#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
28084#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
28085#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
28086#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
28091#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
28092#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
28093#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
28098#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
28103#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
28104#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
28109#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
28110#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
28111#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
28116#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
28117#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
28118#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
28123#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
28124#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
28125#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
28130#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
28131#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
28132#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
28137#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
28138#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
28139#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
28144#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
28145#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
28146#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
28151#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
28156#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
28157#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
28162#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
28163#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
28164#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
28169#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
28170#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
28171#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
28176#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
28177#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
28178#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
28183#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
28184#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
28185#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
28190#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
28191#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
28192#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
28197#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
28198#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
28199#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
28204#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
28209#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
28210#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
28215#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
28216#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
28217#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
28222#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
28223#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
28224#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
28229#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
28230#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
28231#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
28236#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
28237#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
28238#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
28243#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
28244#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
28245#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
28250#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
28251#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
28252#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
28257#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
28262#define USBPHY_TX_D_CAL_MASK (0xFU)
28263#define USBPHY_TX_D_CAL_SHIFT (0U)
28269#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
28270#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
28271#define USBPHY_TX_TXCAL45DM_SHIFT (8U)
28272#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
28273#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
28274#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
28275#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
28276#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
28277#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
28278#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
28283#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
28284#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
28290#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
28291#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
28292#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
28293#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
28294#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
28295#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
28296#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
28297#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
28298#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
28299#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
28304#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
28305#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
28311#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
28312#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
28313#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
28314#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
28315#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
28316#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
28317#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
28318#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
28319#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
28320#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
28325#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
28326#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
28332#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
28333#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
28334#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
28335#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
28336#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
28337#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
28338#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
28339#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
28340#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
28341#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
28346#define USBPHY_RX_ENVADJ_MASK (0x7U)
28347#define USBPHY_RX_ENVADJ_SHIFT (0U)
28355#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
28356#define USBPHY_RX_DISCONADJ_MASK (0x70U)
28357#define USBPHY_RX_DISCONADJ_SHIFT (4U)
28365#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
28366#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
28367#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
28372#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
28377#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
28378#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
28386#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
28387#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
28388#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
28396#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
28397#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
28398#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
28403#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
28408#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
28409#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
28417#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
28418#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
28419#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
28427#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
28428#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
28429#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
28434#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
28439#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
28440#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
28448#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
28449#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
28450#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
28458#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
28459#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
28460#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
28465#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
28470#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
28471#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
28472#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
28473#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
28474#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
28475#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
28476#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
28477#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
28482#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
28483#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
28484#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
28485#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
28486#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
28487#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
28488#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
28489#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
28490#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
28491#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
28492#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
28493#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
28494#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
28495#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
28496#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
28497#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
28498#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
28499#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
28500#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
28501#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
28502#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
28503#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
28504#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
28505#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
28506#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
28507#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
28508#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
28509#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
28510#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
28511#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
28512#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
28513#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
28514#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
28515#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
28516#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
28517#define USBPHY_CTRL_SFTRST_SHIFT (31U)
28518#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
28523#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
28524#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
28525#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
28526#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
28527#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
28528#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
28529#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
28530#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
28535#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
28536#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
28537#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
28538#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
28539#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
28540#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
28541#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
28542#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
28543#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
28544#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
28545#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
28546#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
28547#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
28548#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
28549#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
28550#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
28551#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
28552#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
28553#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
28554#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
28555#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
28556#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
28557#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
28558#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
28559#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
28560#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
28561#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
28562#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
28563#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
28564#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
28565#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
28566#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
28567#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
28568#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
28569#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
28570#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
28571#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
28576#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
28577#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
28578#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
28579#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
28580#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
28581#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
28582#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
28583#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
28588#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
28589#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
28590#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
28591#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
28592#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
28593#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
28594#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
28595#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
28596#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
28597#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
28598#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
28599#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
28600#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
28601#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
28602#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
28603#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
28604#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
28605#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
28606#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
28607#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
28608#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
28609#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
28610#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
28611#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
28612#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
28613#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
28614#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
28615#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
28616#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
28617#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
28618#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
28619#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
28620#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
28621#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
28622#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
28623#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
28624#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
28629#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
28630#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
28631#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
28632#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
28633#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
28634#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
28635#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
28636#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
28641#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
28642#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
28643#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
28644#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
28645#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
28646#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
28647#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
28648#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
28649#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
28650#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
28651#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
28652#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
28653#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
28654#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
28655#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
28656#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
28657#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
28658#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
28659#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
28660#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
28661#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
28662#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
28663#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
28664#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
28665#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
28666#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
28667#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
28668#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
28669#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
28670#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
28671#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
28672#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
28673#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
28674#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
28675#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
28676#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
28677#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
28682#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
28683#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
28688#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
28689#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
28690#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
28695#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
28696#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
28697#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
28698#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
28699#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
28700#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
28701#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
28706#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
28707#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
28708#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
28709#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
28710#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
28711#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
28712#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
28713#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
28714#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
28715#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
28716#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
28717#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
28718#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
28719#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
28720#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
28721#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
28722#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
28723#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
28724#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
28725#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
28726#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
28727#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
28728#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
28729#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
28730#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
28731#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
28732#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
28733#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
28734#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
28735#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
28736#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
28737#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
28738#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
28743#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
28744#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
28745#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
28746#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
28747#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
28748#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
28749#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
28750#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
28751#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
28752#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
28753#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
28754#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
28755#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
28756#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
28757#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
28758#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
28759#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
28760#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
28761#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
28762#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
28763#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
28764#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
28765#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
28766#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
28767#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
28768#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
28769#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
28770#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
28771#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
28772#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
28773#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
28774#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
28775#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
28780#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
28781#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
28782#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
28783#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
28784#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
28785#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
28786#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
28787#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
28788#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
28789#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
28790#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
28791#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
28792#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
28793#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
28794#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
28795#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
28796#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
28797#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
28798#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
28799#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
28800#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
28801#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
28802#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
28803#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
28804#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
28805#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
28806#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
28807#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
28808#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
28809#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
28810#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
28811#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
28812#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
28817#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
28818#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
28819#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
28820#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
28821#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
28822#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
28823#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
28824#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
28825#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
28826#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
28827#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
28828#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
28829#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
28830#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
28831#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
28832#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
28833#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
28834#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
28835#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
28836#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
28837#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
28838#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
28839#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
28840#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
28841#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
28842#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
28843#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
28844#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
28845#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
28846#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
28847#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
28848#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
28849#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
28854#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
28855#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
28856#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
28857#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
28858#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
28859#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
28860#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
28861#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
28862#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
28867#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
28868#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
28875#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
28880#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
28881#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
28888#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
28893#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
28894#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
28901#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
28906#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
28907#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
28914#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
28919#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
28920#define USBPHY_VERSION_STEP_SHIFT (0U)
28921#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
28922#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
28923#define USBPHY_VERSION_MINOR_SHIFT (16U)
28924#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
28925#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
28926#define USBPHY_VERSION_MAJOR_SHIFT (24U)
28927#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
28932#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x3U)
28933#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (0U)
28939#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
28940#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
28941#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
28942#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
28943#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK (0x800U)
28944#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT (11U)
28945#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
28946#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
28947#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
28948#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
28949#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
28950#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
28951#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
28952#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
28953#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
28954#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
28955#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
28956#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
28961#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
28966#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x3U)
28967#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (0U)
28973#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
28974#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
28975#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
28976#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
28977#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
28978#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
28979#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
28980#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
28981#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
28982#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
28983#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
28984#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
28985#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
28986#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
28987#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
28988#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
28989#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
28990#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
28995#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
29000#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x3U)
29001#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (0U)
29007#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
29008#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
29009#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
29010#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
29011#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
29012#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
29013#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
29014#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
29015#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
29016#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
29017#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
29018#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
29019#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
29020#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
29021#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
29022#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
29023#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
29024#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
29029#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
29034#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x3U)
29035#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (0U)
29041#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
29042#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
29043#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
29044#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
29045#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
29046#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
29047#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
29048#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
29049#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
29050#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
29051#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
29052#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
29053#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
29054#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
29055#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
29056#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
29057#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
29058#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
29063#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
29068#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
29069#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
29080#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
29081#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
29082#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
29087#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
29088#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
29089#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
29090#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
29091#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
29092#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
29093#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
29094#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
29095#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
29096#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
29097#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
29098#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
29099#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
29100#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
29101#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
29106#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
29107#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
29108#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
29115#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
29116#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
29117#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
29122#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
29123#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)
29124#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
29129#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
29130#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
29131#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
29136#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
29137#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
29138#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
29143#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
29148#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
29149#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
29160#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
29161#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
29162#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
29167#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
29168#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
29169#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
29170#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
29171#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
29172#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
29173#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
29174#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
29175#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
29176#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
29177#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
29178#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
29179#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
29180#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
29181#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
29186#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
29187#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
29188#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
29195#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
29196#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
29197#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
29202#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
29203#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
29204#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
29209#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
29210#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
29211#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
29216#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
29217#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
29218#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
29223#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
29228#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
29229#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
29240#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
29241#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
29242#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
29247#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
29248#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
29249#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
29250#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
29251#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
29252#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
29253#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
29254#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
29255#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
29256#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
29257#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
29258#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
29259#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
29260#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
29261#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
29266#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
29267#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
29268#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
29275#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
29276#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
29277#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
29282#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
29283#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
29284#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
29289#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
29290#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
29291#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
29296#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
29297#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
29298#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
29303#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
29308#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
29309#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
29320#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
29321#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
29322#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
29327#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
29328#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
29329#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
29330#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
29331#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
29332#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
29333#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
29334#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
29335#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
29336#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
29337#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
29338#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
29339#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
29340#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
29341#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
29346#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
29347#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
29348#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
29355#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
29356#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
29357#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
29362#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
29363#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
29364#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
29369#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
29370#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
29371#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
29376#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
29377#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
29378#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
29383#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
29388#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
29389#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
29394#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
29395#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
29396#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
29401#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
29402#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
29403#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
29408#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
29409#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
29410#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
29415#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
29416#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
29417#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
29422#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
29427#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
29428#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
29433#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
29434#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
29435#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
29440#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
29441#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)
29442#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
29447#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
29448#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
29449#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
29454#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
29455#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
29456#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
29461#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
29466#define USBPHY_ANACTRL_TESTCLK_SEL_MASK (0x1U)
29467#define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT (0U)
29468#define USBPHY_ANACTRL_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
29469#define USBPHY_ANACTRL_PFD_CLKGATE_MASK (0x2U)
29470#define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT (1U)
29475#define USBPHY_ANACTRL_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
29476#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
29477#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
29484#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
29485#define USBPHY_ANACTRL_PFD_FRAC_MASK (0x3F0U)
29486#define USBPHY_ANACTRL_PFD_FRAC_SHIFT (4U)
29487#define USBPHY_ANACTRL_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
29488#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
29489#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
29494#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
29495#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK (0x1800U)
29496#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT (11U)
29501#define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
29502#define USBPHY_ANACTRL_EMPH_EN_MASK (0x2000U)
29503#define USBPHY_ANACTRL_EMPH_EN_SHIFT (13U)
29508#define USBPHY_ANACTRL_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
29509#define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK (0xC000U)
29510#define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT (14U)
29517#define USBPHY_ANACTRL_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
29518#define USBPHY_ANACTRL_PFD_STABLE_MASK (0x80000000U)
29519#define USBPHY_ANACTRL_PFD_STABLE_SHIFT (31U)
29520#define USBPHY_ANACTRL_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
29525#define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK (0x1U)
29526#define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT (0U)
29527#define USBPHY_ANACTRL_SET_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
29528#define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK (0x2U)
29529#define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT (1U)
29534#define USBPHY_ANACTRL_SET_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
29535#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
29536#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
29543#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
29544#define USBPHY_ANACTRL_SET_PFD_FRAC_MASK (0x3F0U)
29545#define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT (4U)
29546#define USBPHY_ANACTRL_SET_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
29547#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
29548#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
29553#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
29554#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK (0x1800U)
29555#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
29560#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
29561#define USBPHY_ANACTRL_SET_EMPH_EN_MASK (0x2000U)
29562#define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT (13U)
29567#define USBPHY_ANACTRL_SET_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
29568#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK (0xC000U)
29569#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT (14U)
29576#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
29577#define USBPHY_ANACTRL_SET_PFD_STABLE_MASK (0x80000000U)
29578#define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT (31U)
29579#define USBPHY_ANACTRL_SET_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
29584#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK (0x1U)
29585#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT (0U)
29586#define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
29587#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK (0x2U)
29588#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT (1U)
29593#define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
29594#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
29595#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
29602#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
29603#define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK (0x3F0U)
29604#define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT (4U)
29605#define USBPHY_ANACTRL_CLR_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
29606#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
29607#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
29612#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
29613#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK (0x1800U)
29614#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
29619#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
29620#define USBPHY_ANACTRL_CLR_EMPH_EN_MASK (0x2000U)
29621#define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT (13U)
29626#define USBPHY_ANACTRL_CLR_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
29627#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK (0xC000U)
29628#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT (14U)
29635#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
29636#define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK (0x80000000U)
29637#define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT (31U)
29638#define USBPHY_ANACTRL_CLR_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
29643#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK (0x1U)
29644#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT (0U)
29645#define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
29646#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK (0x2U)
29647#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT (1U)
29652#define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
29653#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
29654#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
29661#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
29662#define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK (0x3F0U)
29663#define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT (4U)
29664#define USBPHY_ANACTRL_TOG_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
29665#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
29666#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
29671#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
29672#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK (0x1800U)
29673#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
29678#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
29679#define USBPHY_ANACTRL_TOG_EMPH_EN_MASK (0x2000U)
29680#define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT (13U)
29685#define USBPHY_ANACTRL_TOG_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
29686#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK (0xC000U)
29687#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT (14U)
29694#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
29695#define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK (0x80000000U)
29696#define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT (31U)
29697#define USBPHY_ANACTRL_TOG_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
29702#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
29703#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
29704#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
29705#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
29706#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
29707#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
29708#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
29709#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
29710#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
29711#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
29712#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
29713#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
29714#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
29715#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
29716#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
29717#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
29718#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
29719#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
29720#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
29721#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
29722#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
29723#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
29724#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
29725#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
29726#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
29727#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
29728#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
29729#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
29730#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
29731#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
29732#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
29733#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
29734#define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
29739#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
29740#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
29741#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
29742#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
29743#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
29744#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
29745#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
29746#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
29747#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
29748#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
29749#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
29750#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
29751#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
29752#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
29753#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
29754#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
29755#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
29756#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
29757#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
29758#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
29759#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
29760#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
29761#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
29762#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
29763#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
29764#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
29765#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
29766#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
29767#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
29768#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
29769#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
29770#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
29771#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
29776#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
29777#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
29778#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
29779#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
29780#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
29781#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
29782#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
29783#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
29784#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
29785#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
29786#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
29787#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
29788#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
29789#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
29790#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
29791#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
29792#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
29793#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
29794#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
29795#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
29796#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
29797#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
29798#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
29799#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
29800#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
29801#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
29802#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
29803#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
29804#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
29805#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
29806#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
29807#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
29808#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
29813#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
29814#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
29815#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
29816#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
29817#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
29818#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
29819#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
29820#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
29821#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
29822#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
29823#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
29824#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
29825#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
29826#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
29827#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
29828#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
29829#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
29830#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
29831#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
29832#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
29833#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
29834#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
29835#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
29836#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
29837#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
29838#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
29839#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
29840#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
29841#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
29842#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
29843#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
29844#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
29845#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
29850#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
29851#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
29852#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
29853#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
29854#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
29855#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
29860#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
29861#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
29862#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
29863#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
29864#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
29865#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
29870#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
29871#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
29872#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
29873#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
29874#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
29875#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
29880#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
29881#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
29882#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
29883#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
29884#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
29885#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
29890#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
29891#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
29892#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
29893#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
29894#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
29895#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
29896#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
29897#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
29898#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
29899#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
29900#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
29901#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
29902#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
29903#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
29904#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
29905#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
29906#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
29907#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
29908#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
29909#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
29910#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
29911#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
29912#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
29913#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
29914#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
29915#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
29916#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
29917#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
29918#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
29919#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
29924#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
29925#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
29926#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
29927#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
29928#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
29929#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
29930#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
29931#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
29932#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
29933#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
29934#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
29935#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
29936#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
29937#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
29938#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
29939#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
29940#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
29941#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
29942#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
29943#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
29944#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
29945#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
29946#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
29947#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
29948#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
29949#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
29950#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
29951#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
29952#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
29953#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
29958#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
29959#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
29960#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
29961#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
29962#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
29963#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
29964#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
29965#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
29966#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
29967#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
29968#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
29969#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
29970#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
29971#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
29972#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
29973#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
29974#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
29975#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
29976#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
29977#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
29978#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
29979#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
29980#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
29981#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
29982#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
29983#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
29984#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
29985#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
29986#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
29987#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
29992#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
29993#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
29994#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
29995#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
29996#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
29997#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
29998#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
29999#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
30000#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
30001#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
30002#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
30003#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
30004#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
30005#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
30006#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
30007#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
30008#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
30009#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
30010#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
30011#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
30012#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
30013#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
30014#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
30015#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
30016#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
30017#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
30018#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
30019#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
30020#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
30021#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
30027 /* end of group USBPHY_Register_Masks */
30028
30029
30030/* USBPHY - Peripheral instance base addresses */
30032#define USBPHY_BASE (0x400A2000u)
30034#define USBPHY ((USBPHY_Type *)USBPHY_BASE)
30036#define USBPHY_BASE_ADDRS { USBPHY_BASE }
30038#define USBPHY_BASE_PTRS { USBPHY }
30039
30042 /* end of group USBPHY_Peripheral_Access_Layer */
30043
30044
30045/* ----------------------------------------------------------------------------
30046 -- VREF Peripheral Access Layer
30047 ---------------------------------------------------------------------------- */
30048
30055typedef struct {
30056 __IO uint8_t TRM;
30057 __IO uint8_t SC;
30058} VREF_Type;
30059
30060/* ----------------------------------------------------------------------------
30061 -- VREF Register Masks
30062 ---------------------------------------------------------------------------- */
30063
30071#define VREF_TRM_TRIM_MASK (0x3FU)
30072#define VREF_TRM_TRIM_SHIFT (0U)
30077#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
30078#define VREF_TRM_CHOPEN_MASK (0x40U)
30079#define VREF_TRM_CHOPEN_SHIFT (6U)
30084#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
30089#define VREF_SC_MODE_LV_MASK (0x3U)
30090#define VREF_SC_MODE_LV_SHIFT (0U)
30097#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
30098#define VREF_SC_VREFST_MASK (0x4U)
30099#define VREF_SC_VREFST_SHIFT (2U)
30104#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
30105#define VREF_SC_ICOMPEN_MASK (0x20U)
30106#define VREF_SC_ICOMPEN_SHIFT (5U)
30111#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
30112#define VREF_SC_REGEN_MASK (0x40U)
30113#define VREF_SC_REGEN_SHIFT (6U)
30118#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
30119#define VREF_SC_VREFEN_MASK (0x80U)
30120#define VREF_SC_VREFEN_SHIFT (7U)
30125#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
30131 /* end of group VREF_Register_Masks */
30132
30133
30134/* VREF - Peripheral instance base addresses */
30136#define VREF_BASE (0x40074000u)
30138#define VREF ((VREF_Type *)VREF_BASE)
30140#define VREF_BASE_ADDRS { VREF_BASE }
30142#define VREF_BASE_PTRS { VREF }
30143
30146 /* end of group VREF_Peripheral_Access_Layer */
30147
30148
30149/* ----------------------------------------------------------------------------
30150 -- WDOG Peripheral Access Layer
30151 ---------------------------------------------------------------------------- */
30152
30159typedef struct {
30160 __IO uint16_t STCTRLH;
30161 __IO uint16_t STCTRLL;
30162 __IO uint16_t TOVALH;
30163 __IO uint16_t TOVALL;
30164 __IO uint16_t WINH;
30165 __IO uint16_t WINL;
30166 __IO uint16_t REFRESH;
30167 __IO uint16_t UNLOCK;
30168 __IO uint16_t TMROUTH;
30169 __IO uint16_t TMROUTL;
30170 __IO uint16_t RSTCNT;
30171 __IO uint16_t PRESC;
30172} WDOG_Type;
30173
30174/* ----------------------------------------------------------------------------
30175 -- WDOG Register Masks
30176 ---------------------------------------------------------------------------- */
30177
30185#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
30186#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
30191#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
30192#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
30193#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
30198#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
30199#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
30200#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
30205#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
30206#define WDOG_STCTRLH_WINEN_MASK (0x8U)
30207#define WDOG_STCTRLH_WINEN_SHIFT (3U)
30212#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
30213#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
30214#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
30219#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
30220#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
30221#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
30226#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
30227#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
30228#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
30233#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
30234#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
30235#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
30240#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
30241#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
30242#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
30243#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
30244#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
30245#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
30250#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
30251#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
30252#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
30259#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
30260#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
30261#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
30266#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
30271#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
30272#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
30273#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
30278#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
30279#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
30280#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
30285#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
30286#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
30287#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
30292#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
30293#define WDOG_WINH_WINHIGH_SHIFT (0U)
30294#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
30299#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
30300#define WDOG_WINL_WINLOW_SHIFT (0U)
30301#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
30306#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
30307#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
30308#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
30313#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
30314#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
30315#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
30320#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
30321#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
30322#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
30327#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
30328#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
30329#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
30334#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
30335#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
30336#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
30341#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
30342#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
30343#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
30349 /* end of group WDOG_Register_Masks */
30350
30351
30352/* WDOG - Peripheral instance base addresses */
30354#define WDOG_BASE (0x40052000u)
30356#define WDOG ((WDOG_Type *)WDOG_BASE)
30358#define WDOG_BASE_ADDRS { WDOG_BASE }
30360#define WDOG_BASE_PTRS { WDOG }
30362#define WDOG_IRQS { WDOG_EWM_IRQn }
30363
30366 /* end of group WDOG_Peripheral_Access_Layer */
30367
30368
30369/*
30370** End of section using anonymous unions
30371*/
30372
30373#if defined(__ARMCC_VERSION)
30374 #if (__ARMCC_VERSION >= 6010050)
30375 #pragma clang diagnostic pop
30376 #else
30377 #pragma pop
30378 #endif
30379#elif defined(__CWCC__)
30380 #pragma pop
30381#elif defined(__GNUC__)
30382 /* leave anonymous unions enabled */
30383#elif defined(__IAR_SYSTEMS_ICC__)
30384 #pragma language=default
30385#else
30386 #error Not supported compiler type
30387#endif
30388
30391 /* end of group Peripheral_access_layer */
30392
30393
30394/* ----------------------------------------------------------------------------
30395 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
30396 ---------------------------------------------------------------------------- */
30397
30403#if defined(__ARMCC_VERSION)
30404 #if (__ARMCC_VERSION >= 6010050)
30405 #pragma clang system_header
30406 #endif
30407#elif defined(__IAR_SYSTEMS_ICC__)
30408 #pragma system_include
30409#endif
30410
30417#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
30424#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
30425
30428 /* end of group Bit_Field_Generic_Macros */
30429
30430
30431/* ----------------------------------------------------------------------------
30432 -- SDK Compatibility
30433 ---------------------------------------------------------------------------- */
30434
30440#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
30441#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
30442#define FMC_PFB0CR_RFU_MASK FMC_PFB01CR_RFU_MASK
30443#define FMC_PFB0CR_RFU_SHIFT FMC_PFB01CR_RFU_SHIFT
30444#define FMC_PFB0CR_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
30445#define FMC_PFB0CR_B0IPE_SHIFT FMC_PFB01CR_B0IPE_SHIFT
30446#define FMC_PFB0CR_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
30447#define FMC_PFB0CR_B0DPE_SHIFT FMC_PFB01CR_B0DPE_SHIFT
30448#define FMC_PFB0CR_B0ICE_MASK FMC_PFB01CR_B0ICE_MASK
30449#define FMC_PFB0CR_B0ICE_SHIFT FMC_PFB01CR_B0ICE_SHIFT
30450#define FMC_PFB0CR_B0DCE_MASK FMC_PFB01CR_B0DCE_MASK
30451#define FMC_PFB0CR_B0DCE_SHIFT FMC_PFB01CR_B0DCE_SHIFT
30452#define FMC_PFB0CR_CRC_MASK FMC_PFB01CR_CRC_MASK
30453#define FMC_PFB0CR_CRC_SHIFT FMC_PFB01CR_CRC_SHIFT
30454#define FMC_PFB0CR_CRC(x) FMC_PFB01CR_CRC(x)
30455#define FMC_PFB0CR_B0MW_MASK FMC_PFB01CR_B0MW_MASK
30456#define FMC_PFB0CR_B0MW_SHIFT FMC_PFB01CR_B0MW_SHIFT
30457#define FMC_PFB0CR_B0MW(x) FMC_PFB01CR_B0MW(x)
30458#define FMC_PFB0CR_S_B_INV_MASK FMC_PFB01CR_S_B_INV_MASK
30459#define FMC_PFB0CR_S_B_INV_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
30460#define FMC_PFB0CR_CINV_WAY_MASK FMC_PFB01CR_CINV_WAY_MASK
30461#define FMC_PFB0CR_CINV_WAY_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
30462#define FMC_PFB0CR_CINV_WAY(x) FMC_PFB01CR_CINV_WAY(x)
30463#define FMC_PFB0CR_CLCK_WAY_MASK FMC_PFB01CR_CLCK_WAY_MASK
30464#define FMC_PFB0CR_CLCK_WAY_SHIFT FMC_PFB01CR_CLCK_WAY_SHIFT
30465#define FMC_PFB0CR_CLCK_WAY(x) FMC_PFB01CR_CLCK_WAY(x)
30466#define FMC_PFB0CR_B0RWSC_MASK FMC_PFB01CR_B0RWSC_MASK
30467#define FMC_PFB0CR_B0RWSC_SHIFT FMC_PFB01CR_B0RWSC_SHIFT
30468#define FMC_PFB0CR_B0RWSC(x) FMC_PFB01CR_B0RWSC(x)
30469#define FMC_PFB1CR_RFU_MASK FMC_PFB23CR_RFU_MASK
30470#define FMC_PFB1CR_RFU_SHIFT FMC_PFB23CR_RFU_SHIFT
30471#define FMC_PFB1CR_B1IPE_MASK FMC_PFB23CR_B1IPE_MASK
30472#define FMC_PFB1CR_B1IPE_SHIFT FMC_PFB23CR_B1IPE_SHIFT
30473#define FMC_PFB1CR_B1DPE_MASK FMC_PFB23CR_B1DPE_MASK
30474#define FMC_PFB1CR_B1DPE_SHIFT FMC_PFB23CR_B1DPE_SHIFT
30475#define FMC_PFB1CR_B1ICE_MASK FMC_PFB23CR_B1ICE_MASK
30476#define FMC_PFB1CR_B1ICE_SHIFT FMC_PFB23CR_B1ICE_SHIFT
30477#define FMC_PFB1CR_B1DCE_MASK FMC_PFB23CR_B1DCE_MASK
30478#define FMC_PFB1CR_B1DCE_SHIFT FMC_PFB23CR_B1DCE_SHIFT
30479#define FMC_PFB1CR_B1MW_MASK FMC_PFB23CR_B1MW_MASK
30480#define FMC_PFB1CR_B1MW_SHIFT FMC_PFB23CR_B1MW_SHIFT
30481#define FMC_PFB1CR_B1MW(x) FMC_PFB23CR_B1MW(x)
30482#define FMC_PFB1CR_B1RWSC_MASK FMC_PFB23CR_B1RWSC_MASK
30483#define FMC_PFB1CR_B1RWSC_SHIFT FMC_PFB23CR_B1RWSC_SHIFT
30484#define FMC_PFB1CR_B1RWSC(x) FMC_PFB23CR_B1RWSC(x)
30485#define LLWU_PE8_WUPE130_MASK LLWU_PE8_WUPE30_MASK
30486#define LLWU_PE8_WUPE130_SHIFT LLWU_PE8_WUPE30_SHIFT
30487#define LLWU_PE8_WUPE130(x) LLWU_PE8_WUPE30(x)
30488#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
30489#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
30490#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
30491#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
30492#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
30493#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
30494#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
30495#define PMC_REGSC_BGBDS_MASK This_symbol_has_been_deprecated
30496#define PMC_REGSC_BGBDS_SHIFT This_symbol_has_been_deprecated
30497#define SDHC_VENDOR_EXTDMAEN_MASK This_symbol_has_been_deprecated
30498#define SDHC_VENDOR_EXTDMAEN_SHIFT This_symbol_has_been_deprecated
30499#define SDRAM_CTRL_COC_MASK This_symbol_has_been_deprecated
30500#define SDRAM_CTRL_COC_SHIFT This_symbol_has_been_deprecated
30501#define SDRAM_CTRL_NAM_MASK This_symbol_has_been_deprecated
30502#define SDRAM_CTRL_NAM_SHIFT This_symbol_has_been_deprecated
30503#define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated
30504#define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated
30505#define UART_C6_CP_MASK This_symbol_has_been_deprecated
30506#define UART_C6_CP_SHIFT This_symbol_has_been_deprecated
30507#define UART_C6_CE_MASK This_symbol_has_been_deprecated
30508#define UART_C6_CE_SHIFT This_symbol_has_been_deprecated
30509#define UART_C6_TX709_MASK This_symbol_has_been_deprecated
30510#define UART_C6_TX709_SHIFT This_symbol_has_been_deprecated
30511#define UART_C6_EN709_MASK This_symbol_has_been_deprecated
30512#define UART_C6_EN709_SHIFT This_symbol_has_been_deprecated
30513#define UART_PCTH_PCTH_MASK This_symbol_has_been_deprecated
30514#define UART_PCTH_PCTH_SHIFT This_symbol_has_been_deprecated
30515#define UART_PCTH_PCTH(x) This_symbol_has_been_deprecated
30516#define UART_PCTL_PCTL_MASK This_symbol_has_been_deprecated
30517#define UART_PCTL_PCTL_SHIFT This_symbol_has_been_deprecated
30518#define UART_PCTL_PCTL(x) This_symbol_has_been_deprecated
30519#define UART_IE0_CPTXIE_MASK This_symbol_has_been_deprecated
30520#define UART_IE0_CPTXIE_SHIFT This_symbol_has_been_deprecated
30521#define UART_IE0_CTXDIE_MASK This_symbol_has_been_deprecated
30522#define UART_IE0_CTXDIE_SHIFT This_symbol_has_been_deprecated
30523#define UART_IE0_RPLOFIE_MASK This_symbol_has_been_deprecated
30524#define UART_IE0_RPLOFIE_SHIFT This_symbol_has_been_deprecated
30525#define UART_SDTH_SDTH_MASK This_symbol_has_been_deprecated
30526#define UART_SDTH_SDTH_SHIFT This_symbol_has_been_deprecated
30527#define UART_SDTH_SDTH(x) This_symbol_has_been_deprecated
30528#define UART_SDTL_SDTL_MASK This_symbol_has_been_deprecated
30529#define UART_SDTL_SDTL_SHIFT This_symbol_has_been_deprecated
30530#define UART_SDTL_SDTL(x) This_symbol_has_been_deprecated
30531#define UART_PRE_PREAMBLE_MASK This_symbol_has_been_deprecated
30532#define UART_PRE_PREAMBLE_SHIFT This_symbol_has_been_deprecated
30533#define UART_PRE_PREAMBLE(x) This_symbol_has_been_deprecated
30534#define UART_TPL_TPL_MASK This_symbol_has_been_deprecated
30535#define UART_TPL_TPL_SHIFT This_symbol_has_been_deprecated
30536#define UART_TPL_TPL(x) This_symbol_has_been_deprecated
30537#define UART_IE_TXDIE_MASK This_symbol_has_been_deprecated
30538#define UART_IE_TXDIE_SHIFT This_symbol_has_been_deprecated
30539#define UART_IE_PSIE_MASK This_symbol_has_been_deprecated
30540#define UART_IE_PSIE_SHIFT This_symbol_has_been_deprecated
30541#define UART_IE_PCTEIE_MASK This_symbol_has_been_deprecated
30542#define UART_IE_PCTEIE_SHIFT This_symbol_has_been_deprecated
30543#define UART_IE_PTXIE_MASK This_symbol_has_been_deprecated
30544#define UART_IE_PTXIE_SHIFT This_symbol_has_been_deprecated
30545#define UART_IE_PRXIE_MASK This_symbol_has_been_deprecated
30546#define UART_IE_PRXIE_SHIFT This_symbol_has_been_deprecated
30547#define UART_IE_ISDIE_MASK This_symbol_has_been_deprecated
30548#define UART_IE_ISDIE_SHIFT This_symbol_has_been_deprecated
30549#define UART_IE_WBEIE_MASK This_symbol_has_been_deprecated
30550#define UART_IE_WBEIE_SHIFT This_symbol_has_been_deprecated
30551#define UART_IE_PEIE_MASK This_symbol_has_been_deprecated
30552#define UART_IE_PEIE_SHIFT This_symbol_has_been_deprecated
30553#define UART_WB_WBASE_MASK This_symbol_has_been_deprecated
30554#define UART_WB_WBASE_SHIFT This_symbol_has_been_deprecated
30555#define UART_WB_WBASE(x) This_symbol_has_been_deprecated
30556#define UART_S3_TXFF_MASK This_symbol_has_been_deprecated
30557#define UART_S3_TXFF_SHIFT This_symbol_has_been_deprecated
30558#define UART_S3_PSF_MASK This_symbol_has_been_deprecated
30559#define UART_S3_PSF_SHIFT This_symbol_has_been_deprecated
30560#define UART_S3_PCTEF_MASK This_symbol_has_been_deprecated
30561#define UART_S3_PCTEF_SHIFT This_symbol_has_been_deprecated
30562#define UART_S3_PTXF_MASK This_symbol_has_been_deprecated
30563#define UART_S3_PTXF_SHIFT This_symbol_has_been_deprecated
30564#define UART_S3_PRXF_MASK This_symbol_has_been_deprecated
30565#define UART_S3_PRXF_SHIFT This_symbol_has_been_deprecated
30566#define UART_S3_ISD_MASK This_symbol_has_been_deprecated
30567#define UART_S3_ISD_SHIFT This_symbol_has_been_deprecated
30568#define UART_S3_WBEF_MASK This_symbol_has_been_deprecated
30569#define UART_S3_WBEF_SHIFT This_symbol_has_been_deprecated
30570#define UART_S3_PEF_MASK This_symbol_has_been_deprecated
30571#define UART_S3_PEF_SHIFT This_symbol_has_been_deprecated
30572#define UART_S4_FE_MASK This_symbol_has_been_deprecated
30573#define UART_S4_FE_SHIFT This_symbol_has_been_deprecated
30574#define UART_S4_TXDF_MASK This_symbol_has_been_deprecated
30575#define UART_S4_TXDF_SHIFT This_symbol_has_been_deprecated
30576#define UART_S4_CDET_MASK This_symbol_has_been_deprecated
30577#define UART_S4_CDET_SHIFT This_symbol_has_been_deprecated
30578#define UART_S4_CDET(x) This_symbol_has_been_deprecated
30579#define UART_S4_RPLOF_MASK This_symbol_has_been_deprecated
30580#define UART_S4_RPLOF_SHIFT This_symbol_has_been_deprecated
30581#define UART_S4_LNF_MASK This_symbol_has_been_deprecated
30582#define UART_S4_LNF_SHIFT This_symbol_has_been_deprecated
30583#define UART_RPL_RPL_MASK This_symbol_has_been_deprecated
30584#define UART_RPL_RPL_SHIFT This_symbol_has_been_deprecated
30585#define UART_RPL_RPL(x) This_symbol_has_been_deprecated
30586#define UART_RPREL_RPREL_MASK This_symbol_has_been_deprecated
30587#define UART_RPREL_RPREL_SHIFT This_symbol_has_been_deprecated
30588#define UART_RPREL_RPREL(x) This_symbol_has_been_deprecated
30589#define UART_CPW_CPW_MASK This_symbol_has_been_deprecated
30590#define UART_CPW_CPW_SHIFT This_symbol_has_been_deprecated
30591#define UART_CPW_CPW(x) This_symbol_has_been_deprecated
30592#define UART_RIDTH_RIDTH_MASK This_symbol_has_been_deprecated
30593#define UART_RIDTH_RIDTH_SHIFT This_symbol_has_been_deprecated
30594#define UART_RIDTH_RIDTH(x) This_symbol_has_been_deprecated
30595#define UART_RIDTL_RIDTL_MASK This_symbol_has_been_deprecated
30596#define UART_RIDTL_RIDTL_SHIFT This_symbol_has_been_deprecated
30597#define UART_RIDTL_RIDTL(x) This_symbol_has_been_deprecated
30598#define UART_TIDTH_TIDTH_MASK This_symbol_has_been_deprecated
30599#define UART_TIDTH_TIDTH_SHIFT This_symbol_has_been_deprecated
30600#define UART_TIDTH_TIDTH(x) This_symbol_has_been_deprecated
30601#define UART_TIDTL_TIDTL_MASK This_symbol_has_been_deprecated
30602#define UART_TIDTL_TIDTL_SHIFT This_symbol_has_been_deprecated
30603#define UART_TIDTL_TIDTL(x) This_symbol_has_been_deprecated
30604#define UART_RB1TH_RB1TH_MASK This_symbol_has_been_deprecated
30605#define UART_RB1TH_RB1TH_SHIFT This_symbol_has_been_deprecated
30606#define UART_RB1TH_RB1TH(x) This_symbol_has_been_deprecated
30607#define UART_RB1TL_RB1TL_MASK This_symbol_has_been_deprecated
30608#define UART_RB1TL_RB1TL_SHIFT This_symbol_has_been_deprecated
30609#define UART_RB1TL_RB1TL(x) This_symbol_has_been_deprecated
30610#define UART_TB1TH_TB1TH_MASK This_symbol_has_been_deprecated
30611#define UART_TB1TH_TB1TH_SHIFT This_symbol_has_been_deprecated
30612#define UART_TB1TH_TB1TH(x) This_symbol_has_been_deprecated
30613#define UART_TB1TL_TB1TL_MASK This_symbol_has_been_deprecated
30614#define UART_TB1TL_TB1TL_SHIFT This_symbol_has_been_deprecated
30615#define UART_TB1TL_TB1TL(x) This_symbol_has_been_deprecated
30616#define UART_PROG_REG_MIN_DMC1_MASK This_symbol_has_been_deprecated
30617#define UART_PROG_REG_MIN_DMC1_SHIFT This_symbol_has_been_deprecated
30618#define UART_PROG_REG_MIN_DMC1(x) This_symbol_has_been_deprecated
30619#define UART_PROG_REG_LCV_LEN_MASK This_symbol_has_been_deprecated
30620#define UART_PROG_REG_LCV_LEN_SHIFT This_symbol_has_been_deprecated
30621#define UART_PROG_REG_LCV_LEN(x) This_symbol_has_been_deprecated
30622#define UART_STATE_REG_SM_STATE_MASK This_symbol_has_been_deprecated
30623#define UART_STATE_REG_SM_STATE_SHIFT This_symbol_has_been_deprecated
30624#define UART_STATE_REG_SM_STATE(x) This_symbol_has_been_deprecated
30625#define UART_STATE_REG_TX_STATE_MASK This_symbol_has_been_deprecated
30626#define UART_STATE_REG_TX_STATE_SHIFT This_symbol_has_been_deprecated
30627#define UART_STATE_REG_TX_STATE(x) This_symbol_has_been_deprecated
30628#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
30629#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
30630#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
30631#define USBHS_USBSTS_ULPII_MASK This_symbol_has_been_deprecated
30632#define USBHS_USBSTS_ULPII_SHIFT This_symbol_has_been_deprecated
30633#define USBHS_USBINTR_ULPIE_MASK This_symbol_has_been_deprecated
30634#define USBHS_USBINTR_ULPIE_SHIFT This_symbol_has_been_deprecated
30635#define USBPHY_CTRL_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
30636#define USBPHY_CTRL_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
30637#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
30638#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
30639#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
30640#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
30641#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
30642#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
30643#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
30644#define MCM_ISR_IRQ_MASK MCM_ISCR_IRQ_MASK
30645#define MCM_ISR_IRQ_SHIFT MCM_ISCR_IRQ_SHIFT
30646#define MCM_ISR_NMI_MASK MCM_ISCR_NMI_MASK
30647#define MCM_ISR_NMI_SHIFT MCM_ISCR_NMI_SHIFT
30648#define MCM_ISR_DHREQ_MASK MCM_ISCR_DHREQ_MASK
30649#define MCM_ISR_DHREQ_SHIFT MCM_ISCR_DHREQ_SHIFT
30650#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
30651#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
30652#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
30653#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
30654#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
30655#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
30656#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
30657#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
30658#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
30659#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
30660#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
30661#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
30662#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
30663#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
30664#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
30665#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
30666#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
30667#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
30668#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
30669#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
30670#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
30671#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
30672#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
30673#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
30674#define DMAMUX0 DMAMUX
30675#define DSPI0 SPI0
30676#define DSPI1 SPI1
30677#define DSPI2 SPI2
30678#define FLEXCAN0 CAN0
30679#define FLEXCAN1 CAN1
30680#define PTA_BASE GPIOA_BASE
30681#define PTA GPIOA
30682#define PTB_BASE GPIOB_BASE
30683#define PTB GPIOB
30684#define PTC_BASE GPIOC_BASE
30685#define PTC GPIOC
30686#define PTD_BASE GPIOD_BASE
30687#define PTD GPIOD
30688#define PTE_BASE GPIOE_BASE
30689#define PTE GPIOE
30690#define Watchdog_IRQn WDOG_EWM_IRQn
30691#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
30692#define LPTimer_IRQn LPTMR0_IRQn
30693#define LPTimer_IRQHandler LPTMR0_IRQHandler
30694#define UART0_LON_IRQn This_symbol_has_been_deprecated
30695#define UART0_LON_IRQHandler This_symbol_has_been_deprecated
30696#define LLW_IRQn LLWU_IRQn
30697#define LLW_IRQHandler LLWU_IRQHandler
30698
30701 /* end of group SDK_Compatibility_Symbols */
30702
30703
30704#endif /* _MK66F18_H_ */
30705
__O
#define __O
Definition core_cm3.h:169
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
DMA
#define DMA
Definition MK60N512MD100.h:2945
IRQn
IRQn
Definition MK60D10.h:157
Reserved85_IRQn
@ Reserved85_IRQn
Definition MK66F18.h:206
MCM_IRQn
@ MCM_IRQn
Definition MK66F18.h:154
PendSV_IRQn
@ PendSV_IRQn
Definition MK66F18.h:133
CAN1_ORed_Message_buffer_IRQn
@ CAN1_ORed_Message_buffer_IRQn
Definition MK66F18.h:231
FTM0_IRQn
@ FTM0_IRQn
Definition MK66F18.h:179
ADC0_IRQn
@ ADC0_IRQn
Definition MK66F18.h:176
WDOG_EWM_IRQn
@ WDOG_EWM_IRQn
Definition MK66F18.h:159
PORTE_IRQn
@ PORTE_IRQn
Definition MK66F18.h:200
I2C2_IRQn
@ I2C2_IRQn
Definition MK66F18.h:211
I2C0_IRQn
@ I2C0_IRQn
Definition MK66F18.h:161
Reserved46_IRQn
@ Reserved46_IRQn
Definition MK66F18.h:167
MCG_IRQn
@ MCG_IRQn
Definition MK66F18.h:194
DMA0_DMA16_IRQn
@ DMA0_DMA16_IRQn
Definition MK66F18.h:137
DMA14_DMA30_IRQn
@ DMA14_DMA30_IRQn
Definition MK66F18.h:151
CAN1_Bus_Off_IRQn
@ CAN1_Bus_Off_IRQn
Definition MK66F18.h:232
NotAvail_IRQn
@ NotAvail_IRQn
Definition MK66F18.h:123
DMA13_DMA29_IRQn
@ DMA13_DMA29_IRQn
Definition MK66F18.h:150
RTC_Seconds_IRQn
@ RTC_Seconds_IRQn
Definition MK66F18.h:184
UART4_RX_TX_IRQn
@ UART4_RX_TX_IRQn
Definition MK66F18.h:203
TPM1_IRQn
@ TPM1_IRQn
Definition MK66F18.h:225
CAN1_Error_IRQn
@ CAN1_Error_IRQn
Definition MK66F18.h:233
PORTD_IRQn
@ PORTD_IRQn
Definition MK66F18.h:199
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition MK66F18.h:128
ADC1_IRQn
@ ADC1_IRQn
Definition MK66F18.h:210
CAN0_ORed_Message_buffer_IRQn
@ CAN0_ORed_Message_buffer_IRQn
Definition MK66F18.h:212
DMA15_DMA31_IRQn
@ DMA15_DMA31_IRQn
Definition MK66F18.h:152
TSI0_IRQn
@ TSI0_IRQn
Definition MK66F18.h:224
SDHC_IRQn
@ SDHC_IRQn
Definition MK66F18.h:218
FTM1_IRQn
@ FTM1_IRQn
Definition MK66F18.h:180
I2S0_Tx_IRQn
@ I2S0_Tx_IRQn
Definition MK66F18.h:165
Reserved84_IRQn
@ Reserved84_IRQn
Definition MK66F18.h:205
CAN0_Wake_Up_IRQn
@ CAN0_Wake_Up_IRQn
Definition MK66F18.h:217
SWI_IRQn
@ SWI_IRQn
Definition MK66F18.h:201
LPUART0_IRQn
@ LPUART0_IRQn
Definition MK66F18.h:223
I2S0_Rx_IRQn
@ I2S0_Rx_IRQn
Definition MK66F18.h:166
SVCall_IRQn
@ SVCall_IRQn
Definition MK66F18.h:131
CAN0_Tx_Warning_IRQn
@ CAN0_Tx_Warning_IRQn
Definition MK66F18.h:215
DMA10_DMA26_IRQn
@ DMA10_DMA26_IRQn
Definition MK66F18.h:147
SPI2_IRQn
@ SPI2_IRQn
Definition MK66F18.h:202
DMA_Error_IRQn
@ DMA_Error_IRQn
Definition MK66F18.h:153
DMA5_DMA21_IRQn
@ DMA5_DMA21_IRQn
Definition MK66F18.h:142
UART0_RX_TX_IRQn
@ UART0_RX_TX_IRQn
Definition MK66F18.h:168
DAC0_IRQn
@ DAC0_IRQn
Definition MK66F18.h:193
DMA3_DMA19_IRQn
@ DMA3_DMA19_IRQn
Definition MK66F18.h:140
FTM2_IRQn
@ FTM2_IRQn
Definition MK66F18.h:181
CMT_IRQn
@ CMT_IRQn
Definition MK66F18.h:182
UsageFault_IRQn
@ UsageFault_IRQn
Definition MK66F18.h:130
UART4_ERR_IRQn
@ UART4_ERR_IRQn
Definition MK66F18.h:204
SysTick_IRQn
@ SysTick_IRQn
Definition MK66F18.h:134
CAN0_Error_IRQn
@ CAN0_Error_IRQn
Definition MK66F18.h:214
UART0_ERR_IRQn
@ UART0_ERR_IRQn
Definition MK66F18.h:169
CAN1_Rx_Warning_IRQn
@ CAN1_Rx_Warning_IRQn
Definition MK66F18.h:235
CMP2_IRQn
@ CMP2_IRQn
Definition MK66F18.h:207
DMA4_DMA20_IRQn
@ DMA4_DMA20_IRQn
Definition MK66F18.h:141
CAN1_Wake_Up_IRQn
@ CAN1_Wake_Up_IRQn
Definition MK66F18.h:236
BusFault_IRQn
@ BusFault_IRQn
Definition MK66F18.h:129
CMP0_IRQn
@ CMP0_IRQn
Definition MK66F18.h:177
ENET_Receive_IRQn
@ ENET_Receive_IRQn
Definition MK66F18.h:221
PDB0_IRQn
@ PDB0_IRQn
Definition MK66F18.h:189
UART2_RX_TX_IRQn
@ UART2_RX_TX_IRQn
Definition MK66F18.h:172
LLWU_IRQn
@ LLWU_IRQn
Definition MK66F18.h:158
DMA7_DMA23_IRQn
@ DMA7_DMA23_IRQn
Definition MK66F18.h:144
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition MK66F18.h:132
RNG_IRQn
@ RNG_IRQn
Definition MK66F18.h:160
UART1_ERR_IRQn
@ UART1_ERR_IRQn
Definition MK66F18.h:171
USBDCD_IRQn
@ USBDCD_IRQn
Definition MK66F18.h:191
LPTMR0_IRQn
@ LPTMR0_IRQn
Definition MK66F18.h:195
DMA8_DMA24_IRQn
@ DMA8_DMA24_IRQn
Definition MK66F18.h:145
USBHSDCD_IRQn
@ USBHSDCD_IRQn
Definition MK66F18.h:227
Read_Collision_IRQn
@ Read_Collision_IRQn
Definition MK66F18.h:156
LVD_LVW_IRQn
@ LVD_LVW_IRQn
Definition MK66F18.h:157
DMA6_DMA22_IRQn
@ DMA6_DMA22_IRQn
Definition MK66F18.h:143
PIT3_IRQn
@ PIT3_IRQn
Definition MK66F18.h:188
Reserved71_IRQn
@ Reserved71_IRQn
Definition MK66F18.h:192
UART2_ERR_IRQn
@ UART2_ERR_IRQn
Definition MK66F18.h:173
SPI1_IRQn
@ SPI1_IRQn
Definition MK66F18.h:164
TPM2_IRQn
@ TPM2_IRQn
Definition MK66F18.h:226
HardFault_IRQn
@ HardFault_IRQn
Definition MK66F18.h:127
CAN0_Rx_Warning_IRQn
@ CAN0_Rx_Warning_IRQn
Definition MK66F18.h:216
I2C3_IRQn
@ I2C3_IRQn
Definition MK66F18.h:228
PIT0_IRQn
@ PIT0_IRQn
Definition MK66F18.h:185
UART3_RX_TX_IRQn
@ UART3_RX_TX_IRQn
Definition MK66F18.h:174
ENET_Error_IRQn
@ ENET_Error_IRQn
Definition MK66F18.h:222
PORTA_IRQn
@ PORTA_IRQn
Definition MK66F18.h:196
FTFE_IRQn
@ FTFE_IRQn
Definition MK66F18.h:155
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition MK66F18.h:219
CMP1_IRQn
@ CMP1_IRQn
Definition MK66F18.h:178
DMA11_DMA27_IRQn
@ DMA11_DMA27_IRQn
Definition MK66F18.h:148
PORTC_IRQn
@ PORTC_IRQn
Definition MK66F18.h:198
ENET_Transmit_IRQn
@ ENET_Transmit_IRQn
Definition MK66F18.h:220
PORTB_IRQn
@ PORTB_IRQn
Definition MK66F18.h:197
UART3_ERR_IRQn
@ UART3_ERR_IRQn
Definition MK66F18.h:175
FTM3_IRQn
@ FTM3_IRQn
Definition MK66F18.h:208
UART1_RX_TX_IRQn
@ UART1_RX_TX_IRQn
Definition MK66F18.h:170
USB0_IRQn
@ USB0_IRQn
Definition MK66F18.h:190
DMA2_DMA18_IRQn
@ DMA2_DMA18_IRQn
Definition MK66F18.h:139
CMP3_IRQn
@ CMP3_IRQn
Definition MK66F18.h:229
CAN0_Bus_Off_IRQn
@ CAN0_Bus_Off_IRQn
Definition MK66F18.h:213
CAN1_Tx_Warning_IRQn
@ CAN1_Tx_Warning_IRQn
Definition MK66F18.h:234
RTC_IRQn
@ RTC_IRQn
Definition MK66F18.h:183
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition MK66F18.h:126
USBHS_IRQn
@ USBHS_IRQn
Definition MK66F18.h:230
PIT1_IRQn
@ PIT1_IRQn
Definition MK66F18.h:186
DMA9_DMA25_IRQn
@ DMA9_DMA25_IRQn
Definition MK66F18.h:146
DAC1_IRQn
@ DAC1_IRQn
Definition MK66F18.h:209
DMA12_DMA28_IRQn
@ DMA12_DMA28_IRQn
Definition MK66F18.h:149
I2C1_IRQn
@ I2C1_IRQn
Definition MK66F18.h:162
SPI0_IRQn
@ SPI0_IRQn
Definition MK66F18.h:163
PIT2_IRQn
@ PIT2_IRQn
Definition MK66F18.h:187
DMA1_DMA17_IRQn
@ DMA1_DMA17_IRQn
Definition MK66F18.h:138
USBDCD_Type::@249::TIMER2_BC11
__IO uint32_t TIMER2_BC11
Definition MK66F18.h:26298
DMA_Type::@223::@224::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition MK66F18.h:6603
PIT_Type::@236::TFLG
__IO uint32_t TFLG
Definition MK66F18.h:18358
CRC_Type::@213::@219::GPOLYH
__IO uint16_t GPOLYH
Definition MK66F18.h:6078
FMC_Type::@232::DATA_MU
__IO uint32_t DATA_MU
Definition MK66F18.h:11224
PDB_Type::@235::INTC
__IO uint32_t INTC
Definition MK66F18.h:18064
CRC_Type::@213::@220::GPOLYLU
__IO uint8_t GPOLYLU
Definition MK66F18.h:6083
USBHSDCD_Type::@255::TIMER2_BC11
__IO uint32_t TIMER2_BC11
Definition MK66F18.h:27774
DMA_Type::@223::SADDR
__IO uint32_t SADDR
Definition MK66F18.h:6599
AXBS_Type::@209::CRS
__IO uint32_t CRS
Definition MK66F18.h:3862
DMA_Type::@223::@228::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition MK66F18.h:6617
FB_Type::@231::CSMR
__IO uint32_t CSMR
Definition MK66F18.h:10986
USBHS_Type::@253::ASYNCLISTADDR
__IO uint32_t ASYNCLISTADDR
Definition MK66F18.h:26532
USB_Type::@248::ENDPT
__IO uint8_t ENDPT
Definition MK66F18.h:25577
SYSMPU_Type::@242::EDR
__I uint32_t EDR
Definition MK66F18.h:23548
CRC_Type::@211::@218::DATAHL
__IO uint8_t DATAHL
Definition MK66F18.h:6071
ENET_Type::@230::TCCR
__IO uint32_t TCCR
Definition MK66F18.h:9675
UART_Type::@244::@246::WP7816B_T0
__IO uint8_t WP7816B_T0
Definition MK66F18.h:24587
SPI_Type::@240::PUSHR
__IO uint32_t PUSHR
Definition MK66F18.h:22986
DMA_Type::@223::@228::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition MK66F18.h:6618
DMA_Type::@223::@224::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition MK66F18.h:6604
UART_Type::@244::@247::WP7816A_T1
__IO uint8_t WP7816A_T1
Definition MK66F18.h:24590
CAN_Type::@210::WORD1
__IO uint32_t WORD1
Definition MK66F18.h:4215
PIT_Type::@236::LDVAL
__IO uint32_t LDVAL
Definition MK66F18.h:18355
CAN_Type::@210::WORD0
__IO uint32_t WORD0
Definition MK66F18.h:4214
ENET_Type::@230::TCSR
__IO uint32_t TCSR
Definition MK66F18.h:9674
FTM_Type::@233::CnV
__IO uint32_t CnV
Definition MK66F18.h:12211
FMC_Type::@232::DATA_UM
__IO uint32_t DATA_UM
Definition MK66F18.h:11223
USBHSDCD_Type::@255::TIMER2_BC12
__IO uint32_t TIMER2_BC12
Definition MK66F18.h:27775
FMC_Type::@232::DATA_LM
__IO uint32_t DATA_LM
Definition MK66F18.h:11226
CRC_Type::@211::DATA
__IO uint32_t DATA
Definition MK66F18.h:6067
FTM_Type::@233::CnSC
__IO uint32_t CnSC
Definition MK66F18.h:12210
DAC_Type::@222::DATL
__IO uint8_t DATL
Definition MK66F18.h:6335
CRC_Type::@213::@220::GPOLYHU
__IO uint8_t GPOLYHU
Definition MK66F18.h:6085
TPM_Type::@243::CnSC
__IO uint32_t CnSC
Definition MK66F18.h:23923
SYSMPU_Type::@242::EAR
__I uint32_t EAR
Definition MK66F18.h:23547
PIT_Type::@236::TCTRL
__IO uint32_t TCTRL
Definition MK66F18.h:18357
PDB_Type::@234::S
__IO uint32_t S
Definition MK66F18.h:18058
USBHS_Type::@253::EPLISTADDR
__IO uint32_t EPLISTADDR
Definition MK66F18.h:26533
CRC_Type::@215::@221::CTRLHU
__IO uint8_t CTRLHU
Definition MK66F18.h:6092
TPM_Type::@243::CnV
__IO uint32_t CnV
Definition MK66F18.h:23924
DMA_Type::@223::DADDR
__IO uint32_t DADDR
Definition MK66F18.h:6608
DMA_Type::@223::SOFF
__IO uint16_t SOFF
Definition MK66F18.h:6600
AXBS_Type::@209::PRS
__IO uint32_t PRS
Definition MK66F18.h:3860
PDB_Type::@235::INT
__IO uint32_t INT
Definition MK66F18.h:18065
FB_Type::@231::CSAR
__IO uint32_t CSAR
Definition MK66F18.h:10985
CRC_Type::@211::@217::DATAH
__IO uint16_t DATAH
Definition MK66F18.h:6065
CRC_Type::@213::@219::GPOLYL
__IO uint16_t GPOLYL
Definition MK66F18.h:6077
PDB_Type::@234::C1
__IO uint32_t C1
Definition MK66F18.h:18057
DAC_Type::@222::DATH
__IO uint8_t DATH
Definition MK66F18.h:6336
DMA_Type::@223::DLAST_SGA
__IO uint32_t DLAST_SGA
Definition MK66F18.h:6614
DMA_Type::@223::SLAST
__IO uint32_t SLAST
Definition MK66F18.h:6607
CRC_Type::@213::GPOLY
__IO uint32_t GPOLY
Definition MK66F18.h:6080
DMA_Type::@223::@224::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition MK66F18.h:6605
CRC_Type::@213::@220::GPOLYLL
__IO uint8_t GPOLYLL
Definition MK66F18.h:6082
CRC_Type::@211::@218::DATALU
__IO uint8_t DATALU
Definition MK66F18.h:6070
DMA_Type::@223::@226::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition MK66F18.h:6611
CAN_Type::@210::ID
__IO uint32_t ID
Definition MK66F18.h:4213
CRC_Type::@211::@217::DATAL
__IO uint16_t DATAL
Definition MK66F18.h:6064
DMA_Type::@223::CSR
__IO uint16_t CSR
Definition MK66F18.h:6615
USBHS_Type::@251::DEVICEADDR
__IO uint32_t DEVICEADDR
Definition MK66F18.h:26528
CRC_Type::@215::CTRL
__IO uint32_t CTRL
Definition MK66F18.h:6089
CAN_Type::@210::CS
__IO uint32_t CS
Definition MK66F18.h:4212
DMA_Type::@223::ATTR
__IO uint16_t ATTR
Definition MK66F18.h:6601
SPI_Type::@240::PUSHR_SLAVE
__IO uint32_t PUSHR_SLAVE
Definition MK66F18.h:22987
UART_Type::@244::@246::WP7816A_T0
__IO uint8_t WP7816A_T0
Definition MK66F18.h:24586
USBHS_Type::@251::PERIODICLISTBASE
__IO uint32_t PERIODICLISTBASE
Definition MK66F18.h:26529
CRC_Type::@211::@218::DATALL
__IO uint8_t DATALL
Definition MK66F18.h:6069
DMA_Type::@223::DOFF
__IO uint16_t DOFF
Definition MK66F18.h:6609
CRC_Type::@211::@218::DATAHU
__IO uint8_t DATAHU
Definition MK66F18.h:6072
FMC_Type::@232::DATA_ML
__IO uint32_t DATA_ML
Definition MK66F18.h:11225
SDRAM_Type::@237::CM
__IO uint32_t CM
Definition MK66F18.h:21192
USBDCD_Type::@249::TIMER2_BC12
__IO uint32_t TIMER2_BC12
Definition MK66F18.h:26299
UART_Type::@244::@247::WP7816B_T1
__IO uint8_t WP7816B_T1
Definition MK66F18.h:24591
FB_Type::@231::CSCR
__IO uint32_t CSCR
Definition MK66F18.h:10987
SDRAM_Type::@237::AC
__IO uint32_t AC
Definition MK66F18.h:21191
DMA_Type::@223::@226::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition MK66F18.h:6612
CRC_Type::@213::@220::GPOLYHL
__IO uint8_t GPOLYHL
Definition MK66F18.h:6084
PIT_Type::@236::CVAL
__I uint32_t CVAL
Definition MK66F18.h:18356
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition MK60D10.h:336
kDmaRequestMux0FTM1Channel0
@ kDmaRequestMux0FTM1Channel0
Definition MK66F18.h:330
kDmaRequestMux0DAC0
@ kDmaRequestMux0DAC0
Definition MK66F18.h:360
kDmaRequestMux0FTM0Channel7
@ kDmaRequestMux0FTM0Channel7
Definition MK66F18.h:328
kDmaRequestMux0UART2Tx
@ kDmaRequestMux0UART2Tx
Definition MK66F18.h:304
kDmaRequestMux0I2C0
@ kDmaRequestMux0I2C0
Definition MK66F18.h:316
kDmaRequestMux0CMP2CMP3
@ kDmaRequestMux0CMP2CMP3
Definition MK66F18.h:357
kDmaRequestMux0CMP0
@ kDmaRequestMux0CMP0
Definition MK66F18.h:355
kDmaRequestMux0DAC1
@ kDmaRequestMux0DAC1
Definition MK66F18.h:361
kDmaRequestMux0UART3Tx
@ kDmaRequestMux0UART3Tx
Definition MK66F18.h:306
kDmaRequestMux0FTM3Channel1
@ kDmaRequestMux0FTM3Channel1
Definition MK66F18.h:342
kDmaRequestMux0TPM1Channel0
@ kDmaRequestMux0TPM1Channel0
Definition MK66F18.h:331
kDmaRequestMux0TPM1Channel1
@ kDmaRequestMux0TPM1Channel1
Definition MK66F18.h:334
kDmaRequestMux0CMP1
@ kDmaRequestMux0CMP1
Definition MK66F18.h:356
kDmaRequestMux0FTM3Channel7
@ kDmaRequestMux0FTM3Channel7
Definition MK66F18.h:351
kDmaRequestMux0SPI1Tx
@ kDmaRequestMux0SPI1Tx
Definition MK66F18.h:314
kDmaRequestMux0IEEE1588Timer1
@ kDmaRequestMux0IEEE1588Timer1
Definition MK66F18.h:371
kDmaRequestMux0FTM2Channel1
@ kDmaRequestMux0FTM2Channel1
Definition MK66F18.h:339
kDmaRequestMux0I2S0Tx
@ kDmaRequestMux0I2S0Tx
Definition MK66F18.h:310
kDmaRequestMux0PortE
@ kDmaRequestMux0PortE
Definition MK66F18.h:368
kDmaRequestMux0AlwaysOn63
@ kDmaRequestMux0AlwaysOn63
Definition MK66F18.h:382
kDmaRequestMux0FTM1TPM1Channel1
@ kDmaRequestMux0FTM1TPM1Channel1
Definition MK66F18.h:332
kDmaRequestMux0IEEE1588Timer3
@ kDmaRequestMux0IEEE1588Timer3
Definition MK66F18.h:376
kDmaRequestMux0SPI0Tx
@ kDmaRequestMux0SPI0Tx
Definition MK66F18.h:312
kDmaRequestMux0FTM0Channel1
@ kDmaRequestMux0FTM0Channel1
Definition MK66F18.h:322
kDmaRequestMux0I2C0I2C3
@ kDmaRequestMux0I2C0I2C3
Definition MK66F18.h:315
kDmaRequestMux0FTM0Channel5
@ kDmaRequestMux0FTM0Channel5
Definition MK66F18.h:326
kDmaRequestMux0FTM2Channel0
@ kDmaRequestMux0FTM2Channel0
Definition MK66F18.h:336
kDmaRequestMux0I2C2
@ kDmaRequestMux0I2C2
Definition MK66F18.h:320
kDmaRequestMux0AlwaysOn61
@ kDmaRequestMux0AlwaysOn61
Definition MK66F18.h:380
kDmaRequestMux0UART1Tx
@ kDmaRequestMux0UART1Tx
Definition MK66F18.h:302
kDmaRequestMux0SPI2Tx
@ kDmaRequestMux0SPI2Tx
Definition MK66F18.h:352
kDmaRequestMux0Reserved11
@ kDmaRequestMux0Reserved11
Definition MK66F18.h:308
kDmaRequestMux0UART4
@ kDmaRequestMux0UART4
Definition MK66F18.h:307
kDmaRequestMux0FTM0Channel6
@ kDmaRequestMux0FTM0Channel6
Definition MK66F18.h:327
kDmaRequestMux0LPUART0Rx
@ kDmaRequestMux0LPUART0Rx
Definition MK66F18.h:377
kDmaRequestMux0UART3Rx
@ kDmaRequestMux0UART3Rx
Definition MK66F18.h:305
kDmaRequestMux0FTM3Channel7SPI2Tx
@ kDmaRequestMux0FTM3Channel7SPI2Tx
Definition MK66F18.h:350
kDmaRequestMux0UART1Rx
@ kDmaRequestMux0UART1Rx
Definition MK66F18.h:301
kDmaRequestMux0FTM2TPM2Channel1
@ kDmaRequestMux0FTM2TPM2Channel1
Definition MK66F18.h:338
kDmaRequestMux0PortB
@ kDmaRequestMux0PortB
Definition MK66F18.h:365
kDmaRequestMux0TPM2Overflow
@ kDmaRequestMux0TPM2Overflow
Definition MK66F18.h:375
kDmaRequestMux0ADC1
@ kDmaRequestMux0ADC1
Definition MK66F18.h:354
kDmaRequestMux0CMP3
@ kDmaRequestMux0CMP3
Definition MK66F18.h:359
kDmaRequestMux0PortC
@ kDmaRequestMux0PortC
Definition MK66F18.h:366
kDmaRequestMux0FTM3Channel0
@ kDmaRequestMux0FTM3Channel0
Definition MK66F18.h:341
kDmaRequestMux0FTM1TPM1Channel0
@ kDmaRequestMux0FTM1TPM1Channel0
Definition MK66F18.h:329
kDmaRequestMux0FTM1Channel1
@ kDmaRequestMux0FTM1Channel1
Definition MK66F18.h:333
kDmaRequestMux0CMP2
@ kDmaRequestMux0CMP2
Definition MK66F18.h:358
kDmaRequestMux0TSI0
@ kDmaRequestMux0TSI0
Definition MK66F18.h:298
kDmaRequestMux0FTM3Channel6SPI2Rx
@ kDmaRequestMux0FTM3Channel6SPI2Rx
Definition MK66F18.h:347
kDmaRequestMux0TPM2Channel1
@ kDmaRequestMux0TPM2Channel1
Definition MK66F18.h:340
kDmaRequestMux0FTM0Channel4
@ kDmaRequestMux0FTM0Channel4
Definition MK66F18.h:325
kDmaRequestMux0CMT
@ kDmaRequestMux0CMT
Definition MK66F18.h:362
kDmaRequestMux0SPI2Rx
@ kDmaRequestMux0SPI2Rx
Definition MK66F18.h:349
kDmaRequestMux0I2S0Rx
@ kDmaRequestMux0I2S0Rx
Definition MK66F18.h:309
kDmaRequestMux0TPM2Channel0
@ kDmaRequestMux0TPM2Channel0
Definition MK66F18.h:337
kDmaRequestMux0AlwaysOn60
@ kDmaRequestMux0AlwaysOn60
Definition MK66F18.h:379
kDmaRequestMux0FTM3Channel2
@ kDmaRequestMux0FTM3Channel2
Definition MK66F18.h:343
kDmaRequestMux0IEEE1588Timer0
@ kDmaRequestMux0IEEE1588Timer0
Definition MK66F18.h:369
kDmaRequestMux0I2C1I2C2
@ kDmaRequestMux0I2C1I2C2
Definition MK66F18.h:318
kDmaRequestMux0FTM3Channel4
@ kDmaRequestMux0FTM3Channel4
Definition MK66F18.h:345
kDmaRequestMux0FTM3Channel5
@ kDmaRequestMux0FTM3Channel5
Definition MK66F18.h:346
kDmaRequestMux0Disable
@ kDmaRequestMux0Disable
Definition MK66F18.h:297
kDmaRequestMux0PortA
@ kDmaRequestMux0PortA
Definition MK66F18.h:364
kDmaRequestMux0PortD
@ kDmaRequestMux0PortD
Definition MK66F18.h:367
kDmaRequestMux0UART2Rx
@ kDmaRequestMux0UART2Rx
Definition MK66F18.h:303
kDmaRequestMux0ADC0
@ kDmaRequestMux0ADC0
Definition MK66F18.h:353
kDmaRequestMux0IEEE1588Timer2TPM2Overflow
@ kDmaRequestMux0IEEE1588Timer2TPM2Overflow
Definition MK66F18.h:373
kDmaRequestMux0I2C3
@ kDmaRequestMux0I2C3
Definition MK66F18.h:317
kDmaRequestMux0FTM3Channel3
@ kDmaRequestMux0FTM3Channel3
Definition MK66F18.h:344
kDmaRequestMux0FTM0Channel3
@ kDmaRequestMux0FTM0Channel3
Definition MK66F18.h:324
kDmaRequestMux0IEEE1588Timer2
@ kDmaRequestMux0IEEE1588Timer2
Definition MK66F18.h:374
kDmaRequestMux0UART0Rx
@ kDmaRequestMux0UART0Rx
Definition MK66F18.h:299
kDmaRequestMux0FTM0Channel0
@ kDmaRequestMux0FTM0Channel0
Definition MK66F18.h:321
kDmaRequestMux0FTM3Channel6
@ kDmaRequestMux0FTM3Channel6
Definition MK66F18.h:348
kDmaRequestMux0SPI1Rx
@ kDmaRequestMux0SPI1Rx
Definition MK66F18.h:313
kDmaRequestMux0AlwaysOn62
@ kDmaRequestMux0AlwaysOn62
Definition MK66F18.h:381
kDmaRequestMux0LPUART0Tx
@ kDmaRequestMux0LPUART0Tx
Definition MK66F18.h:378
kDmaRequestMux0FTM2TPM2Channel0
@ kDmaRequestMux0FTM2TPM2Channel0
Definition MK66F18.h:335
kDmaRequestMux0FTM0Channel2
@ kDmaRequestMux0FTM0Channel2
Definition MK66F18.h:323
kDmaRequestMux0IEEE1588Timer1TPM1Overflow
@ kDmaRequestMux0IEEE1588Timer1TPM1Overflow
Definition MK66F18.h:370
kDmaRequestMux0UART0Tx
@ kDmaRequestMux0UART0Tx
Definition MK66F18.h:300
kDmaRequestMux0SPI0Rx
@ kDmaRequestMux0SPI0Rx
Definition MK66F18.h:311
kDmaRequestMux0TPM1Overflow
@ kDmaRequestMux0TPM1Overflow
Definition MK66F18.h:372
kDmaRequestMux0I2C1
@ kDmaRequestMux0I2C1
Definition MK66F18.h:319
kDmaRequestMux0PDB
@ kDmaRequestMux0PDB
Definition MK66F18.h:363
ADC_Type
Definition MK60D10.h:449
AIPS_Type
Definition MK60D10.h:726
AXBS_Type
Definition MK60D10.h:2032
CAN_Type
Definition MK60D10.h:2166
CAU_Type
Definition MK60D10.h:2591
CMP_Type
Definition MK60D10.h:3104
CMT_Type
Definition MK60D10.h:3241
CRC_Type
Definition MK60D10.h:3382
DAC_Type
Definition MK60D10.h:3574
DMAMUX_Type
Definition MK60D10.h:4580
DMA_Type
Definition MK60D10.h:3706
ENET_Type
Definition MK60D10.h:4638
EWM_Type
Definition MK60D10.h:5537
FB_Type
Definition MK60D10.h:5622
FMC_Type
Definition MK60D10.h:5755
FTFE_Type
Definition MK64F12.h:10306
FTM_Type
Definition MK60D10.h:6173
GPIO_Type
Definition MK60D10.h:6852
I2C_Type
Definition MK60D10.h:6947
I2S_Type
Definition MK60D10.h:7149
LLWU_Type
Definition MK60D10.h:7536
LMEM_Type
Definition MK65F18.h:15751
LPTMR_Type
Definition MK60D10.h:7782
LPUART_Type
Definition MK65F18.h:16247
MCG_Type
Definition MK60D10.h:7875
MCM_Type
Definition MK60D10.h:8113
NV_Type
Definition MK60D10.h:8235
OSC_Type
Definition MK60D10.h:8389
PDB_Type
Definition MK60D10.h:8453
PIT_Type
Definition MK60D10.h:8640
PMC_Type
Definition MK60D10.h:8739
PORT_Type
Definition MK60D10.h:8832
RCM_Type
Definition MK60D10.h:8973
RFSYS_Type
Definition MK60D10.h:9084
RFVBAT_Type
Definition MK60D10.h:9145
RNG_Type
Definition MK60D10.h:9206
RTC_Type
Definition MK60D10.h:9305
SDHC_Type
Definition MK60D10.h:9520
SDRAM_Type
Definition MK65F18.h:21186
SIM_Type
Definition MK60D10.h:10117
SMC_Type
Definition MK60D10.h:10560
SPI_Type
Definition MK60D10.h:10645
SYSMPU_Type
Definition MK60D10.h:10978
TPM_Type
Definition MK65F18.h:23918
TSI_Type
Definition MK60D10.h:11191
UART_Type
Definition MK60D10.h:11447
USBDCD_Type
Definition MK60D10.h:12538
USBHSDCD_Type
Definition MK65F18.h:27766
USBHS_Type
Definition MK65F18.h:26501
USBPHY_Type
Definition MK65F18.h:27977
USB_Type
Definition MK60D10.h:12089
VREF_Type
Definition MK60D10.h:12656
WDOG_Type
Definition MK60D10.h:12726